drivers/gpu/drm/amd/display/include/grph_object_defs.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_GRPH_OBJECT_DEFS_H__
  27 #define __DAL_GRPH_OBJECT_DEFS_H__
  28
  29 #include "grph_object_id.h"
  30
  31 /* ********************************************************************
  32  * ********************************************************************
  33  *
  34  *  These defines shared between All Graphics Objects
  35  *
  36  * ********************************************************************
  37  * ********************************************************************
  38  */
  39
  40 /* HPD unit id - HW direct translation */
  41 enum hpd_source_id {
  42         HPD_SOURCEID1 = 0,
  43         HPD_SOURCEID2,
  44         HPD_SOURCEID3,
  45         HPD_SOURCEID4,
  46         HPD_SOURCEID5,
  47         HPD_SOURCEID6,
  48
  49         HPD_SOURCEID_COUNT,
  50         HPD_SOURCEID_UNKNOWN
  51 };
  52
  53 /* DDC unit id - HW direct translation */
  54 enum channel_id {
  55         CHANNEL_ID_UNKNOWN = 0,
  56         CHANNEL_ID_DDC1,
  57         CHANNEL_ID_DDC2,
  58         CHANNEL_ID_DDC3,
  59         CHANNEL_ID_DDC4,
  60         CHANNEL_ID_DDC5,
  61         CHANNEL_ID_DDC6,
  62         CHANNEL_ID_DDC_VGA,
  63         CHANNEL_ID_I2C_PAD,
  64         CHANNEL_ID_COUNT
  65 };
  66
  67 #define DECODE_CHANNEL_ID(ch_id) \
  68         (ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
  69         (ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
  70         (ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
  71         (ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
  72         (ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
  73         (ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
  74         (ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
  75         (ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
  76
  77 enum transmitter {
  78         TRANSMITTER_UNKNOWN = (-1L),
  79         TRANSMITTER_UNIPHY_A,
  80         TRANSMITTER_UNIPHY_B,
  81         TRANSMITTER_UNIPHY_C,
  82         TRANSMITTER_UNIPHY_D,
  83         TRANSMITTER_UNIPHY_E,
  84         TRANSMITTER_UNIPHY_F,
  85         TRANSMITTER_NUTMEG_CRT,
  86         TRANSMITTER_TRAVIS_CRT,
  87         TRANSMITTER_TRAVIS_LCD,
  88         TRANSMITTER_UNIPHY_G,
  89         TRANSMITTER_COUNT
  90 };
  91
  92 /* Generic source of the synchronisation input/output signal */
  93 /* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
  94 enum sync_source {
  95         SYNC_SOURCE_NONE = 0,
  96
  97         /* Source based on controllers */
  98         SYNC_SOURCE_CONTROLLER0,
  99         SYNC_SOURCE_CONTROLLER1,
 100         SYNC_SOURCE_CONTROLLER2,
 101         SYNC_SOURCE_CONTROLLER3,
 102         SYNC_SOURCE_CONTROLLER4,
 103         SYNC_SOURCE_CONTROLLER5,
 104
 105         /* Source based on GSL group */
 106         SYNC_SOURCE_GSL_GROUP0,
 107         SYNC_SOURCE_GSL_GROUP1,
 108         SYNC_SOURCE_GSL_GROUP2,
 109
 110         /* Source based on GSL IOs */
 111         /* These IOs normally used as GSL input/output */
 112         SYNC_SOURCE_GSL_IO_FIRST,
 113         SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
 114         SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
 115         SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
 116         SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
 117         SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
 118
 119         /* Source based on regular IOs */
 120         SYNC_SOURCE_IO_FIRST,
 121         SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
 122         SYNC_SOURCE_IO_GENERIC_B,
 123         SYNC_SOURCE_IO_GENERIC_C,
 124         SYNC_SOURCE_IO_GENERIC_D,
 125         SYNC_SOURCE_IO_GENERIC_E,
 126         SYNC_SOURCE_IO_GENERIC_F,
 127         SYNC_SOURCE_IO_HPD1,
 128         SYNC_SOURCE_IO_HPD2,
 129         SYNC_SOURCE_IO_HSYNC_A,
 130         SYNC_SOURCE_IO_VSYNC_A,
 131         SYNC_SOURCE_IO_HSYNC_B,
 132         SYNC_SOURCE_IO_VSYNC_B,
 133         SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
 134
 135         /* Misc. flow control sources */
 136         SYNC_SOURCE_DUAL_GPU_PIN
 137 };
 138
 139
 140 #endif