drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "cikd.h"
  30
  31 #include "uvd/uvd_4_2_d.h"
  32 #include "uvd/uvd_4_2_sh_mask.h"
  33
  34 #include "oss/oss_2_0_d.h"
  35 #include "oss/oss_2_0_sh_mask.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38
  39 #include "smu/smu_7_0_1_d.h"
  40 #include "smu/smu_7_0_1_sh_mask.h"
  41
  42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
  43 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
  45 static int uvd_v4_2_start(struct amdgpu_device *adev);
  46 static void uvd_v4_2_stop(struct amdgpu_device *adev);
  47 static int uvd_v4_2_set_clockgating_state(void *handle,
  48                                 enum amd_clockgating_state state);
  49 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
  50                              bool sw_mode);
  51 /**
  52  * uvd_v4_2_ring_get_rptr - get read pointer
  53  *
  54  * @ring: amdgpu_ring pointer
  55  *
  56  * Returns the current hardware read pointer
  57  */
  58 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
  59 {
  60         struct amdgpu_device *adev = ring->adev;
  61
  62         return RREG32(mmUVD_RBC_RB_RPTR);
  63 }
  64
  65 /**
  66  * uvd_v4_2_ring_get_wptr - get write pointer
  67  *
  68  * @ring: amdgpu_ring pointer
  69  *
  70  * Returns the current hardware write pointer
  71  */
  72 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
  73 {
  74         struct amdgpu_device *adev = ring->adev;
  75
  76         return RREG32(mmUVD_RBC_RB_WPTR);
  77 }
  78
  79 /**
  80  * uvd_v4_2_ring_set_wptr - set write pointer
  81  *
  82  * @ring: amdgpu_ring pointer
  83  *
  84  * Commits the write pointer to the hardware
  85  */
  86 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
  87 {
  88         struct amdgpu_device *adev = ring->adev;
  89
  90         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  91 }
  92
  93 static int uvd_v4_2_early_init(void *handle)
  94 {
  95         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  96
  97         uvd_v4_2_set_ring_funcs(adev);
  98         uvd_v4_2_set_irq_funcs(adev);
  99
 100         return 0;
 101 }
 102
 103 static int uvd_v4_2_sw_init(void *handle)
 104 {
 105         struct amdgpu_ring *ring;
 106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 107         int r;
 108
 109         /* UVD TRAP */
 110         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 111         if (r)
 112                 return r;
 113
 114         r = amdgpu_uvd_sw_init(adev);
 115         if (r)
 116                 return r;
 117
 118         r = amdgpu_uvd_resume(adev);
 119         if (r)
 120                 return r;
 121
 122         ring = &adev->uvd.ring;
 123         sprintf(ring->name, "uvd");
 124         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 125
 126         return r;
 127 }
 128
 129 static int uvd_v4_2_sw_fini(void *handle)
 130 {
 131         int r;
 132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 133
 134         r = amdgpu_uvd_suspend(adev);
 135         if (r)
 136                 return r;
 137
 138         return amdgpu_uvd_sw_fini(adev);
 139 }
 140
 141 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 142                                  bool enable);
 143 /**
 144  * uvd_v4_2_hw_init - start and test UVD block
 145  *
 146  * @adev: amdgpu_device pointer
 147  *
 148  * Initialize the hardware, boot up the VCPU and do some testing
 149  */
 150 static int uvd_v4_2_hw_init(void *handle)
 151 {
 152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 153         struct amdgpu_ring *ring = &adev->uvd.ring;
 154         uint32_t tmp;
 155         int r;
 156
 157         uvd_v4_2_enable_mgcg(adev, true);
 158         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 159
 160         ring->ready = true;
 161         r = amdgpu_ring_test_ring(ring);
 162         if (r) {
 163                 ring->ready = false;
 164                 goto done;
 165         }
 166
 167         r = amdgpu_ring_alloc(ring, 10);
 168         if (r) {
 169                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 170                 goto done;
 171         }
 172
 173         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 174         amdgpu_ring_write(ring, tmp);
 175         amdgpu_ring_write(ring, 0xFFFFF);
 176
 177         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 178         amdgpu_ring_write(ring, tmp);
 179         amdgpu_ring_write(ring, 0xFFFFF);
 180
 181         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 182         amdgpu_ring_write(ring, tmp);
 183         amdgpu_ring_write(ring, 0xFFFFF);
 184
 185         /* Clear timeout status bits */
 186         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 187         amdgpu_ring_write(ring, 0x8);
 188
 189         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 190         amdgpu_ring_write(ring, 3);
 191
 192         amdgpu_ring_commit(ring);
 193
 194 done:
 195         if (!r)
 196                 DRM_INFO("UVD initialized successfully.\n");
 197
 198         return r;
 199 }
 200
 201 /**
 202  * uvd_v4_2_hw_fini - stop the hardware block
 203  *
 204  * @adev: amdgpu_device pointer
 205  *
 206  * Stop the UVD block, mark ring as not ready any more
 207  */
 208 static int uvd_v4_2_hw_fini(void *handle)
 209 {
 210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 211         struct amdgpu_ring *ring = &adev->uvd.ring;
 212
 213         if (RREG32(mmUVD_STATUS) != 0)
 214                 uvd_v4_2_stop(adev);
 215
 216         ring->ready = false;
 217
 218         return 0;
 219 }
 220
 221 static int uvd_v4_2_suspend(void *handle)
 222 {
 223         int r;
 224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 225
 226         r = uvd_v4_2_hw_fini(adev);
 227         if (r)
 228                 return r;
 229
 230         return amdgpu_uvd_suspend(adev);
 231 }
 232
 233 static int uvd_v4_2_resume(void *handle)
 234 {
 235         int r;
 236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 237
 238         r = amdgpu_uvd_resume(adev);
 239         if (r)
 240                 return r;
 241
 242         return uvd_v4_2_hw_init(adev);
 243 }
 244
 245 /**
 246  * uvd_v4_2_start - start UVD block
 247  *
 248  * @adev: amdgpu_device pointer
 249  *
 250  * Setup and start the UVD block
 251  */
 252 static int uvd_v4_2_start(struct amdgpu_device *adev)
 253 {
 254         struct amdgpu_ring *ring = &adev->uvd.ring;
 255         uint32_t rb_bufsz;
 256         int i, j, r;
 257         u32 tmp;
 258         /* disable byte swapping */
 259         u32 lmi_swap_cntl = 0;
 260         u32 mp_swap_cntl = 0;
 261
 262         /* set uvd busy */
 263         WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
 264
 265         uvd_v4_2_set_dcm(adev, true);
 266         WREG32(mmUVD_CGC_GATE, 0);
 267
 268         /* take UVD block out of reset */
 269         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 270         mdelay(5);
 271
 272         /* enable VCPU clock */
 273         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 274
 275         /* disable interupt */
 276         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 277
 278 #ifdef __BIG_ENDIAN
 279         /* swap (8 in 32) RB and IB */
 280         lmi_swap_cntl = 0xa;
 281         mp_swap_cntl = 0;
 282 #endif
 283         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 284         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 285         /* initialize UVD memory controller */
 286         WREG32(mmUVD_LMI_CTRL, 0x203108);
 287
 288         tmp = RREG32(mmUVD_MPC_CNTL);
 289         WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
 290
 291         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 292         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 293         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 294         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 295         WREG32(mmUVD_MPC_SET_ALU, 0);
 296         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 297
 298         uvd_v4_2_mc_resume(adev);
 299
 300         tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
 301         WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
 302
 303         /* enable UMC */
 304         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 305
 306         WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
 307
 308         WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 309
 310         WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 311
 312         mdelay(10);
 313
 314         for (i = 0; i < 10; ++i) {
 315                 uint32_t status;
 316                 for (j = 0; j < 100; ++j) {
 317                         status = RREG32(mmUVD_STATUS);
 318                         if (status & 2)
 319                                 break;
 320                         mdelay(10);
 321                 }
 322                 r = 0;
 323                 if (status & 2)
 324                         break;
 325
 326                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 327                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 328                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 329                 mdelay(10);
 330                 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 331                 mdelay(10);
 332                 r = -1;
 333         }
 334
 335         if (r) {
 336                 DRM_ERROR("UVD not responding, giving up!!!\n");
 337                 return r;
 338         }
 339
 340         /* enable interupt */
 341         WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
 342
 343         WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
 344
 345         /* force RBC into idle state */
 346         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 347
 348         /* Set the write pointer delay */
 349         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 350
 351         /* programm the 4GB memory segment for rptr and ring buffer */
 352         WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
 353                                    (0x7 << 16) | (0x1 << 31));
 354
 355         /* Initialize the ring buffer's read and write pointers */
 356         WREG32(mmUVD_RBC_RB_RPTR, 0x0);
 357
 358         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 359         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 360
 361         /* set the ring address */
 362         WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
 363
 364         /* Set ring buffer size */
 365         rb_bufsz = order_base_2(ring->ring_size);
 366         rb_bufsz = (0x1 << 8) | rb_bufsz;
 367         WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
 368
 369         return 0;
 370 }
 371
 372 /**
 373  * uvd_v4_2_stop - stop UVD block
 374  *
 375  * @adev: amdgpu_device pointer
 376  *
 377  * stop the UVD block
 378  */
 379 static void uvd_v4_2_stop(struct amdgpu_device *adev)
 380 {
 381         uint32_t i, j;
 382         uint32_t status;
 383
 384         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 385
 386         for (i = 0; i < 10; ++i) {
 387                 for (j = 0; j < 100; ++j) {
 388                         status = RREG32(mmUVD_STATUS);
 389                         if (status & 2)
 390                                 break;
 391                         mdelay(1);
 392                 }
 393                 if (status & 2)
 394                         break;
 395         }
 396
 397         for (i = 0; i < 10; ++i) {
 398                 for (j = 0; j < 100; ++j) {
 399                         status = RREG32(mmUVD_LMI_STATUS);
 400                         if (status & 0xf)
 401                                 break;
 402                         mdelay(1);
 403                 }
 404                 if (status & 0xf)
 405                         break;
 406         }
 407
 408         /* Stall UMC and register bus before resetting VCPU */
 409         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 410
 411         for (i = 0; i < 10; ++i) {
 412                 for (j = 0; j < 100; ++j) {
 413                         status = RREG32(mmUVD_LMI_STATUS);
 414                         if (status & 0x240)
 415                                 break;
 416                         mdelay(1);
 417                 }
 418                 if (status & 0x240)
 419                         break;
 420         }
 421
 422         WREG32_P(0x3D49, 0, ~(1 << 2));
 423
 424         WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
 425
 426         /* put LMI, VCPU, RBC etc... into reset */
 427         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 428                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 429                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 430
 431         WREG32(mmUVD_STATUS, 0);
 432
 433         uvd_v4_2_set_dcm(adev, false);
 434 }
 435
 436 /**
 437  * uvd_v4_2_ring_emit_fence - emit an fence & trap command
 438  *
 439  * @ring: amdgpu_ring pointer
 440  * @fence: fence to emit
 441  *
 442  * Write a fence and a trap command to the ring.
 443  */
 444 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 445                                      unsigned flags)
 446 {
 447         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 448
 449         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 450         amdgpu_ring_write(ring, seq);
 451         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 452         amdgpu_ring_write(ring, addr & 0xffffffff);
 453         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 454         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 455         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 456         amdgpu_ring_write(ring, 0);
 457
 458         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 459         amdgpu_ring_write(ring, 0);
 460         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 461         amdgpu_ring_write(ring, 0);
 462         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 463         amdgpu_ring_write(ring, 2);
 464 }
 465
 466 /**
 467  * uvd_v4_2_ring_test_ring - register write test
 468  *
 469  * @ring: amdgpu_ring pointer
 470  *
 471  * Test if we can successfully write to the context register
 472  */
 473 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
 474 {
 475         struct amdgpu_device *adev = ring->adev;
 476         uint32_t tmp = 0;
 477         unsigned i;
 478         int r;
 479
 480         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 481         r = amdgpu_ring_alloc(ring, 3);
 482         if (r) {
 483                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 484                           ring->idx, r);
 485                 return r;
 486         }
 487         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 488         amdgpu_ring_write(ring, 0xDEADBEEF);
 489         amdgpu_ring_commit(ring);
 490         for (i = 0; i < adev->usec_timeout; i++) {
 491                 tmp = RREG32(mmUVD_CONTEXT_ID);
 492                 if (tmp == 0xDEADBEEF)
 493                         break;
 494                 DRM_UDELAY(1);
 495         }
 496
 497         if (i < adev->usec_timeout) {
 498                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 499                          ring->idx, i);
 500         } else {
 501                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 502                           ring->idx, tmp);
 503                 r = -EINVAL;
 504         }
 505         return r;
 506 }
 507
 508 /**
 509  * uvd_v4_2_ring_emit_ib - execute indirect buffer
 510  *
 511  * @ring: amdgpu_ring pointer
 512  * @ib: indirect buffer to execute
 513  *
 514  * Write ring commands to execute the indirect buffer
 515  */
 516 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
 517                                   struct amdgpu_ib *ib,
 518                                   unsigned vmid, bool ctx_switch)
 519 {
 520         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
 521         amdgpu_ring_write(ring, ib->gpu_addr);
 522         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 523         amdgpu_ring_write(ring, ib->length_dw);
 524 }
 525
 526 /**
 527  * uvd_v4_2_mc_resume - memory controller programming
 528  *
 529  * @adev: amdgpu_device pointer
 530  *
 531  * Let the UVD memory controller know it's offsets
 532  */
 533 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
 534 {
 535         uint64_t addr;
 536         uint32_t size;
 537
 538         /* programm the VCPU memory controller bits 0-27 */
 539         addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
 540         size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
 541         WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
 542         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 543
 544         addr += size;
 545         size = AMDGPU_UVD_HEAP_SIZE >> 3;
 546         WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
 547         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 548
 549         addr += size;
 550         size = (AMDGPU_UVD_STACK_SIZE +
 551                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
 552         WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
 553         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 554
 555         /* bits 28-31 */
 556         addr = (adev->uvd.gpu_addr >> 28) & 0xF;
 557         WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 558
 559         /* bits 32-39 */
 560         addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
 561         WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 562
 563         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 564         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 565         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 566 }
 567
 568 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 569                                  bool enable)
 570 {
 571         u32 orig, data;
 572
 573         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
 574                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 575                 data |= 0xfff;
 576                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 577
 578                 orig = data = RREG32(mmUVD_CGC_CTRL);
 579                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 580                 if (orig != data)
 581                         WREG32(mmUVD_CGC_CTRL, data);
 582         } else {
 583                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
 584                 data &= ~0xfff;
 585                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
 586
 587                 orig = data = RREG32(mmUVD_CGC_CTRL);
 588                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 589                 if (orig != data)
 590                         WREG32(mmUVD_CGC_CTRL, data);
 591         }
 592 }
 593
 594 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
 595                              bool sw_mode)
 596 {
 597         u32 tmp, tmp2;
 598
 599         WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
 600
 601         tmp = RREG32(mmUVD_CGC_CTRL);
 602         tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 603         tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 604                 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
 605                 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
 606
 607         if (sw_mode) {
 608                 tmp &= ~0x7ffff800;
 609                 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
 610                         UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
 611                         (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
 612         } else {
 613                 tmp |= 0x7ffff800;
 614                 tmp2 = 0;
 615         }
 616
 617         WREG32(mmUVD_CGC_CTRL, tmp);
 618         WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
 619 }
 620
 621 static bool uvd_v4_2_is_idle(void *handle)
 622 {
 623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 624
 625         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 626 }
 627
 628 static int uvd_v4_2_wait_for_idle(void *handle)
 629 {
 630         unsigned i;
 631         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 632
 633         for (i = 0; i < adev->usec_timeout; i++) {
 634                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 635                         return 0;
 636         }
 637         return -ETIMEDOUT;
 638 }
 639
 640 static int uvd_v4_2_soft_reset(void *handle)
 641 {
 642         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 643
 644         uvd_v4_2_stop(adev);
 645
 646         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 647                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 648         mdelay(5);
 649
 650         return uvd_v4_2_start(adev);
 651 }
 652
 653 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
 654                                         struct amdgpu_irq_src *source,
 655                                         unsigned type,
 656                                         enum amdgpu_interrupt_state state)
 657 {
 658         // TODO
 659         return 0;
 660 }
 661
 662 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
 663                                       struct amdgpu_irq_src *source,
 664                                       struct amdgpu_iv_entry *entry)
 665 {
 666         DRM_DEBUG("IH: UVD TRAP\n");
 667         amdgpu_fence_process(&adev->uvd.ring);
 668         return 0;
 669 }
 670
 671 static int uvd_v4_2_set_clockgating_state(void *handle,
 672                                           enum amd_clockgating_state state)
 673 {
 674         return 0;
 675 }
 676
 677 static int uvd_v4_2_set_powergating_state(void *handle,
 678                                           enum amd_powergating_state state)
 679 {
 680         /* This doesn't actually powergate the UVD block.
 681          * That's done in the dpm code via the SMC.  This
 682          * just re-inits the block as necessary.  The actual
 683          * gating still happens in the dpm code.  We should
 684          * revisit this when there is a cleaner line between
 685          * the smc and the hw blocks
 686          */
 687         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 688
 689         if (state == AMD_PG_STATE_GATE) {
 690                 uvd_v4_2_stop(adev);
 691                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
 692                         if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
 693                                 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
 694                                 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
 695                                                         UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
 696                                                         UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
 697                                 mdelay(20);
 698                         }
 699                 }
 700                 return 0;
 701         } else {
 702                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
 703                         if (RREG32_SMC(ixCURRENT_PG_STATUS) &
 704                                 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
 705                                 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
 706                                                 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
 707                                                 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
 708                                 mdelay(30);
 709                         }
 710                 }
 711                 return uvd_v4_2_start(adev);
 712         }
 713 }
 714
 715 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
 716         .name = "uvd_v4_2",
 717         .early_init = uvd_v4_2_early_init,
 718         .late_init = NULL,
 719         .sw_init = uvd_v4_2_sw_init,
 720         .sw_fini = uvd_v4_2_sw_fini,
 721         .hw_init = uvd_v4_2_hw_init,
 722         .hw_fini = uvd_v4_2_hw_fini,
 723         .suspend = uvd_v4_2_suspend,
 724         .resume = uvd_v4_2_resume,
 725         .is_idle = uvd_v4_2_is_idle,
 726         .wait_for_idle = uvd_v4_2_wait_for_idle,
 727         .soft_reset = uvd_v4_2_soft_reset,
 728         .set_clockgating_state = uvd_v4_2_set_clockgating_state,
 729         .set_powergating_state = uvd_v4_2_set_powergating_state,
 730 };
 731
 732 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
 733         .type = AMDGPU_RING_TYPE_UVD,
 734         .align_mask = 0xf,
 735         .nop = PACKET0(mmUVD_NO_OP, 0),
 736         .support_64bit_ptrs = false,
 737         .get_rptr = uvd_v4_2_ring_get_rptr,
 738         .get_wptr = uvd_v4_2_ring_get_wptr,
 739         .set_wptr = uvd_v4_2_ring_set_wptr,
 740         .parse_cs = amdgpu_uvd_ring_parse_cs,
 741         .emit_frame_size =
 742                 14, /* uvd_v4_2_ring_emit_fence  x1 no user fence */
 743         .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */
 744         .emit_ib = uvd_v4_2_ring_emit_ib,
 745         .emit_fence = uvd_v4_2_ring_emit_fence,
 746         .test_ring = uvd_v4_2_ring_test_ring,
 747         .test_ib = amdgpu_uvd_ring_test_ib,
 748         .insert_nop = amdgpu_ring_insert_nop,
 749         .pad_ib = amdgpu_ring_generic_pad_ib,
 750         .begin_use = amdgpu_uvd_ring_begin_use,
 751         .end_use = amdgpu_uvd_ring_end_use,
 752 };
 753
 754 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
 755 {
 756         adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
 757 }
 758
 759 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
 760         .set = uvd_v4_2_set_interrupt_state,
 761         .process = uvd_v4_2_process_interrupt,
 762 };
 763
 764 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
 765 {
 766         adev->uvd.irq.num_types = 1;
 767         adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
 768 }
 769
 770 const struct amdgpu_ip_block_version uvd_v4_2_ip_block =
 771 {
 772                 .type = AMD_IP_BLOCK_TYPE_UVD,
 773                 .major = 4,
 774                 .minor = 2,
 775                 .rev = 0,
 776                 .funcs = &uvd_v4_2_ip_funcs,
 777 };