drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static void i8xx_disable_fbc(struct drm_device *dev)
  48 {
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         u32 fbc_ctl;
  51
  52         /* Disable compression */
  53         fbc_ctl = I915_READ(FBC_CONTROL);
  54         if ((fbc_ctl & FBC_CTL_EN) == 0)
  55                 return;
  56
  57         fbc_ctl &= ~FBC_CTL_EN;
  58         I915_WRITE(FBC_CONTROL, fbc_ctl);
  59
  60         /* Wait for compressing bit to clear */
  61         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62                 DRM_DEBUG_KMS("FBC idle timed out\n");
  63                 return;
  64         }
  65
  66         DRM_DEBUG_KMS("disabled FBC\n");
  67 }
  68
  69 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  70 {
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_i915_private *dev_priv = dev->dev_private;
  73         struct drm_framebuffer *fb = crtc->fb;
  74         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  75         struct drm_i915_gem_object *obj = intel_fb->obj;
  76         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  77         int cfb_pitch;
  78         int plane, i;
  79         u32 fbc_ctl, fbc_ctl2;
  80
  81         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  82         if (fb->pitches[0] < cfb_pitch)
  83                 cfb_pitch = fb->pitches[0];
  84
  85         /* FBC_CTL wants 64B units */
  86         cfb_pitch = (cfb_pitch / 64) - 1;
  87         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  88
  89         /* Clear old tags */
  90         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  91                 I915_WRITE(FBC_TAG + (i * 4), 0);
  92
  93         /* Set it up... */
  94         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  95         fbc_ctl2 |= plane;
  96         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  97         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  98
  99         /* enable it... */
 100         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 101         if (IS_I945GM(dev))
 102                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 103         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 104         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 105         fbc_ctl |= obj->fence_reg;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 109                       cfb_pitch, crtc->y, intel_crtc->plane);
 110 }
 111
 112 static bool i8xx_fbc_enabled(struct drm_device *dev)
 113 {
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115
 116         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 117 }
 118
 119 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 120 {
 121         struct drm_device *dev = crtc->dev;
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         struct drm_framebuffer *fb = crtc->fb;
 124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 125         struct drm_i915_gem_object *obj = intel_fb->obj;
 126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 127         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 128         unsigned long stall_watermark = 200;
 129         u32 dpfc_ctl;
 130
 131         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 132         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 133         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 134
 135         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 136                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 137                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 138         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 139
 140         /* enable it... */
 141         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 142
 143         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 144 }
 145
 146 static void g4x_disable_fbc(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         u32 dpfc_ctl;
 150
 151         /* Disable compression */
 152         dpfc_ctl = I915_READ(DPFC_CONTROL);
 153         if (dpfc_ctl & DPFC_CTL_EN) {
 154                 dpfc_ctl &= ~DPFC_CTL_EN;
 155                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 156
 157                 DRM_DEBUG_KMS("disabled FBC\n");
 158         }
 159 }
 160
 161 static bool g4x_fbc_enabled(struct drm_device *dev)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164
 165         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 166 }
 167
 168 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 169 {
 170         struct drm_i915_private *dev_priv = dev->dev_private;
 171         u32 blt_ecoskpd;
 172
 173         /* Make sure blitter notifies FBC of writes */
 174         gen6_gt_force_wake_get(dev_priv);
 175         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 176         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 177                 GEN6_BLITTER_LOCK_SHIFT;
 178         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 179         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 180         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 181         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 182                          GEN6_BLITTER_LOCK_SHIFT);
 183         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 184         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 185         gen6_gt_force_wake_put(dev_priv);
 186 }
 187
 188 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 189 {
 190         struct drm_device *dev = crtc->dev;
 191         struct drm_i915_private *dev_priv = dev->dev_private;
 192         struct drm_framebuffer *fb = crtc->fb;
 193         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 194         struct drm_i915_gem_object *obj = intel_fb->obj;
 195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 196         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 197         unsigned long stall_watermark = 200;
 198         u32 dpfc_ctl;
 199
 200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 201         dpfc_ctl &= DPFC_RESERVED;
 202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 203         /* Set persistent mode for front-buffer rendering, ala X. */
 204         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 205         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 206         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 207
 208         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 209                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 210                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 211         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 212         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 213         /* enable it... */
 214         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 215
 216         if (IS_GEN6(dev)) {
 217                 I915_WRITE(SNB_DPFC_CTL_SA,
 218                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 219                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 220                 sandybridge_blit_fbc_update(dev);
 221         }
 222
 223         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 224 }
 225
 226 static void ironlake_disable_fbc(struct drm_device *dev)
 227 {
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 dpfc_ctl;
 230
 231         /* Disable compression */
 232         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 233         if (dpfc_ctl & DPFC_CTL_EN) {
 234                 dpfc_ctl &= ~DPFC_CTL_EN;
 235                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 236
 237                 DRM_DEBUG_KMS("disabled FBC\n");
 238         }
 239 }
 240
 241 static bool ironlake_fbc_enabled(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244
 245         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 246 }
 247
 248 bool intel_fbc_enabled(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251
 252         if (!dev_priv->display.fbc_enabled)
 253                 return false;
 254
 255         return dev_priv->display.fbc_enabled(dev);
 256 }
 257
 258 static void intel_fbc_work_fn(struct work_struct *__work)
 259 {
 260         struct intel_fbc_work *work =
 261                 container_of(to_delayed_work(__work),
 262                              struct intel_fbc_work, work);
 263         struct drm_device *dev = work->crtc->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265
 266         mutex_lock(&dev->struct_mutex);
 267         if (work == dev_priv->fbc_work) {
 268                 /* Double check that we haven't switched fb without cancelling
 269                  * the prior work.
 270                  */
 271                 if (work->crtc->fb == work->fb) {
 272                         dev_priv->display.enable_fbc(work->crtc,
 273                                                      work->interval);
 274
 275                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 276                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 277                         dev_priv->cfb_y = work->crtc->y;
 278                 }
 279
 280                 dev_priv->fbc_work = NULL;
 281         }
 282         mutex_unlock(&dev->struct_mutex);
 283
 284         kfree(work);
 285 }
 286
 287 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 288 {
 289         if (dev_priv->fbc_work == NULL)
 290                 return;
 291
 292         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 293
 294         /* Synchronisation is provided by struct_mutex and checking of
 295          * dev_priv->fbc_work, so we can perform the cancellation
 296          * entirely asynchronously.
 297          */
 298         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 299                 /* tasklet was killed before being run, clean up */
 300                 kfree(dev_priv->fbc_work);
 301
 302         /* Mark the work as no longer wanted so that if it does
 303          * wake-up (because the work was already running and waiting
 304          * for our mutex), it will discover that is no longer
 305          * necessary to run.
 306          */
 307         dev_priv->fbc_work = NULL;
 308 }
 309
 310 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 311 {
 312         struct intel_fbc_work *work;
 313         struct drm_device *dev = crtc->dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         if (!dev_priv->display.enable_fbc)
 317                 return;
 318
 319         intel_cancel_fbc_work(dev_priv);
 320
 321         work = kzalloc(sizeof *work, GFP_KERNEL);
 322         if (work == NULL) {
 323                 dev_priv->display.enable_fbc(crtc, interval);
 324                 return;
 325         }
 326
 327         work->crtc = crtc;
 328         work->fb = crtc->fb;
 329         work->interval = interval;
 330         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 331
 332         dev_priv->fbc_work = work;
 333
 334         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 335
 336         /* Delay the actual enabling to let pageflipping cease and the
 337          * display to settle before starting the compression. Note that
 338          * this delay also serves a second purpose: it allows for a
 339          * vblank to pass after disabling the FBC before we attempt
 340          * to modify the control registers.
 341          *
 342          * A more complicated solution would involve tracking vblanks
 343          * following the termination of the page-flipping sequence
 344          * and indeed performing the enable as a co-routine and not
 345          * waiting synchronously upon the vblank.
 346          */
 347         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 348 }
 349
 350 void intel_disable_fbc(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353
 354         intel_cancel_fbc_work(dev_priv);
 355
 356         if (!dev_priv->display.disable_fbc)
 357                 return;
 358
 359         dev_priv->display.disable_fbc(dev);
 360         dev_priv->cfb_plane = -1;
 361 }
 362
 363 /**
 364  * intel_update_fbc - enable/disable FBC as needed
 365  * @dev: the drm_device
 366  *
 367  * Set up the framebuffer compression hardware at mode set time.  We
 368  * enable it if possible:
 369  *   - plane A only (on pre-965)
 370  *   - no pixel mulitply/line duplication
 371  *   - no alpha buffer discard
 372  *   - no dual wide
 373  *   - framebuffer <= 2048 in width, 1536 in height
 374  *
 375  * We can't assume that any compression will take place (worst case),
 376  * so the compressed buffer has to be the same size as the uncompressed
 377  * one.  It also must reside (along with the line length buffer) in
 378  * stolen memory.
 379  *
 380  * We need to enable/disable FBC on a global basis.
 381  */
 382 void intel_update_fbc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         struct drm_crtc *crtc = NULL, *tmp_crtc;
 386         struct intel_crtc *intel_crtc;
 387         struct drm_framebuffer *fb;
 388         struct intel_framebuffer *intel_fb;
 389         struct drm_i915_gem_object *obj;
 390         int enable_fbc;
 391
 392         if (!i915_powersave)
 393                 return;
 394
 395         if (!I915_HAS_FBC(dev))
 396                 return;
 397
 398         /*
 399          * If FBC is already on, we just have to verify that we can
 400          * keep it that way...
 401          * Need to disable if:
 402          *   - more than one pipe is active
 403          *   - changing FBC params (stride, fence, mode)
 404          *   - new fb is too large to fit in compressed buffer
 405          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 406          */
 407         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 408                 if (tmp_crtc->enabled &&
 409                     !to_intel_crtc(tmp_crtc)->primary_disabled &&
 410                     tmp_crtc->fb) {
 411                         if (crtc) {
 412                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 413                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 414                                 goto out_disable;
 415                         }
 416                         crtc = tmp_crtc;
 417                 }
 418         }
 419
 420         if (!crtc || crtc->fb == NULL) {
 421                 DRM_DEBUG_KMS("no output, disabling\n");
 422                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 423                 goto out_disable;
 424         }
 425
 426         intel_crtc = to_intel_crtc(crtc);
 427         fb = crtc->fb;
 428         intel_fb = to_intel_framebuffer(fb);
 429         obj = intel_fb->obj;
 430
 431         enable_fbc = i915_enable_fbc;
 432         if (enable_fbc < 0) {
 433                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 434                 enable_fbc = 1;
 435                 if (INTEL_INFO(dev)->gen <= 6)
 436                         enable_fbc = 0;
 437         }
 438         if (!enable_fbc) {
 439                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 440                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 441                 goto out_disable;
 442         }
 443         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 444             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 445                 DRM_DEBUG_KMS("mode incompatible with compression, "
 446                               "disabling\n");
 447                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 448                 goto out_disable;
 449         }
 450         if ((crtc->mode.hdisplay > 2048) ||
 451             (crtc->mode.vdisplay > 1536)) {
 452                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 453                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 454                 goto out_disable;
 455         }
 456         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 457                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 458                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 459                 goto out_disable;
 460         }
 461
 462         /* The use of a CPU fence is mandatory in order to detect writes
 463          * by the CPU to the scanout and trigger updates to the FBC.
 464          */
 465         if (obj->tiling_mode != I915_TILING_X ||
 466             obj->fence_reg == I915_FENCE_REG_NONE) {
 467                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 468                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 469                 goto out_disable;
 470         }
 471
 472         /* If the kernel debugger is active, always disable compression */
 473         if (in_dbg_master())
 474                 goto out_disable;
 475
 476         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 477                 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
 478                 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
 479                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 480                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 481                 goto out_disable;
 482         }
 483
 484         /* If the scanout has not changed, don't modify the FBC settings.
 485          * Note that we make the fundamental assumption that the fb->obj
 486          * cannot be unpinned (and have its GTT offset and fence revoked)
 487          * without first being decoupled from the scanout and FBC disabled.
 488          */
 489         if (dev_priv->cfb_plane == intel_crtc->plane &&
 490             dev_priv->cfb_fb == fb->base.id &&
 491             dev_priv->cfb_y == crtc->y)
 492                 return;
 493
 494         if (intel_fbc_enabled(dev)) {
 495                 /* We update FBC along two paths, after changing fb/crtc
 496                  * configuration (modeswitching) and after page-flipping
 497                  * finishes. For the latter, we know that not only did
 498                  * we disable the FBC at the start of the page-flip
 499                  * sequence, but also more than one vblank has passed.
 500                  *
 501                  * For the former case of modeswitching, it is possible
 502                  * to switch between two FBC valid configurations
 503                  * instantaneously so we do need to disable the FBC
 504                  * before we can modify its control registers. We also
 505                  * have to wait for the next vblank for that to take
 506                  * effect. However, since we delay enabling FBC we can
 507                  * assume that a vblank has passed since disabling and
 508                  * that we can safely alter the registers in the deferred
 509                  * callback.
 510                  *
 511                  * In the scenario that we go from a valid to invalid
 512                  * and then back to valid FBC configuration we have
 513                  * no strict enforcement that a vblank occurred since
 514                  * disabling the FBC. However, along all current pipe
 515                  * disabling paths we do need to wait for a vblank at
 516                  * some point. And we wait before enabling FBC anyway.
 517                  */
 518                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 519                 intel_disable_fbc(dev);
 520         }
 521
 522         intel_enable_fbc(crtc, 500);
 523         return;
 524
 525 out_disable:
 526         /* Multiple disables should be harmless */
 527         if (intel_fbc_enabled(dev)) {
 528                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 529                 intel_disable_fbc(dev);
 530         }
 531         i915_gem_stolen_cleanup_compression(dev);
 532 }
 533
 534 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 535 {
 536         drm_i915_private_t *dev_priv = dev->dev_private;
 537         u32 tmp;
 538
 539         tmp = I915_READ(CLKCFG);
 540
 541         switch (tmp & CLKCFG_FSB_MASK) {
 542         case CLKCFG_FSB_533:
 543                 dev_priv->fsb_freq = 533; /* 133*4 */
 544                 break;
 545         case CLKCFG_FSB_800:
 546                 dev_priv->fsb_freq = 800; /* 200*4 */
 547                 break;
 548         case CLKCFG_FSB_667:
 549                 dev_priv->fsb_freq =  667; /* 167*4 */
 550                 break;
 551         case CLKCFG_FSB_400:
 552                 dev_priv->fsb_freq = 400; /* 100*4 */
 553                 break;
 554         }
 555
 556         switch (tmp & CLKCFG_MEM_MASK) {
 557         case CLKCFG_MEM_533:
 558                 dev_priv->mem_freq = 533;
 559                 break;
 560         case CLKCFG_MEM_667:
 561                 dev_priv->mem_freq = 667;
 562                 break;
 563         case CLKCFG_MEM_800:
 564                 dev_priv->mem_freq = 800;
 565                 break;
 566         }
 567
 568         /* detect pineview DDR3 setting */
 569         tmp = I915_READ(CSHRDDR3CTL);
 570         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 571 }
 572
 573 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 574 {
 575         drm_i915_private_t *dev_priv = dev->dev_private;
 576         u16 ddrpll, csipll;
 577
 578         ddrpll = I915_READ16(DDRMPLL1);
 579         csipll = I915_READ16(CSIPLL0);
 580
 581         switch (ddrpll & 0xff) {
 582         case 0xc:
 583                 dev_priv->mem_freq = 800;
 584                 break;
 585         case 0x10:
 586                 dev_priv->mem_freq = 1066;
 587                 break;
 588         case 0x14:
 589                 dev_priv->mem_freq = 1333;
 590                 break;
 591         case 0x18:
 592                 dev_priv->mem_freq = 1600;
 593                 break;
 594         default:
 595                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 596                                  ddrpll & 0xff);
 597                 dev_priv->mem_freq = 0;
 598                 break;
 599         }
 600
 601         dev_priv->ips.r_t = dev_priv->mem_freq;
 602
 603         switch (csipll & 0x3ff) {
 604         case 0x00c:
 605                 dev_priv->fsb_freq = 3200;
 606                 break;
 607         case 0x00e:
 608                 dev_priv->fsb_freq = 3733;
 609                 break;
 610         case 0x010:
 611                 dev_priv->fsb_freq = 4266;
 612                 break;
 613         case 0x012:
 614                 dev_priv->fsb_freq = 4800;
 615                 break;
 616         case 0x014:
 617                 dev_priv->fsb_freq = 5333;
 618                 break;
 619         case 0x016:
 620                 dev_priv->fsb_freq = 5866;
 621                 break;
 622         case 0x018:
 623                 dev_priv->fsb_freq = 6400;
 624                 break;
 625         default:
 626                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 627                                  csipll & 0x3ff);
 628                 dev_priv->fsb_freq = 0;
 629                 break;
 630         }
 631
 632         if (dev_priv->fsb_freq == 3200) {
 633                 dev_priv->ips.c_m = 0;
 634         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 635                 dev_priv->ips.c_m = 1;
 636         } else {
 637                 dev_priv->ips.c_m = 2;
 638         }
 639 }
 640
 641 static const struct cxsr_latency cxsr_latency_table[] = {
 642         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 643         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 644         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 645         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 646         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 647
 648         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 649         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 650         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 651         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 652         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 653
 654         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 655         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 656         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 657         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 658         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 659
 660         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 661         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 662         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 663         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 664         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 665
 666         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 667         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 668         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 669         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 670         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 671
 672         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 673         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 674         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 675         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 676         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 677 };
 678
 679 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 680                                                          int is_ddr3,
 681                                                          int fsb,
 682                                                          int mem)
 683 {
 684         const struct cxsr_latency *latency;
 685         int i;
 686
 687         if (fsb == 0 || mem == 0)
 688                 return NULL;
 689
 690         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 691                 latency = &cxsr_latency_table[i];
 692                 if (is_desktop == latency->is_desktop &&
 693                     is_ddr3 == latency->is_ddr3 &&
 694                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 695                         return latency;
 696         }
 697
 698         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 699
 700         return NULL;
 701 }
 702
 703 static void pineview_disable_cxsr(struct drm_device *dev)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706
 707         /* deactivate cxsr */
 708         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 709 }
 710
 711 /*
 712  * Latency for FIFO fetches is dependent on several factors:
 713  *   - memory configuration (speed, channels)
 714  *   - chipset
 715  *   - current MCH state
 716  * It can be fairly high in some situations, so here we assume a fairly
 717  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 718  * set this value too high, the FIFO will fetch frequently to stay full)
 719  * and power consumption (set it too low to save power and we might see
 720  * FIFO underruns and display "flicker").
 721  *
 722  * A value of 5us seems to be a good balance; safe for very low end
 723  * platforms but not overly aggressive on lower latency configs.
 724  */
 725 static const int latency_ns = 5000;
 726
 727 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         uint32_t dsparb = I915_READ(DSPARB);
 731         int size;
 732
 733         size = dsparb & 0x7f;
 734         if (plane)
 735                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 736
 737         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 738                       plane ? "B" : "A", size);
 739
 740         return size;
 741 }
 742
 743 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 744 {
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746         uint32_t dsparb = I915_READ(DSPARB);
 747         int size;
 748
 749         size = dsparb & 0x1ff;
 750         if (plane)
 751                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 752         size >>= 1; /* Convert to cachelines */
 753
 754         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 755                       plane ? "B" : "A", size);
 756
 757         return size;
 758 }
 759
 760 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         uint32_t dsparb = I915_READ(DSPARB);
 764         int size;
 765
 766         size = dsparb & 0x7f;
 767         size >>= 2; /* Convert to cachelines */
 768
 769         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 770                       plane ? "B" : "A",
 771                       size);
 772
 773         return size;
 774 }
 775
 776 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         uint32_t dsparb = I915_READ(DSPARB);
 780         int size;
 781
 782         size = dsparb & 0x7f;
 783         size >>= 1; /* Convert to cachelines */
 784
 785         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 786                       plane ? "B" : "A", size);
 787
 788         return size;
 789 }
 790
 791 /* Pineview has different values for various configs */
 792 static const struct intel_watermark_params pineview_display_wm = {
 793         PINEVIEW_DISPLAY_FIFO,
 794         PINEVIEW_MAX_WM,
 795         PINEVIEW_DFT_WM,
 796         PINEVIEW_GUARD_WM,
 797         PINEVIEW_FIFO_LINE_SIZE
 798 };
 799 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 800         PINEVIEW_DISPLAY_FIFO,
 801         PINEVIEW_MAX_WM,
 802         PINEVIEW_DFT_HPLLOFF_WM,
 803         PINEVIEW_GUARD_WM,
 804         PINEVIEW_FIFO_LINE_SIZE
 805 };
 806 static const struct intel_watermark_params pineview_cursor_wm = {
 807         PINEVIEW_CURSOR_FIFO,
 808         PINEVIEW_CURSOR_MAX_WM,
 809         PINEVIEW_CURSOR_DFT_WM,
 810         PINEVIEW_CURSOR_GUARD_WM,
 811         PINEVIEW_FIFO_LINE_SIZE,
 812 };
 813 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 814         PINEVIEW_CURSOR_FIFO,
 815         PINEVIEW_CURSOR_MAX_WM,
 816         PINEVIEW_CURSOR_DFT_WM,
 817         PINEVIEW_CURSOR_GUARD_WM,
 818         PINEVIEW_FIFO_LINE_SIZE
 819 };
 820 static const struct intel_watermark_params g4x_wm_info = {
 821         G4X_FIFO_SIZE,
 822         G4X_MAX_WM,
 823         G4X_MAX_WM,
 824         2,
 825         G4X_FIFO_LINE_SIZE,
 826 };
 827 static const struct intel_watermark_params g4x_cursor_wm_info = {
 828         I965_CURSOR_FIFO,
 829         I965_CURSOR_MAX_WM,
 830         I965_CURSOR_DFT_WM,
 831         2,
 832         G4X_FIFO_LINE_SIZE,
 833 };
 834 static const struct intel_watermark_params valleyview_wm_info = {
 835         VALLEYVIEW_FIFO_SIZE,
 836         VALLEYVIEW_MAX_WM,
 837         VALLEYVIEW_MAX_WM,
 838         2,
 839         G4X_FIFO_LINE_SIZE,
 840 };
 841 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 842         I965_CURSOR_FIFO,
 843         VALLEYVIEW_CURSOR_MAX_WM,
 844         I965_CURSOR_DFT_WM,
 845         2,
 846         G4X_FIFO_LINE_SIZE,
 847 };
 848 static const struct intel_watermark_params i965_cursor_wm_info = {
 849         I965_CURSOR_FIFO,
 850         I965_CURSOR_MAX_WM,
 851         I965_CURSOR_DFT_WM,
 852         2,
 853         I915_FIFO_LINE_SIZE,
 854 };
 855 static const struct intel_watermark_params i945_wm_info = {
 856         I945_FIFO_SIZE,
 857         I915_MAX_WM,
 858         1,
 859         2,
 860         I915_FIFO_LINE_SIZE
 861 };
 862 static const struct intel_watermark_params i915_wm_info = {
 863         I915_FIFO_SIZE,
 864         I915_MAX_WM,
 865         1,
 866         2,
 867         I915_FIFO_LINE_SIZE
 868 };
 869 static const struct intel_watermark_params i855_wm_info = {
 870         I855GM_FIFO_SIZE,
 871         I915_MAX_WM,
 872         1,
 873         2,
 874         I830_FIFO_LINE_SIZE
 875 };
 876 static const struct intel_watermark_params i830_wm_info = {
 877         I830_FIFO_SIZE,
 878         I915_MAX_WM,
 879         1,
 880         2,
 881         I830_FIFO_LINE_SIZE
 882 };
 883
 884 static const struct intel_watermark_params ironlake_display_wm_info = {
 885         ILK_DISPLAY_FIFO,
 886         ILK_DISPLAY_MAXWM,
 887         ILK_DISPLAY_DFTWM,
 888         2,
 889         ILK_FIFO_LINE_SIZE
 890 };
 891 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 892         ILK_CURSOR_FIFO,
 893         ILK_CURSOR_MAXWM,
 894         ILK_CURSOR_DFTWM,
 895         2,
 896         ILK_FIFO_LINE_SIZE
 897 };
 898 static const struct intel_watermark_params ironlake_display_srwm_info = {
 899         ILK_DISPLAY_SR_FIFO,
 900         ILK_DISPLAY_MAX_SRWM,
 901         ILK_DISPLAY_DFT_SRWM,
 902         2,
 903         ILK_FIFO_LINE_SIZE
 904 };
 905 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 906         ILK_CURSOR_SR_FIFO,
 907         ILK_CURSOR_MAX_SRWM,
 908         ILK_CURSOR_DFT_SRWM,
 909         2,
 910         ILK_FIFO_LINE_SIZE
 911 };
 912
 913 static const struct intel_watermark_params sandybridge_display_wm_info = {
 914         SNB_DISPLAY_FIFO,
 915         SNB_DISPLAY_MAXWM,
 916         SNB_DISPLAY_DFTWM,
 917         2,
 918         SNB_FIFO_LINE_SIZE
 919 };
 920 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 921         SNB_CURSOR_FIFO,
 922         SNB_CURSOR_MAXWM,
 923         SNB_CURSOR_DFTWM,
 924         2,
 925         SNB_FIFO_LINE_SIZE
 926 };
 927 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 928         SNB_DISPLAY_SR_FIFO,
 929         SNB_DISPLAY_MAX_SRWM,
 930         SNB_DISPLAY_DFT_SRWM,
 931         2,
 932         SNB_FIFO_LINE_SIZE
 933 };
 934 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 935         SNB_CURSOR_SR_FIFO,
 936         SNB_CURSOR_MAX_SRWM,
 937         SNB_CURSOR_DFT_SRWM,
 938         2,
 939         SNB_FIFO_LINE_SIZE
 940 };
 941
 942
 943 /**
 944  * intel_calculate_wm - calculate watermark level
 945  * @clock_in_khz: pixel clock
 946  * @wm: chip FIFO params
 947  * @pixel_size: display pixel size
 948  * @latency_ns: memory latency for the platform
 949  *
 950  * Calculate the watermark level (the level at which the display plane will
 951  * start fetching from memory again).  Each chip has a different display
 952  * FIFO size and allocation, so the caller needs to figure that out and pass
 953  * in the correct intel_watermark_params structure.
 954  *
 955  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 956  * on the pixel size.  When it reaches the watermark level, it'll start
 957  * fetching FIFO line sized based chunks from memory until the FIFO fills
 958  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 959  * will occur, and a display engine hang could result.
 960  */
 961 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 962                                         const struct intel_watermark_params *wm,
 963                                         int fifo_size,
 964                                         int pixel_size,
 965                                         unsigned long latency_ns)
 966 {
 967         long entries_required, wm_size;
 968
 969         /*
 970          * Note: we need to make sure we don't overflow for various clock &
 971          * latency values.
 972          * clocks go from a few thousand to several hundred thousand.
 973          * latency is usually a few thousand
 974          */
 975         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 976                 1000;
 977         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 978
 979         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 980
 981         wm_size = fifo_size - (entries_required + wm->guard_size);
 982
 983         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 984
 985         /* Don't promote wm_size to unsigned... */
 986         if (wm_size > (long)wm->max_wm)
 987                 wm_size = wm->max_wm;
 988         if (wm_size <= 0)
 989                 wm_size = wm->default_wm;
 990         return wm_size;
 991 }
 992
 993 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 994 {
 995         struct drm_crtc *crtc, *enabled = NULL;
 996
 997         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 998                 if (crtc->enabled && crtc->fb) {
 999                         if (enabled)
1000                                 return NULL;
1001                         enabled = crtc;
1002                 }
1003         }
1004
1005         return enabled;
1006 }
1007
1008 static void pineview_update_wm(struct drm_device *dev)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         struct drm_crtc *crtc;
1012         const struct cxsr_latency *latency;
1013         u32 reg;
1014         unsigned long wm;
1015
1016         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1017                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1018         if (!latency) {
1019                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1020                 pineview_disable_cxsr(dev);
1021                 return;
1022         }
1023
1024         crtc = single_enabled_crtc(dev);
1025         if (crtc) {
1026                 int clock = crtc->mode.clock;
1027                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1028
1029                 /* Display SR */
1030                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1031                                         pineview_display_wm.fifo_size,
1032                                         pixel_size, latency->display_sr);
1033                 reg = I915_READ(DSPFW1);
1034                 reg &= ~DSPFW_SR_MASK;
1035                 reg |= wm << DSPFW_SR_SHIFT;
1036                 I915_WRITE(DSPFW1, reg);
1037                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1038
1039                 /* cursor SR */
1040                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1041                                         pineview_display_wm.fifo_size,
1042                                         pixel_size, latency->cursor_sr);
1043                 reg = I915_READ(DSPFW3);
1044                 reg &= ~DSPFW_CURSOR_SR_MASK;
1045                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1046                 I915_WRITE(DSPFW3, reg);
1047
1048                 /* Display HPLL off SR */
1049                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1050                                         pineview_display_hplloff_wm.fifo_size,
1051                                         pixel_size, latency->display_hpll_disable);
1052                 reg = I915_READ(DSPFW3);
1053                 reg &= ~DSPFW_HPLL_SR_MASK;
1054                 reg |= wm & DSPFW_HPLL_SR_MASK;
1055                 I915_WRITE(DSPFW3, reg);
1056
1057                 /* cursor HPLL off SR */
1058                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1059                                         pineview_display_hplloff_wm.fifo_size,
1060                                         pixel_size, latency->cursor_hpll_disable);
1061                 reg = I915_READ(DSPFW3);
1062                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1063                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1064                 I915_WRITE(DSPFW3, reg);
1065                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1066
1067                 /* activate cxsr */
1068                 I915_WRITE(DSPFW3,
1069                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1070                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1071         } else {
1072                 pineview_disable_cxsr(dev);
1073                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1074         }
1075 }
1076
1077 static bool g4x_compute_wm0(struct drm_device *dev,
1078                             int plane,
1079                             const struct intel_watermark_params *display,
1080                             int display_latency_ns,
1081                             const struct intel_watermark_params *cursor,
1082                             int cursor_latency_ns,
1083                             int *plane_wm,
1084                             int *cursor_wm)
1085 {
1086         struct drm_crtc *crtc;
1087         int htotal, hdisplay, clock, pixel_size;
1088         int line_time_us, line_count;
1089         int entries, tlb_miss;
1090
1091         crtc = intel_get_crtc_for_plane(dev, plane);
1092         if (crtc->fb == NULL || !crtc->enabled) {
1093                 *cursor_wm = cursor->guard_size;
1094                 *plane_wm = display->guard_size;
1095                 return false;
1096         }
1097
1098         htotal = crtc->mode.htotal;
1099         hdisplay = crtc->mode.hdisplay;
1100         clock = crtc->mode.clock;
1101         pixel_size = crtc->fb->bits_per_pixel / 8;
1102
1103         /* Use the small buffer method to calculate plane watermark */
1104         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1105         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1106         if (tlb_miss > 0)
1107                 entries += tlb_miss;
1108         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1109         *plane_wm = entries + display->guard_size;
1110         if (*plane_wm > (int)display->max_wm)
1111                 *plane_wm = display->max_wm;
1112
1113         /* Use the large buffer method to calculate cursor watermark */
1114         line_time_us = ((htotal * 1000) / clock);
1115         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1116         entries = line_count * 64 * pixel_size;
1117         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1118         if (tlb_miss > 0)
1119                 entries += tlb_miss;
1120         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1121         *cursor_wm = entries + cursor->guard_size;
1122         if (*cursor_wm > (int)cursor->max_wm)
1123                 *cursor_wm = (int)cursor->max_wm;
1124
1125         return true;
1126 }
1127
1128 /*
1129  * Check the wm result.
1130  *
1131  * If any calculated watermark values is larger than the maximum value that
1132  * can be programmed into the associated watermark register, that watermark
1133  * must be disabled.
1134  */
1135 static bool g4x_check_srwm(struct drm_device *dev,
1136                            int display_wm, int cursor_wm,
1137                            const struct intel_watermark_params *display,
1138                            const struct intel_watermark_params *cursor)
1139 {
1140         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1141                       display_wm, cursor_wm);
1142
1143         if (display_wm > display->max_wm) {
1144                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1145                               display_wm, display->max_wm);
1146                 return false;
1147         }
1148
1149         if (cursor_wm > cursor->max_wm) {
1150                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1151                               cursor_wm, cursor->max_wm);
1152                 return false;
1153         }
1154
1155         if (!(display_wm || cursor_wm)) {
1156                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1157                 return false;
1158         }
1159
1160         return true;
1161 }
1162
1163 static bool g4x_compute_srwm(struct drm_device *dev,
1164                              int plane,
1165                              int latency_ns,
1166                              const struct intel_watermark_params *display,
1167                              const struct intel_watermark_params *cursor,
1168                              int *display_wm, int *cursor_wm)
1169 {
1170         struct drm_crtc *crtc;
1171         int hdisplay, htotal, pixel_size, clock;
1172         unsigned long line_time_us;
1173         int line_count, line_size;
1174         int small, large;
1175         int entries;
1176
1177         if (!latency_ns) {
1178                 *display_wm = *cursor_wm = 0;
1179                 return false;
1180         }
1181
1182         crtc = intel_get_crtc_for_plane(dev, plane);
1183         hdisplay = crtc->mode.hdisplay;
1184         htotal = crtc->mode.htotal;
1185         clock = crtc->mode.clock;
1186         pixel_size = crtc->fb->bits_per_pixel / 8;
1187
1188         line_time_us = (htotal * 1000) / clock;
1189         line_count = (latency_ns / line_time_us + 1000) / 1000;
1190         line_size = hdisplay * pixel_size;
1191
1192         /* Use the minimum of the small and large buffer method for primary */
1193         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1194         large = line_count * line_size;
1195
1196         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1197         *display_wm = entries + display->guard_size;
1198
1199         /* calculate the self-refresh watermark for display cursor */
1200         entries = line_count * pixel_size * 64;
1201         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1202         *cursor_wm = entries + cursor->guard_size;
1203
1204         return g4x_check_srwm(dev,
1205                               *display_wm, *cursor_wm,
1206                               display, cursor);
1207 }
1208
1209 static bool vlv_compute_drain_latency(struct drm_device *dev,
1210                                      int plane,
1211                                      int *plane_prec_mult,
1212                                      int *plane_dl,
1213                                      int *cursor_prec_mult,
1214                                      int *cursor_dl)
1215 {
1216         struct drm_crtc *crtc;
1217         int clock, pixel_size;
1218         int entries;
1219
1220         crtc = intel_get_crtc_for_plane(dev, plane);
1221         if (crtc->fb == NULL || !crtc->enabled)
1222                 return false;
1223
1224         clock = crtc->mode.clock;       /* VESA DOT Clock */
1225         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1226
1227         entries = (clock / 1000) * pixel_size;
1228         *plane_prec_mult = (entries > 256) ?
1229                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1230         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1231                                                      pixel_size);
1232
1233         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1234         *cursor_prec_mult = (entries > 256) ?
1235                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1236         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1237
1238         return true;
1239 }
1240
1241 /*
1242  * Update drain latency registers of memory arbiter
1243  *
1244  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1245  * to be programmed. Each plane has a drain latency multiplier and a drain
1246  * latency value.
1247  */
1248
1249 static void vlv_update_drain_latency(struct drm_device *dev)
1250 {
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1253         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1254         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1255                                                         either 16 or 32 */
1256
1257         /* For plane A, Cursor A */
1258         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1259                                       &cursor_prec_mult, &cursora_dl)) {
1260                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1261                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1262                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1263                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1264
1265                 I915_WRITE(VLV_DDL1, cursora_prec |
1266                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1267                                 planea_prec | planea_dl);
1268         }
1269
1270         /* For plane B, Cursor B */
1271         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1272                                       &cursor_prec_mult, &cursorb_dl)) {
1273                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1274                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1275                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1276                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1277
1278                 I915_WRITE(VLV_DDL2, cursorb_prec |
1279                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1280                                 planeb_prec | planeb_dl);
1281         }
1282 }
1283
1284 #define single_plane_enabled(mask) is_power_of_2(mask)
1285
1286 static void valleyview_update_wm(struct drm_device *dev)
1287 {
1288         static const int sr_latency_ns = 12000;
1289         struct drm_i915_private *dev_priv = dev->dev_private;
1290         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1291         int plane_sr, cursor_sr;
1292         unsigned int enabled = 0;
1293
1294         vlv_update_drain_latency(dev);
1295
1296         if (g4x_compute_wm0(dev, 0,
1297                             &valleyview_wm_info, latency_ns,
1298                             &valleyview_cursor_wm_info, latency_ns,
1299                             &planea_wm, &cursora_wm))
1300                 enabled |= 1;
1301
1302         if (g4x_compute_wm0(dev, 1,
1303                             &valleyview_wm_info, latency_ns,
1304                             &valleyview_cursor_wm_info, latency_ns,
1305                             &planeb_wm, &cursorb_wm))
1306                 enabled |= 2;
1307
1308         plane_sr = cursor_sr = 0;
1309         if (single_plane_enabled(enabled) &&
1310             g4x_compute_srwm(dev, ffs(enabled) - 1,
1311                              sr_latency_ns,
1312                              &valleyview_wm_info,
1313                              &valleyview_cursor_wm_info,
1314                              &plane_sr, &cursor_sr))
1315                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1316         else
1317                 I915_WRITE(FW_BLC_SELF_VLV,
1318                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1319
1320         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1321                       planea_wm, cursora_wm,
1322                       planeb_wm, cursorb_wm,
1323                       plane_sr, cursor_sr);
1324
1325         I915_WRITE(DSPFW1,
1326                    (plane_sr << DSPFW_SR_SHIFT) |
1327                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1328                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1329                    planea_wm);
1330         I915_WRITE(DSPFW2,
1331                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1332                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1333         I915_WRITE(DSPFW3,
1334                    (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1335 }
1336
1337 static void g4x_update_wm(struct drm_device *dev)
1338 {
1339         static const int sr_latency_ns = 12000;
1340         struct drm_i915_private *dev_priv = dev->dev_private;
1341         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1342         int plane_sr, cursor_sr;
1343         unsigned int enabled = 0;
1344
1345         if (g4x_compute_wm0(dev, 0,
1346                             &g4x_wm_info, latency_ns,
1347                             &g4x_cursor_wm_info, latency_ns,
1348                             &planea_wm, &cursora_wm))
1349                 enabled |= 1;
1350
1351         if (g4x_compute_wm0(dev, 1,
1352                             &g4x_wm_info, latency_ns,
1353                             &g4x_cursor_wm_info, latency_ns,
1354                             &planeb_wm, &cursorb_wm))
1355                 enabled |= 2;
1356
1357         plane_sr = cursor_sr = 0;
1358         if (single_plane_enabled(enabled) &&
1359             g4x_compute_srwm(dev, ffs(enabled) - 1,
1360                              sr_latency_ns,
1361                              &g4x_wm_info,
1362                              &g4x_cursor_wm_info,
1363                              &plane_sr, &cursor_sr))
1364                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1365         else
1366                 I915_WRITE(FW_BLC_SELF,
1367                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1368
1369         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1370                       planea_wm, cursora_wm,
1371                       planeb_wm, cursorb_wm,
1372                       plane_sr, cursor_sr);
1373
1374         I915_WRITE(DSPFW1,
1375                    (plane_sr << DSPFW_SR_SHIFT) |
1376                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1377                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1378                    planea_wm);
1379         I915_WRITE(DSPFW2,
1380                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1381                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1382         /* HPLL off in SR has some issues on G4x... disable it */
1383         I915_WRITE(DSPFW3,
1384                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1385                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1386 }
1387
1388 static void i965_update_wm(struct drm_device *dev)
1389 {
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         struct drm_crtc *crtc;
1392         int srwm = 1;
1393         int cursor_sr = 16;
1394
1395         /* Calc sr entries for one plane configs */
1396         crtc = single_enabled_crtc(dev);
1397         if (crtc) {
1398                 /* self-refresh has much higher latency */
1399                 static const int sr_latency_ns = 12000;
1400                 int clock = crtc->mode.clock;
1401                 int htotal = crtc->mode.htotal;
1402                 int hdisplay = crtc->mode.hdisplay;
1403                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1404                 unsigned long line_time_us;
1405                 int entries;
1406
1407                 line_time_us = ((htotal * 1000) / clock);
1408
1409                 /* Use ns/us then divide to preserve precision */
1410                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1411                         pixel_size * hdisplay;
1412                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1413                 srwm = I965_FIFO_SIZE - entries;
1414                 if (srwm < 0)
1415                         srwm = 1;
1416                 srwm &= 0x1ff;
1417                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1418                               entries, srwm);
1419
1420                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1421                         pixel_size * 64;
1422                 entries = DIV_ROUND_UP(entries,
1423                                           i965_cursor_wm_info.cacheline_size);
1424                 cursor_sr = i965_cursor_wm_info.fifo_size -
1425                         (entries + i965_cursor_wm_info.guard_size);
1426
1427                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1428                         cursor_sr = i965_cursor_wm_info.max_wm;
1429
1430                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1431                               "cursor %d\n", srwm, cursor_sr);
1432
1433                 if (IS_CRESTLINE(dev))
1434                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1435         } else {
1436                 /* Turn off self refresh if both pipes are enabled */
1437                 if (IS_CRESTLINE(dev))
1438                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1439                                    & ~FW_BLC_SELF_EN);
1440         }
1441
1442         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1443                       srwm);
1444
1445         /* 965 has limitations... */
1446         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1447                    (8 << 16) | (8 << 8) | (8 << 0));
1448         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1449         /* update cursor SR watermark */
1450         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1451 }
1452
1453 static void i9xx_update_wm(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456         const struct intel_watermark_params *wm_info;
1457         uint32_t fwater_lo;
1458         uint32_t fwater_hi;
1459         int cwm, srwm = 1;
1460         int fifo_size;
1461         int planea_wm, planeb_wm;
1462         struct drm_crtc *crtc, *enabled = NULL;
1463
1464         if (IS_I945GM(dev))
1465                 wm_info = &i945_wm_info;
1466         else if (!IS_GEN2(dev))
1467                 wm_info = &i915_wm_info;
1468         else
1469                 wm_info = &i855_wm_info;
1470
1471         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1472         crtc = intel_get_crtc_for_plane(dev, 0);
1473         if (crtc->enabled && crtc->fb) {
1474                 int cpp = crtc->fb->bits_per_pixel / 8;
1475                 if (IS_GEN2(dev))
1476                         cpp = 4;
1477
1478                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1479                                                wm_info, fifo_size, cpp,
1480                                                latency_ns);
1481                 enabled = crtc;
1482         } else
1483                 planea_wm = fifo_size - wm_info->guard_size;
1484
1485         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1486         crtc = intel_get_crtc_for_plane(dev, 1);
1487         if (crtc->enabled && crtc->fb) {
1488                 int cpp = crtc->fb->bits_per_pixel / 8;
1489                 if (IS_GEN2(dev))
1490                         cpp = 4;
1491
1492                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1493                                                wm_info, fifo_size, cpp,
1494                                                latency_ns);
1495                 if (enabled == NULL)
1496                         enabled = crtc;
1497                 else
1498                         enabled = NULL;
1499         } else
1500                 planeb_wm = fifo_size - wm_info->guard_size;
1501
1502         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1503
1504         /*
1505          * Overlay gets an aggressive default since video jitter is bad.
1506          */
1507         cwm = 2;
1508
1509         /* Play safe and disable self-refresh before adjusting watermarks. */
1510         if (IS_I945G(dev) || IS_I945GM(dev))
1511                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1512         else if (IS_I915GM(dev))
1513                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1514
1515         /* Calc sr entries for one plane configs */
1516         if (HAS_FW_BLC(dev) && enabled) {
1517                 /* self-refresh has much higher latency */
1518                 static const int sr_latency_ns = 6000;
1519                 int clock = enabled->mode.clock;
1520                 int htotal = enabled->mode.htotal;
1521                 int hdisplay = enabled->mode.hdisplay;
1522                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1523                 unsigned long line_time_us;
1524                 int entries;
1525
1526                 line_time_us = (htotal * 1000) / clock;
1527
1528                 /* Use ns/us then divide to preserve precision */
1529                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1530                         pixel_size * hdisplay;
1531                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1532                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1533                 srwm = wm_info->fifo_size - entries;
1534                 if (srwm < 0)
1535                         srwm = 1;
1536
1537                 if (IS_I945G(dev) || IS_I945GM(dev))
1538                         I915_WRITE(FW_BLC_SELF,
1539                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1540                 else if (IS_I915GM(dev))
1541                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1542         }
1543
1544         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1545                       planea_wm, planeb_wm, cwm, srwm);
1546
1547         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1548         fwater_hi = (cwm & 0x1f);
1549
1550         /* Set request length to 8 cachelines per fetch */
1551         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1552         fwater_hi = fwater_hi | (1 << 8);
1553
1554         I915_WRITE(FW_BLC, fwater_lo);
1555         I915_WRITE(FW_BLC2, fwater_hi);
1556
1557         if (HAS_FW_BLC(dev)) {
1558                 if (enabled) {
1559                         if (IS_I945G(dev) || IS_I945GM(dev))
1560                                 I915_WRITE(FW_BLC_SELF,
1561                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1562                         else if (IS_I915GM(dev))
1563                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1564                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1565                 } else
1566                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1567         }
1568 }
1569
1570 static void i830_update_wm(struct drm_device *dev)
1571 {
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         struct drm_crtc *crtc;
1574         uint32_t fwater_lo;
1575         int planea_wm;
1576
1577         crtc = single_enabled_crtc(dev);
1578         if (crtc == NULL)
1579                 return;
1580
1581         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1582                                        dev_priv->display.get_fifo_size(dev, 0),
1583                                        4, latency_ns);
1584         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1585         fwater_lo |= (3<<8) | planea_wm;
1586
1587         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1588
1589         I915_WRITE(FW_BLC, fwater_lo);
1590 }
1591
1592 #define ILK_LP0_PLANE_LATENCY           700
1593 #define ILK_LP0_CURSOR_LATENCY          1300
1594
1595 /*
1596  * Check the wm result.
1597  *
1598  * If any calculated watermark values is larger than the maximum value that
1599  * can be programmed into the associated watermark register, that watermark
1600  * must be disabled.
1601  */
1602 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1603                                 int fbc_wm, int display_wm, int cursor_wm,
1604                                 const struct intel_watermark_params *display,
1605                                 const struct intel_watermark_params *cursor)
1606 {
1607         struct drm_i915_private *dev_priv = dev->dev_private;
1608
1609         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1610                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1611
1612         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1613                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1614                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1615
1616                 /* fbc has it's own way to disable FBC WM */
1617                 I915_WRITE(DISP_ARB_CTL,
1618                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1619                 return false;
1620         }
1621
1622         if (display_wm > display->max_wm) {
1623                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1624                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1625                 return false;
1626         }
1627
1628         if (cursor_wm > cursor->max_wm) {
1629                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1630                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1631                 return false;
1632         }
1633
1634         if (!(fbc_wm || display_wm || cursor_wm)) {
1635                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1636                 return false;
1637         }
1638
1639         return true;
1640 }
1641
1642 /*
1643  * Compute watermark values of WM[1-3],
1644  */
1645 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1646                                   int latency_ns,
1647                                   const struct intel_watermark_params *display,
1648                                   const struct intel_watermark_params *cursor,
1649                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1650 {
1651         struct drm_crtc *crtc;
1652         unsigned long line_time_us;
1653         int hdisplay, htotal, pixel_size, clock;
1654         int line_count, line_size;
1655         int small, large;
1656         int entries;
1657
1658         if (!latency_ns) {
1659                 *fbc_wm = *display_wm = *cursor_wm = 0;
1660                 return false;
1661         }
1662
1663         crtc = intel_get_crtc_for_plane(dev, plane);
1664         hdisplay = crtc->mode.hdisplay;
1665         htotal = crtc->mode.htotal;
1666         clock = crtc->mode.clock;
1667         pixel_size = crtc->fb->bits_per_pixel / 8;
1668
1669         line_time_us = (htotal * 1000) / clock;
1670         line_count = (latency_ns / line_time_us + 1000) / 1000;
1671         line_size = hdisplay * pixel_size;
1672
1673         /* Use the minimum of the small and large buffer method for primary */
1674         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1675         large = line_count * line_size;
1676
1677         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1678         *display_wm = entries + display->guard_size;
1679
1680         /*
1681          * Spec says:
1682          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1683          */
1684         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1685
1686         /* calculate the self-refresh watermark for display cursor */
1687         entries = line_count * pixel_size * 64;
1688         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1689         *cursor_wm = entries + cursor->guard_size;
1690
1691         return ironlake_check_srwm(dev, level,
1692                                    *fbc_wm, *display_wm, *cursor_wm,
1693                                    display, cursor);
1694 }
1695
1696 static void ironlake_update_wm(struct drm_device *dev)
1697 {
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         int fbc_wm, plane_wm, cursor_wm;
1700         unsigned int enabled;
1701
1702         enabled = 0;
1703         if (g4x_compute_wm0(dev, 0,
1704                             &ironlake_display_wm_info,
1705                             ILK_LP0_PLANE_LATENCY,
1706                             &ironlake_cursor_wm_info,
1707                             ILK_LP0_CURSOR_LATENCY,
1708                             &plane_wm, &cursor_wm)) {
1709                 I915_WRITE(WM0_PIPEA_ILK,
1710                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1711                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1712                               " plane %d, " "cursor: %d\n",
1713                               plane_wm, cursor_wm);
1714                 enabled |= 1;
1715         }
1716
1717         if (g4x_compute_wm0(dev, 1,
1718                             &ironlake_display_wm_info,
1719                             ILK_LP0_PLANE_LATENCY,
1720                             &ironlake_cursor_wm_info,
1721                             ILK_LP0_CURSOR_LATENCY,
1722                             &plane_wm, &cursor_wm)) {
1723                 I915_WRITE(WM0_PIPEB_ILK,
1724                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1725                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1726                               " plane %d, cursor: %d\n",
1727                               plane_wm, cursor_wm);
1728                 enabled |= 2;
1729         }
1730
1731         /*
1732          * Calculate and update the self-refresh watermark only when one
1733          * display plane is used.
1734          */
1735         I915_WRITE(WM3_LP_ILK, 0);
1736         I915_WRITE(WM2_LP_ILK, 0);
1737         I915_WRITE(WM1_LP_ILK, 0);
1738
1739         if (!single_plane_enabled(enabled))
1740                 return;
1741         enabled = ffs(enabled) - 1;
1742
1743         /* WM1 */
1744         if (!ironlake_compute_srwm(dev, 1, enabled,
1745                                    ILK_READ_WM1_LATENCY() * 500,
1746                                    &ironlake_display_srwm_info,
1747                                    &ironlake_cursor_srwm_info,
1748                                    &fbc_wm, &plane_wm, &cursor_wm))
1749                 return;
1750
1751         I915_WRITE(WM1_LP_ILK,
1752                    WM1_LP_SR_EN |
1753                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1754                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1755                    (plane_wm << WM1_LP_SR_SHIFT) |
1756                    cursor_wm);
1757
1758         /* WM2 */
1759         if (!ironlake_compute_srwm(dev, 2, enabled,
1760                                    ILK_READ_WM2_LATENCY() * 500,
1761                                    &ironlake_display_srwm_info,
1762                                    &ironlake_cursor_srwm_info,
1763                                    &fbc_wm, &plane_wm, &cursor_wm))
1764                 return;
1765
1766         I915_WRITE(WM2_LP_ILK,
1767                    WM2_LP_EN |
1768                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1769                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1770                    (plane_wm << WM1_LP_SR_SHIFT) |
1771                    cursor_wm);
1772
1773         /*
1774          * WM3 is unsupported on ILK, probably because we don't have latency
1775          * data for that power state
1776          */
1777 }
1778
1779 static void sandybridge_update_wm(struct drm_device *dev)
1780 {
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1783         u32 val;
1784         int fbc_wm, plane_wm, cursor_wm;
1785         unsigned int enabled;
1786
1787         enabled = 0;
1788         if (g4x_compute_wm0(dev, 0,
1789                             &sandybridge_display_wm_info, latency,
1790                             &sandybridge_cursor_wm_info, latency,
1791                             &plane_wm, &cursor_wm)) {
1792                 val = I915_READ(WM0_PIPEA_ILK);
1793                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1794                 I915_WRITE(WM0_PIPEA_ILK, val |
1795                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1796                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1797                               " plane %d, " "cursor: %d\n",
1798                               plane_wm, cursor_wm);
1799                 enabled |= 1;
1800         }
1801
1802         if (g4x_compute_wm0(dev, 1,
1803                             &sandybridge_display_wm_info, latency,
1804                             &sandybridge_cursor_wm_info, latency,
1805                             &plane_wm, &cursor_wm)) {
1806                 val = I915_READ(WM0_PIPEB_ILK);
1807                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1808                 I915_WRITE(WM0_PIPEB_ILK, val |
1809                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1810                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1811                               " plane %d, cursor: %d\n",
1812                               plane_wm, cursor_wm);
1813                 enabled |= 2;
1814         }
1815
1816         if ((dev_priv->num_pipe == 3) &&
1817             g4x_compute_wm0(dev, 2,
1818                             &sandybridge_display_wm_info, latency,
1819                             &sandybridge_cursor_wm_info, latency,
1820                             &plane_wm, &cursor_wm)) {
1821                 val = I915_READ(WM0_PIPEC_IVB);
1822                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1823                 I915_WRITE(WM0_PIPEC_IVB, val |
1824                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1825                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1826                               " plane %d, cursor: %d\n",
1827                               plane_wm, cursor_wm);
1828                 enabled |= 3;
1829         }
1830
1831         /*
1832          * Calculate and update the self-refresh watermark only when one
1833          * display plane is used.
1834          *
1835          * SNB support 3 levels of watermark.
1836          *
1837          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1838          * and disabled in the descending order
1839          *
1840          */
1841         I915_WRITE(WM3_LP_ILK, 0);
1842         I915_WRITE(WM2_LP_ILK, 0);
1843         I915_WRITE(WM1_LP_ILK, 0);
1844
1845         if (!single_plane_enabled(enabled) ||
1846             dev_priv->sprite_scaling_enabled)
1847                 return;
1848         enabled = ffs(enabled) - 1;
1849
1850         /* WM1 */
1851         if (!ironlake_compute_srwm(dev, 1, enabled,
1852                                    SNB_READ_WM1_LATENCY() * 500,
1853                                    &sandybridge_display_srwm_info,
1854                                    &sandybridge_cursor_srwm_info,
1855                                    &fbc_wm, &plane_wm, &cursor_wm))
1856                 return;
1857
1858         I915_WRITE(WM1_LP_ILK,
1859                    WM1_LP_SR_EN |
1860                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1861                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1862                    (plane_wm << WM1_LP_SR_SHIFT) |
1863                    cursor_wm);
1864
1865         /* WM2 */
1866         if (!ironlake_compute_srwm(dev, 2, enabled,
1867                                    SNB_READ_WM2_LATENCY() * 500,
1868                                    &sandybridge_display_srwm_info,
1869                                    &sandybridge_cursor_srwm_info,
1870                                    &fbc_wm, &plane_wm, &cursor_wm))
1871                 return;
1872
1873         I915_WRITE(WM2_LP_ILK,
1874                    WM2_LP_EN |
1875                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1876                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1877                    (plane_wm << WM1_LP_SR_SHIFT) |
1878                    cursor_wm);
1879
1880         /* WM3 */
1881         if (!ironlake_compute_srwm(dev, 3, enabled,
1882                                    SNB_READ_WM3_LATENCY() * 500,
1883                                    &sandybridge_display_srwm_info,
1884                                    &sandybridge_cursor_srwm_info,
1885                                    &fbc_wm, &plane_wm, &cursor_wm))
1886                 return;
1887
1888         I915_WRITE(WM3_LP_ILK,
1889                    WM3_LP_EN |
1890                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1891                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1892                    (plane_wm << WM1_LP_SR_SHIFT) |
1893                    cursor_wm);
1894 }
1895
1896 static void
1897 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1898                                  struct drm_display_mode *mode)
1899 {
1900         struct drm_i915_private *dev_priv = dev->dev_private;
1901         u32 temp;
1902
1903         temp = I915_READ(PIPE_WM_LINETIME(pipe));
1904         temp &= ~PIPE_WM_LINETIME_MASK;
1905
1906         /* The WM are computed with base on how long it takes to fill a single
1907          * row at the given clock rate, multiplied by 8.
1908          * */
1909         temp |= PIPE_WM_LINETIME_TIME(
1910                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1911
1912         /* IPS watermarks are only used by pipe A, and are ignored by
1913          * pipes B and C.  They are calculated similarly to the common
1914          * linetime values, except that we are using CD clock frequency
1915          * in MHz instead of pixel rate for the division.
1916          *
1917          * This is a placeholder for the IPS watermark calculation code.
1918          */
1919
1920         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1921 }
1922
1923 static bool
1924 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1925                               uint32_t sprite_width, int pixel_size,
1926                               const struct intel_watermark_params *display,
1927                               int display_latency_ns, int *sprite_wm)
1928 {
1929         struct drm_crtc *crtc;
1930         int clock;
1931         int entries, tlb_miss;
1932
1933         crtc = intel_get_crtc_for_plane(dev, plane);
1934         if (crtc->fb == NULL || !crtc->enabled) {
1935                 *sprite_wm = display->guard_size;
1936                 return false;
1937         }
1938
1939         clock = crtc->mode.clock;
1940
1941         /* Use the small buffer method to calculate the sprite watermark */
1942         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1943         tlb_miss = display->fifo_size*display->cacheline_size -
1944                 sprite_width * 8;
1945         if (tlb_miss > 0)
1946                 entries += tlb_miss;
1947         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1948         *sprite_wm = entries + display->guard_size;
1949         if (*sprite_wm > (int)display->max_wm)
1950                 *sprite_wm = display->max_wm;
1951
1952         return true;
1953 }
1954
1955 static bool
1956 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1957                                 uint32_t sprite_width, int pixel_size,
1958                                 const struct intel_watermark_params *display,
1959                                 int latency_ns, int *sprite_wm)
1960 {
1961         struct drm_crtc *crtc;
1962         unsigned long line_time_us;
1963         int clock;
1964         int line_count, line_size;
1965         int small, large;
1966         int entries;
1967
1968         if (!latency_ns) {
1969                 *sprite_wm = 0;
1970                 return false;
1971         }
1972
1973         crtc = intel_get_crtc_for_plane(dev, plane);
1974         clock = crtc->mode.clock;
1975         if (!clock) {
1976                 *sprite_wm = 0;
1977                 return false;
1978         }
1979
1980         line_time_us = (sprite_width * 1000) / clock;
1981         if (!line_time_us) {
1982                 *sprite_wm = 0;
1983                 return false;
1984         }
1985
1986         line_count = (latency_ns / line_time_us + 1000) / 1000;
1987         line_size = sprite_width * pixel_size;
1988
1989         /* Use the minimum of the small and large buffer method for primary */
1990         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1991         large = line_count * line_size;
1992
1993         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1994         *sprite_wm = entries + display->guard_size;
1995
1996         return *sprite_wm > 0x3ff ? false : true;
1997 }
1998
1999 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2000                                          uint32_t sprite_width, int pixel_size)
2001 {
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2004         u32 val;
2005         int sprite_wm, reg;
2006         int ret;
2007
2008         switch (pipe) {
2009         case 0:
2010                 reg = WM0_PIPEA_ILK;
2011                 break;
2012         case 1:
2013                 reg = WM0_PIPEB_ILK;
2014                 break;
2015         case 2:
2016                 reg = WM0_PIPEC_IVB;
2017                 break;
2018         default:
2019                 return; /* bad pipe */
2020         }
2021
2022         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2023                                             &sandybridge_display_wm_info,
2024                                             latency, &sprite_wm);
2025         if (!ret) {
2026                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2027                               pipe);
2028                 return;
2029         }
2030
2031         val = I915_READ(reg);
2032         val &= ~WM0_PIPE_SPRITE_MASK;
2033         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2034         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2035
2036
2037         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2038                                               pixel_size,
2039                                               &sandybridge_display_srwm_info,
2040                                               SNB_READ_WM1_LATENCY() * 500,
2041                                               &sprite_wm);
2042         if (!ret) {
2043                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2044                               pipe);
2045                 return;
2046         }
2047         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2048
2049         /* Only IVB has two more LP watermarks for sprite */
2050         if (!IS_IVYBRIDGE(dev))
2051                 return;
2052
2053         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2054                                               pixel_size,
2055                                               &sandybridge_display_srwm_info,
2056                                               SNB_READ_WM2_LATENCY() * 500,
2057                                               &sprite_wm);
2058         if (!ret) {
2059                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2060                               pipe);
2061                 return;
2062         }
2063         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2064
2065         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2066                                               pixel_size,
2067                                               &sandybridge_display_srwm_info,
2068                                               SNB_READ_WM3_LATENCY() * 500,
2069                                               &sprite_wm);
2070         if (!ret) {
2071                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2072                               pipe);
2073                 return;
2074         }
2075         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2076 }
2077
2078 /**
2079  * intel_update_watermarks - update FIFO watermark values based on current modes
2080  *
2081  * Calculate watermark values for the various WM regs based on current mode
2082  * and plane configuration.
2083  *
2084  * There are several cases to deal with here:
2085  *   - normal (i.e. non-self-refresh)
2086  *   - self-refresh (SR) mode
2087  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2088  *   - lines are small relative to FIFO size (buffer can hold more than 2
2089  *     lines), so need to account for TLB latency
2090  *
2091  *   The normal calculation is:
2092  *     watermark = dotclock * bytes per pixel * latency
2093  *   where latency is platform & configuration dependent (we assume pessimal
2094  *   values here).
2095  *
2096  *   The SR calculation is:
2097  *     watermark = (trunc(latency/line time)+1) * surface width *
2098  *       bytes per pixel
2099  *   where
2100  *     line time = htotal / dotclock
2101  *     surface width = hdisplay for normal plane and 64 for cursor
2102  *   and latency is assumed to be high, as above.
2103  *
2104  * The final value programmed to the register should always be rounded up,
2105  * and include an extra 2 entries to account for clock crossings.
2106  *
2107  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2108  * to set the non-SR watermarks to 8.
2109  */
2110 void intel_update_watermarks(struct drm_device *dev)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114         if (dev_priv->display.update_wm)
2115                 dev_priv->display.update_wm(dev);
2116 }
2117
2118 void intel_update_linetime_watermarks(struct drm_device *dev,
2119                 int pipe, struct drm_display_mode *mode)
2120 {
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122
2123         if (dev_priv->display.update_linetime_wm)
2124                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2125 }
2126
2127 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2128                                     uint32_t sprite_width, int pixel_size)
2129 {
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131
2132         if (dev_priv->display.update_sprite_wm)
2133                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2134                                                    pixel_size);
2135 }
2136
2137 static struct drm_i915_gem_object *
2138 intel_alloc_context_page(struct drm_device *dev)
2139 {
2140         struct drm_i915_gem_object *ctx;
2141         int ret;
2142
2143         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2144
2145         ctx = i915_gem_alloc_object(dev, 4096);
2146         if (!ctx) {
2147                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2148                 return NULL;
2149         }
2150
2151         ret = i915_gem_object_pin(ctx, 4096, true, false);
2152         if (ret) {
2153                 DRM_ERROR("failed to pin power context: %d\n", ret);
2154                 goto err_unref;
2155         }
2156
2157         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2158         if (ret) {
2159                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2160                 goto err_unpin;
2161         }
2162
2163         return ctx;
2164
2165 err_unpin:
2166         i915_gem_object_unpin(ctx);
2167 err_unref:
2168         drm_gem_object_unreference(&ctx->base);
2169         mutex_unlock(&dev->struct_mutex);
2170         return NULL;
2171 }
2172
2173 /**
2174  * Lock protecting IPS related data structures
2175  */
2176 DEFINE_SPINLOCK(mchdev_lock);
2177
2178 /* Global for IPS driver to get at the current i915 device. Protected by
2179  * mchdev_lock. */
2180 static struct drm_i915_private *i915_mch_dev;
2181
2182 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2183 {
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         u16 rgvswctl;
2186
2187         assert_spin_locked(&mchdev_lock);
2188
2189         rgvswctl = I915_READ16(MEMSWCTL);
2190         if (rgvswctl & MEMCTL_CMD_STS) {
2191                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2192                 return false; /* still busy with another command */
2193         }
2194
2195         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2196                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2197         I915_WRITE16(MEMSWCTL, rgvswctl);
2198         POSTING_READ16(MEMSWCTL);
2199
2200         rgvswctl |= MEMCTL_CMD_STS;
2201         I915_WRITE16(MEMSWCTL, rgvswctl);
2202
2203         return true;
2204 }
2205
2206 static void ironlake_enable_drps(struct drm_device *dev)
2207 {
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209         u32 rgvmodectl = I915_READ(MEMMODECTL);
2210         u8 fmax, fmin, fstart, vstart;
2211
2212         spin_lock_irq(&mchdev_lock);
2213
2214         /* Enable temp reporting */
2215         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2216         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2217
2218         /* 100ms RC evaluation intervals */
2219         I915_WRITE(RCUPEI, 100000);
2220         I915_WRITE(RCDNEI, 100000);
2221
2222         /* Set max/min thresholds to 90ms and 80ms respectively */
2223         I915_WRITE(RCBMAXAVG, 90000);
2224         I915_WRITE(RCBMINAVG, 80000);
2225
2226         I915_WRITE(MEMIHYST, 1);
2227
2228         /* Set up min, max, and cur for interrupt handling */
2229         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2230         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2231         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2232                 MEMMODE_FSTART_SHIFT;
2233
2234         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2235                 PXVFREQ_PX_SHIFT;
2236
2237         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2238         dev_priv->ips.fstart = fstart;
2239
2240         dev_priv->ips.max_delay = fstart;
2241         dev_priv->ips.min_delay = fmin;
2242         dev_priv->ips.cur_delay = fstart;
2243
2244         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2245                          fmax, fmin, fstart);
2246
2247         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2248
2249         /*
2250          * Interrupts will be enabled in ironlake_irq_postinstall
2251          */
2252
2253         I915_WRITE(VIDSTART, vstart);
2254         POSTING_READ(VIDSTART);
2255
2256         rgvmodectl |= MEMMODE_SWMODE_EN;
2257         I915_WRITE(MEMMODECTL, rgvmodectl);
2258
2259         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2260                 DRM_ERROR("stuck trying to change perf mode\n");
2261         mdelay(1);
2262
2263         ironlake_set_drps(dev, fstart);
2264
2265         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2266                 I915_READ(0x112e0);
2267         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2268         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2269         getrawmonotonic(&dev_priv->ips.last_time2);
2270
2271         spin_unlock_irq(&mchdev_lock);
2272 }
2273
2274 static void ironlake_disable_drps(struct drm_device *dev)
2275 {
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277         u16 rgvswctl;
2278
2279         spin_lock_irq(&mchdev_lock);
2280
2281         rgvswctl = I915_READ16(MEMSWCTL);
2282
2283         /* Ack interrupts, disable EFC interrupt */
2284         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2285         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2286         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2287         I915_WRITE(DEIIR, DE_PCU_EVENT);
2288         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2289
2290         /* Go back to the starting frequency */
2291         ironlake_set_drps(dev, dev_priv->ips.fstart);
2292         mdelay(1);
2293         rgvswctl |= MEMCTL_CMD_STS;
2294         I915_WRITE(MEMSWCTL, rgvswctl);
2295         mdelay(1);
2296
2297         spin_unlock_irq(&mchdev_lock);
2298 }
2299
2300 /* There's a funny hw issue where the hw returns all 0 when reading from
2301  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2302  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2303  * all limits and the gpu stuck at whatever frequency it is at atm).
2304  */
2305 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2306 {
2307         u32 limits;
2308
2309         limits = 0;
2310
2311         if (*val >= dev_priv->rps.max_delay)
2312                 *val = dev_priv->rps.max_delay;
2313         limits |= dev_priv->rps.max_delay << 24;
2314
2315         /* Only set the down limit when we've reached the lowest level to avoid
2316          * getting more interrupts, otherwise leave this clear. This prevents a
2317          * race in the hw when coming out of rc6: There's a tiny window where
2318          * the hw runs at the minimal clock before selecting the desired
2319          * frequency, if the down threshold expires in that window we will not
2320          * receive a down interrupt. */
2321         if (*val <= dev_priv->rps.min_delay) {
2322                 *val = dev_priv->rps.min_delay;
2323                 limits |= dev_priv->rps.min_delay << 16;
2324         }
2325
2326         return limits;
2327 }
2328
2329 void gen6_set_rps(struct drm_device *dev, u8 val)
2330 {
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         u32 limits = gen6_rps_limits(dev_priv, &val);
2333
2334         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2335         WARN_ON(val > dev_priv->rps.max_delay);
2336         WARN_ON(val < dev_priv->rps.min_delay);
2337
2338         if (val == dev_priv->rps.cur_delay)
2339                 return;
2340
2341         I915_WRITE(GEN6_RPNSWREQ,
2342                    GEN6_FREQUENCY(val) |
2343                    GEN6_OFFSET(0) |
2344                    GEN6_AGGRESSIVE_TURBO);
2345
2346         /* Make sure we continue to get interrupts
2347          * until we hit the minimum or maximum frequencies.
2348          */
2349         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2350
2351         POSTING_READ(GEN6_RPNSWREQ);
2352
2353         dev_priv->rps.cur_delay = val;
2354
2355         trace_intel_gpu_freq_change(val * 50);
2356 }
2357
2358 static void gen6_disable_rps(struct drm_device *dev)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361
2362         I915_WRITE(GEN6_RC_CONTROL, 0);
2363         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2364         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2365         I915_WRITE(GEN6_PMIER, 0);
2366         /* Complete PM interrupt masking here doesn't race with the rps work
2367          * item again unmasking PM interrupts because that is using a different
2368          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2369          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2370
2371         spin_lock_irq(&dev_priv->rps.lock);
2372         dev_priv->rps.pm_iir = 0;
2373         spin_unlock_irq(&dev_priv->rps.lock);
2374
2375         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2376 }
2377
2378 int intel_enable_rc6(const struct drm_device *dev)
2379 {
2380         /* Respect the kernel parameter if it is set */
2381         if (i915_enable_rc6 >= 0)
2382                 return i915_enable_rc6;
2383
2384         if (INTEL_INFO(dev)->gen == 5) {
2385 #ifdef CONFIG_INTEL_IOMMU
2386                 /* Disable rc6 on ilk if VT-d is on. */
2387                 if (intel_iommu_gfx_mapped)
2388                         return false;
2389 #endif
2390                 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2391                 return INTEL_RC6_ENABLE;
2392         }
2393
2394         if (IS_HASWELL(dev)) {
2395                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2396                 return INTEL_RC6_ENABLE;
2397         }
2398
2399         /* snb/ivb have more than one rc6 state. */
2400         if (INTEL_INFO(dev)->gen == 6) {
2401                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2402                 return INTEL_RC6_ENABLE;
2403         }
2404
2405         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2406         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2407 }
2408
2409 static void gen6_enable_rps(struct drm_device *dev)
2410 {
2411         struct drm_i915_private *dev_priv = dev->dev_private;
2412         struct intel_ring_buffer *ring;
2413         u32 rp_state_cap;
2414         u32 gt_perf_status;
2415         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2416         u32 gtfifodbg;
2417         int rc6_mode;
2418         int i, ret;
2419
2420         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2421
2422         /* Here begins a magic sequence of register writes to enable
2423          * auto-downclocking.
2424          *
2425          * Perhaps there might be some value in exposing these to
2426          * userspace...
2427          */
2428         I915_WRITE(GEN6_RC_STATE, 0);
2429
2430         /* Clear the DBG now so we don't confuse earlier errors */
2431         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2432                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2433                 I915_WRITE(GTFIFODBG, gtfifodbg);
2434         }
2435
2436         gen6_gt_force_wake_get(dev_priv);
2437
2438         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2439         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2440
2441         /* In units of 100MHz */
2442         dev_priv->rps.max_delay = rp_state_cap & 0xff;
2443         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2444         dev_priv->rps.cur_delay = 0;
2445
2446         /* disable the counters and set deterministic thresholds */
2447         I915_WRITE(GEN6_RC_CONTROL, 0);
2448
2449         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2450         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2451         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2452         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2453         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2454
2455         for_each_ring(ring, dev_priv, i)
2456                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2457
2458         I915_WRITE(GEN6_RC_SLEEP, 0);
2459         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2460         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2461         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2462         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2463
2464         /* Check if we are enabling RC6 */
2465         rc6_mode = intel_enable_rc6(dev_priv->dev);
2466         if (rc6_mode & INTEL_RC6_ENABLE)
2467                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2468
2469         /* We don't use those on Haswell */
2470         if (!IS_HASWELL(dev)) {
2471                 if (rc6_mode & INTEL_RC6p_ENABLE)
2472                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2473
2474                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2475                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2476         }
2477
2478         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2479                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2480                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2481                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2482
2483         I915_WRITE(GEN6_RC_CONTROL,
2484                    rc6_mask |
2485                    GEN6_RC_CTL_EI_MODE(1) |
2486                    GEN6_RC_CTL_HW_ENABLE);
2487
2488         I915_WRITE(GEN6_RPNSWREQ,
2489                    GEN6_FREQUENCY(10) |
2490                    GEN6_OFFSET(0) |
2491                    GEN6_AGGRESSIVE_TURBO);
2492         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2493                    GEN6_FREQUENCY(12));
2494
2495         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2496         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2497                    dev_priv->rps.max_delay << 24 |
2498                    dev_priv->rps.min_delay << 16);
2499
2500         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2501         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2502         I915_WRITE(GEN6_RP_UP_EI, 66000);
2503         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2504
2505         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2506         I915_WRITE(GEN6_RP_CONTROL,
2507                    GEN6_RP_MEDIA_TURBO |
2508                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2509                    GEN6_RP_MEDIA_IS_GFX |
2510                    GEN6_RP_ENABLE |
2511                    GEN6_RP_UP_BUSY_AVG |
2512                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2513
2514         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2515         if (!ret) {
2516                 pcu_mbox = 0;
2517                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2518                 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2519                         dev_priv->rps.max_delay = pcu_mbox & 0xff;
2520                         DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2521                 }
2522         } else {
2523                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2524         }
2525
2526         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2527
2528         /* requires MSI enabled */
2529         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2530         spin_lock_irq(&dev_priv->rps.lock);
2531         WARN_ON(dev_priv->rps.pm_iir != 0);
2532         I915_WRITE(GEN6_PMIMR, 0);
2533         spin_unlock_irq(&dev_priv->rps.lock);
2534         /* enable all PM interrupts */
2535         I915_WRITE(GEN6_PMINTRMSK, 0);
2536
2537         rc6vids = 0;
2538         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2539         if (IS_GEN6(dev) && ret) {
2540                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2541         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2542                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2543                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2544                 rc6vids &= 0xffff00;
2545                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2546                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2547                 if (ret)
2548                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2549         }
2550
2551         gen6_gt_force_wake_put(dev_priv);
2552 }
2553
2554 static void gen6_update_ring_freq(struct drm_device *dev)
2555 {
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         int min_freq = 15;
2558         int gpu_freq;
2559         unsigned int ia_freq, max_ia_freq;
2560         int scaling_factor = 180;
2561
2562         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2563
2564         max_ia_freq = cpufreq_quick_get_max(0);
2565         /*
2566          * Default to measured freq if none found, PCU will ensure we don't go
2567          * over
2568          */
2569         if (!max_ia_freq)
2570                 max_ia_freq = tsc_khz;
2571
2572         /* Convert from kHz to MHz */
2573         max_ia_freq /= 1000;
2574
2575         /*
2576          * For each potential GPU frequency, load a ring frequency we'd like
2577          * to use for memory access.  We do this by specifying the IA frequency
2578          * the PCU should use as a reference to determine the ring frequency.
2579          */
2580         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2581              gpu_freq--) {
2582                 int diff = dev_priv->rps.max_delay - gpu_freq;
2583
2584                 /*
2585                  * For GPU frequencies less than 750MHz, just use the lowest
2586                  * ring freq.
2587                  */
2588                 if (gpu_freq < min_freq)
2589                         ia_freq = 800;
2590                 else
2591                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2592                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2593                 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2594
2595                 sandybridge_pcode_write(dev_priv,
2596                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2597                                         ia_freq | gpu_freq);
2598         }
2599 }
2600
2601 void ironlake_teardown_rc6(struct drm_device *dev)
2602 {
2603         struct drm_i915_private *dev_priv = dev->dev_private;
2604
2605         if (dev_priv->ips.renderctx) {
2606                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2607                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2608                 dev_priv->ips.renderctx = NULL;
2609         }
2610
2611         if (dev_priv->ips.pwrctx) {
2612                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2613                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2614                 dev_priv->ips.pwrctx = NULL;
2615         }
2616 }
2617
2618 static void ironlake_disable_rc6(struct drm_device *dev)
2619 {
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621
2622         if (I915_READ(PWRCTXA)) {
2623                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2624                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2625                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2626                          50);
2627
2628                 I915_WRITE(PWRCTXA, 0);
2629                 POSTING_READ(PWRCTXA);
2630
2631                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2632                 POSTING_READ(RSTDBYCTL);
2633         }
2634 }
2635
2636 static int ironlake_setup_rc6(struct drm_device *dev)
2637 {
2638         struct drm_i915_private *dev_priv = dev->dev_private;
2639
2640         if (dev_priv->ips.renderctx == NULL)
2641                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2642         if (!dev_priv->ips.renderctx)
2643                 return -ENOMEM;
2644
2645         if (dev_priv->ips.pwrctx == NULL)
2646                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2647         if (!dev_priv->ips.pwrctx) {
2648                 ironlake_teardown_rc6(dev);
2649                 return -ENOMEM;
2650         }
2651
2652         return 0;
2653 }
2654
2655 static void ironlake_enable_rc6(struct drm_device *dev)
2656 {
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2659         bool was_interruptible;
2660         int ret;
2661
2662         /* rc6 disabled by default due to repeated reports of hanging during
2663          * boot and resume.
2664          */
2665         if (!intel_enable_rc6(dev))
2666                 return;
2667
2668         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2669
2670         ret = ironlake_setup_rc6(dev);
2671         if (ret)
2672                 return;
2673
2674         was_interruptible = dev_priv->mm.interruptible;
2675         dev_priv->mm.interruptible = false;
2676
2677         /*
2678          * GPU can automatically power down the render unit if given a page
2679          * to save state.
2680          */
2681         ret = intel_ring_begin(ring, 6);
2682         if (ret) {
2683                 ironlake_teardown_rc6(dev);
2684                 dev_priv->mm.interruptible = was_interruptible;
2685                 return;
2686         }
2687
2688         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2689         intel_ring_emit(ring, MI_SET_CONTEXT);
2690         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2691                         MI_MM_SPACE_GTT |
2692                         MI_SAVE_EXT_STATE_EN |
2693                         MI_RESTORE_EXT_STATE_EN |
2694                         MI_RESTORE_INHIBIT);
2695         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2696         intel_ring_emit(ring, MI_NOOP);
2697         intel_ring_emit(ring, MI_FLUSH);
2698         intel_ring_advance(ring);
2699
2700         /*
2701          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2702          * does an implicit flush, combined with MI_FLUSH above, it should be
2703          * safe to assume that renderctx is valid
2704          */
2705         ret = intel_ring_idle(ring);
2706         dev_priv->mm.interruptible = was_interruptible;
2707         if (ret) {
2708                 DRM_ERROR("failed to enable ironlake power power savings\n");
2709                 ironlake_teardown_rc6(dev);
2710                 return;
2711         }
2712
2713         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2714         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2715 }
2716
2717 static unsigned long intel_pxfreq(u32 vidfreq)
2718 {
2719         unsigned long freq;
2720         int div = (vidfreq & 0x3f0000) >> 16;
2721         int post = (vidfreq & 0x3000) >> 12;
2722         int pre = (vidfreq & 0x7);
2723
2724         if (!pre)
2725                 return 0;
2726
2727         freq = ((div * 133333) / ((1<<post) * pre));
2728
2729         return freq;
2730 }
2731
2732 static const struct cparams {
2733         u16 i;
2734         u16 t;
2735         u16 m;
2736         u16 c;
2737 } cparams[] = {
2738         { 1, 1333, 301, 28664 },
2739         { 1, 1066, 294, 24460 },
2740         { 1, 800, 294, 25192 },
2741         { 0, 1333, 276, 27605 },
2742         { 0, 1066, 276, 27605 },
2743         { 0, 800, 231, 23784 },
2744 };
2745
2746 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2747 {
2748         u64 total_count, diff, ret;
2749         u32 count1, count2, count3, m = 0, c = 0;
2750         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2751         int i;
2752
2753         assert_spin_locked(&mchdev_lock);
2754
2755         diff1 = now - dev_priv->ips.last_time1;
2756
2757         /* Prevent division-by-zero if we are asking too fast.
2758          * Also, we don't get interesting results if we are polling
2759          * faster than once in 10ms, so just return the saved value
2760          * in such cases.
2761          */
2762         if (diff1 <= 10)
2763                 return dev_priv->ips.chipset_power;
2764
2765         count1 = I915_READ(DMIEC);
2766         count2 = I915_READ(DDREC);
2767         count3 = I915_READ(CSIEC);
2768
2769         total_count = count1 + count2 + count3;
2770
2771         /* FIXME: handle per-counter overflow */
2772         if (total_count < dev_priv->ips.last_count1) {
2773                 diff = ~0UL - dev_priv->ips.last_count1;
2774                 diff += total_count;
2775         } else {
2776                 diff = total_count - dev_priv->ips.last_count1;
2777         }
2778
2779         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2780                 if (cparams[i].i == dev_priv->ips.c_m &&
2781                     cparams[i].t == dev_priv->ips.r_t) {
2782                         m = cparams[i].m;
2783                         c = cparams[i].c;
2784                         break;
2785                 }
2786         }
2787
2788         diff = div_u64(diff, diff1);
2789         ret = ((m * diff) + c);
2790         ret = div_u64(ret, 10);
2791
2792         dev_priv->ips.last_count1 = total_count;
2793         dev_priv->ips.last_time1 = now;
2794
2795         dev_priv->ips.chipset_power = ret;
2796
2797         return ret;
2798 }
2799
2800 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2801 {
2802         unsigned long val;
2803
2804         if (dev_priv->info->gen != 5)
2805                 return 0;
2806
2807         spin_lock_irq(&mchdev_lock);
2808
2809         val = __i915_chipset_val(dev_priv);
2810
2811         spin_unlock_irq(&mchdev_lock);
2812
2813         return val;
2814 }
2815
2816 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2817 {
2818         unsigned long m, x, b;
2819         u32 tsfs;
2820
2821         tsfs = I915_READ(TSFS);
2822
2823         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2824         x = I915_READ8(TR1);
2825
2826         b = tsfs & TSFS_INTR_MASK;
2827
2828         return ((m * x) / 127) - b;
2829 }
2830
2831 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2832 {
2833         static const struct v_table {
2834                 u16 vd; /* in .1 mil */
2835                 u16 vm; /* in .1 mil */
2836         } v_table[] = {
2837                 { 0, 0, },
2838                 { 375, 0, },
2839                 { 500, 0, },
2840                 { 625, 0, },
2841                 { 750, 0, },
2842                 { 875, 0, },
2843                 { 1000, 0, },
2844                 { 1125, 0, },
2845                 { 4125, 3000, },
2846                 { 4125, 3000, },
2847                 { 4125, 3000, },
2848                 { 4125, 3000, },
2849                 { 4125, 3000, },
2850                 { 4125, 3000, },
2851                 { 4125, 3000, },
2852                 { 4125, 3000, },
2853                 { 4125, 3000, },
2854                 { 4125, 3000, },
2855                 { 4125, 3000, },
2856                 { 4125, 3000, },
2857                 { 4125, 3000, },
2858                 { 4125, 3000, },
2859                 { 4125, 3000, },
2860                 { 4125, 3000, },
2861                 { 4125, 3000, },
2862                 { 4125, 3000, },
2863                 { 4125, 3000, },
2864                 { 4125, 3000, },
2865                 { 4125, 3000, },
2866                 { 4125, 3000, },
2867                 { 4125, 3000, },
2868                 { 4125, 3000, },
2869                 { 4250, 3125, },
2870                 { 4375, 3250, },
2871                 { 4500, 3375, },
2872                 { 4625, 3500, },
2873                 { 4750, 3625, },
2874                 { 4875, 3750, },
2875                 { 5000, 3875, },
2876                 { 5125, 4000, },
2877                 { 5250, 4125, },
2878                 { 5375, 4250, },
2879                 { 5500, 4375, },
2880                 { 5625, 4500, },
2881                 { 5750, 4625, },
2882                 { 5875, 4750, },
2883                 { 6000, 4875, },
2884                 { 6125, 5000, },
2885                 { 6250, 5125, },
2886                 { 6375, 5250, },
2887                 { 6500, 5375, },
2888                 { 6625, 5500, },
2889                 { 6750, 5625, },
2890                 { 6875, 5750, },
2891                 { 7000, 5875, },
2892                 { 7125, 6000, },
2893                 { 7250, 6125, },
2894                 { 7375, 6250, },
2895                 { 7500, 6375, },
2896                 { 7625, 6500, },
2897                 { 7750, 6625, },
2898                 { 7875, 6750, },
2899                 { 8000, 6875, },
2900                 { 8125, 7000, },
2901                 { 8250, 7125, },
2902                 { 8375, 7250, },
2903                 { 8500, 7375, },
2904                 { 8625, 7500, },
2905                 { 8750, 7625, },
2906                 { 8875, 7750, },
2907                 { 9000, 7875, },
2908                 { 9125, 8000, },
2909                 { 9250, 8125, },
2910                 { 9375, 8250, },
2911                 { 9500, 8375, },
2912                 { 9625, 8500, },
2913                 { 9750, 8625, },
2914                 { 9875, 8750, },
2915                 { 10000, 8875, },
2916                 { 10125, 9000, },
2917                 { 10250, 9125, },
2918                 { 10375, 9250, },
2919                 { 10500, 9375, },
2920                 { 10625, 9500, },
2921                 { 10750, 9625, },
2922                 { 10875, 9750, },
2923                 { 11000, 9875, },
2924                 { 11125, 10000, },
2925                 { 11250, 10125, },
2926                 { 11375, 10250, },
2927                 { 11500, 10375, },
2928                 { 11625, 10500, },
2929                 { 11750, 10625, },
2930                 { 11875, 10750, },
2931                 { 12000, 10875, },
2932                 { 12125, 11000, },
2933                 { 12250, 11125, },
2934                 { 12375, 11250, },
2935                 { 12500, 11375, },
2936                 { 12625, 11500, },
2937                 { 12750, 11625, },
2938                 { 12875, 11750, },
2939                 { 13000, 11875, },
2940                 { 13125, 12000, },
2941                 { 13250, 12125, },
2942                 { 13375, 12250, },
2943                 { 13500, 12375, },
2944                 { 13625, 12500, },
2945                 { 13750, 12625, },
2946                 { 13875, 12750, },
2947                 { 14000, 12875, },
2948                 { 14125, 13000, },
2949                 { 14250, 13125, },
2950                 { 14375, 13250, },
2951                 { 14500, 13375, },
2952                 { 14625, 13500, },
2953                 { 14750, 13625, },
2954                 { 14875, 13750, },
2955                 { 15000, 13875, },
2956                 { 15125, 14000, },
2957                 { 15250, 14125, },
2958                 { 15375, 14250, },
2959                 { 15500, 14375, },
2960                 { 15625, 14500, },
2961                 { 15750, 14625, },
2962                 { 15875, 14750, },
2963                 { 16000, 14875, },
2964                 { 16125, 15000, },
2965         };
2966         if (dev_priv->info->is_mobile)
2967                 return v_table[pxvid].vm;
2968         else
2969                 return v_table[pxvid].vd;
2970 }
2971
2972 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
2973 {
2974         struct timespec now, diff1;
2975         u64 diff;
2976         unsigned long diffms;
2977         u32 count;
2978
2979         assert_spin_locked(&mchdev_lock);
2980
2981         getrawmonotonic(&now);
2982         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
2983
2984         /* Don't divide by 0 */
2985         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2986         if (!diffms)
2987                 return;
2988
2989         count = I915_READ(GFXEC);
2990
2991         if (count < dev_priv->ips.last_count2) {
2992                 diff = ~0UL - dev_priv->ips.last_count2;
2993                 diff += count;
2994         } else {
2995                 diff = count - dev_priv->ips.last_count2;
2996         }
2997
2998         dev_priv->ips.last_count2 = count;
2999         dev_priv->ips.last_time2 = now;
3000
3001         /* More magic constants... */
3002         diff = diff * 1181;
3003         diff = div_u64(diff, diffms * 10);
3004         dev_priv->ips.gfx_power = diff;
3005 }
3006
3007 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3008 {
3009         if (dev_priv->info->gen != 5)
3010                 return;
3011
3012         spin_lock_irq(&mchdev_lock);
3013
3014         __i915_update_gfx_val(dev_priv);
3015
3016         spin_unlock_irq(&mchdev_lock);
3017 }
3018
3019 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3020 {
3021         unsigned long t, corr, state1, corr2, state2;
3022         u32 pxvid, ext_v;
3023
3024         assert_spin_locked(&mchdev_lock);
3025
3026         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3027         pxvid = (pxvid >> 24) & 0x7f;
3028         ext_v = pvid_to_extvid(dev_priv, pxvid);
3029
3030         state1 = ext_v;
3031
3032         t = i915_mch_val(dev_priv);
3033
3034         /* Revel in the empirically derived constants */
3035
3036         /* Correction factor in 1/100000 units */
3037         if (t > 80)
3038                 corr = ((t * 2349) + 135940);
3039         else if (t >= 50)
3040                 corr = ((t * 964) + 29317);
3041         else /* < 50 */
3042                 corr = ((t * 301) + 1004);
3043
3044         corr = corr * ((150142 * state1) / 10000 - 78642);
3045         corr /= 100000;
3046         corr2 = (corr * dev_priv->ips.corr);
3047
3048         state2 = (corr2 * state1) / 10000;
3049         state2 /= 100; /* convert to mW */
3050
3051         __i915_update_gfx_val(dev_priv);
3052
3053         return dev_priv->ips.gfx_power + state2;
3054 }
3055
3056 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3057 {
3058         unsigned long val;
3059
3060         if (dev_priv->info->gen != 5)
3061                 return 0;
3062
3063         spin_lock_irq(&mchdev_lock);
3064
3065         val = __i915_gfx_val(dev_priv);
3066
3067         spin_unlock_irq(&mchdev_lock);
3068
3069         return val;
3070 }
3071
3072 /**
3073  * i915_read_mch_val - return value for IPS use
3074  *
3075  * Calculate and return a value for the IPS driver to use when deciding whether
3076  * we have thermal and power headroom to increase CPU or GPU power budget.
3077  */
3078 unsigned long i915_read_mch_val(void)
3079 {
3080         struct drm_i915_private *dev_priv;
3081         unsigned long chipset_val, graphics_val, ret = 0;
3082
3083         spin_lock_irq(&mchdev_lock);
3084         if (!i915_mch_dev)
3085                 goto out_unlock;
3086         dev_priv = i915_mch_dev;
3087
3088         chipset_val = __i915_chipset_val(dev_priv);
3089         graphics_val = __i915_gfx_val(dev_priv);
3090
3091         ret = chipset_val + graphics_val;
3092
3093 out_unlock:
3094         spin_unlock_irq(&mchdev_lock);
3095
3096         return ret;
3097 }
3098 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3099
3100 /**
3101  * i915_gpu_raise - raise GPU frequency limit
3102  *
3103  * Raise the limit; IPS indicates we have thermal headroom.
3104  */
3105 bool i915_gpu_raise(void)
3106 {
3107         struct drm_i915_private *dev_priv;
3108         bool ret = true;
3109
3110         spin_lock_irq(&mchdev_lock);
3111         if (!i915_mch_dev) {
3112                 ret = false;
3113                 goto out_unlock;
3114         }
3115         dev_priv = i915_mch_dev;
3116
3117         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3118                 dev_priv->ips.max_delay--;
3119
3120 out_unlock:
3121         spin_unlock_irq(&mchdev_lock);
3122
3123         return ret;
3124 }
3125 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3126
3127 /**
3128  * i915_gpu_lower - lower GPU frequency limit
3129  *
3130  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3131  * frequency maximum.
3132  */
3133 bool i915_gpu_lower(void)
3134 {
3135         struct drm_i915_private *dev_priv;
3136         bool ret = true;
3137
3138         spin_lock_irq(&mchdev_lock);
3139         if (!i915_mch_dev) {
3140                 ret = false;
3141                 goto out_unlock;
3142         }
3143         dev_priv = i915_mch_dev;
3144
3145         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3146                 dev_priv->ips.max_delay++;
3147
3148 out_unlock:
3149         spin_unlock_irq(&mchdev_lock);
3150
3151         return ret;
3152 }
3153 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3154
3155 /**
3156  * i915_gpu_busy - indicate GPU business to IPS
3157  *
3158  * Tell the IPS driver whether or not the GPU is busy.
3159  */
3160 bool i915_gpu_busy(void)
3161 {
3162         struct drm_i915_private *dev_priv;
3163         struct intel_ring_buffer *ring;
3164         bool ret = false;
3165         int i;
3166
3167         spin_lock_irq(&mchdev_lock);
3168         if (!i915_mch_dev)
3169                 goto out_unlock;
3170         dev_priv = i915_mch_dev;
3171
3172         for_each_ring(ring, dev_priv, i)
3173                 ret |= !list_empty(&ring->request_list);
3174
3175 out_unlock:
3176         spin_unlock_irq(&mchdev_lock);
3177
3178         return ret;
3179 }
3180 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3181
3182 /**
3183  * i915_gpu_turbo_disable - disable graphics turbo
3184  *
3185  * Disable graphics turbo by resetting the max frequency and setting the
3186  * current frequency to the default.
3187  */
3188 bool i915_gpu_turbo_disable(void)
3189 {
3190         struct drm_i915_private *dev_priv;
3191         bool ret = true;
3192
3193         spin_lock_irq(&mchdev_lock);
3194         if (!i915_mch_dev) {
3195                 ret = false;
3196                 goto out_unlock;
3197         }
3198         dev_priv = i915_mch_dev;
3199
3200         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3201
3202         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3203                 ret = false;
3204
3205 out_unlock:
3206         spin_unlock_irq(&mchdev_lock);
3207
3208         return ret;
3209 }
3210 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3211
3212 /**
3213  * Tells the intel_ips driver that the i915 driver is now loaded, if
3214  * IPS got loaded first.
3215  *
3216  * This awkward dance is so that neither module has to depend on the
3217  * other in order for IPS to do the appropriate communication of
3218  * GPU turbo limits to i915.
3219  */
3220 static void
3221 ips_ping_for_i915_load(void)
3222 {
3223         void (*link)(void);
3224
3225         link = symbol_get(ips_link_to_i915_driver);
3226         if (link) {
3227                 link();
3228                 symbol_put(ips_link_to_i915_driver);
3229         }
3230 }
3231
3232 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3233 {
3234         /* We only register the i915 ips part with intel-ips once everything is
3235          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3236         spin_lock_irq(&mchdev_lock);
3237         i915_mch_dev = dev_priv;
3238         spin_unlock_irq(&mchdev_lock);
3239
3240         ips_ping_for_i915_load();
3241 }
3242
3243 void intel_gpu_ips_teardown(void)
3244 {
3245         spin_lock_irq(&mchdev_lock);
3246         i915_mch_dev = NULL;
3247         spin_unlock_irq(&mchdev_lock);
3248 }
3249 static void intel_init_emon(struct drm_device *dev)
3250 {
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252         u32 lcfuse;
3253         u8 pxw[16];
3254         int i;
3255
3256         /* Disable to program */
3257         I915_WRITE(ECR, 0);
3258         POSTING_READ(ECR);
3259
3260         /* Program energy weights for various events */
3261         I915_WRITE(SDEW, 0x15040d00);
3262         I915_WRITE(CSIEW0, 0x007f0000);
3263         I915_WRITE(CSIEW1, 0x1e220004);
3264         I915_WRITE(CSIEW2, 0x04000004);
3265
3266         for (i = 0; i < 5; i++)
3267                 I915_WRITE(PEW + (i * 4), 0);
3268         for (i = 0; i < 3; i++)
3269                 I915_WRITE(DEW + (i * 4), 0);
3270
3271         /* Program P-state weights to account for frequency power adjustment */
3272         for (i = 0; i < 16; i++) {
3273                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3274                 unsigned long freq = intel_pxfreq(pxvidfreq);
3275                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3276                         PXVFREQ_PX_SHIFT;
3277                 unsigned long val;
3278
3279                 val = vid * vid;
3280                 val *= (freq / 1000);
3281                 val *= 255;
3282                 val /= (127*127*900);
3283                 if (val > 0xff)
3284                         DRM_ERROR("bad pxval: %ld\n", val);
3285                 pxw[i] = val;
3286         }
3287         /* Render standby states get 0 weight */
3288         pxw[14] = 0;
3289         pxw[15] = 0;
3290
3291         for (i = 0; i < 4; i++) {
3292                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3293                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3294                 I915_WRITE(PXW + (i * 4), val);
3295         }
3296
3297         /* Adjust magic regs to magic values (more experimental results) */
3298         I915_WRITE(OGW0, 0);
3299         I915_WRITE(OGW1, 0);
3300         I915_WRITE(EG0, 0x00007f00);
3301         I915_WRITE(EG1, 0x0000000e);
3302         I915_WRITE(EG2, 0x000e0000);
3303         I915_WRITE(EG3, 0x68000300);
3304         I915_WRITE(EG4, 0x42000000);
3305         I915_WRITE(EG5, 0x00140031);
3306         I915_WRITE(EG6, 0);
3307         I915_WRITE(EG7, 0);
3308
3309         for (i = 0; i < 8; i++)
3310                 I915_WRITE(PXWL + (i * 4), 0);
3311
3312         /* Enable PMON + select events */
3313         I915_WRITE(ECR, 0x80000019);
3314
3315         lcfuse = I915_READ(LCFUSE02);
3316
3317         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3318 }
3319
3320 void intel_disable_gt_powersave(struct drm_device *dev)
3321 {
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323
3324         if (IS_IRONLAKE_M(dev)) {
3325                 ironlake_disable_drps(dev);
3326                 ironlake_disable_rc6(dev);
3327         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3328                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3329                 mutex_lock(&dev_priv->rps.hw_lock);
3330                 gen6_disable_rps(dev);
3331                 mutex_unlock(&dev_priv->rps.hw_lock);
3332         }
3333 }
3334
3335 static void intel_gen6_powersave_work(struct work_struct *work)
3336 {
3337         struct drm_i915_private *dev_priv =
3338                 container_of(work, struct drm_i915_private,
3339                              rps.delayed_resume_work.work);
3340         struct drm_device *dev = dev_priv->dev;
3341
3342         mutex_lock(&dev_priv->rps.hw_lock);
3343         gen6_enable_rps(dev);
3344         gen6_update_ring_freq(dev);
3345         mutex_unlock(&dev_priv->rps.hw_lock);
3346 }
3347
3348 void intel_enable_gt_powersave(struct drm_device *dev)
3349 {
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351
3352         if (IS_IRONLAKE_M(dev)) {
3353                 ironlake_enable_drps(dev);
3354                 ironlake_enable_rc6(dev);
3355                 intel_init_emon(dev);
3356         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3357                 /*
3358                  * PCU communication is slow and this doesn't need to be
3359                  * done at any specific time, so do this out of our fast path
3360                  * to make resume and init faster.
3361                  */
3362                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3363                                       round_jiffies_up_relative(HZ));
3364         }
3365 }
3366
3367 static void ibx_init_clock_gating(struct drm_device *dev)
3368 {
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370
3371         /*
3372          * On Ibex Peak and Cougar Point, we need to disable clock
3373          * gating for the panel power sequencer or it will fail to
3374          * start up when no ports are active.
3375          */
3376         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3377 }
3378
3379 static void ironlake_init_clock_gating(struct drm_device *dev)
3380 {
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3383
3384         /* Required for FBC */
3385         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3386                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3387                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3388
3389         I915_WRITE(PCH_3DCGDIS0,
3390                    MARIUNIT_CLOCK_GATE_DISABLE |
3391                    SVSMUNIT_CLOCK_GATE_DISABLE);
3392         I915_WRITE(PCH_3DCGDIS1,
3393                    VFMUNIT_CLOCK_GATE_DISABLE);
3394
3395         /*
3396          * According to the spec the following bits should be set in
3397          * order to enable memory self-refresh
3398          * The bit 22/21 of 0x42004
3399          * The bit 5 of 0x42020
3400          * The bit 15 of 0x45000
3401          */
3402         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3403                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3404                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3405         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3406         I915_WRITE(DISP_ARB_CTL,
3407                    (I915_READ(DISP_ARB_CTL) |
3408                     DISP_FBC_WM_DIS));
3409         I915_WRITE(WM3_LP_ILK, 0);
3410         I915_WRITE(WM2_LP_ILK, 0);
3411         I915_WRITE(WM1_LP_ILK, 0);
3412
3413         /*
3414          * Based on the document from hardware guys the following bits
3415          * should be set unconditionally in order to enable FBC.
3416          * The bit 22 of 0x42000
3417          * The bit 22 of 0x42004
3418          * The bit 7,8,9 of 0x42020.
3419          */
3420         if (IS_IRONLAKE_M(dev)) {
3421                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3422                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3423                            ILK_FBCQ_DIS);
3424                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3425                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3426                            ILK_DPARB_GATE);
3427         }
3428
3429         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3430
3431         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3432                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3433                    ILK_ELPIN_409_SELECT);
3434         I915_WRITE(_3D_CHICKEN2,
3435                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3436                    _3D_CHICKEN2_WM_READ_PIPELINED);
3437
3438         /* WaDisableRenderCachePipelinedFlush */
3439         I915_WRITE(CACHE_MODE_0,
3440                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3441
3442         ibx_init_clock_gating(dev);
3443 }
3444
3445 static void cpt_init_clock_gating(struct drm_device *dev)
3446 {
3447         struct drm_i915_private *dev_priv = dev->dev_private;
3448         int pipe;
3449
3450         /*
3451          * On Ibex Peak and Cougar Point, we need to disable clock
3452          * gating for the panel power sequencer or it will fail to
3453          * start up when no ports are active.
3454          */
3455         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3456         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3457                    DPLS_EDP_PPS_FIX_DIS);
3458         /* WADP0ClockGatingDisable */
3459         for_each_pipe(pipe) {
3460                 I915_WRITE(TRANS_CHICKEN1(pipe),
3461                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3462         }
3463 }
3464
3465 static void gen6_init_clock_gating(struct drm_device *dev)
3466 {
3467         struct drm_i915_private *dev_priv = dev->dev_private;
3468         int pipe;
3469         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3470
3471         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3472
3473         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3474                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3475                    ILK_ELPIN_409_SELECT);
3476
3477         I915_WRITE(WM3_LP_ILK, 0);
3478         I915_WRITE(WM2_LP_ILK, 0);
3479         I915_WRITE(WM1_LP_ILK, 0);
3480
3481         I915_WRITE(CACHE_MODE_0,
3482                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3483
3484         I915_WRITE(GEN6_UCGCTL1,
3485                    I915_READ(GEN6_UCGCTL1) |
3486                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3487                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3488
3489         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3490          * gating disable must be set.  Failure to set it results in
3491          * flickering pixels due to Z write ordering failures after
3492          * some amount of runtime in the Mesa "fire" demo, and Unigine
3493          * Sanctuary and Tropics, and apparently anything else with
3494          * alpha test or pixel discard.
3495          *
3496          * According to the spec, bit 11 (RCCUNIT) must also be set,
3497          * but we didn't debug actual testcases to find it out.
3498          *
3499          * Also apply WaDisableVDSUnitClockGating and
3500          * WaDisableRCPBUnitClockGating.
3501          */
3502         I915_WRITE(GEN6_UCGCTL2,
3503                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3504                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3505                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3506
3507         /* Bspec says we need to always set all mask bits. */
3508         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3509                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3510
3511         /*
3512          * According to the spec the following bits should be
3513          * set in order to enable memory self-refresh and fbc:
3514          * The bit21 and bit22 of 0x42000
3515          * The bit21 and bit22 of 0x42004
3516          * The bit5 and bit7 of 0x42020
3517          * The bit14 of 0x70180
3518          * The bit14 of 0x71180
3519          */
3520         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3521                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3522                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3523         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3524                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3525                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3526         I915_WRITE(ILK_DSPCLK_GATE_D,
3527                    I915_READ(ILK_DSPCLK_GATE_D) |
3528                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3529                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3530
3531         /* WaMbcDriverBootEnable */
3532         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3533                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3534
3535         for_each_pipe(pipe) {
3536                 I915_WRITE(DSPCNTR(pipe),
3537                            I915_READ(DSPCNTR(pipe)) |
3538                            DISPPLANE_TRICKLE_FEED_DISABLE);
3539                 intel_flush_display_plane(dev_priv, pipe);
3540         }
3541
3542         /* The default value should be 0x200 according to docs, but the two
3543          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3544         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3545         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3546
3547         cpt_init_clock_gating(dev);
3548 }
3549
3550 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3551 {
3552         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3553
3554         reg &= ~GEN7_FF_SCHED_MASK;
3555         reg |= GEN7_FF_TS_SCHED_HW;
3556         reg |= GEN7_FF_VS_SCHED_HW;
3557         reg |= GEN7_FF_DS_SCHED_HW;
3558
3559         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3560 }
3561
3562 static void lpt_init_clock_gating(struct drm_device *dev)
3563 {
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565
3566         /*
3567          * TODO: this bit should only be enabled when really needed, then
3568          * disabled when not needed anymore in order to save power.
3569          */
3570         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3571                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3572                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3573                            PCH_LP_PARTITION_LEVEL_DISABLE);
3574 }
3575
3576 static void haswell_init_clock_gating(struct drm_device *dev)
3577 {
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int pipe;
3580
3581         I915_WRITE(WM3_LP_ILK, 0);
3582         I915_WRITE(WM2_LP_ILK, 0);
3583         I915_WRITE(WM1_LP_ILK, 0);
3584
3585         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3586          * This implements the WaDisableRCZUnitClockGating workaround.
3587          */
3588         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3589
3590         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3591         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3592                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3593
3594         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3595         I915_WRITE(GEN7_L3CNTLREG1,
3596                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3597         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3598                         GEN7_WA_L3_CHICKEN_MODE);
3599
3600         /* This is required by WaCatErrorRejectionIssue */
3601         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3602                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3603                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3604
3605         for_each_pipe(pipe) {
3606                 I915_WRITE(DSPCNTR(pipe),
3607                            I915_READ(DSPCNTR(pipe)) |
3608                            DISPPLANE_TRICKLE_FEED_DISABLE);
3609                 intel_flush_display_plane(dev_priv, pipe);
3610         }
3611
3612         gen7_setup_fixed_func_scheduler(dev_priv);
3613
3614         /* WaDisable4x2SubspanOptimization */
3615         I915_WRITE(CACHE_MODE_1,
3616                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3617
3618         /* WaMbcDriverBootEnable */
3619         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3620                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3621
3622         /* XXX: This is a workaround for early silicon revisions and should be
3623          * removed later.
3624          */
3625         I915_WRITE(WM_DBG,
3626                         I915_READ(WM_DBG) |
3627                         WM_DBG_DISALLOW_MULTIPLE_LP |
3628                         WM_DBG_DISALLOW_SPRITE |
3629                         WM_DBG_DISALLOW_MAXFIFO);
3630
3631         lpt_init_clock_gating(dev);
3632 }
3633
3634 static void ivybridge_init_clock_gating(struct drm_device *dev)
3635 {
3636         struct drm_i915_private *dev_priv = dev->dev_private;
3637         int pipe;
3638         uint32_t snpcr;
3639
3640         I915_WRITE(WM3_LP_ILK, 0);
3641         I915_WRITE(WM2_LP_ILK, 0);
3642         I915_WRITE(WM1_LP_ILK, 0);
3643
3644         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3645
3646         /* WaDisableEarlyCull */
3647         I915_WRITE(_3D_CHICKEN3,
3648                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3649
3650         /* WaDisableBackToBackFlipFix */
3651         I915_WRITE(IVB_CHICKEN3,
3652                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3653                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3654
3655         /* WaDisablePSDDualDispatchEnable */
3656         if (IS_IVB_GT1(dev))
3657                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3658                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3659         else
3660                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3661                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3662
3663         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3664         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3665                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3666
3667         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3668         I915_WRITE(GEN7_L3CNTLREG1,
3669                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3670         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3671                    GEN7_WA_L3_CHICKEN_MODE);
3672         if (IS_IVB_GT1(dev))
3673                 I915_WRITE(GEN7_ROW_CHICKEN2,
3674                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3675         else
3676                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3677                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3678
3679
3680         /* WaForceL3Serialization */
3681         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3682                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3683
3684         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3685          * gating disable must be set.  Failure to set it results in
3686          * flickering pixels due to Z write ordering failures after
3687          * some amount of runtime in the Mesa "fire" demo, and Unigine
3688          * Sanctuary and Tropics, and apparently anything else with
3689          * alpha test or pixel discard.
3690          *
3691          * According to the spec, bit 11 (RCCUNIT) must also be set,
3692          * but we didn't debug actual testcases to find it out.
3693          *
3694          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3695          * This implements the WaDisableRCZUnitClockGating workaround.
3696          */
3697         I915_WRITE(GEN6_UCGCTL2,
3698                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3699                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3700
3701         /* This is required by WaCatErrorRejectionIssue */
3702         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3703                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3704                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3705
3706         for_each_pipe(pipe) {
3707                 I915_WRITE(DSPCNTR(pipe),
3708                            I915_READ(DSPCNTR(pipe)) |
3709                            DISPPLANE_TRICKLE_FEED_DISABLE);
3710                 intel_flush_display_plane(dev_priv, pipe);
3711         }
3712
3713         /* WaMbcDriverBootEnable */
3714         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3715                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3716
3717         gen7_setup_fixed_func_scheduler(dev_priv);
3718
3719         /* WaDisable4x2SubspanOptimization */
3720         I915_WRITE(CACHE_MODE_1,
3721                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3722
3723         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3724         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3725         snpcr |= GEN6_MBC_SNPCR_MED;
3726         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3727
3728         cpt_init_clock_gating(dev);
3729 }
3730
3731 static void valleyview_init_clock_gating(struct drm_device *dev)
3732 {
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         int pipe;
3735
3736         I915_WRITE(WM3_LP_ILK, 0);
3737         I915_WRITE(WM2_LP_ILK, 0);
3738         I915_WRITE(WM1_LP_ILK, 0);
3739
3740         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3741
3742         /* WaDisableEarlyCull */
3743         I915_WRITE(_3D_CHICKEN3,
3744                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3745
3746         /* WaDisableBackToBackFlipFix */
3747         I915_WRITE(IVB_CHICKEN3,
3748                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3749                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3750
3751         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3752                    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3753
3754         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3755         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3756                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3757
3758         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3759         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3760         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3761
3762         /* WaForceL3Serialization */
3763         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3764                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3765
3766         /* WaDisableDopClockGating */
3767         I915_WRITE(GEN7_ROW_CHICKEN2,
3768                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3769
3770         /* WaForceL3Serialization */
3771         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3772                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3773
3774         /* This is required by WaCatErrorRejectionIssue */
3775         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3776                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3777                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3778
3779         /* WaMbcDriverBootEnable */
3780         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3781                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3782
3783
3784         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3785          * gating disable must be set.  Failure to set it results in
3786          * flickering pixels due to Z write ordering failures after
3787          * some amount of runtime in the Mesa "fire" demo, and Unigine
3788          * Sanctuary and Tropics, and apparently anything else with
3789          * alpha test or pixel discard.
3790          *
3791          * According to the spec, bit 11 (RCCUNIT) must also be set,
3792          * but we didn't debug actual testcases to find it out.
3793          *
3794          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3795          * This implements the WaDisableRCZUnitClockGating workaround.
3796          *
3797          * Also apply WaDisableVDSUnitClockGating and
3798          * WaDisableRCPBUnitClockGating.
3799          */
3800         I915_WRITE(GEN6_UCGCTL2,
3801                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3802                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3803                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3804                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3805                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3806
3807         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3808
3809         for_each_pipe(pipe) {
3810                 I915_WRITE(DSPCNTR(pipe),
3811                            I915_READ(DSPCNTR(pipe)) |
3812                            DISPPLANE_TRICKLE_FEED_DISABLE);
3813                 intel_flush_display_plane(dev_priv, pipe);
3814         }
3815
3816         I915_WRITE(CACHE_MODE_1,
3817                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3818
3819         /*
3820          * On ValleyView, the GUnit needs to signal the GT
3821          * when flip and other events complete.  So enable
3822          * all the GUnit->GT interrupts here
3823          */
3824         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3825                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3826                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3827                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3828                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3829                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3830                    PLANEA_FLIPDONE_INT_EN);
3831
3832         /*
3833          * WaDisableVLVClockGating_VBIIssue
3834          * Disable clock gating on th GCFG unit to prevent a delay
3835          * in the reporting of vblank events.
3836          */
3837         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3838 }
3839
3840 static void g4x_init_clock_gating(struct drm_device *dev)
3841 {
3842         struct drm_i915_private *dev_priv = dev->dev_private;
3843         uint32_t dspclk_gate;
3844
3845         I915_WRITE(RENCLK_GATE_D1, 0);
3846         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3847                    GS_UNIT_CLOCK_GATE_DISABLE |
3848                    CL_UNIT_CLOCK_GATE_DISABLE);
3849         I915_WRITE(RAMCLK_GATE_D, 0);
3850         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3851                 OVRUNIT_CLOCK_GATE_DISABLE |
3852                 OVCUNIT_CLOCK_GATE_DISABLE;
3853         if (IS_GM45(dev))
3854                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3855         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3856
3857         /* WaDisableRenderCachePipelinedFlush */
3858         I915_WRITE(CACHE_MODE_0,
3859                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3860 }
3861
3862 static void crestline_init_clock_gating(struct drm_device *dev)
3863 {
3864         struct drm_i915_private *dev_priv = dev->dev_private;
3865
3866         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3867         I915_WRITE(RENCLK_GATE_D2, 0);
3868         I915_WRITE(DSPCLK_GATE_D, 0);
3869         I915_WRITE(RAMCLK_GATE_D, 0);
3870         I915_WRITE16(DEUC, 0);
3871 }
3872
3873 static void broadwater_init_clock_gating(struct drm_device *dev)
3874 {
3875         struct drm_i915_private *dev_priv = dev->dev_private;
3876
3877         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3878                    I965_RCC_CLOCK_GATE_DISABLE |
3879                    I965_RCPB_CLOCK_GATE_DISABLE |
3880                    I965_ISC_CLOCK_GATE_DISABLE |
3881                    I965_FBC_CLOCK_GATE_DISABLE);
3882         I915_WRITE(RENCLK_GATE_D2, 0);
3883 }
3884
3885 static void gen3_init_clock_gating(struct drm_device *dev)
3886 {
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888         u32 dstate = I915_READ(D_STATE);
3889
3890         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3891                 DSTATE_DOT_CLOCK_GATING;
3892         I915_WRITE(D_STATE, dstate);
3893
3894         if (IS_PINEVIEW(dev))
3895                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
3896
3897         /* IIR "flip pending" means done if this bit is set */
3898         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
3899 }
3900
3901 static void i85x_init_clock_gating(struct drm_device *dev)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904
3905         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3906 }
3907
3908 static void i830_init_clock_gating(struct drm_device *dev)
3909 {
3910         struct drm_i915_private *dev_priv = dev->dev_private;
3911
3912         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3913 }
3914
3915 void intel_init_clock_gating(struct drm_device *dev)
3916 {
3917         struct drm_i915_private *dev_priv = dev->dev_private;
3918
3919         dev_priv->display.init_clock_gating(dev);
3920 }
3921
3922 /* Starting with Haswell, we have different power wells for
3923  * different parts of the GPU. This attempts to enable them all.
3924  */
3925 void intel_init_power_wells(struct drm_device *dev)
3926 {
3927         struct drm_i915_private *dev_priv = dev->dev_private;
3928         unsigned long power_wells[] = {
3929                 HSW_PWR_WELL_CTL1,
3930                 HSW_PWR_WELL_CTL2,
3931                 HSW_PWR_WELL_CTL4
3932         };
3933         int i;
3934
3935         if (!IS_HASWELL(dev))
3936                 return;
3937
3938         mutex_lock(&dev->struct_mutex);
3939
3940         for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3941                 int well = I915_READ(power_wells[i]);
3942
3943                 if ((well & HSW_PWR_WELL_STATE) == 0) {
3944                         I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
3945                         if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
3946                                 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3947                 }
3948         }
3949
3950         mutex_unlock(&dev->struct_mutex);
3951 }
3952
3953 /* Set up chip specific power management-related functions */
3954 void intel_init_pm(struct drm_device *dev)
3955 {
3956         struct drm_i915_private *dev_priv = dev->dev_private;
3957
3958         if (I915_HAS_FBC(dev)) {
3959                 if (HAS_PCH_SPLIT(dev)) {
3960                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3961                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
3962                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
3963                 } else if (IS_GM45(dev)) {
3964                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3965                         dev_priv->display.enable_fbc = g4x_enable_fbc;
3966                         dev_priv->display.disable_fbc = g4x_disable_fbc;
3967                 } else if (IS_CRESTLINE(dev)) {
3968                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3969                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
3970                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
3971                 }
3972                 /* 855GM needs testing */
3973         }
3974
3975         /* For cxsr */
3976         if (IS_PINEVIEW(dev))
3977                 i915_pineview_get_mem_freq(dev);
3978         else if (IS_GEN5(dev))
3979                 i915_ironlake_get_mem_freq(dev);
3980
3981         /* For FIFO watermark updates */
3982         if (HAS_PCH_SPLIT(dev)) {
3983                 if (IS_GEN5(dev)) {
3984                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3985                                 dev_priv->display.update_wm = ironlake_update_wm;
3986                         else {
3987                                 DRM_DEBUG_KMS("Failed to get proper latency. "
3988                                               "Disable CxSR\n");
3989                                 dev_priv->display.update_wm = NULL;
3990                         }
3991                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3992                 } else if (IS_GEN6(dev)) {
3993                         if (SNB_READ_WM0_LATENCY()) {
3994                                 dev_priv->display.update_wm = sandybridge_update_wm;
3995                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3996                         } else {
3997                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
3998                                               "Disable CxSR\n");
3999                                 dev_priv->display.update_wm = NULL;
4000                         }
4001                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4002                 } else if (IS_IVYBRIDGE(dev)) {
4003                         /* FIXME: detect B0+ stepping and use auto training */
4004                         if (SNB_READ_WM0_LATENCY()) {
4005                                 dev_priv->display.update_wm = sandybridge_update_wm;
4006                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4007                         } else {
4008                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4009                                               "Disable CxSR\n");
4010                                 dev_priv->display.update_wm = NULL;
4011                         }
4012                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4013                 } else if (IS_HASWELL(dev)) {
4014                         if (SNB_READ_WM0_LATENCY()) {
4015                                 dev_priv->display.update_wm = sandybridge_update_wm;
4016                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4017                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4018                         } else {
4019                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4020                                               "Disable CxSR\n");
4021                                 dev_priv->display.update_wm = NULL;
4022                         }
4023                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4024                 } else
4025                         dev_priv->display.update_wm = NULL;
4026         } else if (IS_VALLEYVIEW(dev)) {
4027                 dev_priv->display.update_wm = valleyview_update_wm;
4028                 dev_priv->display.init_clock_gating =
4029                         valleyview_init_clock_gating;
4030         } else if (IS_PINEVIEW(dev)) {
4031                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4032                                             dev_priv->is_ddr3,
4033                                             dev_priv->fsb_freq,
4034                                             dev_priv->mem_freq)) {
4035                         DRM_INFO("failed to find known CxSR latency "
4036                                  "(found ddr%s fsb freq %d, mem freq %d), "
4037                                  "disabling CxSR\n",
4038                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4039                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4040                         /* Disable CxSR and never update its watermark again */
4041                         pineview_disable_cxsr(dev);
4042                         dev_priv->display.update_wm = NULL;
4043                 } else
4044                         dev_priv->display.update_wm = pineview_update_wm;
4045                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4046         } else if (IS_G4X(dev)) {
4047                 dev_priv->display.update_wm = g4x_update_wm;
4048                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4049         } else if (IS_GEN4(dev)) {
4050                 dev_priv->display.update_wm = i965_update_wm;
4051                 if (IS_CRESTLINE(dev))
4052                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4053                 else if (IS_BROADWATER(dev))
4054                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4055         } else if (IS_GEN3(dev)) {
4056                 dev_priv->display.update_wm = i9xx_update_wm;
4057                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4058                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4059         } else if (IS_I865G(dev)) {
4060                 dev_priv->display.update_wm = i830_update_wm;
4061                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4062                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4063         } else if (IS_I85X(dev)) {
4064                 dev_priv->display.update_wm = i9xx_update_wm;
4065                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4066                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4067         } else {
4068                 dev_priv->display.update_wm = i830_update_wm;
4069                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4070                 if (IS_845G(dev))
4071                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4072                 else
4073                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4074         }
4075 }
4076
4077 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4078 {
4079         u32 gt_thread_status_mask;
4080
4081         if (IS_HASWELL(dev_priv->dev))
4082                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4083         else
4084                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4085
4086         /* w/a for a sporadic read returning 0 by waiting for the GT
4087          * thread to wake up.
4088          */
4089         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4090                 DRM_ERROR("GT thread status wait timed out\n");
4091 }
4092
4093 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4094 {
4095         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4096         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4097 }
4098
4099 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4100 {
4101         u32 forcewake_ack;
4102
4103         if (IS_HASWELL(dev_priv->dev))
4104                 forcewake_ack = FORCEWAKE_ACK_HSW;
4105         else
4106                 forcewake_ack = FORCEWAKE_ACK;
4107
4108         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4109                             FORCEWAKE_ACK_TIMEOUT_MS))
4110                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4111
4112         I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4113         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4114
4115         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4116                             FORCEWAKE_ACK_TIMEOUT_MS))
4117                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4118
4119         __gen6_gt_wait_for_thread_c0(dev_priv);
4120 }
4121
4122 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4123 {
4124         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4125         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4126 }
4127
4128 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4129 {
4130         u32 forcewake_ack;
4131
4132         if (IS_HASWELL(dev_priv->dev))
4133                 forcewake_ack = FORCEWAKE_ACK_HSW;
4134         else
4135                 forcewake_ack = FORCEWAKE_MT_ACK;
4136
4137         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4138                             FORCEWAKE_ACK_TIMEOUT_MS))
4139                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4140
4141         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4142         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4143
4144         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4145                             FORCEWAKE_ACK_TIMEOUT_MS))
4146                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4147
4148         __gen6_gt_wait_for_thread_c0(dev_priv);
4149 }
4150
4151 /*
4152  * Generally this is called implicitly by the register read function. However,
4153  * if some sequence requires the GT to not power down then this function should
4154  * be called at the beginning of the sequence followed by a call to
4155  * gen6_gt_force_wake_put() at the end of the sequence.
4156  */
4157 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4158 {
4159         unsigned long irqflags;
4160
4161         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4162         if (dev_priv->forcewake_count++ == 0)
4163                 dev_priv->gt.force_wake_get(dev_priv);
4164         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4165 }
4166
4167 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4168 {
4169         u32 gtfifodbg;
4170         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4171         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4172              "MMIO read or write has been dropped %x\n", gtfifodbg))
4173                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4174 }
4175
4176 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4177 {
4178         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4179         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4180         gen6_gt_check_fifodbg(dev_priv);
4181 }
4182
4183 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4184 {
4185         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4186         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4187         gen6_gt_check_fifodbg(dev_priv);
4188 }
4189
4190 /*
4191  * see gen6_gt_force_wake_get()
4192  */
4193 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4194 {
4195         unsigned long irqflags;
4196
4197         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4198         if (--dev_priv->forcewake_count == 0)
4199                 dev_priv->gt.force_wake_put(dev_priv);
4200         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4201 }
4202
4203 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4204 {
4205         int ret = 0;
4206
4207         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4208                 int loop = 500;
4209                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4210                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4211                         udelay(10);
4212                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4213                 }
4214                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4215                         ++ret;
4216                 dev_priv->gt_fifo_count = fifo;
4217         }
4218         dev_priv->gt_fifo_count--;
4219
4220         return ret;
4221 }
4222
4223 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4224 {
4225         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4226 }
4227
4228 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4229 {
4230         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4231                             FORCEWAKE_ACK_TIMEOUT_MS))
4232                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4233
4234         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4235
4236         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4237                             FORCEWAKE_ACK_TIMEOUT_MS))
4238                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4239
4240         __gen6_gt_wait_for_thread_c0(dev_priv);
4241 }
4242
4243 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4244 {
4245         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4246         /* The below doubles as a POSTING_READ */
4247         gen6_gt_check_fifodbg(dev_priv);
4248 }
4249
4250 void intel_gt_reset(struct drm_device *dev)
4251 {
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253
4254         if (IS_VALLEYVIEW(dev)) {
4255                 vlv_force_wake_reset(dev_priv);
4256         } else if (INTEL_INFO(dev)->gen >= 6) {
4257                 __gen6_gt_force_wake_reset(dev_priv);
4258                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4259                         __gen6_gt_force_wake_mt_reset(dev_priv);
4260         }
4261 }
4262
4263 void intel_gt_init(struct drm_device *dev)
4264 {
4265         struct drm_i915_private *dev_priv = dev->dev_private;
4266
4267         spin_lock_init(&dev_priv->gt_lock);
4268
4269         intel_gt_reset(dev);
4270
4271         if (IS_VALLEYVIEW(dev)) {
4272                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4273                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4274         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4275                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4276                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4277         } else if (IS_GEN6(dev)) {
4278                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4279                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4280         }
4281         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4282                           intel_gen6_powersave_work);
4283 }
4284
4285 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4286 {
4287         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4288
4289         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4290                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4291                 return -EAGAIN;
4292         }
4293
4294         I915_WRITE(GEN6_PCODE_DATA, *val);
4295         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4296
4297         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4298                      500)) {
4299                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4300                 return -ETIMEDOUT;
4301         }
4302
4303         *val = I915_READ(GEN6_PCODE_DATA);
4304         I915_WRITE(GEN6_PCODE_DATA, 0);
4305
4306         return 0;
4307 }
4308
4309 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4310 {
4311         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4312
4313         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4314                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4315                 return -EAGAIN;
4316         }
4317
4318         I915_WRITE(GEN6_PCODE_DATA, val);
4319         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4320
4321         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4322                      500)) {
4323                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4324                 return -ETIMEDOUT;
4325         }
4326
4327         I915_WRITE(GEN6_PCODE_DATA, 0);
4328
4329         return 0;
4330 }