drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ras.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v11_0.h"
  33
  34 #include "mp/mp_11_0_offset.h"
  35 #include "mp/mp_11_0_sh_mask.h"
  36 #include "gc/gc_9_0_offset.h"
  37 #include "sdma0/sdma0_4_0_offset.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39
  40 #include "oss/osssys_4_0_offset.h"
  41 #include "oss/osssys_4_0_sh_mask.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
  55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
  58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
  59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
  60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
  61 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
  62 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
  63 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
  64 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
  65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
  66 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
  67
  68 /* address block */
  69 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  70 /* navi10 reg offset define */
  71 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  72 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  73 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  74 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  75 /* memory training timeout define */
  76 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  77
  78 /* For large FW files the time to complete can be very long */
  79 #define USBC_PD_POLLING_LIMIT_S 240
  80
  81 static int psp_v11_0_init_microcode(struct psp_context *psp)
  82 {
  83         struct amdgpu_device *adev = psp->adev;
  84         const char *chip_name;
  85         char fw_name[PSP_FW_NAME_LEN];
  86         int err = 0;
  87         const struct ta_firmware_header_v1_0 *ta_hdr;
  88
  89         DRM_DEBUG("\n");
  90
  91         switch (adev->asic_type) {
  92         case CHIP_VEGA20:
  93                 chip_name = "vega20";
  94                 break;
  95         case CHIP_NAVI10:
  96                 chip_name = "navi10";
  97                 break;
  98         case CHIP_NAVI14:
  99                 chip_name = "navi14";
 100                 break;
 101         case CHIP_NAVI12:
 102                 chip_name = "navi12";
 103                 break;
 104         case CHIP_ARCTURUS:
 105                 chip_name = "arcturus";
 106                 break;
 107         case CHIP_SIENNA_CICHLID:
 108                 chip_name = "sienna_cichlid";
 109                 break;
 110         case CHIP_NAVY_FLOUNDER:
 111                 chip_name = "navy_flounder";
 112                 break;
 113         case CHIP_VANGOGH:
 114                 chip_name = "vangogh";
 115                 break;
 116         case CHIP_DIMGREY_CAVEFISH:
 117                 chip_name = "dimgrey_cavefish";
 118                 break;
 119         case CHIP_BEIGE_GOBY:
 120                 chip_name = "beige_goby";
 121                 break;
 122         default:
 123                 BUG();
 124         }
 125
 126
 127         switch (adev->asic_type) {
 128         case CHIP_VEGA20:
 129         case CHIP_ARCTURUS:
 130                 err = psp_init_sos_microcode(psp, chip_name);
 131                 if (err)
 132                         return err;
 133                 err = psp_init_asd_microcode(psp, chip_name);
 134                 if (err)
 135                         return err;
 136                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 137                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 138                 if (err) {
 139                         release_firmware(adev->psp.ta_fw);
 140                         adev->psp.ta_fw = NULL;
 141                         dev_info(adev->dev,
 142                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 143                 } else {
 144                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 145                         if (err)
 146                                 goto out2;
 147
 148                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 149                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 150                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 151                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 152                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 153                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 154                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 155                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 156                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 157                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 158                 }
 159                 break;
 160         case CHIP_NAVI10:
 161         case CHIP_NAVI14:
 162         case CHIP_NAVI12:
 163                 err = psp_init_sos_microcode(psp, chip_name);
 164                 if (err)
 165                         return err;
 166                 err = psp_init_asd_microcode(psp, chip_name);
 167                 if (err)
 168                         return err;
 169                 if (amdgpu_sriov_vf(adev))
 170                         break;
 171                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 172                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 173                 if (err) {
 174                         release_firmware(adev->psp.ta_fw);
 175                         adev->psp.ta_fw = NULL;
 176                         dev_info(adev->dev,
 177                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 178                 } else {
 179                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 180                         if (err)
 181                                 goto out2;
 182
 183                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 184                         adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
 185                         adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
 186                         adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
 187                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 188
 189                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 190
 191                         adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
 192                         adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
 193                         adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
 194                                 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
 195                 }
 196                 break;
 197         case CHIP_SIENNA_CICHLID:
 198         case CHIP_NAVY_FLOUNDER:
 199         case CHIP_DIMGREY_CAVEFISH:
 200                 err = psp_init_sos_microcode(psp, chip_name);
 201                 if (err)
 202                         return err;
 203                 err = psp_init_ta_microcode(psp, chip_name);
 204                 if (err)
 205                         return err;
 206                 break;
 207         case CHIP_BEIGE_GOBY:
 208                 err = psp_init_sos_microcode(psp, chip_name);
 209                 if (err)
 210                         return err;
 211                 break;
 212         case CHIP_VANGOGH:
 213                 err = psp_init_asd_microcode(psp, chip_name);
 214                 if (err)
 215                         return err;
 216                 err = psp_init_toc_microcode(psp, chip_name);
 217                 if (err)
 218                         return err;
 219                 break;
 220         default:
 221                 BUG();
 222         }
 223
 224         return 0;
 225
 226 out2:
 227         release_firmware(adev->psp.ta_fw);
 228         adev->psp.ta_fw = NULL;
 229         return err;
 230 }
 231
 232 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
 233 {
 234         struct amdgpu_device *adev = psp->adev;
 235
 236         int ret;
 237         int retry_loop;
 238
 239         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 240                 /* Wait for bootloader to signify that is
 241                     ready having bit 31 of C2PMSG_35 set to 1 */
 242                 ret = psp_wait_for(psp,
 243                                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 244                                    0x80000000,
 245                                    0x80000000,
 246                                    false);
 247
 248                 if (ret == 0)
 249                         return 0;
 250         }
 251
 252         return ret;
 253 }
 254
 255 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
 256 {
 257         struct amdgpu_device *adev = psp->adev;
 258         uint32_t sol_reg;
 259
 260         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 261
 262         return sol_reg != 0x0;
 263 }
 264
 265 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 266 {
 267         int ret;
 268         uint32_t psp_gfxdrv_command_reg = 0;
 269         struct amdgpu_device *adev = psp->adev;
 270
 271         /* Check tOS sign of life register to confirm sys driver and sOS
 272          * are already been loaded.
 273          */
 274         if (psp_v11_0_is_sos_alive(psp))
 275                 return 0;
 276
 277         ret = psp_v11_0_wait_for_bootloader(psp);
 278         if (ret)
 279                 return ret;
 280
 281         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 282
 283         /* Copy PSP KDB binary to memory */
 284         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 285
 286         /* Provide the PSP KDB to bootloader */
 287         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 288                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 289         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 290         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 291                psp_gfxdrv_command_reg);
 292
 293         ret = psp_v11_0_wait_for_bootloader(psp);
 294
 295         return ret;
 296 }
 297
 298 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
 299 {
 300         int ret;
 301         uint32_t psp_gfxdrv_command_reg = 0;
 302         struct amdgpu_device *adev = psp->adev;
 303
 304         /* Check tOS sign of life register to confirm sys driver and sOS
 305          * are already been loaded.
 306          */
 307         if (psp_v11_0_is_sos_alive(psp))
 308                 return 0;
 309
 310         ret = psp_v11_0_wait_for_bootloader(psp);
 311         if (ret)
 312                 return ret;
 313
 314         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 315
 316         /* Copy PSP SPL binary to memory */
 317         memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size);
 318
 319         /* Provide the PSP SPL to bootloader */
 320         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 321                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 322         psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
 323         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 324                psp_gfxdrv_command_reg);
 325
 326         ret = psp_v11_0_wait_for_bootloader(psp);
 327
 328         return ret;
 329 }
 330
 331 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 332 {
 333         int ret;
 334         uint32_t psp_gfxdrv_command_reg = 0;
 335         struct amdgpu_device *adev = psp->adev;
 336
 337         /* Check sOS sign of life register to confirm sys driver and sOS
 338          * are already been loaded.
 339          */
 340         if (psp_v11_0_is_sos_alive(psp))
 341                 return 0;
 342
 343         ret = psp_v11_0_wait_for_bootloader(psp);
 344         if (ret)
 345                 return ret;
 346
 347         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 348
 349         /* Copy PSP System Driver binary to memory */
 350         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 351
 352         /* Provide the sys driver to bootloader */
 353         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 354                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 355         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 356         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 357                psp_gfxdrv_command_reg);
 358
 359         /* there might be handshake issue with hardware which needs delay */
 360         mdelay(20);
 361
 362         ret = psp_v11_0_wait_for_bootloader(psp);
 363
 364         return ret;
 365 }
 366
 367 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 368 {
 369         int ret;
 370         unsigned int psp_gfxdrv_command_reg = 0;
 371         struct amdgpu_device *adev = psp->adev;
 372
 373         /* Check sOS sign of life register to confirm sys driver and sOS
 374          * are already been loaded.
 375          */
 376         if (psp_v11_0_is_sos_alive(psp))
 377                 return 0;
 378
 379         ret = psp_v11_0_wait_for_bootloader(psp);
 380         if (ret)
 381                 return ret;
 382
 383         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 384
 385         /* Copy Secure OS binary to PSP memory */
 386         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 387
 388         /* Provide the PSP secure OS to bootloader */
 389         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 390                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 391         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 392         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 393                psp_gfxdrv_command_reg);
 394
 395         /* there might be handshake issue with hardware which needs delay */
 396         mdelay(20);
 397         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 398                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 399                            0, true);
 400
 401         return ret;
 402 }
 403
 404 static int psp_v11_0_ring_init(struct psp_context *psp,
 405                               enum psp_ring_type ring_type)
 406 {
 407         int ret = 0;
 408         struct psp_ring *ring;
 409         struct amdgpu_device *adev = psp->adev;
 410
 411         ring = &psp->km_ring;
 412
 413         ring->ring_type = ring_type;
 414
 415         /* allocate 4k Page of Local Frame Buffer memory for ring */
 416         ring->ring_size = 0x1000;
 417         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 418                                       AMDGPU_GEM_DOMAIN_VRAM,
 419                                       &adev->firmware.rbuf,
 420                                       &ring->ring_mem_mc_addr,
 421                                       (void **)&ring->ring_mem);
 422         if (ret) {
 423                 ring->ring_size = 0;
 424                 return ret;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int psp_v11_0_ring_stop(struct psp_context *psp,
 431                               enum psp_ring_type ring_type)
 432 {
 433         int ret = 0;
 434         struct amdgpu_device *adev = psp->adev;
 435
 436         /* Write the ring destroy command*/
 437         if (amdgpu_sriov_vf(adev))
 438                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 439                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 440         else
 441                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 442                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 443
 444         /* there might be handshake issue with hardware which needs delay */
 445         mdelay(20);
 446
 447         /* Wait for response flag (bit 31) */
 448         if (amdgpu_sriov_vf(adev))
 449                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 450                                    0x80000000, 0x80000000, false);
 451         else
 452                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 453                                    0x80000000, 0x80000000, false);
 454
 455         return ret;
 456 }
 457
 458 static int psp_v11_0_ring_create(struct psp_context *psp,
 459                                 enum psp_ring_type ring_type)
 460 {
 461         int ret = 0;
 462         unsigned int psp_ring_reg = 0;
 463         struct psp_ring *ring = &psp->km_ring;
 464         struct amdgpu_device *adev = psp->adev;
 465
 466         if (amdgpu_sriov_vf(adev)) {
 467                 ret = psp_v11_0_ring_stop(psp, ring_type);
 468                 if (ret) {
 469                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 470                         return ret;
 471                 }
 472
 473                 /* Write low address of the ring to C2PMSG_102 */
 474                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 475                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 476                 /* Write high address of the ring to C2PMSG_103 */
 477                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 478                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 479
 480                 /* Write the ring initialization command to C2PMSG_101 */
 481                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 482                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 483
 484                 /* there might be handshake issue with hardware which needs delay */
 485                 mdelay(20);
 486
 487                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 488                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 489                                    0x80000000, 0x8000FFFF, false);
 490
 491         } else {
 492                 /* Wait for sOS ready for ring creation */
 493                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 494                                    0x80000000, 0x80000000, false);
 495                 if (ret) {
 496                         DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
 497                         return ret;
 498                 }
 499
 500                 /* Write low address of the ring to C2PMSG_69 */
 501                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 502                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 503                 /* Write high address of the ring to C2PMSG_70 */
 504                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 505                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 506                 /* Write size of ring to C2PMSG_71 */
 507                 psp_ring_reg = ring->ring_size;
 508                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 509                 /* Write the ring initialization command to C2PMSG_64 */
 510                 psp_ring_reg = ring_type;
 511                 psp_ring_reg = psp_ring_reg << 16;
 512                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 513
 514                 /* there might be handshake issue with hardware which needs delay */
 515                 mdelay(20);
 516
 517                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 518                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 519                                    0x80000000, 0x8000FFFF, false);
 520         }
 521
 522         return ret;
 523 }
 524
 525
 526 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 527                                  enum psp_ring_type ring_type)
 528 {
 529         int ret = 0;
 530         struct psp_ring *ring = &psp->km_ring;
 531         struct amdgpu_device *adev = psp->adev;
 532
 533         ret = psp_v11_0_ring_stop(psp, ring_type);
 534         if (ret)
 535                 DRM_ERROR("Fail to stop psp ring\n");
 536
 537         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 538                               &ring->ring_mem_mc_addr,
 539                               (void **)&ring->ring_mem);
 540
 541         return ret;
 542 }
 543
 544 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 545 {
 546         int ret;
 547         uint32_t offset;
 548         struct amdgpu_device *adev = psp->adev;
 549
 550         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 551
 552         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 553
 554         if (ret) {
 555                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 556                 return -EINVAL;
 557         }
 558
 559         /*send the mode 1 reset command*/
 560         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 561
 562         msleep(500);
 563
 564         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 565
 566         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 567
 568         if (ret) {
 569                 DRM_INFO("psp mode 1 reset failed!\n");
 570                 return -EINVAL;
 571         }
 572
 573         DRM_INFO("psp mode1 reset succeed \n");
 574
 575         return 0;
 576 }
 577
 578 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 579 {
 580         int ret;
 581         int i;
 582         uint32_t data_32;
 583         int max_wait;
 584         struct amdgpu_device *adev = psp->adev;
 585
 586         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 587         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
 588         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
 589
 590         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 591         for (i = 0; i < max_wait; i++) {
 592                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 593                                    0x80000000, 0x80000000, false);
 594                 if (ret == 0)
 595                         break;
 596         }
 597         if (i < max_wait)
 598                 ret = 0;
 599         else
 600                 ret = -ETIME;
 601
 602         DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
 603                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 604                   (ret == 0) ? "succeed" : "failed",
 605                   i, adev->usec_timeout/1000);
 606         return ret;
 607 }
 608
 609 /*
 610  * save and restore process
 611  */
 612 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 613 {
 614         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 615         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 616         struct amdgpu_device *adev = psp->adev;
 617         uint32_t p2c_header[4];
 618         uint32_t sz;
 619         void *buf;
 620         int ret;
 621
 622         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 623                 DRM_DEBUG("Memory training is not supported.\n");
 624                 return 0;
 625         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 626                 DRM_ERROR("Memory training initialization failure.\n");
 627                 return -EINVAL;
 628         }
 629
 630         if (psp_v11_0_is_sos_alive(psp)) {
 631                 DRM_DEBUG("SOS is alive, skip memory training.\n");
 632                 return 0;
 633         }
 634
 635         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 636         DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 637                   pcache[0], pcache[1], pcache[2], pcache[3],
 638                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 639
 640         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 641                 DRM_DEBUG("Short training depends on restore.\n");
 642                 ops |= PSP_MEM_TRAIN_RESTORE;
 643         }
 644
 645         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 646             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 647                 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
 648                 ops |= PSP_MEM_TRAIN_SAVE;
 649         }
 650
 651         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 652             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 653               pcache[3] == p2c_header[3])) {
 654                 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 655                 ops |= PSP_MEM_TRAIN_SAVE;
 656         }
 657
 658         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 659             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 660                 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
 661                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 662         }
 663
 664         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 665                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 666                 ops |= PSP_MEM_TRAIN_SAVE;
 667         }
 668
 669         DRM_DEBUG("Memory training ops:%x.\n", ops);
 670
 671         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 672                 /*
 673                  * Long training will encroach a certain amount on the bottom of VRAM;
 674                  * save the content from the bottom of VRAM to system memory
 675                  * before training, and restore it after training to avoid
 676                  * VRAM corruption.
 677                  */
 678                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 679
 680                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 681                         DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 682                                   adev->gmc.visible_vram_size,
 683                                   adev->mman.aper_base_kaddr);
 684                         return -EINVAL;
 685                 }
 686
 687                 buf = vmalloc(sz);
 688                 if (!buf) {
 689                         DRM_ERROR("failed to allocate system memory.\n");
 690                         return -ENOMEM;
 691                 }
 692
 693                 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 694                 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 695                 if (ret) {
 696                         DRM_ERROR("Send long training msg failed.\n");
 697                         vfree(buf);
 698                         return ret;
 699                 }
 700
 701                 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 702                 adev->hdp.funcs->flush_hdp(adev, NULL);
 703                 vfree(buf);
 704         }
 705
 706         if (ops & PSP_MEM_TRAIN_SAVE) {
 707                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 708         }
 709
 710         if (ops & PSP_MEM_TRAIN_RESTORE) {
 711                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 712         }
 713
 714         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 715                 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 716                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 717                 if (ret) {
 718                         DRM_ERROR("send training msg failed.\n");
 719                         return ret;
 720                 }
 721         }
 722         ctx->training_cnt++;
 723         return 0;
 724 }
 725
 726 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
 727 {
 728         uint32_t data;
 729         struct amdgpu_device *adev = psp->adev;
 730
 731         if (amdgpu_sriov_vf(adev))
 732                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 733         else
 734                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 735
 736         return data;
 737 }
 738
 739 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 740 {
 741         struct amdgpu_device *adev = psp->adev;
 742
 743         if (amdgpu_sriov_vf(adev)) {
 744                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 745                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 746         } else
 747                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 748 }
 749
 750 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr)
 751 {
 752         struct amdgpu_device *adev = psp->adev;
 753         uint32_t reg_status;
 754         int ret, i = 0;
 755
 756         /* Write lower 32-bit address of the PD Controller FW */
 757         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr));
 758         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 759                              0x80000000, 0x80000000, false);
 760         if (ret)
 761                 return ret;
 762
 763         /* Fireup interrupt so PSP can pick up the lower address */
 764         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000);
 765         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 766                              0x80000000, 0x80000000, false);
 767         if (ret)
 768                 return ret;
 769
 770         reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
 771
 772         if ((reg_status & 0xFFFF) != 0) {
 773                 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n",
 774                                 reg_status & 0xFFFF);
 775                 return -EIO;
 776         }
 777
 778         /* Write upper 32-bit address of the PD Controller FW */
 779         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr));
 780
 781         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 782                              0x80000000, 0x80000000, false);
 783         if (ret)
 784                 return ret;
 785
 786         /* Fireup interrupt so PSP can pick up the upper address */
 787         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000);
 788
 789         /* FW load takes very long time */
 790         do {
 791                 msleep(1000);
 792                 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
 793
 794                 if (reg_status & 0x80000000)
 795                         goto done;
 796
 797         } while (++i < USBC_PD_POLLING_LIMIT_S);
 798
 799         return -ETIME;
 800 done:
 801
 802         if ((reg_status & 0xFFFF) != 0) {
 803                 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n",
 804                                 reg_status & 0xFFFF);
 805                 return -EIO;
 806         }
 807
 808         return 0;
 809 }
 810
 811 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 812 {
 813         struct amdgpu_device *adev = psp->adev;
 814         int ret;
 815
 816         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 817
 818         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 819                                      0x80000000, 0x80000000, false);
 820         if (!ret)
 821                 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
 822
 823         return ret;
 824 }
 825
 826 static const struct psp_funcs psp_v11_0_funcs = {
 827         .init_microcode = psp_v11_0_init_microcode,
 828         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 829         .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
 830         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 831         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 832         .ring_init = psp_v11_0_ring_init,
 833         .ring_create = psp_v11_0_ring_create,
 834         .ring_stop = psp_v11_0_ring_stop,
 835         .ring_destroy = psp_v11_0_ring_destroy,
 836         .mode1_reset = psp_v11_0_mode1_reset,
 837         .mem_training = psp_v11_0_memory_training,
 838         .ring_get_wptr = psp_v11_0_ring_get_wptr,
 839         .ring_set_wptr = psp_v11_0_ring_set_wptr,
 840         .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
 841         .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
 842 };
 843
 844 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 845 {
 846         psp->funcs = &psp_v11_0_funcs;
 847 }