drivers/gpu/drm/amd/amdgpu/df_v3_6.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "df_v3_6.h"
  25
  26 #include "df/df_3_6_default.h"
  27 #include "df/df_3_6_offset.h"
  28 #include "df/df_3_6_sh_mask.h"
  29
  30 #define DF_3_6_SMN_REG_INST_DIST        0x8
  31 #define DF_3_6_INST_CNT                 8
  32
  33 /* Defined in global_features.h as FTI_PERFMON_VISIBLE */
  34 #define DF_V3_6_MAX_COUNTERS            4
  35
  36 /* get flags from df perfmon config */
  37 #define DF_V3_6_GET_EVENT(x)            (x & 0xFFUL)
  38 #define DF_V3_6_GET_INSTANCE(x)         ((x >> 8) & 0xFFUL)
  39 #define DF_V3_6_GET_UNITMASK(x)         ((x >> 16) & 0xFFUL)
  40 #define DF_V3_6_PERFMON_OVERFLOW        0xFFFFFFFFFFFFULL
  41
  42 static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
  43                                        16, 32, 0, 0, 0, 2, 4, 8};
  44
  45 static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
  46                                  uint32_t ficaa_val)
  47 {
  48         unsigned long flags, address, data;
  49         uint32_t ficadl_val, ficadh_val;
  50
  51         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  52         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  53
  54         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  55         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
  56         WREG32(data, ficaa_val);
  57
  58         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
  59         ficadl_val = RREG32(data);
  60
  61         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
  62         ficadh_val = RREG32(data);
  63
  64         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  65
  66         return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
  67 }
  68
  69 static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
  70                              uint32_t ficadl_val, uint32_t ficadh_val)
  71 {
  72         unsigned long flags, address, data;
  73
  74         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  75         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  76
  77         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  78         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
  79         WREG32(data, ficaa_val);
  80
  81         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
  82         WREG32(data, ficadl_val);
  83
  84         WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
  85         WREG32(data, ficadh_val);
  86
  87         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  88 }
  89
  90 /*
  91  * df_v3_6_perfmon_rreg - read perfmon lo and hi
  92  *
  93  * required to be atomic.  no mmio method provided so subsequent reads for lo
  94  * and hi require to preserve df finite state machine
  95  */
  96 static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
  97                             uint32_t lo_addr, uint32_t *lo_val,
  98                             uint32_t hi_addr, uint32_t *hi_val)
  99 {
 100         unsigned long flags, address, data;
 101
 102         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 103         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 104
 105         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 106         WREG32(address, lo_addr);
 107         *lo_val = RREG32(data);
 108         WREG32(address, hi_addr);
 109         *hi_val = RREG32(data);
 110         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 111 }
 112
 113 /*
 114  * df_v3_6_perfmon_wreg - write to perfmon lo and hi
 115  *
 116  * required to be atomic.  no mmio method provided so subsequent reads after
 117  * data writes cannot occur to preserve data fabrics finite state machine.
 118  */
 119 static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
 120                             uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
 121 {
 122         unsigned long flags, address, data;
 123
 124         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 125         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 126
 127         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 128         WREG32(address, lo_addr);
 129         WREG32(data, lo_val);
 130         WREG32(address, hi_addr);
 131         WREG32(data, hi_val);
 132         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 133 }
 134
 135 /* same as perfmon_wreg but return status on write value check */
 136 static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev,
 137                                           uint32_t lo_addr, uint32_t lo_val,
 138                                           uint32_t hi_addr, uint32_t  hi_val)
 139 {
 140         unsigned long flags, address, data;
 141         uint32_t lo_val_rb, hi_val_rb;
 142
 143         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 144         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 145
 146         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 147         WREG32(address, lo_addr);
 148         WREG32(data, lo_val);
 149         WREG32(address, hi_addr);
 150         WREG32(data, hi_val);
 151
 152         WREG32(address, lo_addr);
 153         lo_val_rb = RREG32(data);
 154         WREG32(address, hi_addr);
 155         hi_val_rb = RREG32(data);
 156         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 157
 158         if (!(lo_val == lo_val_rb && hi_val == hi_val_rb))
 159                 return -EBUSY;
 160
 161         return 0;
 162 }
 163
 164
 165 /*
 166  * retry arming counters every 100 usecs within 1 millisecond interval.
 167  * if retry fails after time out, return error.
 168  */
 169 #define ARM_RETRY_USEC_TIMEOUT  1000
 170 #define ARM_RETRY_USEC_INTERVAL 100
 171 static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev,
 172                                           uint32_t lo_addr, uint32_t lo_val,
 173                                           uint32_t hi_addr, uint32_t  hi_val)
 174 {
 175         int countdown = ARM_RETRY_USEC_TIMEOUT;
 176
 177         while (countdown) {
 178
 179                 if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val,
 180                                                      hi_addr, hi_val))
 181                         break;
 182
 183                 countdown -= ARM_RETRY_USEC_INTERVAL;
 184                 udelay(ARM_RETRY_USEC_INTERVAL);
 185         }
 186
 187         return countdown > 0 ? 0 : -ETIME;
 188 }
 189
 190 /* get the number of df counters available */
 191 static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
 192                 struct device_attribute *attr,
 193                 char *buf)
 194 {
 195         struct amdgpu_device *adev;
 196         struct drm_device *ddev;
 197         int i, count;
 198
 199         ddev = dev_get_drvdata(dev);
 200         adev = drm_to_adev(ddev);
 201         count = 0;
 202
 203         for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
 204                 if (adev->df_perfmon_config_assign_mask[i] == 0)
 205                         count++;
 206         }
 207
 208         return sysfs_emit(buf, "%i\n", count);
 209 }
 210
 211 /* device attr for available perfmon counters */
 212 static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
 213
 214 static void df_v3_6_query_hashes(struct amdgpu_device *adev)
 215 {
 216         u32 tmp;
 217
 218         adev->df.hash_status.hash_64k = false;
 219         adev->df.hash_status.hash_2m = false;
 220         adev->df.hash_status.hash_1g = false;
 221
 222         /* encoding for hash-enabled on Arcturus and Aldebaran */
 223         if ((adev->asic_type == CHIP_ARCTURUS &&
 224              adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||
 225              (adev->asic_type == CHIP_ALDEBARAN &&
 226               adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {
 227                 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
 228                 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
 229                                                 DF_CS_UMC_AON0_DfGlobalCtrl,
 230                                                 GlbHashIntlvCtl64K);
 231                 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
 232                                                 DF_CS_UMC_AON0_DfGlobalCtrl,
 233                                                 GlbHashIntlvCtl2M);
 234                 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
 235                                                 DF_CS_UMC_AON0_DfGlobalCtrl,
 236                                                 GlbHashIntlvCtl1G);
 237         }
 238 }
 239
 240 /* init perfmons */
 241 static void df_v3_6_sw_init(struct amdgpu_device *adev)
 242 {
 243         int i, ret;
 244
 245         ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
 246         if (ret)
 247                 DRM_ERROR("failed to create file for available df counters\n");
 248
 249         for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
 250                 adev->df_perfmon_config_assign_mask[i] = 0;
 251
 252         df_v3_6_query_hashes(adev);
 253 }
 254
 255 static void df_v3_6_sw_fini(struct amdgpu_device *adev)
 256 {
 257
 258         device_remove_file(adev->dev, &dev_attr_df_cntr_avail);
 259
 260 }
 261
 262 static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
 263                                           bool enable)
 264 {
 265         u32 tmp;
 266
 267         if (enable) {
 268                 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
 269                 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 270                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
 271         } else
 272                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
 273                              mmFabricConfigAccessControl_DEFAULT);
 274 }
 275
 276 static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
 277 {
 278         u32 tmp;
 279
 280         tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
 281         if (adev->asic_type == CHIP_ALDEBARAN)
 282                 tmp &=
 283                 ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
 284         else
 285                 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
 286
 287         tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 288
 289         return tmp;
 290 }
 291
 292 static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
 293 {
 294         int fb_channel_number;
 295
 296         fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
 297         if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
 298                 fb_channel_number = 0;
 299
 300         return df_v3_6_channel_number[fb_channel_number];
 301 }
 302
 303 static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 304                                                      bool enable)
 305 {
 306         u32 tmp;
 307
 308         if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
 309                 /* Put DF on broadcast mode */
 310                 adev->df.funcs->enable_broadcast_mode(adev, true);
 311
 312                 if (enable) {
 313                         tmp = RREG32_SOC15(DF, 0,
 314                                         mmDF_PIE_AON0_DfGlobalClkGater);
 315                         tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 316                         tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
 317                         WREG32_SOC15(DF, 0,
 318                                         mmDF_PIE_AON0_DfGlobalClkGater, tmp);
 319                 } else {
 320                         tmp = RREG32_SOC15(DF, 0,
 321                                         mmDF_PIE_AON0_DfGlobalClkGater);
 322                         tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 323                         tmp |= DF_V3_6_MGCG_DISABLE;
 324                         WREG32_SOC15(DF, 0,
 325                                         mmDF_PIE_AON0_DfGlobalClkGater, tmp);
 326                 }
 327
 328                 /* Exit broadcast mode */
 329                 adev->df.funcs->enable_broadcast_mode(adev, false);
 330         }
 331 }
 332
 333 static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
 334                                           u32 *flags)
 335 {
 336         u32 tmp;
 337
 338         /* AMD_CG_SUPPORT_DF_MGCG */
 339         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
 340         if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
 341                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 342 }
 343
 344 /* get assigned df perfmon ctr as int */
 345 static bool df_v3_6_pmc_has_counter(struct amdgpu_device *adev,
 346                                       uint64_t config,
 347                                       int counter_idx)
 348 {
 349
 350         return ((config & 0x0FFFFFFUL) ==
 351                         adev->df_perfmon_config_assign_mask[counter_idx]);
 352
 353 }
 354
 355 /* get address based on counter assignment */
 356 static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
 357                                  uint64_t config,
 358                                  int counter_idx,
 359                                  int is_ctrl,
 360                                  uint32_t *lo_base_addr,
 361                                  uint32_t *hi_base_addr)
 362 {
 363         if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
 364                 return;
 365
 366         switch (counter_idx) {
 367
 368         case 0:
 369                 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4;
 370                 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi4 : smnPerfMonCtrHi4;
 371                 break;
 372         case 1:
 373                 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5;
 374                 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi5 : smnPerfMonCtrHi5;
 375                 break;
 376         case 2:
 377                 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6;
 378                 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi6 : smnPerfMonCtrHi6;
 379                 break;
 380         case 3:
 381                 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7;
 382                 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi7 : smnPerfMonCtrHi7;
 383                 break;
 384
 385         }
 386
 387 }
 388
 389 /* get read counter address */
 390 static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
 391                                           uint64_t config,
 392                                           int counter_idx,
 393                                           uint32_t *lo_base_addr,
 394                                           uint32_t *hi_base_addr)
 395 {
 396         df_v3_6_pmc_get_addr(adev, config, counter_idx, 0, lo_base_addr,
 397                                                                 hi_base_addr);
 398 }
 399
 400 /* get control counter settings i.e. address and values to set */
 401 static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
 402                                           uint64_t config,
 403                                           int counter_idx,
 404                                           uint32_t *lo_base_addr,
 405                                           uint32_t *hi_base_addr,
 406                                           uint32_t *lo_val,
 407                                           uint32_t *hi_val,
 408                                           bool is_enable)
 409 {
 410
 411         uint32_t eventsel, instance, unitmask;
 412         uint32_t instance_10, instance_5432, instance_76;
 413
 414         df_v3_6_pmc_get_addr(adev, config, counter_idx, 1, lo_base_addr,
 415                                 hi_base_addr);
 416
 417         if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
 418                 DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
 419                                 *lo_base_addr, *hi_base_addr);
 420                 return -ENXIO;
 421         }
 422
 423         eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
 424         unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
 425         instance = DF_V3_6_GET_INSTANCE(config);
 426
 427         instance_10 = instance & 0x3;
 428         instance_5432 = (instance >> 2) & 0xf;
 429         instance_76 = (instance >> 6) & 0x3;
 430
 431         *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
 432         *lo_val = is_enable ? *lo_val | (1 << 22) : *lo_val & ~(1 << 22);
 433         *hi_val = (instance_76 << 29) | instance_5432;
 434
 435         DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
 436                 config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
 437
 438         return 0;
 439 }
 440
 441 /* add df performance counters for read */
 442 static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
 443                                    uint64_t config)
 444 {
 445         int i;
 446
 447         for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
 448                 if (adev->df_perfmon_config_assign_mask[i] == 0U) {
 449                         adev->df_perfmon_config_assign_mask[i] =
 450                                                         config & 0x0FFFFFFUL;
 451                         return i;
 452                 }
 453         }
 454
 455         return -ENOSPC;
 456 }
 457
 458 #define DEFERRED_ARM_MASK       (1 << 31)
 459 static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
 460                                     int counter_idx, uint64_t config,
 461                                     bool is_deferred)
 462 {
 463
 464         if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
 465                 return -EINVAL;
 466
 467         if (is_deferred)
 468                 adev->df_perfmon_config_assign_mask[counter_idx] |=
 469                                                         DEFERRED_ARM_MASK;
 470         else
 471                 adev->df_perfmon_config_assign_mask[counter_idx] &=
 472                                                         ~DEFERRED_ARM_MASK;
 473
 474         return 0;
 475 }
 476
 477 static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
 478                                     int counter_idx,
 479                                     uint64_t config)
 480 {
 481         return  (df_v3_6_pmc_has_counter(adev, config, counter_idx) &&
 482                         (adev->df_perfmon_config_assign_mask[counter_idx]
 483                                 & DEFERRED_ARM_MASK));
 484
 485 }
 486
 487 /* release performance counter */
 488 static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
 489                                      uint64_t config,
 490                                      int counter_idx)
 491 {
 492         if (df_v3_6_pmc_has_counter(adev, config, counter_idx))
 493                 adev->df_perfmon_config_assign_mask[counter_idx] = 0ULL;
 494 }
 495
 496
 497 static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
 498                                          uint64_t config,
 499                                          int counter_idx)
 500 {
 501         uint32_t lo_base_addr = 0, hi_base_addr = 0;
 502
 503         df_v3_6_pmc_get_read_settings(adev, config, counter_idx, &lo_base_addr,
 504                                       &hi_base_addr);
 505
 506         if ((lo_base_addr == 0) || (hi_base_addr == 0))
 507                 return;
 508
 509         df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
 510 }
 511
 512 /* return available counter if is_add == 1 otherwise return error status. */
 513 static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
 514                              int counter_idx, int is_add)
 515 {
 516         uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
 517         int err = 0, ret = 0;
 518
 519         switch (adev->asic_type) {
 520         case CHIP_VEGA20:
 521         case CHIP_ARCTURUS:
 522                 if (is_add)
 523                         return df_v3_6_pmc_add_cntr(adev, config);
 524
 525                 ret = df_v3_6_pmc_get_ctrl_settings(adev,
 526                                         config,
 527                                         counter_idx,
 528                                         &lo_base_addr,
 529                                         &hi_base_addr,
 530                                         &lo_val,
 531                                         &hi_val,
 532                                         true);
 533
 534                 if (ret)
 535                         return ret;
 536
 537                 err = df_v3_6_perfmon_arm_with_retry(adev,
 538                                                      lo_base_addr,
 539                                                      lo_val,
 540                                                      hi_base_addr,
 541                                                      hi_val);
 542
 543                 if (err)
 544                         ret = df_v3_6_pmc_set_deferred(adev, config,
 545                                                         counter_idx, true);
 546
 547                 break;
 548         default:
 549                 break;
 550         }
 551
 552         return ret;
 553 }
 554
 555 static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
 556                             int counter_idx, int is_remove)
 557 {
 558         uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
 559         int ret = 0;
 560
 561         switch (adev->asic_type) {
 562         case CHIP_VEGA20:
 563         case CHIP_ARCTURUS:
 564                 ret = df_v3_6_pmc_get_ctrl_settings(adev,
 565                         config,
 566                         counter_idx,
 567                         &lo_base_addr,
 568                         &hi_base_addr,
 569                         &lo_val,
 570                         &hi_val,
 571                         false);
 572
 573                 if (ret)
 574                         return ret;
 575
 576                 df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
 577                                                         hi_base_addr, hi_val);
 578
 579                 if (is_remove) {
 580                         df_v3_6_reset_perfmon_cntr(adev, config, counter_idx);
 581                         df_v3_6_pmc_release_cntr(adev, config, counter_idx);
 582                 }
 583
 584                 break;
 585         default:
 586                 break;
 587         }
 588
 589         return ret;
 590 }
 591
 592 static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
 593                                   uint64_t config,
 594                                   int counter_idx,
 595                                   uint64_t *count)
 596 {
 597         uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0;
 598         *count = 0;
 599
 600         switch (adev->asic_type) {
 601         case CHIP_VEGA20:
 602         case CHIP_ARCTURUS:
 603                 df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
 604                                                 &lo_base_addr, &hi_base_addr);
 605
 606                 if ((lo_base_addr == 0) || (hi_base_addr == 0))
 607                         return;
 608
 609                 /* rearm the counter or throw away count value on failure */
 610                 if (df_v3_6_pmc_is_deferred(adev, config, counter_idx)) {
 611                         int rearm_err = df_v3_6_perfmon_arm_with_status(adev,
 612                                                         lo_base_addr, lo_val,
 613                                                         hi_base_addr, hi_val);
 614
 615                         if (rearm_err)
 616                                 return;
 617
 618                         df_v3_6_pmc_set_deferred(adev, config, counter_idx,
 619                                                                         false);
 620                 }
 621
 622                 df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
 623                                 hi_base_addr, &hi_val);
 624
 625                 *count  = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
 626
 627                 if (*count >= DF_V3_6_PERFMON_OVERFLOW)
 628                         *count = 0;
 629
 630                 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
 631                          config, lo_base_addr, hi_base_addr, lo_val, hi_val);
 632
 633                 break;
 634         default:
 635                 break;
 636         }
 637 }
 638
 639 const struct amdgpu_df_funcs df_v3_6_funcs = {
 640         .sw_init = df_v3_6_sw_init,
 641         .sw_fini = df_v3_6_sw_fini,
 642         .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
 643         .get_fb_channel_number = df_v3_6_get_fb_channel_number,
 644         .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
 645         .update_medium_grain_clock_gating =
 646                         df_v3_6_update_medium_grain_clock_gating,
 647         .get_clockgating_state = df_v3_6_get_clockgating_state,
 648         .pmc_start = df_v3_6_pmc_start,
 649         .pmc_stop = df_v3_6_pmc_stop,
 650         .pmc_get_count = df_v3_6_pmc_get_count,
 651         .get_fica = df_v3_6_get_fica,
 652         .set_fica = df_v3_6_set_fica,
 653 };