drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32
  33 #include "vid.h"
  34 #include "amdgpu.h"
  35 #include "amdgpu_display.h"
  36 #include "amdgpu_ucode.h"
  37 #include "atom.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_pm.h"
  40
  41 #include "amd_shared.h"
  42 #include "amdgpu_dm_irq.h"
  43 #include "dm_helpers.h"
  44 #include "amdgpu_dm_mst_types.h"
  45 #if defined(CONFIG_DEBUG_FS)
  46 #include "amdgpu_dm_debugfs.h"
  47 #endif
  48
  49 #include "ivsrcid/ivsrcid_vislands30.h"
  50
  51 #include <linux/module.h>
  52 #include <linux/moduleparam.h>
  53 #include <linux/version.h>
  54 #include <linux/types.h>
  55 #include <linux/pm_runtime.h>
  56 #include <linux/firmware.h>
  57
  58 #include <drm/drmP.h>
  59 #include <drm/drm_atomic.h>
  60 #include <drm/drm_atomic_uapi.h>
  61 #include <drm/drm_atomic_helper.h>
  62 #include <drm/drm_dp_mst_helper.h>
  63 #include <drm/drm_fb_helper.h>
  64 #include <drm/drm_edid.h>
  65
  66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  67 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  68
  69 #include "dcn/dcn_1_0_offset.h"
  70 #include "dcn/dcn_1_0_sh_mask.h"
  71 #include "soc15_hw_ip.h"
  72 #include "vega10_ip_offset.h"
  73
  74 #include "soc15_common.h"
  75 #endif
  76
  77 #include "modules/inc/mod_freesync.h"
  78 #include "modules/power/power_helpers.h"
  79 #include "modules/inc/mod_info_packet.h"
  80
  81 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  83
  84 /**
  85  * DOC: overview
  86  *
  87  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  88  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  89  * requests into DC requests, and DC responses into DRM responses.
  90  *
  91  * The root control structure is &struct amdgpu_display_manager.
  92  */
  93
  94 /* basic init/fini API */
  95 static int amdgpu_dm_init(struct amdgpu_device *adev);
  96 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  97
  98 /*
  99  * initializes drm_device display related structures, based on the information
 100  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 101  * drm_encoder, drm_mode_config
 102  *
 103  * Returns 0 on success
 104  */
 105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 106 /* removes and deallocates the drm structures, created by the above function */
 107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 108
 109 static void
 110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 111
 112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 113                                 struct drm_plane *plane,
 114                                 unsigned long possible_crtcs);
 115 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 116                                struct drm_plane *plane,
 117                                uint32_t link_index);
 118 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 119                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 120                                     uint32_t link_index,
 121                                     struct amdgpu_encoder *amdgpu_encoder);
 122 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 123                                   struct amdgpu_encoder *aencoder,
 124                                   uint32_t link_index);
 125
 126 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 127
 128 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 129                                    struct drm_atomic_state *state,
 130                                    bool nonblock);
 131
 132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 133
 134 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 135                                   struct drm_atomic_state *state);
 136
 137 static void handle_cursor_update(struct drm_plane *plane,
 138                                  struct drm_plane_state *old_plane_state);
 139
 140
 141
 142 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
 143         DRM_PLANE_TYPE_PRIMARY,
 144         DRM_PLANE_TYPE_PRIMARY,
 145         DRM_PLANE_TYPE_PRIMARY,
 146         DRM_PLANE_TYPE_PRIMARY,
 147         DRM_PLANE_TYPE_PRIMARY,
 148         DRM_PLANE_TYPE_PRIMARY,
 149 };
 150
 151 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
 152         DRM_PLANE_TYPE_PRIMARY,
 153         DRM_PLANE_TYPE_PRIMARY,
 154         DRM_PLANE_TYPE_PRIMARY,
 155         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 156 };
 157
 158 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
 159         DRM_PLANE_TYPE_PRIMARY,
 160         DRM_PLANE_TYPE_PRIMARY,
 161         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
 162 };
 163
 164 /*
 165  * dm_vblank_get_counter
 166  *
 167  * @brief
 168  * Get counter for number of vertical blanks
 169  *
 170  * @param
 171  * struct amdgpu_device *adev - [in] desired amdgpu device
 172  * int disp_idx - [in] which CRTC to get the counter from
 173  *
 174  * @return
 175  * Counter for vertical blanks
 176  */
 177 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 178 {
 179         if (crtc >= adev->mode_info.num_crtc)
 180                 return 0;
 181         else {
 182                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 183                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 184                                 acrtc->base.state);
 185
 186
 187                 if (acrtc_state->stream == NULL) {
 188                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 189                                   crtc);
 190                         return 0;
 191                 }
 192
 193                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 194         }
 195 }
 196
 197 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 198                                   u32 *vbl, u32 *position)
 199 {
 200         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 201
 202         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 203                 return -EINVAL;
 204         else {
 205                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 206                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 207                                                 acrtc->base.state);
 208
 209                 if (acrtc_state->stream ==  NULL) {
 210                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 211                                   crtc);
 212                         return 0;
 213                 }
 214
 215                 /*
 216                  * TODO rework base driver to use values directly.
 217                  * for now parse it back into reg-format
 218                  */
 219                 dc_stream_get_scanoutpos(acrtc_state->stream,
 220                                          &v_blank_start,
 221                                          &v_blank_end,
 222                                          &h_position,
 223                                          &v_position);
 224
 225                 *position = v_position | (h_position << 16);
 226                 *vbl = v_blank_start | (v_blank_end << 16);
 227         }
 228
 229         return 0;
 230 }
 231
 232 static bool dm_is_idle(void *handle)
 233 {
 234         /* XXX todo */
 235         return true;
 236 }
 237
 238 static int dm_wait_for_idle(void *handle)
 239 {
 240         /* XXX todo */
 241         return 0;
 242 }
 243
 244 static bool dm_check_soft_reset(void *handle)
 245 {
 246         return false;
 247 }
 248
 249 static int dm_soft_reset(void *handle)
 250 {
 251         /* XXX todo */
 252         return 0;
 253 }
 254
 255 static struct amdgpu_crtc *
 256 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 257                      int otg_inst)
 258 {
 259         struct drm_device *dev = adev->ddev;
 260         struct drm_crtc *crtc;
 261         struct amdgpu_crtc *amdgpu_crtc;
 262
 263         if (otg_inst == -1) {
 264                 WARN_ON(1);
 265                 return adev->mode_info.crtcs[0];
 266         }
 267
 268         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 269                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 270
 271                 if (amdgpu_crtc->otg_inst == otg_inst)
 272                         return amdgpu_crtc;
 273         }
 274
 275         return NULL;
 276 }
 277
 278 static void dm_pflip_high_irq(void *interrupt_params)
 279 {
 280         struct amdgpu_crtc *amdgpu_crtc;
 281         struct common_irq_params *irq_params = interrupt_params;
 282         struct amdgpu_device *adev = irq_params->adev;
 283         unsigned long flags;
 284
 285         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 286
 287         /* IRQ could occur when in initial stage */
 288         /* TODO work and BO cleanup */
 289         if (amdgpu_crtc == NULL) {
 290                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 291                 return;
 292         }
 293
 294         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 295
 296         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 297                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 298                                                  amdgpu_crtc->pflip_status,
 299                                                  AMDGPU_FLIP_SUBMITTED,
 300                                                  amdgpu_crtc->crtc_id,
 301                                                  amdgpu_crtc);
 302                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 303                 return;
 304         }
 305
 306
 307         /* wake up userspace */
 308         if (amdgpu_crtc->event) {
 309                 /* Update to correct count(s) if racing with vblank irq */
 310                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 311
 312                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 313
 314                 /* page flip completed. clean up */
 315                 amdgpu_crtc->event = NULL;
 316
 317         } else
 318                 WARN_ON(1);
 319
 320         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 321         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 322
 323         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 324                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 325
 326         drm_crtc_vblank_put(&amdgpu_crtc->base);
 327 }
 328
 329 static void dm_crtc_high_irq(void *interrupt_params)
 330 {
 331         struct common_irq_params *irq_params = interrupt_params;
 332         struct amdgpu_device *adev = irq_params->adev;
 333         struct amdgpu_crtc *acrtc;
 334         struct dm_crtc_state *acrtc_state;
 335
 336         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 337
 338         if (acrtc) {
 339                 drm_crtc_handle_vblank(&acrtc->base);
 340                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 341
 342                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 343
 344                 if (acrtc_state->stream &&
 345                     acrtc_state->vrr_params.supported &&
 346                     acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 347                         mod_freesync_handle_v_update(
 348                                 adev->dm.freesync_module,
 349                                 acrtc_state->stream,
 350                                 &acrtc_state->vrr_params);
 351
 352                         dc_stream_adjust_vmin_vmax(
 353                                 adev->dm.dc,
 354                                 acrtc_state->stream,
 355                                 &acrtc_state->vrr_params.adjust);
 356                 }
 357         }
 358 }
 359
 360 static int dm_set_clockgating_state(void *handle,
 361                   enum amd_clockgating_state state)
 362 {
 363         return 0;
 364 }
 365
 366 static int dm_set_powergating_state(void *handle,
 367                   enum amd_powergating_state state)
 368 {
 369         return 0;
 370 }
 371
 372 /* Prototypes of private functions */
 373 static int dm_early_init(void* handle);
 374
 375 /* Allocate memory for FBC compressed data  */
 376 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 377 {
 378         struct drm_device *dev = connector->dev;
 379         struct amdgpu_device *adev = dev->dev_private;
 380         struct dm_comressor_info *compressor = &adev->dm.compressor;
 381         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 382         struct drm_display_mode *mode;
 383         unsigned long max_size = 0;
 384
 385         if (adev->dm.dc->fbc_compressor == NULL)
 386                 return;
 387
 388         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 389                 return;
 390
 391         if (compressor->bo_ptr)
 392                 return;
 393
 394
 395         list_for_each_entry(mode, &connector->modes, head) {
 396                 if (max_size < mode->htotal * mode->vtotal)
 397                         max_size = mode->htotal * mode->vtotal;
 398         }
 399
 400         if (max_size) {
 401                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 402                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 403                             &compressor->gpu_addr, &compressor->cpu_addr);
 404
 405                 if (r)
 406                         DRM_ERROR("DM: Failed to initialize FBC\n");
 407                 else {
 408                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 409                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 410                 }
 411
 412         }
 413
 414 }
 415
 416 static int amdgpu_dm_init(struct amdgpu_device *adev)
 417 {
 418         struct dc_init_data init_data;
 419         adev->dm.ddev = adev->ddev;
 420         adev->dm.adev = adev;
 421
 422         /* Zero all the fields */
 423         memset(&init_data, 0, sizeof(init_data));
 424
 425         mutex_init(&adev->dm.dc_lock);
 426
 427         if(amdgpu_dm_irq_init(adev)) {
 428                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 429                 goto error;
 430         }
 431
 432         init_data.asic_id.chip_family = adev->family;
 433
 434         init_data.asic_id.pci_revision_id = adev->rev_id;
 435         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 436
 437         init_data.asic_id.vram_width = adev->gmc.vram_width;
 438         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 439         init_data.asic_id.atombios_base_address =
 440                 adev->mode_info.atom_context->bios;
 441
 442         init_data.driver = adev;
 443
 444         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 445
 446         if (!adev->dm.cgs_device) {
 447                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 448                 goto error;
 449         }
 450
 451         init_data.cgs_device = adev->dm.cgs_device;
 452
 453         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 454
 455         /*
 456          * TODO debug why this doesn't work on Raven
 457          */
 458         if (adev->flags & AMD_IS_APU &&
 459             adev->asic_type >= CHIP_CARRIZO &&
 460             adev->asic_type < CHIP_RAVEN)
 461                 init_data.flags.gpu_vm_support = true;
 462
 463         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 464                 init_data.flags.fbc_support = true;
 465
 466         /* Display Core create. */
 467         adev->dm.dc = dc_create(&init_data);
 468
 469         if (adev->dm.dc) {
 470                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 471         } else {
 472                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 473                 goto error;
 474         }
 475
 476         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 477         if (!adev->dm.freesync_module) {
 478                 DRM_ERROR(
 479                 "amdgpu: failed to initialize freesync_module.\n");
 480         } else
 481                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 482                                 adev->dm.freesync_module);
 483
 484         amdgpu_dm_init_color_mod();
 485
 486         if (amdgpu_dm_initialize_drm_device(adev)) {
 487                 DRM_ERROR(
 488                 "amdgpu: failed to initialize sw for display support.\n");
 489                 goto error;
 490         }
 491
 492         /* Update the actual used number of crtc */
 493         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 494
 495         /* TODO: Add_display_info? */
 496
 497         /* TODO use dynamic cursor width */
 498         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 499         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 500
 501         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 502                 DRM_ERROR(
 503                 "amdgpu: failed to initialize sw for display support.\n");
 504                 goto error;
 505         }
 506
 507 #if defined(CONFIG_DEBUG_FS)
 508         if (dtn_debugfs_init(adev))
 509                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 510 #endif
 511
 512         DRM_DEBUG_DRIVER("KMS initialized.\n");
 513
 514         return 0;
 515 error:
 516         amdgpu_dm_fini(adev);
 517
 518         return -EINVAL;
 519 }
 520
 521 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 522 {
 523         amdgpu_dm_destroy_drm_device(&adev->dm);
 524         /*
 525          * TODO: pageflip, vlank interrupt
 526          *
 527          * amdgpu_dm_irq_fini(adev);
 528          */
 529
 530         if (adev->dm.cgs_device) {
 531                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 532                 adev->dm.cgs_device = NULL;
 533         }
 534         if (adev->dm.freesync_module) {
 535                 mod_freesync_destroy(adev->dm.freesync_module);
 536                 adev->dm.freesync_module = NULL;
 537         }
 538         /* DC Destroy TODO: Replace destroy DAL */
 539         if (adev->dm.dc)
 540                 dc_destroy(&adev->dm.dc);
 541
 542         mutex_destroy(&adev->dm.dc_lock);
 543
 544         return;
 545 }
 546
 547 static int load_dmcu_fw(struct amdgpu_device *adev)
 548 {
 549         const char *fw_name_dmcu;
 550         int r;
 551         const struct dmcu_firmware_header_v1_0 *hdr;
 552
 553         switch(adev->asic_type) {
 554         case CHIP_BONAIRE:
 555         case CHIP_HAWAII:
 556         case CHIP_KAVERI:
 557         case CHIP_KABINI:
 558         case CHIP_MULLINS:
 559         case CHIP_TONGA:
 560         case CHIP_FIJI:
 561         case CHIP_CARRIZO:
 562         case CHIP_STONEY:
 563         case CHIP_POLARIS11:
 564         case CHIP_POLARIS10:
 565         case CHIP_POLARIS12:
 566         case CHIP_VEGAM:
 567         case CHIP_VEGA10:
 568         case CHIP_VEGA12:
 569         case CHIP_VEGA20:
 570                 return 0;
 571         case CHIP_RAVEN:
 572                 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 573                 break;
 574         default:
 575                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 576                 return -EINVAL;
 577         }
 578
 579         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 580                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 581                 return 0;
 582         }
 583
 584         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 585         if (r == -ENOENT) {
 586                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 587                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 588                 adev->dm.fw_dmcu = NULL;
 589                 return 0;
 590         }
 591         if (r) {
 592                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 593                         fw_name_dmcu);
 594                 return r;
 595         }
 596
 597         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 598         if (r) {
 599                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 600                         fw_name_dmcu);
 601                 release_firmware(adev->dm.fw_dmcu);
 602                 adev->dm.fw_dmcu = NULL;
 603                 return r;
 604         }
 605
 606         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 607         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 608         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 609         adev->firmware.fw_size +=
 610                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 611
 612         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 613         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 614         adev->firmware.fw_size +=
 615                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 616
 617         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 618
 619         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 620
 621         return 0;
 622 }
 623
 624 static int dm_sw_init(void *handle)
 625 {
 626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 627
 628         return load_dmcu_fw(adev);
 629 }
 630
 631 static int dm_sw_fini(void *handle)
 632 {
 633         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 634
 635         if(adev->dm.fw_dmcu) {
 636                 release_firmware(adev->dm.fw_dmcu);
 637                 adev->dm.fw_dmcu = NULL;
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 644 {
 645         struct amdgpu_dm_connector *aconnector;
 646         struct drm_connector *connector;
 647         int ret = 0;
 648
 649         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 650
 651         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 652                 aconnector = to_amdgpu_dm_connector(connector);
 653                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 654                     aconnector->mst_mgr.aux) {
 655                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 656                                         aconnector, aconnector->base.base.id);
 657
 658                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 659                         if (ret < 0) {
 660                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 661                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 662                                 return ret;
 663                                 }
 664                         }
 665         }
 666
 667         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 668         return ret;
 669 }
 670
 671 static int dm_late_init(void *handle)
 672 {
 673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 674
 675         struct dmcu_iram_parameters params;
 676         unsigned int linear_lut[16];
 677         int i;
 678         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 679         bool ret;
 680
 681         for (i = 0; i < 16; i++)
 682                 linear_lut[i] = 0xFFFF * i / 15;
 683
 684         params.set = 0;
 685         params.backlight_ramping_start = 0xCCCC;
 686         params.backlight_ramping_reduction = 0xCCCCCCCC;
 687         params.backlight_lut_array_size = 16;
 688         params.backlight_lut_array = linear_lut;
 689
 690         ret = dmcu_load_iram(dmcu, params);
 691
 692         if (!ret)
 693                 return -EINVAL;
 694
 695         return detect_mst_link_for_all_connectors(adev->ddev);
 696 }
 697
 698 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 699 {
 700         struct amdgpu_dm_connector *aconnector;
 701         struct drm_connector *connector;
 702         struct drm_dp_mst_topology_mgr *mgr;
 703         int ret;
 704         bool need_hotplug = false;
 705
 706         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 707
 708         list_for_each_entry(connector, &dev->mode_config.connector_list,
 709                             head) {
 710                 aconnector = to_amdgpu_dm_connector(connector);
 711                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
 712                     aconnector->mst_port)
 713                         continue;
 714
 715                 mgr = &aconnector->mst_mgr;
 716
 717                 if (suspend) {
 718                         drm_dp_mst_topology_mgr_suspend(mgr);
 719                 } else {
 720                         ret = drm_dp_mst_topology_mgr_resume(mgr);
 721                         if (ret < 0) {
 722                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
 723                                 need_hotplug = true;
 724                         }
 725                 }
 726         }
 727
 728         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 729
 730         if (need_hotplug)
 731                 drm_kms_helper_hotplug_event(dev);
 732 }
 733
 734 /**
 735  * dm_hw_init() - Initialize DC device
 736  * @handle: The base driver device containing the amdpgu_dm device.
 737  *
 738  * Initialize the &struct amdgpu_display_manager device. This involves calling
 739  * the initializers of each DM component, then populating the struct with them.
 740  *
 741  * Although the function implies hardware initialization, both hardware and
 742  * software are initialized here. Splitting them out to their relevant init
 743  * hooks is a future TODO item.
 744  *
 745  * Some notable things that are initialized here:
 746  *
 747  * - Display Core, both software and hardware
 748  * - DC modules that we need (freesync and color management)
 749  * - DRM software states
 750  * - Interrupt sources and handlers
 751  * - Vblank support
 752  * - Debug FS entries, if enabled
 753  */
 754 static int dm_hw_init(void *handle)
 755 {
 756         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 757         /* Create DAL display manager */
 758         amdgpu_dm_init(adev);
 759         amdgpu_dm_hpd_init(adev);
 760
 761         return 0;
 762 }
 763
 764 /**
 765  * dm_hw_fini() - Teardown DC device
 766  * @handle: The base driver device containing the amdpgu_dm device.
 767  *
 768  * Teardown components within &struct amdgpu_display_manager that require
 769  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
 770  * were loaded. Also flush IRQ workqueues and disable them.
 771  */
 772 static int dm_hw_fini(void *handle)
 773 {
 774         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 775
 776         amdgpu_dm_hpd_fini(adev);
 777
 778         amdgpu_dm_irq_fini(adev);
 779         amdgpu_dm_fini(adev);
 780         return 0;
 781 }
 782
 783 static int dm_suspend(void *handle)
 784 {
 785         struct amdgpu_device *adev = handle;
 786         struct amdgpu_display_manager *dm = &adev->dm;
 787         int ret = 0;
 788
 789         s3_handle_mst(adev->ddev, true);
 790
 791         amdgpu_dm_irq_suspend(adev);
 792
 793         WARN_ON(adev->dm.cached_state);
 794         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 795
 796         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 797
 798         return ret;
 799 }
 800
 801 static struct amdgpu_dm_connector *
 802 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 803                                              struct drm_crtc *crtc)
 804 {
 805         uint32_t i;
 806         struct drm_connector_state *new_con_state;
 807         struct drm_connector *connector;
 808         struct drm_crtc *crtc_from_state;
 809
 810         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 811                 crtc_from_state = new_con_state->crtc;
 812
 813                 if (crtc_from_state == crtc)
 814                         return to_amdgpu_dm_connector(connector);
 815         }
 816
 817         return NULL;
 818 }
 819
 820 static void emulated_link_detect(struct dc_link *link)
 821 {
 822         struct dc_sink_init_data sink_init_data = { 0 };
 823         struct display_sink_capability sink_caps = { 0 };
 824         enum dc_edid_status edid_status;
 825         struct dc_context *dc_ctx = link->ctx;
 826         struct dc_sink *sink = NULL;
 827         struct dc_sink *prev_sink = NULL;
 828
 829         link->type = dc_connection_none;
 830         prev_sink = link->local_sink;
 831
 832         if (prev_sink != NULL)
 833                 dc_sink_retain(prev_sink);
 834
 835         switch (link->connector_signal) {
 836         case SIGNAL_TYPE_HDMI_TYPE_A: {
 837                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 838                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 839                 break;
 840         }
 841
 842         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 843                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 844                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 845                 break;
 846         }
 847
 848         case SIGNAL_TYPE_DVI_DUAL_LINK: {
 849                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 850                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 851                 break;
 852         }
 853
 854         case SIGNAL_TYPE_LVDS: {
 855                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 856                 sink_caps.signal = SIGNAL_TYPE_LVDS;
 857                 break;
 858         }
 859
 860         case SIGNAL_TYPE_EDP: {
 861                 sink_caps.transaction_type =
 862                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 863                 sink_caps.signal = SIGNAL_TYPE_EDP;
 864                 break;
 865         }
 866
 867         case SIGNAL_TYPE_DISPLAY_PORT: {
 868                 sink_caps.transaction_type =
 869                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 870                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
 871                 break;
 872         }
 873
 874         default:
 875                 DC_ERROR("Invalid connector type! signal:%d\n",
 876                         link->connector_signal);
 877                 return;
 878         }
 879
 880         sink_init_data.link = link;
 881         sink_init_data.sink_signal = sink_caps.signal;
 882
 883         sink = dc_sink_create(&sink_init_data);
 884         if (!sink) {
 885                 DC_ERROR("Failed to create sink!\n");
 886                 return;
 887         }
 888
 889         link->local_sink = sink;
 890
 891         edid_status = dm_helpers_read_local_edid(
 892                         link->ctx,
 893                         link,
 894                         sink);
 895
 896         if (edid_status != EDID_OK)
 897                 DC_ERROR("Failed to read EDID");
 898
 899 }
 900
 901 static int dm_resume(void *handle)
 902 {
 903         struct amdgpu_device *adev = handle;
 904         struct drm_device *ddev = adev->ddev;
 905         struct amdgpu_display_manager *dm = &adev->dm;
 906         struct amdgpu_dm_connector *aconnector;
 907         struct drm_connector *connector;
 908         struct drm_crtc *crtc;
 909         struct drm_crtc_state *new_crtc_state;
 910         struct dm_crtc_state *dm_new_crtc_state;
 911         struct drm_plane *plane;
 912         struct drm_plane_state *new_plane_state;
 913         struct dm_plane_state *dm_new_plane_state;
 914         enum dc_connection_type new_connection_type = dc_connection_none;
 915         int i;
 916
 917         /* power on hardware */
 918         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 919
 920         /* program HPD filter */
 921         dc_resume(dm->dc);
 922
 923         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 924         s3_handle_mst(ddev, false);
 925
 926         /*
 927          * early enable HPD Rx IRQ, should be done before set mode as short
 928          * pulse interrupts are used for MST
 929          */
 930         amdgpu_dm_irq_resume_early(adev);
 931
 932         /* Do detection*/
 933         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
 934                 aconnector = to_amdgpu_dm_connector(connector);
 935
 936                 /*
 937                  * this is the case when traversing through already created
 938                  * MST connectors, should be skipped
 939                  */
 940                 if (aconnector->mst_port)
 941                         continue;
 942
 943                 mutex_lock(&aconnector->hpd_lock);
 944                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
 945                         DRM_ERROR("KMS: Failed to detect connector\n");
 946
 947                 if (aconnector->base.force && new_connection_type == dc_connection_none)
 948                         emulated_link_detect(aconnector->dc_link);
 949                 else
 950                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 951
 952                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
 953                         aconnector->fake_enable = false;
 954
 955                 aconnector->dc_sink = NULL;
 956                 amdgpu_dm_update_connector_after_detect(aconnector);
 957                 mutex_unlock(&aconnector->hpd_lock);
 958         }
 959
 960         /* Force mode set in atomic commit */
 961         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
 962                 new_crtc_state->active_changed = true;
 963
 964         /*
 965          * atomic_check is expected to create the dc states. We need to release
 966          * them here, since they were duplicated as part of the suspend
 967          * procedure.
 968          */
 969         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
 970                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 971                 if (dm_new_crtc_state->stream) {
 972                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
 973                         dc_stream_release(dm_new_crtc_state->stream);
 974                         dm_new_crtc_state->stream = NULL;
 975                 }
 976         }
 977
 978         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
 979                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
 980                 if (dm_new_plane_state->dc_state) {
 981                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
 982                         dc_plane_state_release(dm_new_plane_state->dc_state);
 983                         dm_new_plane_state->dc_state = NULL;
 984                 }
 985         }
 986
 987         drm_atomic_helper_resume(ddev, dm->cached_state);
 988
 989         dm->cached_state = NULL;
 990
 991         amdgpu_dm_irq_resume_late(adev);
 992
 993         return 0;
 994 }
 995
 996 /**
 997  * DOC: DM Lifecycle
 998  *
 999  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1000  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1001  * the base driver's device list to be initialized and torn down accordingly.
1002  *
1003  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1004  */
1005
1006 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1007         .name = "dm",
1008         .early_init = dm_early_init,
1009         .late_init = dm_late_init,
1010         .sw_init = dm_sw_init,
1011         .sw_fini = dm_sw_fini,
1012         .hw_init = dm_hw_init,
1013         .hw_fini = dm_hw_fini,
1014         .suspend = dm_suspend,
1015         .resume = dm_resume,
1016         .is_idle = dm_is_idle,
1017         .wait_for_idle = dm_wait_for_idle,
1018         .check_soft_reset = dm_check_soft_reset,
1019         .soft_reset = dm_soft_reset,
1020         .set_clockgating_state = dm_set_clockgating_state,
1021         .set_powergating_state = dm_set_powergating_state,
1022 };
1023
1024 const struct amdgpu_ip_block_version dm_ip_block =
1025 {
1026         .type = AMD_IP_BLOCK_TYPE_DCE,
1027         .major = 1,
1028         .minor = 0,
1029         .rev = 0,
1030         .funcs = &amdgpu_dm_funcs,
1031 };
1032
1033
1034 /**
1035  * DOC: atomic
1036  *
1037  * *WIP*
1038  */
1039
1040 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1041         .fb_create = amdgpu_display_user_framebuffer_create,
1042         .output_poll_changed = drm_fb_helper_output_poll_changed,
1043         .atomic_check = amdgpu_dm_atomic_check,
1044         .atomic_commit = amdgpu_dm_atomic_commit,
1045 };
1046
1047 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1048         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1049 };
1050
1051 static void
1052 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1053 {
1054         struct drm_connector *connector = &aconnector->base;
1055         struct drm_device *dev = connector->dev;
1056         struct dc_sink *sink;
1057
1058         /* MST handled by drm_mst framework */
1059         if (aconnector->mst_mgr.mst_state == true)
1060                 return;
1061
1062
1063         sink = aconnector->dc_link->local_sink;
1064
1065         /*
1066          * Edid mgmt connector gets first update only in mode_valid hook and then
1067          * the connector sink is set to either fake or physical sink depends on link status.
1068          * Skip if already done during boot.
1069          */
1070         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1071                         && aconnector->dc_em_sink) {
1072
1073                 /*
1074                  * For S3 resume with headless use eml_sink to fake stream
1075                  * because on resume connector->sink is set to NULL
1076                  */
1077                 mutex_lock(&dev->mode_config.mutex);
1078
1079                 if (sink) {
1080                         if (aconnector->dc_sink) {
1081                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1082                                 /*
1083                                  * retain and release below are used to
1084                                  * bump up refcount for sink because the link doesn't point
1085                                  * to it anymore after disconnect, so on next crtc to connector
1086                                  * reshuffle by UMD we will get into unwanted dc_sink release
1087                                  */
1088                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
1089                                         dc_sink_release(aconnector->dc_sink);
1090                         }
1091                         aconnector->dc_sink = sink;
1092                         amdgpu_dm_update_freesync_caps(connector,
1093                                         aconnector->edid);
1094                 } else {
1095                         amdgpu_dm_update_freesync_caps(connector, NULL);
1096                         if (!aconnector->dc_sink)
1097                                 aconnector->dc_sink = aconnector->dc_em_sink;
1098                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
1099                                 dc_sink_retain(aconnector->dc_sink);
1100                 }
1101
1102                 mutex_unlock(&dev->mode_config.mutex);
1103                 return;
1104         }
1105
1106         /*
1107          * TODO: temporary guard to look for proper fix
1108          * if this sink is MST sink, we should not do anything
1109          */
1110         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1111                 return;
1112
1113         if (aconnector->dc_sink == sink) {
1114                 /*
1115                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1116                  * Do nothing!!
1117                  */
1118                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1119                                 aconnector->connector_id);
1120                 return;
1121         }
1122
1123         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1124                 aconnector->connector_id, aconnector->dc_sink, sink);
1125
1126         mutex_lock(&dev->mode_config.mutex);
1127
1128         /*
1129          * 1. Update status of the drm connector
1130          * 2. Send an event and let userspace tell us what to do
1131          */
1132         if (sink) {
1133                 /*
1134                  * TODO: check if we still need the S3 mode update workaround.
1135                  * If yes, put it here.
1136                  */
1137                 if (aconnector->dc_sink)
1138                         amdgpu_dm_update_freesync_caps(connector, NULL);
1139
1140                 aconnector->dc_sink = sink;
1141                 if (sink->dc_edid.length == 0) {
1142                         aconnector->edid = NULL;
1143                         drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1144                 } else {
1145                         aconnector->edid =
1146                                 (struct edid *) sink->dc_edid.raw_edid;
1147
1148
1149                         drm_connector_update_edid_property(connector,
1150                                         aconnector->edid);
1151                         drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1152                                             aconnector->edid);
1153                 }
1154                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1155
1156         } else {
1157                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1158                 amdgpu_dm_update_freesync_caps(connector, NULL);
1159                 drm_connector_update_edid_property(connector, NULL);
1160                 aconnector->num_modes = 0;
1161                 aconnector->dc_sink = NULL;
1162                 aconnector->edid = NULL;
1163         }
1164
1165         mutex_unlock(&dev->mode_config.mutex);
1166 }
1167
1168 static void handle_hpd_irq(void *param)
1169 {
1170         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1171         struct drm_connector *connector = &aconnector->base;
1172         struct drm_device *dev = connector->dev;
1173         enum dc_connection_type new_connection_type = dc_connection_none;
1174
1175         /*
1176          * In case of failure or MST no need to update connector status or notify the OS
1177          * since (for MST case) MST does this in its own context.
1178          */
1179         mutex_lock(&aconnector->hpd_lock);
1180
1181         if (aconnector->fake_enable)
1182                 aconnector->fake_enable = false;
1183
1184         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1185                 DRM_ERROR("KMS: Failed to detect connector\n");
1186
1187         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1188                 emulated_link_detect(aconnector->dc_link);
1189
1190
1191                 drm_modeset_lock_all(dev);
1192                 dm_restore_drm_connector_state(dev, connector);
1193                 drm_modeset_unlock_all(dev);
1194
1195                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1196                         drm_kms_helper_hotplug_event(dev);
1197
1198         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1199                 amdgpu_dm_update_connector_after_detect(aconnector);
1200
1201
1202                 drm_modeset_lock_all(dev);
1203                 dm_restore_drm_connector_state(dev, connector);
1204                 drm_modeset_unlock_all(dev);
1205
1206                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1207                         drm_kms_helper_hotplug_event(dev);
1208         }
1209         mutex_unlock(&aconnector->hpd_lock);
1210
1211 }
1212
1213 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1214 {
1215         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1216         uint8_t dret;
1217         bool new_irq_handled = false;
1218         int dpcd_addr;
1219         int dpcd_bytes_to_read;
1220
1221         const int max_process_count = 30;
1222         int process_count = 0;
1223
1224         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1225
1226         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1227                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1228                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1229                 dpcd_addr = DP_SINK_COUNT;
1230         } else {
1231                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1232                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1233                 dpcd_addr = DP_SINK_COUNT_ESI;
1234         }
1235
1236         dret = drm_dp_dpcd_read(
1237                 &aconnector->dm_dp_aux.aux,
1238                 dpcd_addr,
1239                 esi,
1240                 dpcd_bytes_to_read);
1241
1242         while (dret == dpcd_bytes_to_read &&
1243                 process_count < max_process_count) {
1244                 uint8_t retry;
1245                 dret = 0;
1246
1247                 process_count++;
1248
1249                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1250                 /* handle HPD short pulse irq */
1251                 if (aconnector->mst_mgr.mst_state)
1252                         drm_dp_mst_hpd_irq(
1253                                 &aconnector->mst_mgr,
1254                                 esi,
1255                                 &new_irq_handled);
1256
1257                 if (new_irq_handled) {
1258                         /* ACK at DPCD to notify down stream */
1259                         const int ack_dpcd_bytes_to_write =
1260                                 dpcd_bytes_to_read - 1;
1261
1262                         for (retry = 0; retry < 3; retry++) {
1263                                 uint8_t wret;
1264
1265                                 wret = drm_dp_dpcd_write(
1266                                         &aconnector->dm_dp_aux.aux,
1267                                         dpcd_addr + 1,
1268                                         &esi[1],
1269                                         ack_dpcd_bytes_to_write);
1270                                 if (wret == ack_dpcd_bytes_to_write)
1271                                         break;
1272                         }
1273
1274                         /* check if there is new irq to be handled */
1275                         dret = drm_dp_dpcd_read(
1276                                 &aconnector->dm_dp_aux.aux,
1277                                 dpcd_addr,
1278                                 esi,
1279                                 dpcd_bytes_to_read);
1280
1281                         new_irq_handled = false;
1282                 } else {
1283                         break;
1284                 }
1285         }
1286
1287         if (process_count == max_process_count)
1288                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1289 }
1290
1291 static void handle_hpd_rx_irq(void *param)
1292 {
1293         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1294         struct drm_connector *connector = &aconnector->base;
1295         struct drm_device *dev = connector->dev;
1296         struct dc_link *dc_link = aconnector->dc_link;
1297         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1298         enum dc_connection_type new_connection_type = dc_connection_none;
1299
1300         /*
1301          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1302          * conflict, after implement i2c helper, this mutex should be
1303          * retired.
1304          */
1305         if (dc_link->type != dc_connection_mst_branch)
1306                 mutex_lock(&aconnector->hpd_lock);
1307
1308         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1309                         !is_mst_root_connector) {
1310                 /* Downstream Port status changed. */
1311                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1312                         DRM_ERROR("KMS: Failed to detect connector\n");
1313
1314                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1315                         emulated_link_detect(dc_link);
1316
1317                         if (aconnector->fake_enable)
1318                                 aconnector->fake_enable = false;
1319
1320                         amdgpu_dm_update_connector_after_detect(aconnector);
1321
1322
1323                         drm_modeset_lock_all(dev);
1324                         dm_restore_drm_connector_state(dev, connector);
1325                         drm_modeset_unlock_all(dev);
1326
1327                         drm_kms_helper_hotplug_event(dev);
1328                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1329
1330                         if (aconnector->fake_enable)
1331                                 aconnector->fake_enable = false;
1332
1333                         amdgpu_dm_update_connector_after_detect(aconnector);
1334
1335
1336                         drm_modeset_lock_all(dev);
1337                         dm_restore_drm_connector_state(dev, connector);
1338                         drm_modeset_unlock_all(dev);
1339
1340                         drm_kms_helper_hotplug_event(dev);
1341                 }
1342         }
1343         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1344             (dc_link->type == dc_connection_mst_branch))
1345                 dm_handle_hpd_rx_irq(aconnector);
1346
1347         if (dc_link->type != dc_connection_mst_branch) {
1348                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1349                 mutex_unlock(&aconnector->hpd_lock);
1350         }
1351 }
1352
1353 static void register_hpd_handlers(struct amdgpu_device *adev)
1354 {
1355         struct drm_device *dev = adev->ddev;
1356         struct drm_connector *connector;
1357         struct amdgpu_dm_connector *aconnector;
1358         const struct dc_link *dc_link;
1359         struct dc_interrupt_params int_params = {0};
1360
1361         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1362         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1363
1364         list_for_each_entry(connector,
1365                         &dev->mode_config.connector_list, head) {
1366
1367                 aconnector = to_amdgpu_dm_connector(connector);
1368                 dc_link = aconnector->dc_link;
1369
1370                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1371                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1372                         int_params.irq_source = dc_link->irq_source_hpd;
1373
1374                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1375                                         handle_hpd_irq,
1376                                         (void *) aconnector);
1377                 }
1378
1379                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1380
1381                         /* Also register for DP short pulse (hpd_rx). */
1382                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1383                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1384
1385                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1386                                         handle_hpd_rx_irq,
1387                                         (void *) aconnector);
1388                 }
1389         }
1390 }
1391
1392 /* Register IRQ sources and initialize IRQ callbacks */
1393 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1394 {
1395         struct dc *dc = adev->dm.dc;
1396         struct common_irq_params *c_irq_params;
1397         struct dc_interrupt_params int_params = {0};
1398         int r;
1399         int i;
1400         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1401
1402         if (adev->asic_type == CHIP_VEGA10 ||
1403             adev->asic_type == CHIP_VEGA12 ||
1404             adev->asic_type == CHIP_VEGA20 ||
1405             adev->asic_type == CHIP_RAVEN)
1406                 client_id = SOC15_IH_CLIENTID_DCE;
1407
1408         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1409         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1410
1411         /*
1412          * Actions of amdgpu_irq_add_id():
1413          * 1. Register a set() function with base driver.
1414          *    Base driver will call set() function to enable/disable an
1415          *    interrupt in DC hardware.
1416          * 2. Register amdgpu_dm_irq_handler().
1417          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1418          *    coming from DC hardware.
1419          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1420          *    for acknowledging and handling. */
1421
1422         /* Use VBLANK interrupt */
1423         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1424                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1425                 if (r) {
1426                         DRM_ERROR("Failed to add crtc irq id!\n");
1427                         return r;
1428                 }
1429
1430                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1431                 int_params.irq_source =
1432                         dc_interrupt_to_irq_source(dc, i, 0);
1433
1434                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1435
1436                 c_irq_params->adev = adev;
1437                 c_irq_params->irq_src = int_params.irq_source;
1438
1439                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1440                                 dm_crtc_high_irq, c_irq_params);
1441         }
1442
1443         /* Use GRPH_PFLIP interrupt */
1444         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1445                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1446                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1447                 if (r) {
1448                         DRM_ERROR("Failed to add page flip irq id!\n");
1449                         return r;
1450                 }
1451
1452                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1453                 int_params.irq_source =
1454                         dc_interrupt_to_irq_source(dc, i, 0);
1455
1456                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1457
1458                 c_irq_params->adev = adev;
1459                 c_irq_params->irq_src = int_params.irq_source;
1460
1461                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1462                                 dm_pflip_high_irq, c_irq_params);
1463
1464         }
1465
1466         /* HPD */
1467         r = amdgpu_irq_add_id(adev, client_id,
1468                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1469         if (r) {
1470                 DRM_ERROR("Failed to add hpd irq id!\n");
1471                 return r;
1472         }
1473
1474         register_hpd_handlers(adev);
1475
1476         return 0;
1477 }
1478
1479 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1480 /* Register IRQ sources and initialize IRQ callbacks */
1481 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1482 {
1483         struct dc *dc = adev->dm.dc;
1484         struct common_irq_params *c_irq_params;
1485         struct dc_interrupt_params int_params = {0};
1486         int r;
1487         int i;
1488
1489         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1490         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1491
1492         /*
1493          * Actions of amdgpu_irq_add_id():
1494          * 1. Register a set() function with base driver.
1495          *    Base driver will call set() function to enable/disable an
1496          *    interrupt in DC hardware.
1497          * 2. Register amdgpu_dm_irq_handler().
1498          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1499          *    coming from DC hardware.
1500          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1501          *    for acknowledging and handling.
1502          */
1503
1504         /* Use VSTARTUP interrupt */
1505         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1506                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1507                         i++) {
1508                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1509
1510                 if (r) {
1511                         DRM_ERROR("Failed to add crtc irq id!\n");
1512                         return r;
1513                 }
1514
1515                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1516                 int_params.irq_source =
1517                         dc_interrupt_to_irq_source(dc, i, 0);
1518
1519                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1520
1521                 c_irq_params->adev = adev;
1522                 c_irq_params->irq_src = int_params.irq_source;
1523
1524                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1525                                 dm_crtc_high_irq, c_irq_params);
1526         }
1527
1528         /* Use GRPH_PFLIP interrupt */
1529         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1530                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1531                         i++) {
1532                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1533                 if (r) {
1534                         DRM_ERROR("Failed to add page flip irq id!\n");
1535                         return r;
1536                 }
1537
1538                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1539                 int_params.irq_source =
1540                         dc_interrupt_to_irq_source(dc, i, 0);
1541
1542                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1543
1544                 c_irq_params->adev = adev;
1545                 c_irq_params->irq_src = int_params.irq_source;
1546
1547                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1548                                 dm_pflip_high_irq, c_irq_params);
1549
1550         }
1551
1552         /* HPD */
1553         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1554                         &adev->hpd_irq);
1555         if (r) {
1556                 DRM_ERROR("Failed to add hpd irq id!\n");
1557                 return r;
1558         }
1559
1560         register_hpd_handlers(adev);
1561
1562         return 0;
1563 }
1564 #endif
1565
1566 /*
1567  * Acquires the lock for the atomic state object and returns
1568  * the new atomic state.
1569  *
1570  * This should only be called during atomic check.
1571  */
1572 static int dm_atomic_get_state(struct drm_atomic_state *state,
1573                                struct dm_atomic_state **dm_state)
1574 {
1575         struct drm_device *dev = state->dev;
1576         struct amdgpu_device *adev = dev->dev_private;
1577         struct amdgpu_display_manager *dm = &adev->dm;
1578         struct drm_private_state *priv_state;
1579         int ret;
1580
1581         if (*dm_state)
1582                 return 0;
1583
1584         ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1585         if (ret)
1586                 return ret;
1587
1588         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1589         if (IS_ERR(priv_state))
1590                 return PTR_ERR(priv_state);
1591
1592         *dm_state = to_dm_atomic_state(priv_state);
1593
1594         return 0;
1595 }
1596
1597 struct dm_atomic_state *
1598 dm_atomic_get_new_state(struct drm_atomic_state *state)
1599 {
1600         struct drm_device *dev = state->dev;
1601         struct amdgpu_device *adev = dev->dev_private;
1602         struct amdgpu_display_manager *dm = &adev->dm;
1603         struct drm_private_obj *obj;
1604         struct drm_private_state *new_obj_state;
1605         int i;
1606
1607         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1608                 if (obj->funcs == dm->atomic_obj.funcs)
1609                         return to_dm_atomic_state(new_obj_state);
1610         }
1611
1612         return NULL;
1613 }
1614
1615 struct dm_atomic_state *
1616 dm_atomic_get_old_state(struct drm_atomic_state *state)
1617 {
1618         struct drm_device *dev = state->dev;
1619         struct amdgpu_device *adev = dev->dev_private;
1620         struct amdgpu_display_manager *dm = &adev->dm;
1621         struct drm_private_obj *obj;
1622         struct drm_private_state *old_obj_state;
1623         int i;
1624
1625         for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1626                 if (obj->funcs == dm->atomic_obj.funcs)
1627                         return to_dm_atomic_state(old_obj_state);
1628         }
1629
1630         return NULL;
1631 }
1632
1633 static struct drm_private_state *
1634 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1635 {
1636         struct dm_atomic_state *old_state, *new_state;
1637
1638         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1639         if (!new_state)
1640                 return NULL;
1641
1642         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1643
1644         new_state->context = dc_create_state();
1645         if (!new_state->context) {
1646                 kfree(new_state);
1647                 return NULL;
1648         }
1649
1650         old_state = to_dm_atomic_state(obj->state);
1651         if (old_state && old_state->context)
1652                 dc_resource_state_copy_construct(old_state->context,
1653                                                  new_state->context);
1654
1655         return &new_state->base;
1656 }
1657
1658 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1659                                     struct drm_private_state *state)
1660 {
1661         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1662
1663         if (dm_state && dm_state->context)
1664                 dc_release_state(dm_state->context);
1665
1666         kfree(dm_state);
1667 }
1668
1669 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1670         .atomic_duplicate_state = dm_atomic_duplicate_state,
1671         .atomic_destroy_state = dm_atomic_destroy_state,
1672 };
1673
1674 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1675 {
1676         struct dm_atomic_state *state;
1677         int r;
1678
1679         adev->mode_info.mode_config_initialized = true;
1680
1681         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1682         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1683
1684         adev->ddev->mode_config.max_width = 16384;
1685         adev->ddev->mode_config.max_height = 16384;
1686
1687         adev->ddev->mode_config.preferred_depth = 24;
1688         adev->ddev->mode_config.prefer_shadow = 1;
1689         /* indicates support for immediate flip */
1690         adev->ddev->mode_config.async_page_flip = true;
1691
1692         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1693
1694         drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1695
1696         state = kzalloc(sizeof(*state), GFP_KERNEL);
1697         if (!state)
1698                 return -ENOMEM;
1699
1700         state->context = dc_create_state();
1701         if (!state->context) {
1702                 kfree(state);
1703                 return -ENOMEM;
1704         }
1705
1706         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1707
1708         drm_atomic_private_obj_init(adev->ddev,
1709                                     &adev->dm.atomic_obj,
1710                                     &state->base,
1711                                     &dm_atomic_state_funcs);
1712
1713         r = amdgpu_display_modeset_create_props(adev);
1714         if (r)
1715                 return r;
1716
1717         return 0;
1718 }
1719
1720 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1721 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1722
1723 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1724         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1725
1726 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1727 {
1728 #if defined(CONFIG_ACPI)
1729         struct amdgpu_dm_backlight_caps caps;
1730
1731         if (dm->backlight_caps.caps_valid)
1732                 return;
1733
1734         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1735         if (caps.caps_valid) {
1736                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1737                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1738                 dm->backlight_caps.caps_valid = true;
1739         } else {
1740                 dm->backlight_caps.min_input_signal =
1741                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1742                 dm->backlight_caps.max_input_signal =
1743                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1744         }
1745 #else
1746         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1747         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1748 #endif
1749 }
1750
1751 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1752 {
1753         struct amdgpu_display_manager *dm = bl_get_data(bd);
1754         struct amdgpu_dm_backlight_caps caps;
1755         uint32_t brightness = bd->props.brightness;
1756
1757         amdgpu_dm_update_backlight_caps(dm);
1758         caps = dm->backlight_caps;
1759         /*
1760          * The brightness input is in the range 0-255
1761          * It needs to be rescaled to be between the
1762          * requested min and max input signal
1763          *
1764          * It also needs to be scaled up by 0x101 to
1765          * match the DC interface which has a range of
1766          * 0 to 0xffff
1767          */
1768         brightness =
1769                 brightness
1770                 * 0x101
1771                 * (caps.max_input_signal - caps.min_input_signal)
1772                 / AMDGPU_MAX_BL_LEVEL
1773                 + caps.min_input_signal * 0x101;
1774
1775         if (dc_link_set_backlight_level(dm->backlight_link,
1776                         brightness, 0))
1777                 return 0;
1778         else
1779                 return 1;
1780 }
1781
1782 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1783 {
1784         struct amdgpu_display_manager *dm = bl_get_data(bd);
1785         int ret = dc_link_get_backlight_level(dm->backlight_link);
1786
1787         if (ret == DC_ERROR_UNEXPECTED)
1788                 return bd->props.brightness;
1789         return ret;
1790 }
1791
1792 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1793         .get_brightness = amdgpu_dm_backlight_get_brightness,
1794         .update_status  = amdgpu_dm_backlight_update_status,
1795 };
1796
1797 static void
1798 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1799 {
1800         char bl_name[16];
1801         struct backlight_properties props = { 0 };
1802
1803         amdgpu_dm_update_backlight_caps(dm);
1804
1805         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1806         props.brightness = AMDGPU_MAX_BL_LEVEL;
1807         props.type = BACKLIGHT_RAW;
1808
1809         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1810                         dm->adev->ddev->primary->index);
1811
1812         dm->backlight_dev = backlight_device_register(bl_name,
1813                         dm->adev->ddev->dev,
1814                         dm,
1815                         &amdgpu_dm_backlight_ops,
1816                         &props);
1817
1818         if (IS_ERR(dm->backlight_dev))
1819                 DRM_ERROR("DM: Backlight registration failed!\n");
1820         else
1821                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1822 }
1823
1824 #endif
1825
1826 static int initialize_plane(struct amdgpu_display_manager *dm,
1827                              struct amdgpu_mode_info *mode_info,
1828                              int plane_id)
1829 {
1830         struct drm_plane *plane;
1831         unsigned long possible_crtcs;
1832         int ret = 0;
1833
1834         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
1835         mode_info->planes[plane_id] = plane;
1836
1837         if (!plane) {
1838                 DRM_ERROR("KMS: Failed to allocate plane\n");
1839                 return -ENOMEM;
1840         }
1841         plane->type = mode_info->plane_type[plane_id];
1842
1843         /*
1844          * HACK: IGT tests expect that each plane can only have
1845          * one possible CRTC. For now, set one CRTC for each
1846          * plane that is not an underlay, but still allow multiple
1847          * CRTCs for underlay planes.
1848          */
1849         possible_crtcs = 1 << plane_id;
1850         if (plane_id >= dm->dc->caps.max_streams)
1851                 possible_crtcs = 0xff;
1852
1853         ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1854
1855         if (ret) {
1856                 DRM_ERROR("KMS: Failed to initialize plane\n");
1857                 return ret;
1858         }
1859
1860         return ret;
1861 }
1862
1863
1864 static void register_backlight_device(struct amdgpu_display_manager *dm,
1865                                       struct dc_link *link)
1866 {
1867 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1868         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1869
1870         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1871             link->type != dc_connection_none) {
1872                 /*
1873                  * Event if registration failed, we should continue with
1874                  * DM initialization because not having a backlight control
1875                  * is better then a black screen.
1876                  */
1877                 amdgpu_dm_register_backlight_device(dm);
1878
1879                 if (dm->backlight_dev)
1880                         dm->backlight_link = link;
1881         }
1882 #endif
1883 }
1884
1885
1886 /*
1887  * In this architecture, the association
1888  * connector -> encoder -> crtc
1889  * id not really requried. The crtc and connector will hold the
1890  * display_index as an abstraction to use with DAL component
1891  *
1892  * Returns 0 on success
1893  */
1894 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1895 {
1896         struct amdgpu_display_manager *dm = &adev->dm;
1897         int32_t i;
1898         struct amdgpu_dm_connector *aconnector = NULL;
1899         struct amdgpu_encoder *aencoder = NULL;
1900         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1901         uint32_t link_cnt;
1902         int32_t total_overlay_planes, total_primary_planes;
1903         enum dc_connection_type new_connection_type = dc_connection_none;
1904
1905         link_cnt = dm->dc->caps.max_links;
1906         if (amdgpu_dm_mode_config_init(dm->adev)) {
1907                 DRM_ERROR("DM: Failed to initialize mode config\n");
1908                 return -EINVAL;
1909         }
1910
1911         /* Identify the number of planes to be initialized */
1912         total_overlay_planes = dm->dc->caps.max_slave_planes;
1913         total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1914
1915         /* First initialize overlay planes, index starting after primary planes */
1916         for (i = (total_overlay_planes - 1); i >= 0; i--) {
1917                 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1918                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1919                         goto fail;
1920                 }
1921         }
1922
1923         /* Initialize primary planes */
1924         for (i = (total_primary_planes - 1); i >= 0; i--) {
1925                 if (initialize_plane(dm, mode_info, i)) {
1926                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
1927                         goto fail;
1928                 }
1929         }
1930
1931         for (i = 0; i < dm->dc->caps.max_streams; i++)
1932                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
1933                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1934                         goto fail;
1935                 }
1936
1937         dm->display_indexes_num = dm->dc->caps.max_streams;
1938
1939         /* loops over all connectors on the board */
1940         for (i = 0; i < link_cnt; i++) {
1941                 struct dc_link *link = NULL;
1942
1943                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1944                         DRM_ERROR(
1945                                 "KMS: Cannot support more than %d display indexes\n",
1946                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1947                         continue;
1948                 }
1949
1950                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1951                 if (!aconnector)
1952                         goto fail;
1953
1954                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1955                 if (!aencoder)
1956                         goto fail;
1957
1958                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1959                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1960                         goto fail;
1961                 }
1962
1963                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1964                         DRM_ERROR("KMS: Failed to initialize connector\n");
1965                         goto fail;
1966                 }
1967
1968                 link = dc_get_link_at_index(dm->dc, i);
1969
1970                 if (!dc_link_detect_sink(link, &new_connection_type))
1971                         DRM_ERROR("KMS: Failed to detect connector\n");
1972
1973                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1974                         emulated_link_detect(link);
1975                         amdgpu_dm_update_connector_after_detect(aconnector);
1976
1977                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1978                         amdgpu_dm_update_connector_after_detect(aconnector);
1979                         register_backlight_device(dm, link);
1980                 }
1981
1982
1983         }
1984
1985         /* Software is initialized. Now we can register interrupt handlers. */
1986         switch (adev->asic_type) {
1987         case CHIP_BONAIRE:
1988         case CHIP_HAWAII:
1989         case CHIP_KAVERI:
1990         case CHIP_KABINI:
1991         case CHIP_MULLINS:
1992         case CHIP_TONGA:
1993         case CHIP_FIJI:
1994         case CHIP_CARRIZO:
1995         case CHIP_STONEY:
1996         case CHIP_POLARIS11:
1997         case CHIP_POLARIS10:
1998         case CHIP_POLARIS12:
1999         case CHIP_VEGAM:
2000         case CHIP_VEGA10:
2001         case CHIP_VEGA12:
2002         case CHIP_VEGA20:
2003                 if (dce110_register_irq_handlers(dm->adev)) {
2004                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2005                         goto fail;
2006                 }
2007                 break;
2008 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2009         case CHIP_RAVEN:
2010                 if (dcn10_register_irq_handlers(dm->adev)) {
2011                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2012                         goto fail;
2013                 }
2014                 break;
2015 #endif
2016         default:
2017                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2018                 goto fail;
2019         }
2020
2021         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2022                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2023
2024         return 0;
2025 fail:
2026         kfree(aencoder);
2027         kfree(aconnector);
2028         for (i = 0; i < dm->dc->caps.max_planes; i++)
2029                 kfree(mode_info->planes[i]);
2030         return -EINVAL;
2031 }
2032
2033 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2034 {
2035         drm_mode_config_cleanup(dm->ddev);
2036         drm_atomic_private_obj_fini(&dm->atomic_obj);
2037         return;
2038 }
2039
2040 /******************************************************************************
2041  * amdgpu_display_funcs functions
2042  *****************************************************************************/
2043
2044 /*
2045  * dm_bandwidth_update - program display watermarks
2046  *
2047  * @adev: amdgpu_device pointer
2048  *
2049  * Calculate and program the display watermarks and line buffer allocation.
2050  */
2051 static void dm_bandwidth_update(struct amdgpu_device *adev)
2052 {
2053         /* TODO: implement later */
2054 }
2055
2056 static const struct amdgpu_display_funcs dm_display_funcs = {
2057         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2058         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2059         .backlight_set_level = NULL, /* never called for DC */
2060         .backlight_get_level = NULL, /* never called for DC */
2061         .hpd_sense = NULL,/* called unconditionally */
2062         .hpd_set_polarity = NULL, /* called unconditionally */
2063         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2064         .page_flip_get_scanoutpos =
2065                 dm_crtc_get_scanoutpos,/* called unconditionally */
2066         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2067         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2068 };
2069
2070 #if defined(CONFIG_DEBUG_KERNEL_DC)
2071
2072 static ssize_t s3_debug_store(struct device *device,
2073                               struct device_attribute *attr,
2074                               const char *buf,
2075                               size_t count)
2076 {
2077         int ret;
2078         int s3_state;
2079         struct pci_dev *pdev = to_pci_dev(device);
2080         struct drm_device *drm_dev = pci_get_drvdata(pdev);
2081         struct amdgpu_device *adev = drm_dev->dev_private;
2082
2083         ret = kstrtoint(buf, 0, &s3_state);
2084
2085         if (ret == 0) {
2086                 if (s3_state) {
2087                         dm_resume(adev);
2088                         drm_kms_helper_hotplug_event(adev->ddev);
2089                 } else
2090                         dm_suspend(adev);
2091         }
2092
2093         return ret == 0 ? count : 0;
2094 }
2095
2096 DEVICE_ATTR_WO(s3_debug);
2097
2098 #endif
2099
2100 static int dm_early_init(void *handle)
2101 {
2102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2103
2104         switch (adev->asic_type) {
2105         case CHIP_BONAIRE:
2106         case CHIP_HAWAII:
2107                 adev->mode_info.num_crtc = 6;
2108                 adev->mode_info.num_hpd = 6;
2109                 adev->mode_info.num_dig = 6;
2110                 adev->mode_info.plane_type = dm_plane_type_default;
2111                 break;
2112         case CHIP_KAVERI:
2113                 adev->mode_info.num_crtc = 4;
2114                 adev->mode_info.num_hpd = 6;
2115                 adev->mode_info.num_dig = 7;
2116                 adev->mode_info.plane_type = dm_plane_type_default;
2117                 break;
2118         case CHIP_KABINI:
2119         case CHIP_MULLINS:
2120                 adev->mode_info.num_crtc = 2;
2121                 adev->mode_info.num_hpd = 6;
2122                 adev->mode_info.num_dig = 6;
2123                 adev->mode_info.plane_type = dm_plane_type_default;
2124                 break;
2125         case CHIP_FIJI:
2126         case CHIP_TONGA:
2127                 adev->mode_info.num_crtc = 6;
2128                 adev->mode_info.num_hpd = 6;
2129                 adev->mode_info.num_dig = 7;
2130                 adev->mode_info.plane_type = dm_plane_type_default;
2131                 break;
2132         case CHIP_CARRIZO:
2133                 adev->mode_info.num_crtc = 3;
2134                 adev->mode_info.num_hpd = 6;
2135                 adev->mode_info.num_dig = 9;
2136                 adev->mode_info.plane_type = dm_plane_type_carizzo;
2137                 break;
2138         case CHIP_STONEY:
2139                 adev->mode_info.num_crtc = 2;
2140                 adev->mode_info.num_hpd = 6;
2141                 adev->mode_info.num_dig = 9;
2142                 adev->mode_info.plane_type = dm_plane_type_stoney;
2143                 break;
2144         case CHIP_POLARIS11:
2145         case CHIP_POLARIS12:
2146                 adev->mode_info.num_crtc = 5;
2147                 adev->mode_info.num_hpd = 5;
2148                 adev->mode_info.num_dig = 5;
2149                 adev->mode_info.plane_type = dm_plane_type_default;
2150                 break;
2151         case CHIP_POLARIS10:
2152         case CHIP_VEGAM:
2153                 adev->mode_info.num_crtc = 6;
2154                 adev->mode_info.num_hpd = 6;
2155                 adev->mode_info.num_dig = 6;
2156                 adev->mode_info.plane_type = dm_plane_type_default;
2157                 break;
2158         case CHIP_VEGA10:
2159         case CHIP_VEGA12:
2160         case CHIP_VEGA20:
2161                 adev->mode_info.num_crtc = 6;
2162                 adev->mode_info.num_hpd = 6;
2163                 adev->mode_info.num_dig = 6;
2164                 adev->mode_info.plane_type = dm_plane_type_default;
2165                 break;
2166 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2167         case CHIP_RAVEN:
2168                 adev->mode_info.num_crtc = 4;
2169                 adev->mode_info.num_hpd = 4;
2170                 adev->mode_info.num_dig = 4;
2171                 adev->mode_info.plane_type = dm_plane_type_default;
2172                 break;
2173 #endif
2174         default:
2175                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2176                 return -EINVAL;
2177         }
2178
2179         amdgpu_dm_set_irq_funcs(adev);
2180
2181         if (adev->mode_info.funcs == NULL)
2182                 adev->mode_info.funcs = &dm_display_funcs;
2183
2184         /*
2185          * Note: Do NOT change adev->audio_endpt_rreg and
2186          * adev->audio_endpt_wreg because they are initialised in
2187          * amdgpu_device_init()
2188          */
2189 #if defined(CONFIG_DEBUG_KERNEL_DC)
2190         device_create_file(
2191                 adev->ddev->dev,
2192                 &dev_attr_s3_debug);
2193 #endif
2194
2195         return 0;
2196 }
2197
2198 static bool modeset_required(struct drm_crtc_state *crtc_state,
2199                              struct dc_stream_state *new_stream,
2200                              struct dc_stream_state *old_stream)
2201 {
2202         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2203                 return false;
2204
2205         if (!crtc_state->enable)
2206                 return false;
2207
2208         return crtc_state->active;
2209 }
2210
2211 static bool modereset_required(struct drm_crtc_state *crtc_state)
2212 {
2213         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2214                 return false;
2215
2216         return !crtc_state->enable || !crtc_state->active;
2217 }
2218
2219 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2220 {
2221         drm_encoder_cleanup(encoder);
2222         kfree(encoder);
2223 }
2224
2225 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2226         .destroy = amdgpu_dm_encoder_destroy,
2227 };
2228
2229 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2230                                         struct dc_plane_state *plane_state)
2231 {
2232         plane_state->src_rect.x = state->src_x >> 16;
2233         plane_state->src_rect.y = state->src_y >> 16;
2234         /* we ignore the mantissa for now and do not deal with floating pixels :( */
2235         plane_state->src_rect.width = state->src_w >> 16;
2236
2237         if (plane_state->src_rect.width == 0)
2238                 return false;
2239
2240         plane_state->src_rect.height = state->src_h >> 16;
2241         if (plane_state->src_rect.height == 0)
2242                 return false;
2243
2244         plane_state->dst_rect.x = state->crtc_x;
2245         plane_state->dst_rect.y = state->crtc_y;
2246
2247         if (state->crtc_w == 0)
2248                 return false;
2249
2250         plane_state->dst_rect.width = state->crtc_w;
2251
2252         if (state->crtc_h == 0)
2253                 return false;
2254
2255         plane_state->dst_rect.height = state->crtc_h;
2256
2257         plane_state->clip_rect = plane_state->dst_rect;
2258
2259         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2260         case DRM_MODE_ROTATE_0:
2261                 plane_state->rotation = ROTATION_ANGLE_0;
2262                 break;
2263         case DRM_MODE_ROTATE_90:
2264                 plane_state->rotation = ROTATION_ANGLE_90;
2265                 break;
2266         case DRM_MODE_ROTATE_180:
2267                 plane_state->rotation = ROTATION_ANGLE_180;
2268                 break;
2269         case DRM_MODE_ROTATE_270:
2270                 plane_state->rotation = ROTATION_ANGLE_270;
2271                 break;
2272         default:
2273                 plane_state->rotation = ROTATION_ANGLE_0;
2274                 break;
2275         }
2276
2277         return true;
2278 }
2279 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2280                        uint64_t *tiling_flags)
2281 {
2282         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2283         int r = amdgpu_bo_reserve(rbo, false);
2284
2285         if (unlikely(r)) {
2286                 /* Don't show error message when returning -ERESTARTSYS */
2287                 if (r != -ERESTARTSYS)
2288                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2289                 return r;
2290         }
2291
2292         if (tiling_flags)
2293                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2294
2295         amdgpu_bo_unreserve(rbo);
2296
2297         return r;
2298 }
2299
2300 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2301 {
2302         uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2303
2304         return offset ? (address + offset * 256) : 0;
2305 }
2306
2307 static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
2308                                       const struct amdgpu_framebuffer *afb,
2309                                       struct dc_plane_state *plane_state,
2310                                       uint64_t info)
2311 {
2312         struct dc *dc = adev->dm.dc;
2313         struct dc_dcc_surface_param input;
2314         struct dc_surface_dcc_cap output;
2315         uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2316         uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2317         uint64_t dcc_address;
2318
2319         memset(&input, 0, sizeof(input));
2320         memset(&output, 0, sizeof(output));
2321
2322         if (!offset)
2323                 return false;
2324
2325         if (!dc->cap_funcs.get_dcc_compression_cap)
2326                 return false;
2327
2328         input.format = plane_state->format;
2329         input.surface_size.width =
2330                 plane_state->plane_size.grph.surface_size.width;
2331         input.surface_size.height =
2332                 plane_state->plane_size.grph.surface_size.height;
2333         input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2334
2335         if (plane_state->rotation == ROTATION_ANGLE_0 ||
2336             plane_state->rotation == ROTATION_ANGLE_180)
2337                 input.scan = SCAN_DIRECTION_HORIZONTAL;
2338         else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2339                  plane_state->rotation == ROTATION_ANGLE_270)
2340                 input.scan = SCAN_DIRECTION_VERTICAL;
2341
2342         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2343                 return false;
2344
2345         if (!output.capable)
2346                 return false;
2347
2348         if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2349                 return false;
2350
2351         plane_state->dcc.enable = 1;
2352         plane_state->dcc.grph.meta_pitch =
2353                 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2354         plane_state->dcc.grph.independent_64b_blks = i64b;
2355
2356         dcc_address = get_dcc_address(afb->address, info);
2357         plane_state->address.grph.meta_addr.low_part =
2358                 lower_32_bits(dcc_address);
2359         plane_state->address.grph.meta_addr.high_part =
2360                 upper_32_bits(dcc_address);
2361
2362         return true;
2363 }
2364
2365 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2366                                          struct dc_plane_state *plane_state,
2367                                          const struct amdgpu_framebuffer *amdgpu_fb)
2368 {
2369         uint64_t tiling_flags;
2370         unsigned int awidth;
2371         const struct drm_framebuffer *fb = &amdgpu_fb->base;
2372         int ret = 0;
2373         struct drm_format_name_buf format_name;
2374
2375         ret = get_fb_info(
2376                 amdgpu_fb,
2377                 &tiling_flags);
2378
2379         if (ret)
2380                 return ret;
2381
2382         switch (fb->format->format) {
2383         case DRM_FORMAT_C8:
2384                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2385                 break;
2386         case DRM_FORMAT_RGB565:
2387                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2388                 break;
2389         case DRM_FORMAT_XRGB8888:
2390         case DRM_FORMAT_ARGB8888:
2391                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2392                 break;
2393         case DRM_FORMAT_XRGB2101010:
2394         case DRM_FORMAT_ARGB2101010:
2395                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2396                 break;
2397         case DRM_FORMAT_XBGR2101010:
2398         case DRM_FORMAT_ABGR2101010:
2399                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2400                 break;
2401         case DRM_FORMAT_XBGR8888:
2402         case DRM_FORMAT_ABGR8888:
2403                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2404                 break;
2405         case DRM_FORMAT_NV21:
2406                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2407                 break;
2408         case DRM_FORMAT_NV12:
2409                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2410                 break;
2411         default:
2412                 DRM_ERROR("Unsupported screen format %s\n",
2413                           drm_get_format_name(fb->format->format, &format_name));
2414                 return -EINVAL;
2415         }
2416
2417         memset(&plane_state->address, 0, sizeof(plane_state->address));
2418         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2419         memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
2420
2421         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2422                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
2423                 plane_state->plane_size.grph.surface_size.x = 0;
2424                 plane_state->plane_size.grph.surface_size.y = 0;
2425                 plane_state->plane_size.grph.surface_size.width = fb->width;
2426                 plane_state->plane_size.grph.surface_size.height = fb->height;
2427                 plane_state->plane_size.grph.surface_pitch =
2428                                 fb->pitches[0] / fb->format->cpp[0];
2429                 /* TODO: unhardcode */
2430                 plane_state->color_space = COLOR_SPACE_SRGB;
2431
2432         } else {
2433                 awidth = ALIGN(fb->width, 64);
2434                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2435                 plane_state->plane_size.video.luma_size.x = 0;
2436                 plane_state->plane_size.video.luma_size.y = 0;
2437                 plane_state->plane_size.video.luma_size.width = awidth;
2438                 plane_state->plane_size.video.luma_size.height = fb->height;
2439                 /* TODO: unhardcode */
2440                 plane_state->plane_size.video.luma_pitch = awidth;
2441
2442                 plane_state->plane_size.video.chroma_size.x = 0;
2443                 plane_state->plane_size.video.chroma_size.y = 0;
2444                 plane_state->plane_size.video.chroma_size.width = awidth;
2445                 plane_state->plane_size.video.chroma_size.height = fb->height;
2446                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
2447
2448                 /* TODO: unhardcode */
2449                 plane_state->color_space = COLOR_SPACE_YCBCR709;
2450         }
2451
2452         /* Fill GFX8 params */
2453         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2454                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2455
2456                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2457                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2458                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2459                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2460                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2461
2462                 /* XXX fix me for VI */
2463                 plane_state->tiling_info.gfx8.num_banks = num_banks;
2464                 plane_state->tiling_info.gfx8.array_mode =
2465                                 DC_ARRAY_2D_TILED_THIN1;
2466                 plane_state->tiling_info.gfx8.tile_split = tile_split;
2467                 plane_state->tiling_info.gfx8.bank_width = bankw;
2468                 plane_state->tiling_info.gfx8.bank_height = bankh;
2469                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2470                 plane_state->tiling_info.gfx8.tile_mode =
2471                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2472         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2473                         == DC_ARRAY_1D_TILED_THIN1) {
2474                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2475         }
2476
2477         plane_state->tiling_info.gfx8.pipe_config =
2478                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2479
2480         if (adev->asic_type == CHIP_VEGA10 ||
2481             adev->asic_type == CHIP_VEGA12 ||
2482             adev->asic_type == CHIP_VEGA20 ||
2483             adev->asic_type == CHIP_RAVEN) {
2484                 /* Fill GFX9 params */
2485                 plane_state->tiling_info.gfx9.num_pipes =
2486                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2487                 plane_state->tiling_info.gfx9.num_banks =
2488                         adev->gfx.config.gb_addr_config_fields.num_banks;
2489                 plane_state->tiling_info.gfx9.pipe_interleave =
2490                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2491                 plane_state->tiling_info.gfx9.num_shader_engines =
2492                         adev->gfx.config.gb_addr_config_fields.num_se;
2493                 plane_state->tiling_info.gfx9.max_compressed_frags =
2494                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2495                 plane_state->tiling_info.gfx9.num_rb_per_se =
2496                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2497                 plane_state->tiling_info.gfx9.swizzle =
2498                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2499                 plane_state->tiling_info.gfx9.shaderEnable = 1;
2500
2501                 fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
2502                                           tiling_flags);
2503         }
2504
2505         plane_state->visible = true;
2506         plane_state->scaling_quality.h_taps_c = 0;
2507         plane_state->scaling_quality.v_taps_c = 0;
2508
2509         /* is this needed? is plane_state zeroed at allocation? */
2510         plane_state->scaling_quality.h_taps = 0;
2511         plane_state->scaling_quality.v_taps = 0;
2512         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2513
2514         return ret;
2515
2516 }
2517
2518 static int fill_plane_attributes(struct amdgpu_device *adev,
2519                                  struct dc_plane_state *dc_plane_state,
2520                                  struct drm_plane_state *plane_state,
2521                                  struct drm_crtc_state *crtc_state)
2522 {
2523         const struct amdgpu_framebuffer *amdgpu_fb =
2524                 to_amdgpu_framebuffer(plane_state->fb);
2525         const struct drm_crtc *crtc = plane_state->crtc;
2526         int ret = 0;
2527
2528         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2529                 return -EINVAL;
2530
2531         ret = fill_plane_attributes_from_fb(
2532                 crtc->dev->dev_private,
2533                 dc_plane_state,
2534                 amdgpu_fb);
2535
2536         if (ret)
2537                 return ret;
2538
2539         /*
2540          * Always set input transfer function, since plane state is refreshed
2541          * every time.
2542          */
2543         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2544         if (ret) {
2545                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2546                 dc_plane_state->in_transfer_func = NULL;
2547         }
2548
2549         return ret;
2550 }
2551
2552 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2553                                            const struct dm_connector_state *dm_state,
2554                                            struct dc_stream_state *stream)
2555 {
2556         enum amdgpu_rmx_type rmx_type;
2557
2558         struct rect src = { 0 }; /* viewport in composition space*/
2559         struct rect dst = { 0 }; /* stream addressable area */
2560
2561         /* no mode. nothing to be done */
2562         if (!mode)
2563                 return;
2564
2565         /* Full screen scaling by default */
2566         src.width = mode->hdisplay;
2567         src.height = mode->vdisplay;
2568         dst.width = stream->timing.h_addressable;
2569         dst.height = stream->timing.v_addressable;
2570
2571         if (dm_state) {
2572                 rmx_type = dm_state->scaling;
2573                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2574                         if (src.width * dst.height <
2575                                         src.height * dst.width) {
2576                                 /* height needs less upscaling/more downscaling */
2577                                 dst.width = src.width *
2578                                                 dst.height / src.height;
2579                         } else {
2580                                 /* width needs less upscaling/more downscaling */
2581                                 dst.height = src.height *
2582                                                 dst.width / src.width;
2583                         }
2584                 } else if (rmx_type == RMX_CENTER) {
2585                         dst = src;
2586                 }
2587
2588                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2589                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2590
2591                 if (dm_state->underscan_enable) {
2592                         dst.x += dm_state->underscan_hborder / 2;
2593                         dst.y += dm_state->underscan_vborder / 2;
2594                         dst.width -= dm_state->underscan_hborder;
2595                         dst.height -= dm_state->underscan_vborder;
2596                 }
2597         }
2598
2599         stream->src = src;
2600         stream->dst = dst;
2601
2602         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2603                         dst.x, dst.y, dst.width, dst.height);
2604
2605 }
2606
2607 static enum dc_color_depth
2608 convert_color_depth_from_display_info(const struct drm_connector *connector)
2609 {
2610         struct dm_connector_state *dm_conn_state =
2611                 to_dm_connector_state(connector->state);
2612         uint32_t bpc = connector->display_info.bpc;
2613
2614         /* TODO: Remove this when there's support for max_bpc in drm */
2615         if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2616                 /* Round down to nearest even number. */
2617                 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2618
2619         switch (bpc) {
2620         case 0:
2621                 /*
2622                  * Temporary Work around, DRM doesn't parse color depth for
2623                  * EDID revision before 1.4
2624                  * TODO: Fix edid parsing
2625                  */
2626                 return COLOR_DEPTH_888;
2627         case 6:
2628                 return COLOR_DEPTH_666;
2629         case 8:
2630                 return COLOR_DEPTH_888;
2631         case 10:
2632                 return COLOR_DEPTH_101010;
2633         case 12:
2634                 return COLOR_DEPTH_121212;
2635         case 14:
2636                 return COLOR_DEPTH_141414;
2637         case 16:
2638                 return COLOR_DEPTH_161616;
2639         default:
2640                 return COLOR_DEPTH_UNDEFINED;
2641         }
2642 }
2643
2644 static enum dc_aspect_ratio
2645 get_aspect_ratio(const struct drm_display_mode *mode_in)
2646 {
2647         /* 1-1 mapping, since both enums follow the HDMI spec. */
2648         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2649 }
2650
2651 static enum dc_color_space
2652 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2653 {
2654         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2655
2656         switch (dc_crtc_timing->pixel_encoding) {
2657         case PIXEL_ENCODING_YCBCR422:
2658         case PIXEL_ENCODING_YCBCR444:
2659         case PIXEL_ENCODING_YCBCR420:
2660         {
2661                 /*
2662                  * 27030khz is the separation point between HDTV and SDTV
2663                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2664                  * respectively
2665                  */
2666                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
2667                         if (dc_crtc_timing->flags.Y_ONLY)
2668                                 color_space =
2669                                         COLOR_SPACE_YCBCR709_LIMITED;
2670                         else
2671                                 color_space = COLOR_SPACE_YCBCR709;
2672                 } else {
2673                         if (dc_crtc_timing->flags.Y_ONLY)
2674                                 color_space =
2675                                         COLOR_SPACE_YCBCR601_LIMITED;
2676                         else
2677                                 color_space = COLOR_SPACE_YCBCR601;
2678                 }
2679
2680         }
2681         break;
2682         case PIXEL_ENCODING_RGB:
2683                 color_space = COLOR_SPACE_SRGB;
2684                 break;
2685
2686         default:
2687                 WARN_ON(1);
2688                 break;
2689         }
2690
2691         return color_space;
2692 }
2693
2694 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2695 {
2696         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2697                 return;
2698
2699         timing_out->display_color_depth--;
2700 }
2701
2702 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2703                                                 const struct drm_display_info *info)
2704 {
2705         int normalized_clk;
2706         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2707                 return;
2708         do {
2709                 normalized_clk = timing_out->pix_clk_100hz / 10;
2710                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2711                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2712                         normalized_clk /= 2;
2713                 /* Adjusting pix clock following on HDMI spec based on colour depth */
2714                 switch (timing_out->display_color_depth) {
2715                 case COLOR_DEPTH_101010:
2716                         normalized_clk = (normalized_clk * 30) / 24;
2717                         break;
2718                 case COLOR_DEPTH_121212:
2719                         normalized_clk = (normalized_clk * 36) / 24;
2720                         break;
2721                 case COLOR_DEPTH_161616:
2722                         normalized_clk = (normalized_clk * 48) / 24;
2723                         break;
2724                 default:
2725                         return;
2726                 }
2727                 if (normalized_clk <= info->max_tmds_clock)
2728                         return;
2729                 reduce_mode_colour_depth(timing_out);
2730
2731         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2732
2733 }
2734
2735 static void
2736 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2737                                              const struct drm_display_mode *mode_in,
2738                                              const struct drm_connector *connector,
2739                                              const struct dc_stream_state *old_stream)
2740 {
2741         struct dc_crtc_timing *timing_out = &stream->timing;
2742         const struct drm_display_info *info = &connector->display_info;
2743
2744         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2745
2746         timing_out->h_border_left = 0;
2747         timing_out->h_border_right = 0;
2748         timing_out->v_border_top = 0;
2749         timing_out->v_border_bottom = 0;
2750         /* TODO: un-hardcode */
2751         if (drm_mode_is_420_only(info, mode_in)
2752                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2753                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2754         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2755                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2756                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2757         else
2758                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2759
2760         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2761         timing_out->display_color_depth = convert_color_depth_from_display_info(
2762                         connector);
2763         timing_out->scan_type = SCANNING_TYPE_NODATA;
2764         timing_out->hdmi_vic = 0;
2765
2766         if(old_stream) {
2767                 timing_out->vic = old_stream->timing.vic;
2768                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2769                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2770         } else {
2771                 timing_out->vic = drm_match_cea_mode(mode_in);
2772                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2773                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2774                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2775                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2776         }
2777
2778         timing_out->h_addressable = mode_in->crtc_hdisplay;
2779         timing_out->h_total = mode_in->crtc_htotal;
2780         timing_out->h_sync_width =
2781                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2782         timing_out->h_front_porch =
2783                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2784         timing_out->v_total = mode_in->crtc_vtotal;
2785         timing_out->v_addressable = mode_in->crtc_vdisplay;
2786         timing_out->v_front_porch =
2787                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2788         timing_out->v_sync_width =
2789                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2790         timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
2791         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2792
2793         stream->output_color_space = get_output_color_space(timing_out);
2794
2795         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2796         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2797         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
2798                 adjust_colour_depth_from_display_info(timing_out, info);
2799 }
2800
2801 static void fill_audio_info(struct audio_info *audio_info,
2802                             const struct drm_connector *drm_connector,
2803                             const struct dc_sink *dc_sink)
2804 {
2805         int i = 0;
2806         int cea_revision = 0;
2807         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2808
2809         audio_info->manufacture_id = edid_caps->manufacturer_id;
2810         audio_info->product_id = edid_caps->product_id;
2811
2812         cea_revision = drm_connector->display_info.cea_rev;
2813
2814         strscpy(audio_info->display_name,
2815                 edid_caps->display_name,
2816                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
2817
2818         if (cea_revision >= 3) {
2819                 audio_info->mode_count = edid_caps->audio_mode_count;
2820
2821                 for (i = 0; i < audio_info->mode_count; ++i) {
2822                         audio_info->modes[i].format_code =
2823                                         (enum audio_format_code)
2824                                         (edid_caps->audio_modes[i].format_code);
2825                         audio_info->modes[i].channel_count =
2826                                         edid_caps->audio_modes[i].channel_count;
2827                         audio_info->modes[i].sample_rates.all =
2828                                         edid_caps->audio_modes[i].sample_rate;
2829                         audio_info->modes[i].sample_size =
2830                                         edid_caps->audio_modes[i].sample_size;
2831                 }
2832         }
2833
2834         audio_info->flags.all = edid_caps->speaker_flags;
2835
2836         /* TODO: We only check for the progressive mode, check for interlace mode too */
2837         if (drm_connector->latency_present[0]) {
2838                 audio_info->video_latency = drm_connector->video_latency[0];
2839                 audio_info->audio_latency = drm_connector->audio_latency[0];
2840         }
2841
2842         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2843
2844 }
2845
2846 static void
2847 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2848                                       struct drm_display_mode *dst_mode)
2849 {
2850         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2851         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2852         dst_mode->crtc_clock = src_mode->crtc_clock;
2853         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2854         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2855         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2856         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2857         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2858         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2859         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2860         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2861         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2862         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2863         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2864 }
2865
2866 static void
2867 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2868                                         const struct drm_display_mode *native_mode,
2869                                         bool scale_enabled)
2870 {
2871         if (scale_enabled) {
2872                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2873         } else if (native_mode->clock == drm_mode->clock &&
2874                         native_mode->htotal == drm_mode->htotal &&
2875                         native_mode->vtotal == drm_mode->vtotal) {
2876                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2877         } else {
2878                 /* no scaling nor amdgpu inserted, no need to patch */
2879         }
2880 }
2881
2882 static struct dc_sink *
2883 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2884 {
2885         struct dc_sink_init_data sink_init_data = { 0 };
2886         struct dc_sink *sink = NULL;
2887         sink_init_data.link = aconnector->dc_link;
2888         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2889
2890         sink = dc_sink_create(&sink_init_data);
2891         if (!sink) {
2892                 DRM_ERROR("Failed to create sink!\n");
2893                 return NULL;
2894         }
2895         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2896
2897         return sink;
2898 }
2899
2900 static void set_multisync_trigger_params(
2901                 struct dc_stream_state *stream)
2902 {
2903         if (stream->triggered_crtc_reset.enabled) {
2904                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2905                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2906         }
2907 }
2908
2909 static void set_master_stream(struct dc_stream_state *stream_set[],
2910                               int stream_count)
2911 {
2912         int j, highest_rfr = 0, master_stream = 0;
2913
2914         for (j = 0;  j < stream_count; j++) {
2915                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2916                         int refresh_rate = 0;
2917
2918                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
2919                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2920                         if (refresh_rate > highest_rfr) {
2921                                 highest_rfr = refresh_rate;
2922                                 master_stream = j;
2923                         }
2924                 }
2925         }
2926         for (j = 0;  j < stream_count; j++) {
2927                 if (stream_set[j])
2928                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2929         }
2930 }
2931
2932 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2933 {
2934         int i = 0;
2935
2936         if (context->stream_count < 2)
2937                 return;
2938         for (i = 0; i < context->stream_count ; i++) {
2939                 if (!context->streams[i])
2940                         continue;
2941                 /*
2942                  * TODO: add a function to read AMD VSDB bits and set
2943                  * crtc_sync_master.multi_sync_enabled flag
2944                  * For now it's set to false
2945                  */
2946                 set_multisync_trigger_params(context->streams[i]);
2947         }
2948         set_master_stream(context->streams, context->stream_count);
2949 }
2950
2951 static struct dc_stream_state *
2952 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2953                        const struct drm_display_mode *drm_mode,
2954                        const struct dm_connector_state *dm_state,
2955                        const struct dc_stream_state *old_stream)
2956 {
2957         struct drm_display_mode *preferred_mode = NULL;
2958         struct drm_connector *drm_connector;
2959         struct dc_stream_state *stream = NULL;
2960         struct drm_display_mode mode = *drm_mode;
2961         bool native_mode_found = false;
2962         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2963         int mode_refresh;
2964         int preferred_refresh = 0;
2965
2966         struct dc_sink *sink = NULL;
2967         if (aconnector == NULL) {
2968                 DRM_ERROR("aconnector is NULL!\n");
2969                 return stream;
2970         }
2971
2972         drm_connector = &aconnector->base;
2973
2974         if (!aconnector->dc_sink) {
2975                 sink = create_fake_sink(aconnector);
2976                 if (!sink)
2977                         return stream;
2978         } else {
2979                 sink = aconnector->dc_sink;
2980         }
2981
2982         stream = dc_create_stream_for_sink(sink);
2983
2984         if (stream == NULL) {
2985                 DRM_ERROR("Failed to create stream for sink!\n");
2986                 goto finish;
2987         }
2988
2989         stream->dm_stream_context = aconnector;
2990
2991         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2992                 /* Search for preferred mode */
2993                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2994                         native_mode_found = true;
2995                         break;
2996                 }
2997         }
2998         if (!native_mode_found)
2999                 preferred_mode = list_first_entry_or_null(
3000                                 &aconnector->base.modes,
3001                                 struct drm_display_mode,
3002                                 head);
3003
3004         mode_refresh = drm_mode_vrefresh(&mode);
3005
3006         if (preferred_mode == NULL) {
3007                 /*
3008                  * This may not be an error, the use case is when we have no
3009                  * usermode calls to reset and set mode upon hotplug. In this
3010                  * case, we call set mode ourselves to restore the previous mode
3011                  * and the modelist may not be filled in in time.
3012                  */
3013                 DRM_DEBUG_DRIVER("No preferred mode found\n");
3014         } else {
3015                 decide_crtc_timing_for_drm_display_mode(
3016                                 &mode, preferred_mode,
3017                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3018                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3019         }
3020
3021         if (!dm_state)
3022                 drm_mode_set_crtcinfo(&mode, 0);
3023
3024         /*
3025         * If scaling is enabled and refresh rate didn't change
3026         * we copy the vic and polarities of the old timings
3027         */
3028         if (!scale || mode_refresh != preferred_refresh)
3029                 fill_stream_properties_from_drm_display_mode(stream,
3030                         &mode, &aconnector->base, NULL);
3031         else
3032                 fill_stream_properties_from_drm_display_mode(stream,
3033                         &mode, &aconnector->base, old_stream);
3034
3035         update_stream_scaling_settings(&mode, dm_state, stream);
3036
3037         fill_audio_info(
3038                 &stream->audio_info,
3039                 drm_connector,
3040                 sink);
3041
3042         update_stream_signal(stream, sink);
3043
3044 finish:
3045         if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
3046                 dc_sink_release(sink);
3047
3048         return stream;
3049 }
3050
3051 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3052 {
3053         drm_crtc_cleanup(crtc);
3054         kfree(crtc);
3055 }
3056
3057 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3058                                   struct drm_crtc_state *state)
3059 {
3060         struct dm_crtc_state *cur = to_dm_crtc_state(state);
3061
3062         /* TODO Destroy dc_stream objects are stream object is flattened */
3063         if (cur->stream)
3064                 dc_stream_release(cur->stream);
3065
3066
3067         __drm_atomic_helper_crtc_destroy_state(state);
3068
3069
3070         kfree(state);
3071 }
3072
3073 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3074 {
3075         struct dm_crtc_state *state;
3076
3077         if (crtc->state)
3078                 dm_crtc_destroy_state(crtc, crtc->state);
3079
3080         state = kzalloc(sizeof(*state), GFP_KERNEL);
3081         if (WARN_ON(!state))
3082                 return;
3083
3084         crtc->state = &state->base;
3085         crtc->state->crtc = crtc;
3086
3087 }
3088
3089 static struct drm_crtc_state *
3090 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3091 {
3092         struct dm_crtc_state *state, *cur;
3093
3094         cur = to_dm_crtc_state(crtc->state);
3095
3096         if (WARN_ON(!crtc->state))
3097                 return NULL;
3098
3099         state = kzalloc(sizeof(*state), GFP_KERNEL);
3100         if (!state)
3101                 return NULL;
3102
3103         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3104
3105         if (cur->stream) {
3106                 state->stream = cur->stream;
3107                 dc_stream_retain(state->stream);
3108         }
3109
3110         state->vrr_params = cur->vrr_params;
3111         state->vrr_infopacket = cur->vrr_infopacket;
3112         state->abm_level = cur->abm_level;
3113         state->vrr_supported = cur->vrr_supported;
3114         state->freesync_config = cur->freesync_config;
3115         state->crc_enabled = cur->crc_enabled;
3116
3117         /* TODO Duplicate dc_stream after objects are stream object is flattened */
3118
3119         return &state->base;
3120 }
3121
3122
3123 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3124 {
3125         enum dc_irq_source irq_source;
3126         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3127         struct amdgpu_device *adev = crtc->dev->dev_private;
3128
3129         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3130         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3131 }
3132
3133 static int dm_enable_vblank(struct drm_crtc *crtc)
3134 {
3135         return dm_set_vblank(crtc, true);
3136 }
3137
3138 static void dm_disable_vblank(struct drm_crtc *crtc)
3139 {
3140         dm_set_vblank(crtc, false);
3141 }
3142
3143 /* Implemented only the options currently availible for the driver */
3144 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3145         .reset = dm_crtc_reset_state,
3146         .destroy = amdgpu_dm_crtc_destroy,
3147         .gamma_set = drm_atomic_helper_legacy_gamma_set,
3148         .set_config = drm_atomic_helper_set_config,
3149         .page_flip = drm_atomic_helper_page_flip,
3150         .atomic_duplicate_state = dm_crtc_duplicate_state,
3151         .atomic_destroy_state = dm_crtc_destroy_state,
3152         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3153         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3154         .enable_vblank = dm_enable_vblank,
3155         .disable_vblank = dm_disable_vblank,
3156 };
3157
3158 static enum drm_connector_status
3159 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3160 {
3161         bool connected;
3162         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3163
3164         /*
3165          * Notes:
3166          * 1. This interface is NOT called in context of HPD irq.
3167          * 2. This interface *is called* in context of user-mode ioctl. Which
3168          * makes it a bad place for *any* MST-related activity.
3169          */
3170
3171         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3172             !aconnector->fake_enable)
3173                 connected = (aconnector->dc_sink != NULL);
3174         else
3175                 connected = (aconnector->base.force == DRM_FORCE_ON);
3176
3177         return (connected ? connector_status_connected :
3178                         connector_status_disconnected);
3179 }
3180
3181 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3182                                             struct drm_connector_state *connector_state,
3183                                             struct drm_property *property,
3184                                             uint64_t val)
3185 {
3186         struct drm_device *dev = connector->dev;
3187         struct amdgpu_device *adev = dev->dev_private;
3188         struct dm_connector_state *dm_old_state =
3189                 to_dm_connector_state(connector->state);
3190         struct dm_connector_state *dm_new_state =
3191                 to_dm_connector_state(connector_state);
3192
3193         int ret = -EINVAL;
3194
3195         if (property == dev->mode_config.scaling_mode_property) {
3196                 enum amdgpu_rmx_type rmx_type;
3197
3198                 switch (val) {
3199                 case DRM_MODE_SCALE_CENTER:
3200                         rmx_type = RMX_CENTER;
3201                         break;
3202                 case DRM_MODE_SCALE_ASPECT:
3203                         rmx_type = RMX_ASPECT;
3204                         break;
3205                 case DRM_MODE_SCALE_FULLSCREEN:
3206                         rmx_type = RMX_FULL;
3207                         break;
3208                 case DRM_MODE_SCALE_NONE:
3209                 default:
3210                         rmx_type = RMX_OFF;
3211                         break;
3212                 }
3213
3214                 if (dm_old_state->scaling == rmx_type)
3215                         return 0;
3216
3217                 dm_new_state->scaling = rmx_type;
3218                 ret = 0;
3219         } else if (property == adev->mode_info.underscan_hborder_property) {
3220                 dm_new_state->underscan_hborder = val;
3221                 ret = 0;
3222         } else if (property == adev->mode_info.underscan_vborder_property) {
3223                 dm_new_state->underscan_vborder = val;
3224                 ret = 0;
3225         } else if (property == adev->mode_info.underscan_property) {
3226                 dm_new_state->underscan_enable = val;
3227                 ret = 0;
3228         } else if (property == adev->mode_info.max_bpc_property) {
3229                 dm_new_state->max_bpc = val;
3230                 ret = 0;
3231         } else if (property == adev->mode_info.abm_level_property) {
3232                 dm_new_state->abm_level = val;
3233                 ret = 0;
3234         }
3235
3236         return ret;
3237 }
3238
3239 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3240                                             const struct drm_connector_state *state,
3241                                             struct drm_property *property,
3242                                             uint64_t *val)
3243 {
3244         struct drm_device *dev = connector->dev;
3245         struct amdgpu_device *adev = dev->dev_private;
3246         struct dm_connector_state *dm_state =
3247                 to_dm_connector_state(state);
3248         int ret = -EINVAL;
3249
3250         if (property == dev->mode_config.scaling_mode_property) {
3251                 switch (dm_state->scaling) {
3252                 case RMX_CENTER:
3253                         *val = DRM_MODE_SCALE_CENTER;
3254                         break;
3255                 case RMX_ASPECT:
3256                         *val = DRM_MODE_SCALE_ASPECT;
3257                         break;
3258                 case RMX_FULL:
3259                         *val = DRM_MODE_SCALE_FULLSCREEN;
3260                         break;
3261                 case RMX_OFF:
3262                 default:
3263                         *val = DRM_MODE_SCALE_NONE;
3264                         break;
3265                 }
3266                 ret = 0;
3267         } else if (property == adev->mode_info.underscan_hborder_property) {
3268                 *val = dm_state->underscan_hborder;
3269                 ret = 0;
3270         } else if (property == adev->mode_info.underscan_vborder_property) {
3271                 *val = dm_state->underscan_vborder;
3272                 ret = 0;
3273         } else if (property == adev->mode_info.underscan_property) {
3274                 *val = dm_state->underscan_enable;
3275                 ret = 0;
3276         } else if (property == adev->mode_info.max_bpc_property) {
3277                 *val = dm_state->max_bpc;
3278                 ret = 0;
3279         } else if (property == adev->mode_info.abm_level_property) {
3280                 *val = dm_state->abm_level;
3281                 ret = 0;
3282         }
3283
3284         return ret;
3285 }
3286
3287 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3288 {
3289         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3290         const struct dc_link *link = aconnector->dc_link;
3291         struct amdgpu_device *adev = connector->dev->dev_private;
3292         struct amdgpu_display_manager *dm = &adev->dm;
3293
3294 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3295         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3296
3297         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3298             link->type != dc_connection_none &&
3299             dm->backlight_dev) {
3300                 backlight_device_unregister(dm->backlight_dev);
3301                 dm->backlight_dev = NULL;
3302         }
3303 #endif
3304         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3305         drm_connector_unregister(connector);
3306         drm_connector_cleanup(connector);
3307         kfree(connector);
3308 }
3309
3310 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3311 {
3312         struct dm_connector_state *state =
3313                 to_dm_connector_state(connector->state);
3314
3315         if (connector->state)
3316                 __drm_atomic_helper_connector_destroy_state(connector->state);
3317
3318         kfree(state);
3319
3320         state = kzalloc(sizeof(*state), GFP_KERNEL);
3321
3322         if (state) {
3323                 state->scaling = RMX_OFF;
3324                 state->underscan_enable = false;
3325                 state->underscan_hborder = 0;
3326                 state->underscan_vborder = 0;
3327                 state->max_bpc = 8;
3328
3329                 __drm_atomic_helper_connector_reset(connector, &state->base);
3330         }
3331 }
3332
3333 struct drm_connector_state *
3334 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3335 {
3336         struct dm_connector_state *state =
3337                 to_dm_connector_state(connector->state);
3338
3339         struct dm_connector_state *new_state =
3340                         kmemdup(state, sizeof(*state), GFP_KERNEL);
3341
3342         if (!new_state)
3343                 return NULL;
3344
3345         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3346
3347         new_state->freesync_capable = state->freesync_capable;
3348         new_state->abm_level = state->abm_level;
3349         new_state->scaling = state->scaling;
3350         new_state->underscan_enable = state->underscan_enable;
3351         new_state->underscan_hborder = state->underscan_hborder;
3352         new_state->underscan_vborder = state->underscan_vborder;
3353         new_state->max_bpc = state->max_bpc;
3354
3355         return &new_state->base;
3356 }
3357
3358 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3359         .reset = amdgpu_dm_connector_funcs_reset,
3360         .detect = amdgpu_dm_connector_detect,
3361         .fill_modes = drm_helper_probe_single_connector_modes,
3362         .destroy = amdgpu_dm_connector_destroy,
3363         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3364         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3365         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3366         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3367 };
3368
3369 static int get_modes(struct drm_connector *connector)
3370 {
3371         return amdgpu_dm_connector_get_modes(connector);
3372 }
3373
3374 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3375 {
3376         struct dc_sink_init_data init_params = {
3377                         .link = aconnector->dc_link,
3378                         .sink_signal = SIGNAL_TYPE_VIRTUAL
3379         };
3380         struct edid *edid;
3381
3382         if (!aconnector->base.edid_blob_ptr) {
3383                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3384                                 aconnector->base.name);
3385
3386                 aconnector->base.force = DRM_FORCE_OFF;
3387                 aconnector->base.override_edid = false;
3388                 return;
3389         }
3390
3391         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3392
3393         aconnector->edid = edid;
3394
3395         aconnector->dc_em_sink = dc_link_add_remote_sink(
3396                 aconnector->dc_link,
3397                 (uint8_t *)edid,
3398                 (edid->extensions + 1) * EDID_LENGTH,
3399                 &init_params);
3400
3401         if (aconnector->base.force == DRM_FORCE_ON)
3402                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3403                 aconnector->dc_link->local_sink :
3404                 aconnector->dc_em_sink;
3405 }
3406
3407 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3408 {
3409         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3410
3411         /*
3412          * In case of headless boot with force on for DP managed connector
3413          * Those settings have to be != 0 to get initial modeset
3414          */
3415         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3416                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3417                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3418         }
3419
3420
3421         aconnector->base.override_edid = true;
3422         create_eml_sink(aconnector);
3423 }
3424
3425 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3426                                    struct drm_display_mode *mode)
3427 {
3428         int result = MODE_ERROR;
3429         struct dc_sink *dc_sink;
3430         struct amdgpu_device *adev = connector->dev->dev_private;
3431         /* TODO: Unhardcode stream count */
3432         struct dc_stream_state *stream;
3433         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3434         enum dc_status dc_result = DC_OK;
3435
3436         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3437                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3438                 return result;
3439
3440         /*
3441          * Only run this the first time mode_valid is called to initilialize
3442          * EDID mgmt
3443          */
3444         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3445                 !aconnector->dc_em_sink)
3446                 handle_edid_mgmt(aconnector);
3447
3448         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3449
3450         if (dc_sink == NULL) {
3451                 DRM_ERROR("dc_sink is NULL!\n");
3452                 goto fail;
3453         }
3454
3455         stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
3456         if (stream == NULL) {
3457                 DRM_ERROR("Failed to create stream for sink!\n");
3458                 goto fail;
3459         }
3460
3461         dc_result = dc_validate_stream(adev->dm.dc, stream);
3462
3463         if (dc_result == DC_OK)
3464                 result = MODE_OK;
3465         else
3466                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3467                               mode->vdisplay,
3468                               mode->hdisplay,
3469                               mode->clock,
3470                               dc_result);
3471
3472         dc_stream_release(stream);
3473
3474 fail:
3475         /* TODO: error handling*/
3476         return result;
3477 }
3478
3479 static const struct drm_connector_helper_funcs
3480 amdgpu_dm_connector_helper_funcs = {
3481         /*
3482          * If hotplugging a second bigger display in FB Con mode, bigger resolution
3483          * modes will be filtered by drm_mode_validate_size(), and those modes
3484          * are missing after user start lightdm. So we need to renew modes list.
3485          * in get_modes call back, not just return the modes count
3486          */
3487         .get_modes = get_modes,
3488         .mode_valid = amdgpu_dm_connector_mode_valid,
3489 };
3490
3491 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3492 {
3493 }
3494
3495 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3496                                        struct drm_crtc_state *state)
3497 {
3498         struct amdgpu_device *adev = crtc->dev->dev_private;
3499         struct dc *dc = adev->dm.dc;
3500         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3501         int ret = -EINVAL;
3502
3503         if (unlikely(!dm_crtc_state->stream &&
3504                      modeset_required(state, NULL, dm_crtc_state->stream))) {
3505                 WARN_ON(1);
3506                 return ret;
3507         }
3508
3509         /* In some use cases, like reset, no stream is attached */
3510         if (!dm_crtc_state->stream)
3511                 return 0;
3512
3513         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
3514                 return 0;
3515
3516         return ret;
3517 }
3518
3519 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3520                                       const struct drm_display_mode *mode,
3521                                       struct drm_display_mode *adjusted_mode)
3522 {
3523         return true;
3524 }
3525
3526 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3527         .disable = dm_crtc_helper_disable,
3528         .atomic_check = dm_crtc_helper_atomic_check,
3529         .mode_fixup = dm_crtc_helper_mode_fixup
3530 };
3531
3532 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3533 {
3534
3535 }
3536
3537 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3538                                           struct drm_crtc_state *crtc_state,
3539                                           struct drm_connector_state *conn_state)
3540 {
3541         return 0;
3542 }
3543
3544 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3545         .disable = dm_encoder_helper_disable,
3546         .atomic_check = dm_encoder_helper_atomic_check
3547 };
3548
3549 static void dm_drm_plane_reset(struct drm_plane *plane)
3550 {
3551         struct dm_plane_state *amdgpu_state = NULL;
3552
3553         if (plane->state)
3554                 plane->funcs->atomic_destroy_state(plane, plane->state);
3555
3556         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
3557         WARN_ON(amdgpu_state == NULL);
3558
3559         if (amdgpu_state) {
3560                 plane->state = &amdgpu_state->base;
3561                 plane->state->plane = plane;
3562                 plane->state->rotation = DRM_MODE_ROTATE_0;
3563         }
3564 }
3565
3566 static struct drm_plane_state *
3567 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3568 {
3569         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3570
3571         old_dm_plane_state = to_dm_plane_state(plane->state);
3572         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3573         if (!dm_plane_state)
3574                 return NULL;
3575
3576         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3577
3578         if (old_dm_plane_state->dc_state) {
3579                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3580                 dc_plane_state_retain(dm_plane_state->dc_state);
3581         }
3582
3583         return &dm_plane_state->base;
3584 }
3585
3586 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3587                                 struct drm_plane_state *state)
3588 {
3589         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3590
3591         if (dm_plane_state->dc_state)
3592                 dc_plane_state_release(dm_plane_state->dc_state);
3593
3594         drm_atomic_helper_plane_destroy_state(plane, state);
3595 }
3596
3597 static const struct drm_plane_funcs dm_plane_funcs = {
3598         .update_plane   = drm_atomic_helper_update_plane,
3599         .disable_plane  = drm_atomic_helper_disable_plane,
3600         .destroy        = drm_primary_helper_destroy,
3601         .reset = dm_drm_plane_reset,
3602         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3603         .atomic_destroy_state = dm_drm_plane_destroy_state,
3604 };
3605
3606 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3607                                       struct drm_plane_state *new_state)
3608 {
3609         struct amdgpu_framebuffer *afb;
3610         struct drm_gem_object *obj;
3611         struct amdgpu_device *adev;
3612         struct amdgpu_bo *rbo;
3613         uint64_t chroma_addr = 0;
3614         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3615         uint64_t tiling_flags, dcc_address;
3616         unsigned int awidth;
3617         uint32_t domain;
3618         int r;
3619
3620         dm_plane_state_old = to_dm_plane_state(plane->state);
3621         dm_plane_state_new = to_dm_plane_state(new_state);
3622
3623         if (!new_state->fb) {
3624                 DRM_DEBUG_DRIVER("No FB bound\n");
3625                 return 0;
3626         }
3627
3628         afb = to_amdgpu_framebuffer(new_state->fb);
3629         obj = new_state->fb->obj[0];
3630         rbo = gem_to_amdgpu_bo(obj);
3631         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3632         r = amdgpu_bo_reserve(rbo, false);
3633         if (unlikely(r != 0))
3634                 return r;
3635
3636         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3637                 domain = amdgpu_display_supported_domains(adev);
3638         else
3639                 domain = AMDGPU_GEM_DOMAIN_VRAM;
3640
3641         r = amdgpu_bo_pin(rbo, domain);
3642         if (unlikely(r != 0)) {
3643                 if (r != -ERESTARTSYS)
3644                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3645                 amdgpu_bo_unreserve(rbo);
3646                 return r;
3647         }
3648
3649         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3650         if (unlikely(r != 0)) {
3651                 amdgpu_bo_unpin(rbo);
3652                 amdgpu_bo_unreserve(rbo);
3653                 DRM_ERROR("%p bind failed\n", rbo);
3654                 return r;
3655         }
3656
3657         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3658
3659         amdgpu_bo_unreserve(rbo);
3660
3661         afb->address = amdgpu_bo_gpu_offset(rbo);
3662
3663         amdgpu_bo_ref(rbo);
3664
3665         if (dm_plane_state_new->dc_state &&
3666                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3667                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3668
3669                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3670                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3671                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3672
3673                         dcc_address =
3674                                 get_dcc_address(afb->address, tiling_flags);
3675                         plane_state->address.grph.meta_addr.low_part =
3676                                 lower_32_bits(dcc_address);
3677                         plane_state->address.grph.meta_addr.high_part =
3678                                 upper_32_bits(dcc_address);
3679                 } else {
3680                         awidth = ALIGN(new_state->fb->width, 64);
3681                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3682                         plane_state->address.video_progressive.luma_addr.low_part
3683                                                         = lower_32_bits(afb->address);
3684                         plane_state->address.video_progressive.luma_addr.high_part
3685                                                         = upper_32_bits(afb->address);
3686                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3687                         plane_state->address.video_progressive.chroma_addr.low_part
3688                                                         = lower_32_bits(chroma_addr);
3689                         plane_state->address.video_progressive.chroma_addr.high_part
3690                                                         = upper_32_bits(chroma_addr);
3691                 }
3692         }
3693
3694         return 0;
3695 }
3696
3697 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3698                                        struct drm_plane_state *old_state)
3699 {
3700         struct amdgpu_bo *rbo;
3701         int r;
3702
3703         if (!old_state->fb)
3704                 return;
3705
3706         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3707         r = amdgpu_bo_reserve(rbo, false);
3708         if (unlikely(r)) {
3709                 DRM_ERROR("failed to reserve rbo before unpin\n");
3710                 return;
3711         }
3712
3713         amdgpu_bo_unpin(rbo);
3714         amdgpu_bo_unreserve(rbo);
3715         amdgpu_bo_unref(&rbo);
3716 }
3717
3718 static int dm_plane_atomic_check(struct drm_plane *plane,
3719                                  struct drm_plane_state *state)
3720 {
3721         struct amdgpu_device *adev = plane->dev->dev_private;
3722         struct dc *dc = adev->dm.dc;
3723         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3724
3725         if (!dm_plane_state->dc_state)
3726                 return 0;
3727
3728         if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3729                 return -EINVAL;
3730
3731         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3732                 return 0;
3733
3734         return -EINVAL;
3735 }
3736
3737 static int dm_plane_atomic_async_check(struct drm_plane *plane,
3738                                        struct drm_plane_state *new_plane_state)
3739 {
3740         struct drm_plane_state *old_plane_state =
3741                 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3742
3743         /* Only support async updates on cursor planes. */
3744         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3745                 return -EINVAL;
3746
3747         /*
3748          * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3749          * async commits so don't allow fb changes.
3750          */
3751         if (old_plane_state->fb != new_plane_state->fb)
3752                 return -EINVAL;
3753
3754         return 0;
3755 }
3756
3757 static void dm_plane_atomic_async_update(struct drm_plane *plane,
3758                                          struct drm_plane_state *new_state)
3759 {
3760         struct drm_plane_state *old_state =
3761                 drm_atomic_get_old_plane_state(new_state->state, plane);
3762
3763         if (plane->state->fb != new_state->fb)
3764                 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3765
3766         plane->state->src_x = new_state->src_x;
3767         plane->state->src_y = new_state->src_y;
3768         plane->state->src_w = new_state->src_w;
3769         plane->state->src_h = new_state->src_h;
3770         plane->state->crtc_x = new_state->crtc_x;
3771         plane->state->crtc_y = new_state->crtc_y;
3772         plane->state->crtc_w = new_state->crtc_w;
3773         plane->state->crtc_h = new_state->crtc_h;
3774
3775         handle_cursor_update(plane, old_state);
3776 }
3777
3778 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3779         .prepare_fb = dm_plane_helper_prepare_fb,
3780         .cleanup_fb = dm_plane_helper_cleanup_fb,
3781         .atomic_check = dm_plane_atomic_check,
3782         .atomic_async_check = dm_plane_atomic_async_check,
3783         .atomic_async_update = dm_plane_atomic_async_update
3784 };
3785
3786 /*
3787  * TODO: these are currently initialized to rgb formats only.
3788  * For future use cases we should either initialize them dynamically based on
3789  * plane capabilities, or initialize this array to all formats, so internal drm
3790  * check will succeed, and let DC implement proper check
3791  */
3792 static const uint32_t rgb_formats[] = {
3793         DRM_FORMAT_RGB888,
3794         DRM_FORMAT_XRGB8888,
3795         DRM_FORMAT_ARGB8888,
3796         DRM_FORMAT_RGBA8888,
3797         DRM_FORMAT_XRGB2101010,
3798         DRM_FORMAT_XBGR2101010,
3799         DRM_FORMAT_ARGB2101010,
3800         DRM_FORMAT_ABGR2101010,
3801         DRM_FORMAT_XBGR8888,
3802         DRM_FORMAT_ABGR8888,
3803 };
3804
3805 static const uint32_t yuv_formats[] = {
3806         DRM_FORMAT_NV12,
3807         DRM_FORMAT_NV21,
3808 };
3809
3810 static const u32 cursor_formats[] = {
3811         DRM_FORMAT_ARGB8888
3812 };
3813
3814 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3815                                 struct drm_plane *plane,
3816                                 unsigned long possible_crtcs)
3817 {
3818         int res = -EPERM;
3819
3820         switch (plane->type) {
3821         case DRM_PLANE_TYPE_PRIMARY:
3822                 res = drm_universal_plane_init(
3823                                 dm->adev->ddev,
3824                                 plane,
3825                                 possible_crtcs,
3826                                 &dm_plane_funcs,
3827                                 rgb_formats,
3828                                 ARRAY_SIZE(rgb_formats),
3829                                 NULL, plane->type, NULL);
3830                 break;
3831         case DRM_PLANE_TYPE_OVERLAY:
3832                 res = drm_universal_plane_init(
3833                                 dm->adev->ddev,
3834                                 plane,
3835                                 possible_crtcs,
3836                                 &dm_plane_funcs,
3837                                 yuv_formats,
3838                                 ARRAY_SIZE(yuv_formats),
3839                                 NULL, plane->type, NULL);
3840                 break;
3841         case DRM_PLANE_TYPE_CURSOR:
3842                 res = drm_universal_plane_init(
3843                                 dm->adev->ddev,
3844                                 plane,
3845                                 possible_crtcs,
3846                                 &dm_plane_funcs,
3847                                 cursor_formats,
3848                                 ARRAY_SIZE(cursor_formats),
3849                                 NULL, plane->type, NULL);
3850                 break;
3851         }
3852
3853         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
3854
3855         /* Create (reset) the plane state */
3856         if (plane->funcs->reset)
3857                 plane->funcs->reset(plane);
3858
3859
3860         return res;
3861 }
3862
3863 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3864                                struct drm_plane *plane,
3865                                uint32_t crtc_index)
3866 {
3867         struct amdgpu_crtc *acrtc = NULL;
3868         struct drm_plane *cursor_plane;
3869
3870         int res = -ENOMEM;
3871
3872         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3873         if (!cursor_plane)
3874                 goto fail;
3875
3876         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
3877         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3878
3879         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3880         if (!acrtc)
3881                 goto fail;
3882
3883         res = drm_crtc_init_with_planes(
3884                         dm->ddev,
3885                         &acrtc->base,
3886                         plane,
3887                         cursor_plane,
3888                         &amdgpu_dm_crtc_funcs, NULL);
3889
3890         if (res)
3891                 goto fail;
3892
3893         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3894
3895         /* Create (reset) the plane state */
3896         if (acrtc->base.funcs->reset)
3897                 acrtc->base.funcs->reset(&acrtc->base);
3898
3899         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3900         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3901
3902         acrtc->crtc_id = crtc_index;
3903         acrtc->base.enabled = false;
3904         acrtc->otg_inst = -1;
3905
3906         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3907         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3908                                    true, MAX_COLOR_LUT_ENTRIES);
3909         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3910
3911         return 0;
3912
3913 fail:
3914         kfree(acrtc);
3915         kfree(cursor_plane);
3916         return res;
3917 }
3918
3919
3920 static int to_drm_connector_type(enum signal_type st)
3921 {
3922         switch (st) {
3923         case SIGNAL_TYPE_HDMI_TYPE_A:
3924                 return DRM_MODE_CONNECTOR_HDMIA;
3925         case SIGNAL_TYPE_EDP:
3926                 return DRM_MODE_CONNECTOR_eDP;
3927         case SIGNAL_TYPE_LVDS:
3928                 return DRM_MODE_CONNECTOR_LVDS;
3929         case SIGNAL_TYPE_RGB:
3930                 return DRM_MODE_CONNECTOR_VGA;
3931         case SIGNAL_TYPE_DISPLAY_PORT:
3932         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3933                 return DRM_MODE_CONNECTOR_DisplayPort;
3934         case SIGNAL_TYPE_DVI_DUAL_LINK:
3935         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3936                 return DRM_MODE_CONNECTOR_DVID;
3937         case SIGNAL_TYPE_VIRTUAL:
3938                 return DRM_MODE_CONNECTOR_VIRTUAL;
3939
3940         default:
3941                 return DRM_MODE_CONNECTOR_Unknown;
3942         }
3943 }
3944
3945 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3946 {
3947         return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3948 }
3949
3950 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3951 {
3952         struct drm_encoder *encoder;
3953         struct amdgpu_encoder *amdgpu_encoder;
3954
3955         encoder = amdgpu_dm_connector_to_encoder(connector);
3956
3957         if (encoder == NULL)
3958                 return;
3959
3960         amdgpu_encoder = to_amdgpu_encoder(encoder);
3961
3962         amdgpu_encoder->native_mode.clock = 0;
3963
3964         if (!list_empty(&connector->probed_modes)) {
3965                 struct drm_display_mode *preferred_mode = NULL;
3966
3967                 list_for_each_entry(preferred_mode,
3968                                     &connector->probed_modes,
3969                                     head) {
3970                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3971                                 amdgpu_encoder->native_mode = *preferred_mode;
3972
3973                         break;
3974                 }
3975
3976         }
3977 }
3978
3979 static struct drm_display_mode *
3980 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3981                              char *name,
3982                              int hdisplay, int vdisplay)
3983 {
3984         struct drm_device *dev = encoder->dev;
3985         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3986         struct drm_display_mode *mode = NULL;
3987         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3988
3989         mode = drm_mode_duplicate(dev, native_mode);
3990
3991         if (mode == NULL)
3992                 return NULL;
3993
3994         mode->hdisplay = hdisplay;
3995         mode->vdisplay = vdisplay;
3996         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3997         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3998
3999         return mode;
4000
4001 }
4002
4003 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4004                                                  struct drm_connector *connector)
4005 {
4006         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4007         struct drm_display_mode *mode = NULL;
4008         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4009         struct amdgpu_dm_connector *amdgpu_dm_connector =
4010                                 to_amdgpu_dm_connector(connector);
4011         int i;
4012         int n;
4013         struct mode_size {
4014                 char name[DRM_DISPLAY_MODE_LEN];
4015                 int w;
4016                 int h;
4017         } common_modes[] = {
4018                 {  "640x480",  640,  480},
4019                 {  "800x600",  800,  600},
4020                 { "1024x768", 1024,  768},
4021                 { "1280x720", 1280,  720},
4022                 { "1280x800", 1280,  800},
4023                 {"1280x1024", 1280, 1024},
4024                 { "1440x900", 1440,  900},
4025                 {"1680x1050", 1680, 1050},
4026                 {"1600x1200", 1600, 1200},
4027                 {"1920x1080", 1920, 1080},
4028                 {"1920x1200", 1920, 1200}
4029         };
4030
4031         n = ARRAY_SIZE(common_modes);
4032
4033         for (i = 0; i < n; i++) {
4034                 struct drm_display_mode *curmode = NULL;
4035                 bool mode_existed = false;
4036
4037                 if (common_modes[i].w > native_mode->hdisplay ||
4038                     common_modes[i].h > native_mode->vdisplay ||
4039                    (common_modes[i].w == native_mode->hdisplay &&
4040                     common_modes[i].h == native_mode->vdisplay))
4041                         continue;
4042
4043                 list_for_each_entry(curmode, &connector->probed_modes, head) {
4044                         if (common_modes[i].w == curmode->hdisplay &&
4045                             common_modes[i].h == curmode->vdisplay) {
4046                                 mode_existed = true;
4047                                 break;
4048                         }
4049                 }
4050
4051                 if (mode_existed)
4052                         continue;
4053
4054                 mode = amdgpu_dm_create_common_mode(encoder,
4055                                 common_modes[i].name, common_modes[i].w,
4056                                 common_modes[i].h);
4057                 drm_mode_probed_add(connector, mode);
4058                 amdgpu_dm_connector->num_modes++;
4059         }
4060 }
4061
4062 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4063                                               struct edid *edid)
4064 {
4065         struct amdgpu_dm_connector *amdgpu_dm_connector =
4066                         to_amdgpu_dm_connector(connector);
4067
4068         if (edid) {
4069                 /* empty probed_modes */
4070                 INIT_LIST_HEAD(&connector->probed_modes);
4071                 amdgpu_dm_connector->num_modes =
4072                                 drm_add_edid_modes(connector, edid);
4073
4074                 amdgpu_dm_get_native_mode(connector);
4075         } else {
4076                 amdgpu_dm_connector->num_modes = 0;
4077         }
4078 }
4079
4080 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
4081 {
4082         struct amdgpu_dm_connector *amdgpu_dm_connector =
4083                         to_amdgpu_dm_connector(connector);
4084         struct drm_encoder *encoder;
4085         struct edid *edid = amdgpu_dm_connector->edid;
4086
4087         encoder = amdgpu_dm_connector_to_encoder(connector);
4088
4089         if (!edid || !drm_edid_is_valid(edid)) {
4090                 amdgpu_dm_connector->num_modes =
4091                                 drm_add_modes_noedid(connector, 640, 480);
4092         } else {
4093                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4094                 amdgpu_dm_connector_add_common_modes(encoder, connector);
4095         }
4096         amdgpu_dm_fbc_init(connector);
4097
4098         return amdgpu_dm_connector->num_modes;
4099 }
4100
4101 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4102                                      struct amdgpu_dm_connector *aconnector,
4103                                      int connector_type,
4104                                      struct dc_link *link,
4105                                      int link_index)
4106 {
4107         struct amdgpu_device *adev = dm->ddev->dev_private;
4108
4109         aconnector->connector_id = link_index;
4110         aconnector->dc_link = link;
4111         aconnector->base.interlace_allowed = false;
4112         aconnector->base.doublescan_allowed = false;
4113         aconnector->base.stereo_allowed = false;
4114         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4115         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4116         mutex_init(&aconnector->hpd_lock);
4117
4118         /*
4119          * configure support HPD hot plug connector_>polled default value is 0
4120          * which means HPD hot plug not supported
4121          */
4122         switch (connector_type) {
4123         case DRM_MODE_CONNECTOR_HDMIA:
4124                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4125                 aconnector->base.ycbcr_420_allowed =
4126                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4127                 break;
4128         case DRM_MODE_CONNECTOR_DisplayPort:
4129                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4130                 aconnector->base.ycbcr_420_allowed =
4131                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
4132                 break;
4133         case DRM_MODE_CONNECTOR_DVID:
4134                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4135                 break;
4136         default:
4137                 break;
4138         }
4139
4140         drm_object_attach_property(&aconnector->base.base,
4141                                 dm->ddev->mode_config.scaling_mode_property,
4142                                 DRM_MODE_SCALE_NONE);
4143
4144         drm_object_attach_property(&aconnector->base.base,
4145                                 adev->mode_info.underscan_property,
4146                                 UNDERSCAN_OFF);
4147         drm_object_attach_property(&aconnector->base.base,
4148                                 adev->mode_info.underscan_hborder_property,
4149                                 0);
4150         drm_object_attach_property(&aconnector->base.base,
4151                                 adev->mode_info.underscan_vborder_property,
4152                                 0);
4153         drm_object_attach_property(&aconnector->base.base,
4154                                 adev->mode_info.max_bpc_property,
4155                                 0);
4156
4157         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4158             dc_is_dmcu_initialized(adev->dm.dc)) {
4159                 drm_object_attach_property(&aconnector->base.base,
4160                                 adev->mode_info.abm_level_property, 0);
4161         }
4162
4163         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4164             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4165             connector_type == DRM_MODE_CONNECTOR_eDP) {
4166                 drm_connector_attach_vrr_capable_property(
4167                         &aconnector->base);
4168         }
4169 }
4170
4171 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4172                               struct i2c_msg *msgs, int num)
4173 {
4174         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4175         struct ddc_service *ddc_service = i2c->ddc_service;
4176         struct i2c_command cmd;
4177         int i;
4178         int result = -EIO;
4179
4180         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
4181
4182         if (!cmd.payloads)
4183                 return result;
4184
4185         cmd.number_of_payloads = num;
4186         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4187         cmd.speed = 100;
4188
4189         for (i = 0; i < num; i++) {
4190                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4191                 cmd.payloads[i].address = msgs[i].addr;
4192                 cmd.payloads[i].length = msgs[i].len;
4193                 cmd.payloads[i].data = msgs[i].buf;
4194         }
4195
4196         if (dc_submit_i2c(
4197                         ddc_service->ctx->dc,
4198                         ddc_service->ddc_pin->hw_info.ddc_channel,
4199                         &cmd))
4200                 result = num;
4201
4202         kfree(cmd.payloads);
4203         return result;
4204 }
4205
4206 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
4207 {
4208         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4209 }
4210
4211 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4212         .master_xfer = amdgpu_dm_i2c_xfer,
4213         .functionality = amdgpu_dm_i2c_func,
4214 };
4215
4216 static struct amdgpu_i2c_adapter *
4217 create_i2c(struct ddc_service *ddc_service,
4218            int link_index,
4219            int *res)
4220 {
4221         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4222         struct amdgpu_i2c_adapter *i2c;
4223
4224         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
4225         if (!i2c)
4226                 return NULL;
4227         i2c->base.owner = THIS_MODULE;
4228         i2c->base.class = I2C_CLASS_DDC;
4229         i2c->base.dev.parent = &adev->pdev->dev;
4230         i2c->base.algo = &amdgpu_dm_i2c_algo;
4231         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4232         i2c_set_adapdata(&i2c->base, i2c);
4233         i2c->ddc_service = ddc_service;
4234         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
4235
4236         return i2c;
4237 }
4238
4239
4240 /*
4241  * Note: this function assumes that dc_link_detect() was called for the
4242  * dc_link which will be represented by this aconnector.
4243  */
4244 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4245                                     struct amdgpu_dm_connector *aconnector,
4246                                     uint32_t link_index,
4247                                     struct amdgpu_encoder *aencoder)
4248 {
4249         int res = 0;
4250         int connector_type;
4251         struct dc *dc = dm->dc;
4252         struct dc_link *link = dc_get_link_at_index(dc, link_index);
4253         struct amdgpu_i2c_adapter *i2c;
4254
4255         link->priv = aconnector;
4256
4257         DRM_DEBUG_DRIVER("%s()\n", __func__);
4258
4259         i2c = create_i2c(link->ddc, link->link_index, &res);
4260         if (!i2c) {
4261                 DRM_ERROR("Failed to create i2c adapter data\n");
4262                 return -ENOMEM;
4263         }
4264
4265         aconnector->i2c = i2c;
4266         res = i2c_add_adapter(&i2c->base);
4267
4268         if (res) {
4269                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4270                 goto out_free;
4271         }
4272
4273         connector_type = to_drm_connector_type(link->connector_signal);
4274
4275         res = drm_connector_init(
4276                         dm->ddev,
4277                         &aconnector->base,
4278                         &amdgpu_dm_connector_funcs,
4279                         connector_type);
4280
4281         if (res) {
4282                 DRM_ERROR("connector_init failed\n");
4283                 aconnector->connector_id = -1;
4284                 goto out_free;
4285         }
4286
4287         drm_connector_helper_add(
4288                         &aconnector->base,
4289                         &amdgpu_dm_connector_helper_funcs);
4290
4291         if (aconnector->base.funcs->reset)
4292                 aconnector->base.funcs->reset(&aconnector->base);
4293
4294         amdgpu_dm_connector_init_helper(
4295                 dm,
4296                 aconnector,
4297                 connector_type,
4298                 link,
4299                 link_index);
4300
4301         drm_connector_attach_encoder(
4302                 &aconnector->base, &aencoder->base);
4303
4304         drm_connector_register(&aconnector->base);
4305 #if defined(CONFIG_DEBUG_FS)
4306         res = connector_debugfs_init(aconnector);
4307         if (res) {
4308                 DRM_ERROR("Failed to create debugfs for connector");
4309                 goto out_free;
4310         }
4311 #endif
4312
4313         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4314                 || connector_type == DRM_MODE_CONNECTOR_eDP)
4315                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4316
4317 out_free:
4318         if (res) {
4319                 kfree(i2c);
4320                 aconnector->i2c = NULL;
4321         }
4322         return res;
4323 }
4324
4325 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4326 {
4327         switch (adev->mode_info.num_crtc) {
4328         case 1:
4329                 return 0x1;
4330         case 2:
4331                 return 0x3;
4332         case 3:
4333                 return 0x7;
4334         case 4:
4335                 return 0xf;
4336         case 5:
4337                 return 0x1f;
4338         case 6:
4339         default:
4340                 return 0x3f;
4341         }
4342 }
4343
4344 static int amdgpu_dm_encoder_init(struct drm_device *dev,
4345                                   struct amdgpu_encoder *aencoder,
4346                                   uint32_t link_index)
4347 {
4348         struct amdgpu_device *adev = dev->dev_private;
4349
4350         int res = drm_encoder_init(dev,
4351                                    &aencoder->base,
4352                                    &amdgpu_dm_encoder_funcs,
4353                                    DRM_MODE_ENCODER_TMDS,
4354                                    NULL);
4355
4356         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4357
4358         if (!res)
4359                 aencoder->encoder_id = link_index;
4360         else
4361                 aencoder->encoder_id = -1;
4362
4363         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4364
4365         return res;
4366 }
4367
4368 static void manage_dm_interrupts(struct amdgpu_device *adev,
4369                                  struct amdgpu_crtc *acrtc,
4370                                  bool enable)
4371 {
4372         /*
4373          * this is not correct translation but will work as soon as VBLANK
4374          * constant is the same as PFLIP
4375          */
4376         int irq_type =
4377                 amdgpu_display_crtc_idx_to_irq_type(
4378                         adev,
4379                         acrtc->crtc_id);
4380
4381         if (enable) {
4382                 drm_crtc_vblank_on(&acrtc->base);
4383                 amdgpu_irq_get(
4384                         adev,
4385                         &adev->pageflip_irq,
4386                         irq_type);
4387         } else {
4388
4389                 amdgpu_irq_put(
4390                         adev,
4391                         &adev->pageflip_irq,
4392                         irq_type);
4393                 drm_crtc_vblank_off(&acrtc->base);
4394         }
4395 }
4396
4397 static bool
4398 is_scaling_state_different(const struct dm_connector_state *dm_state,
4399                            const struct dm_connector_state *old_dm_state)
4400 {
4401         if (dm_state->scaling != old_dm_state->scaling)
4402                 return true;
4403         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4404                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4405                         return true;
4406         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4407                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4408                         return true;
4409         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4410                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4411                 return true;
4412         return false;
4413 }
4414
4415 static void remove_stream(struct amdgpu_device *adev,
4416                           struct amdgpu_crtc *acrtc,
4417                           struct dc_stream_state *stream)
4418 {
4419         /* this is the update mode case */
4420
4421         acrtc->otg_inst = -1;
4422         acrtc->enabled = false;
4423 }
4424
4425 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4426                                struct dc_cursor_position *position)
4427 {
4428         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4429         int x, y;
4430         int xorigin = 0, yorigin = 0;
4431
4432         if (!crtc || !plane->state->fb) {
4433                 position->enable = false;
4434                 position->x = 0;
4435                 position->y = 0;
4436                 return 0;
4437         }
4438
4439         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4440             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4441                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4442                           __func__,
4443                           plane->state->crtc_w,
4444                           plane->state->crtc_h);
4445                 return -EINVAL;
4446         }
4447
4448         x = plane->state->crtc_x;
4449         y = plane->state->crtc_y;
4450         /* avivo cursor are offset into the total surface */
4451         x += crtc->primary->state->src_x >> 16;
4452         y += crtc->primary->state->src_y >> 16;
4453         if (x < 0) {
4454                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4455                 x = 0;
4456         }
4457         if (y < 0) {
4458                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4459                 y = 0;
4460         }
4461         position->enable = true;
4462         position->x = x;
4463         position->y = y;
4464         position->x_hotspot = xorigin;
4465         position->y_hotspot = yorigin;
4466
4467         return 0;
4468 }
4469
4470 static void handle_cursor_update(struct drm_plane *plane,
4471                                  struct drm_plane_state *old_plane_state)
4472 {
4473         struct amdgpu_device *adev = plane->dev->dev_private;
4474         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4475         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4476         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4477         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4478         uint64_t address = afb ? afb->address : 0;
4479         struct dc_cursor_position position;
4480         struct dc_cursor_attributes attributes;
4481         int ret;
4482
4483         if (!plane->state->fb && !old_plane_state->fb)
4484                 return;
4485
4486         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
4487                          __func__,
4488                          amdgpu_crtc->crtc_id,
4489                          plane->state->crtc_w,
4490                          plane->state->crtc_h);
4491
4492         ret = get_cursor_position(plane, crtc, &position);
4493         if (ret)
4494                 return;
4495
4496         if (!position.enable) {
4497                 /* turn off cursor */
4498                 if (crtc_state && crtc_state->stream) {
4499                         mutex_lock(&adev->dm.dc_lock);
4500                         dc_stream_set_cursor_position(crtc_state->stream,
4501                                                       &position);
4502                         mutex_unlock(&adev->dm.dc_lock);
4503                 }
4504                 return;
4505         }
4506
4507         amdgpu_crtc->cursor_width = plane->state->crtc_w;
4508         amdgpu_crtc->cursor_height = plane->state->crtc_h;
4509
4510         attributes.address.high_part = upper_32_bits(address);
4511         attributes.address.low_part  = lower_32_bits(address);
4512         attributes.width             = plane->state->crtc_w;
4513         attributes.height            = plane->state->crtc_h;
4514         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4515         attributes.rotation_angle    = 0;
4516         attributes.attribute_flags.value = 0;
4517
4518         attributes.pitch = attributes.width;
4519
4520         if (crtc_state->stream) {
4521                 mutex_lock(&adev->dm.dc_lock);
4522                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4523                                                          &attributes))
4524                         DRM_ERROR("DC failed to set cursor attributes\n");
4525
4526                 if (!dc_stream_set_cursor_position(crtc_state->stream,
4527                                                    &position))
4528                         DRM_ERROR("DC failed to set cursor position\n");
4529                 mutex_unlock(&adev->dm.dc_lock);
4530         }
4531 }
4532
4533 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4534 {
4535
4536         assert_spin_locked(&acrtc->base.dev->event_lock);
4537         WARN_ON(acrtc->event);
4538
4539         acrtc->event = acrtc->base.state->event;
4540
4541         /* Set the flip status */
4542         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4543
4544         /* Mark this event as consumed */
4545         acrtc->base.state->event = NULL;
4546
4547         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4548                                                  acrtc->crtc_id);
4549 }
4550
4551 static void update_freesync_state_on_stream(
4552         struct amdgpu_display_manager *dm,
4553         struct dm_crtc_state *new_crtc_state,
4554         struct dc_stream_state *new_stream,
4555         struct dc_plane_state *surface,
4556         u32 flip_timestamp_in_us)
4557 {
4558         struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
4559         struct dc_info_packet vrr_infopacket = {0};
4560         struct mod_freesync_config config = new_crtc_state->freesync_config;
4561
4562         if (!new_stream)
4563                 return;
4564
4565         /*
4566          * TODO: Determine why min/max totals and vrefresh can be 0 here.
4567          * For now it's sufficient to just guard against these conditions.
4568          */
4569
4570         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4571                 return;
4572
4573         if (new_crtc_state->vrr_supported &&
4574             config.min_refresh_in_uhz &&
4575             config.max_refresh_in_uhz) {
4576                 config.state = new_crtc_state->base.vrr_enabled ?
4577                         VRR_STATE_ACTIVE_VARIABLE :
4578                         VRR_STATE_INACTIVE;
4579         } else {
4580                 config.state = VRR_STATE_UNSUPPORTED;
4581         }
4582
4583         mod_freesync_build_vrr_params(dm->freesync_module,
4584                                       new_stream,
4585                                       &config, &vrr_params);
4586
4587         if (surface) {
4588                 mod_freesync_handle_preflip(
4589                         dm->freesync_module,
4590                         surface,
4591                         new_stream,
4592                         flip_timestamp_in_us,
4593                         &vrr_params);
4594         }
4595
4596         mod_freesync_build_vrr_infopacket(
4597                 dm->freesync_module,
4598                 new_stream,
4599                 &vrr_params,
4600                 PACKET_TYPE_VRR,
4601                 TRANSFER_FUNC_UNKNOWN,
4602                 &vrr_infopacket);
4603
4604         new_crtc_state->freesync_timing_changed |=
4605                 (memcmp(&new_crtc_state->vrr_params.adjust,
4606                         &vrr_params.adjust,
4607                         sizeof(vrr_params.adjust)) != 0);
4608
4609         new_crtc_state->freesync_vrr_info_changed |=
4610                 (memcmp(&new_crtc_state->vrr_infopacket,
4611                         &vrr_infopacket,
4612                         sizeof(vrr_infopacket)) != 0);
4613
4614         new_crtc_state->vrr_params = vrr_params;
4615         new_crtc_state->vrr_infopacket = vrr_infopacket;
4616
4617         new_stream->adjust = new_crtc_state->vrr_params.adjust;
4618         new_stream->vrr_infopacket = vrr_infopacket;
4619
4620         if (new_crtc_state->freesync_vrr_info_changed)
4621                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4622                               new_crtc_state->base.crtc->base.id,
4623                               (int)new_crtc_state->base.vrr_enabled,
4624                               (int)vrr_params.state);
4625 }
4626
4627 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4628                                     struct dc_state *dc_state,
4629                                     struct drm_device *dev,
4630                                     struct amdgpu_display_manager *dm,
4631                                     struct drm_crtc *pcrtc,
4632                                     bool *wait_for_vblank)
4633 {
4634         uint32_t i, r;
4635         uint64_t timestamp_ns;
4636         struct drm_plane *plane;
4637         struct drm_plane_state *old_plane_state, *new_plane_state;
4638         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4639         struct drm_crtc_state *new_pcrtc_state =
4640                         drm_atomic_get_new_crtc_state(state, pcrtc);
4641         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4642         struct dm_crtc_state *dm_old_crtc_state =
4643                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4644         int flip_count = 0, planes_count = 0, vpos, hpos;
4645         unsigned long flags;
4646         struct amdgpu_bo *abo;
4647         uint64_t tiling_flags, dcc_address;
4648         uint32_t target, target_vblank;
4649
4650         struct {
4651                 struct dc_surface_update surface_updates[MAX_SURFACES];
4652                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
4653                 struct dc_stream_update stream_update;
4654         } *flip;
4655
4656         struct {
4657                 struct dc_surface_update surface_updates[MAX_SURFACES];
4658                 struct dc_plane_info plane_infos[MAX_SURFACES];
4659                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
4660                 struct dc_stream_update stream_update;
4661         } *full;
4662
4663         flip = kzalloc(sizeof(*flip), GFP_KERNEL);
4664         full = kzalloc(sizeof(*full), GFP_KERNEL);
4665
4666         if (!flip || !full) {
4667                 dm_error("Failed to allocate update bundles\n");
4668                 goto cleanup;
4669         }
4670
4671         /* update planes when needed */
4672         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4673                 struct drm_crtc *crtc = new_plane_state->crtc;
4674                 struct drm_crtc_state *new_crtc_state;
4675                 struct drm_framebuffer *fb = new_plane_state->fb;
4676                 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
4677                 bool pflip_needed;
4678                 struct dc_plane_state *dc_plane;
4679                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4680
4681                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4682                         handle_cursor_update(plane, old_plane_state);
4683                         continue;
4684                 }
4685
4686                 if (!fb || !crtc || pcrtc != crtc)
4687                         continue;
4688
4689                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4690                 if (!new_crtc_state->active)
4691                         continue;
4692
4693                 pflip_needed = old_plane_state->fb &&
4694                         old_plane_state->fb != new_plane_state->fb;
4695
4696                 dc_plane = dm_new_plane_state->dc_state;
4697
4698                 if (pflip_needed) {
4699                         /*
4700                          * Assume even ONE crtc with immediate flip means
4701                          * entire can't wait for VBLANK
4702                          * TODO Check if it's correct
4703                          */
4704                         if (new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
4705                                 *wait_for_vblank = false;
4706
4707                         /*
4708                          * TODO This might fail and hence better not used, wait
4709                          * explicitly on fences instead
4710                          * and in general should be called for
4711                          * blocking commit to as per framework helpers
4712                          */
4713                         abo = gem_to_amdgpu_bo(fb->obj[0]);
4714                         r = amdgpu_bo_reserve(abo, true);
4715                         if (unlikely(r != 0)) {
4716                                 DRM_ERROR("failed to reserve buffer before flip\n");
4717                                 WARN_ON(1);
4718                         }
4719
4720                         /* Wait for all fences on this FB */
4721                         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4722                                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
4723
4724                         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
4725
4726                         amdgpu_bo_unreserve(abo);
4727
4728                         flip->flip_addrs[flip_count].address.grph.addr.low_part = lower_32_bits(afb->address);
4729                         flip->flip_addrs[flip_count].address.grph.addr.high_part = upper_32_bits(afb->address);
4730
4731                         dcc_address = get_dcc_address(afb->address, tiling_flags);
4732                         flip->flip_addrs[flip_count].address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
4733                         flip->flip_addrs[flip_count].address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
4734
4735                         flip->flip_addrs[flip_count].flip_immediate =
4736                                         (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4737
4738                         timestamp_ns = ktime_get_ns();
4739                         flip->flip_addrs[flip_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
4740                         flip->surface_updates[flip_count].flip_addr = &flip->flip_addrs[flip_count];
4741                         flip->surface_updates[flip_count].surface = dc_plane;
4742
4743                         if (!flip->surface_updates[flip_count].surface) {
4744                                 DRM_ERROR("No surface for CRTC: id=%d\n",
4745                                                 acrtc_attach->crtc_id);
4746                                 continue;
4747                         }
4748
4749                         if (plane == pcrtc->primary)
4750                                 update_freesync_state_on_stream(
4751                                         dm,
4752                                         acrtc_state,
4753                                         acrtc_state->stream,
4754                                         dc_plane,
4755                                         flip->flip_addrs[flip_count].flip_timestamp_in_us);
4756
4757                         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
4758                                          __func__,
4759                                          flip->flip_addrs[flip_count].address.grph.addr.high_part,
4760                                          flip->flip_addrs[flip_count].address.grph.addr.low_part);
4761
4762                         flip_count += 1;
4763                 }
4764
4765                 full->surface_updates[planes_count].surface = dc_plane;
4766                 if (new_pcrtc_state->color_mgmt_changed) {
4767                         full->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
4768                         full->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
4769                 }
4770
4771
4772                 full->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
4773                 full->scaling_infos[planes_count].src_rect = dc_plane->src_rect;
4774                 full->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect;
4775                 full->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect;
4776                 full->surface_updates[planes_count].scaling_info = &full->scaling_infos[planes_count];
4777
4778
4779                 full->plane_infos[planes_count].color_space = dc_plane->color_space;
4780                 full->plane_infos[planes_count].format = dc_plane->format;
4781                 full->plane_infos[planes_count].plane_size = dc_plane->plane_size;
4782                 full->plane_infos[planes_count].rotation = dc_plane->rotation;
4783                 full->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
4784                 full->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
4785                 full->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
4786                 full->plane_infos[planes_count].visible = dc_plane->visible;
4787                 full->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
4788                 full->plane_infos[planes_count].dcc = dc_plane->dcc;
4789                 full->surface_updates[planes_count].plane_info = &full->plane_infos[planes_count];
4790
4791                 planes_count += 1;
4792
4793         }
4794
4795         /*
4796          * TODO: For proper atomic behaviour, we should be calling into DC once with
4797          * all the changes.  However, DC refuses to do pageflips and non-pageflip
4798          * changes in the same call.  Change DC to respect atomic behaviour,
4799          * hopefully eliminating dc_*_update structs in their entirety.
4800          */
4801         if (flip_count) {
4802                 target = (uint32_t)drm_crtc_vblank_count(pcrtc) + *wait_for_vblank;
4803                 /* Prepare wait for target vblank early - before the fence-waits */
4804                 target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) +
4805                                 amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id);
4806
4807                 /*
4808                  * Wait until we're out of the vertical blank period before the one
4809                  * targeted by the flip
4810                  */
4811                 while ((acrtc_attach->enabled &&
4812                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
4813                                                             0, &vpos, &hpos, NULL,
4814                                                             NULL, &pcrtc->hwmode)
4815                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4816                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4817                         (int)(target_vblank -
4818                           amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
4819                         usleep_range(1000, 1100);
4820                 }
4821
4822                 if (acrtc_attach->base.state->event) {
4823                         drm_crtc_vblank_get(pcrtc);
4824
4825                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4826
4827                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
4828                         prepare_flip_isr(acrtc_attach);
4829
4830                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4831                 }
4832
4833                 if (acrtc_state->stream) {
4834
4835                         if (acrtc_state->freesync_timing_changed)
4836                                 flip->stream_update.adjust =
4837                                         &acrtc_state->stream->adjust;
4838
4839                         if (acrtc_state->freesync_vrr_info_changed)
4840                                 flip->stream_update.vrr_infopacket =
4841                                         &acrtc_state->stream->vrr_infopacket;
4842                 }
4843
4844                 mutex_lock(&dm->dc_lock);
4845                 dc_commit_updates_for_stream(dm->dc,
4846                                                      flip->surface_updates,
4847                                                      flip_count,
4848                                                      acrtc_state->stream,
4849                                                      &flip->stream_update,
4850                                                      dc_state);
4851                 mutex_unlock(&dm->dc_lock);
4852         }
4853
4854         if (planes_count) {
4855                 if (new_pcrtc_state->mode_changed) {
4856                         full->stream_update.src = acrtc_state->stream->src;
4857                         full->stream_update.dst = acrtc_state->stream->dst;
4858                 }
4859
4860                 if (new_pcrtc_state->color_mgmt_changed)
4861                         full->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
4862
4863                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
4864                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
4865                         full->stream_update.abm_level = &acrtc_state->abm_level;
4866
4867                 mutex_lock(&dm->dc_lock);
4868                 dc_commit_updates_for_stream(dm->dc,
4869                                                      full->surface_updates,
4870                                                      planes_count,
4871                                                      acrtc_state->stream,
4872                                                      &full->stream_update,
4873                                                      dc_state);
4874                 mutex_unlock(&dm->dc_lock);
4875         }
4876
4877 cleanup:
4878         kfree(flip);
4879         kfree(full);
4880 }
4881
4882 /*
4883  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4884  * @crtc_state: the DRM CRTC state
4885  * @stream_state: the DC stream state.
4886  *
4887  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4888  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4889  */
4890 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4891                                                 struct dc_stream_state *stream_state)
4892 {
4893         stream_state->mode_changed =
4894                 crtc_state->mode_changed || crtc_state->active_changed;
4895 }
4896
4897 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4898                                    struct drm_atomic_state *state,
4899                                    bool nonblock)
4900 {
4901         struct drm_crtc *crtc;
4902         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4903         struct amdgpu_device *adev = dev->dev_private;
4904         int i;
4905
4906         /*
4907          * We evade vblanks and pflips on crtc that
4908          * should be changed. We do it here to flush & disable
4909          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4910          * it will update crtc->dm_crtc_state->stream pointer which is used in
4911          * the ISRs.
4912          */
4913         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4914                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4915                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4916                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4917
4918                 if (drm_atomic_crtc_needs_modeset(new_crtc_state)
4919                     && dm_old_crtc_state->stream) {
4920                         /*
4921                          * If the stream is removed and CRC capture was
4922                          * enabled on the CRTC the extra vblank reference
4923                          * needs to be dropped since CRC capture will be
4924                          * disabled.
4925                          */
4926                         if (!dm_new_crtc_state->stream
4927                             && dm_new_crtc_state->crc_enabled) {
4928                                 drm_crtc_vblank_put(crtc);
4929                                 dm_new_crtc_state->crc_enabled = false;
4930                         }
4931
4932                         manage_dm_interrupts(adev, acrtc, false);
4933                 }
4934         }
4935         /*
4936          * Add check here for SoC's that support hardware cursor plane, to
4937          * unset legacy_cursor_update
4938          */
4939
4940         return drm_atomic_helper_commit(dev, state, nonblock);
4941
4942         /*TODO Handle EINTR, reenable IRQ*/
4943 }
4944
4945 /**
4946  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4947  * @state: The atomic state to commit
4948  *
4949  * This will tell DC to commit the constructed DC state from atomic_check,
4950  * programming the hardware. Any failures here implies a hardware failure, since
4951  * atomic check should have filtered anything non-kosher.
4952  */
4953 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4954 {
4955         struct drm_device *dev = state->dev;
4956         struct amdgpu_device *adev = dev->dev_private;
4957         struct amdgpu_display_manager *dm = &adev->dm;
4958         struct dm_atomic_state *dm_state;
4959         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
4960         uint32_t i, j;
4961         struct drm_crtc *crtc;
4962         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4963         unsigned long flags;
4964         bool wait_for_vblank = true;
4965         struct drm_connector *connector;
4966         struct drm_connector_state *old_con_state, *new_con_state;
4967         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4968         int crtc_disable_count = 0;
4969
4970         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4971
4972         dm_state = dm_atomic_get_new_state(state);
4973         if (dm_state && dm_state->context) {
4974                 dc_state = dm_state->context;
4975         } else {
4976                 /* No state changes, retain current state. */
4977                 dc_state_temp = dc_create_state();
4978                 ASSERT(dc_state_temp);
4979                 dc_state = dc_state_temp;
4980                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
4981         }
4982
4983         /* update changed items */
4984         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4985                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4986
4987                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4988                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4989
4990                 DRM_DEBUG_DRIVER(
4991                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4992                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4993                         "connectors_changed:%d\n",
4994                         acrtc->crtc_id,
4995                         new_crtc_state->enable,
4996                         new_crtc_state->active,
4997                         new_crtc_state->planes_changed,
4998                         new_crtc_state->mode_changed,
4999                         new_crtc_state->active_changed,
5000                         new_crtc_state->connectors_changed);
5001
5002                 /* Copy all transient state flags into dc state */
5003                 if (dm_new_crtc_state->stream) {
5004                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5005                                                             dm_new_crtc_state->stream);
5006                 }
5007
5008                 /* handles headless hotplug case, updating new_state and
5009                  * aconnector as needed
5010                  */
5011
5012                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5013
5014                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5015
5016                         if (!dm_new_crtc_state->stream) {
5017                                 /*
5018                                  * this could happen because of issues with
5019                                  * userspace notifications delivery.
5020                                  * In this case userspace tries to set mode on
5021                                  * display which is disconnected in fact.
5022                                  * dc_sink is NULL in this case on aconnector.
5023                                  * We expect reset mode will come soon.
5024                                  *
5025                                  * This can also happen when unplug is done
5026                                  * during resume sequence ended
5027                                  *
5028                                  * In this case, we want to pretend we still
5029                                  * have a sink to keep the pipe running so that
5030                                  * hw state is consistent with the sw state
5031                                  */
5032                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5033                                                 __func__, acrtc->base.base.id);
5034                                 continue;
5035                         }
5036
5037                         if (dm_old_crtc_state->stream)
5038                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5039
5040                         pm_runtime_get_noresume(dev->dev);
5041
5042                         acrtc->enabled = true;
5043                         acrtc->hw_mode = new_crtc_state->mode;
5044                         crtc->hwmode = new_crtc_state->mode;
5045                 } else if (modereset_required(new_crtc_state)) {
5046                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5047
5048                         /* i.e. reset mode */
5049                         if (dm_old_crtc_state->stream)
5050                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5051                 }
5052         } /* for_each_crtc_in_state() */
5053
5054         if (dc_state) {
5055                 dm_enable_per_frame_crtc_master_sync(dc_state);
5056                 mutex_lock(&dm->dc_lock);
5057                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5058                 mutex_unlock(&dm->dc_lock);
5059         }
5060
5061         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5062                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5063
5064                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5065
5066                 if (dm_new_crtc_state->stream != NULL) {
5067                         const struct dc_stream_status *status =
5068                                         dc_stream_get_status(dm_new_crtc_state->stream);
5069
5070                         if (!status)
5071                                 status = dc_stream_get_status_from_state(dc_state,
5072                                                                          dm_new_crtc_state->stream);
5073
5074                         if (!status)
5075                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5076                         else
5077                                 acrtc->otg_inst = status->primary_otg_inst;
5078                 }
5079         }
5080
5081         /* Handle connector state changes */
5082         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5083                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5084                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5085                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5086                 struct dc_surface_update dummy_updates[MAX_SURFACES];
5087                 struct dc_stream_update stream_update;
5088                 struct dc_stream_status *status = NULL;
5089
5090                 memset(&dummy_updates, 0, sizeof(dummy_updates));
5091                 memset(&stream_update, 0, sizeof(stream_update));
5092
5093                 if (acrtc) {
5094                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5095                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5096                 }
5097
5098                 /* Skip any modesets/resets */
5099                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5100                         continue;
5101
5102                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5103                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5104
5105                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5106                                 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5107                         continue;
5108
5109                 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5110                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5111                                         dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5112
5113                         stream_update.src = dm_new_crtc_state->stream->src;
5114                         stream_update.dst = dm_new_crtc_state->stream->dst;
5115                 }
5116
5117                 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5118                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5119
5120                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
5121                 }
5122
5123                 status = dc_stream_get_status(dm_new_crtc_state->stream);
5124                 WARN_ON(!status);
5125                 WARN_ON(!status->plane_count);
5126
5127                 /*
5128                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
5129                  * Here we create an empty update on each plane.
5130                  * To fix this, DC should permit updating only stream properties.
5131                  */
5132                 for (j = 0; j < status->plane_count; j++)
5133                         dummy_updates[j].surface = status->plane_states[0];
5134
5135
5136                 mutex_lock(&dm->dc_lock);
5137                 dc_commit_updates_for_stream(dm->dc,
5138                                                      dummy_updates,
5139                                                      status->plane_count,
5140                                                      dm_new_crtc_state->stream,
5141                                                      &stream_update,
5142                                                      dc_state);
5143                 mutex_unlock(&dm->dc_lock);
5144         }
5145
5146         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5147                         new_crtc_state, i) {
5148                 /*
5149                  * loop to enable interrupts on newly arrived crtc
5150                  */
5151                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5152                 bool modeset_needed;
5153
5154                 if (old_crtc_state->active && !new_crtc_state->active)
5155                         crtc_disable_count++;
5156
5157                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5158                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5159                 modeset_needed = modeset_required(
5160                                 new_crtc_state,
5161                                 dm_new_crtc_state->stream,
5162                                 dm_old_crtc_state->stream);
5163
5164                 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5165                         continue;
5166
5167                 manage_dm_interrupts(adev, acrtc, true);
5168
5169 #ifdef CONFIG_DEBUG_FS
5170                 /* The stream has changed so CRC capture needs to re-enabled. */
5171                 if (dm_new_crtc_state->crc_enabled)
5172                         amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5173 #endif
5174         }
5175
5176         /* update planes when needed per crtc*/
5177         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5178                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5179
5180                 if (dm_new_crtc_state->stream)
5181                         amdgpu_dm_commit_planes(state, dc_state, dev,
5182                                                 dm, crtc, &wait_for_vblank);
5183         }
5184
5185
5186         /*
5187          * send vblank event on all events not handled in flip and
5188          * mark consumed event for drm_atomic_helper_commit_hw_done
5189          */
5190         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5191         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5192
5193                 if (new_crtc_state->event)
5194                         drm_send_event_locked(dev, &new_crtc_state->event->base);
5195
5196                 new_crtc_state->event = NULL;
5197         }
5198         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5199
5200         /* Signal HW programming completion */
5201         drm_atomic_helper_commit_hw_done(state);
5202
5203         if (wait_for_vblank)
5204                 drm_atomic_helper_wait_for_flip_done(dev, state);
5205
5206         drm_atomic_helper_cleanup_planes(dev, state);
5207
5208         /*
5209          * Finally, drop a runtime PM reference for each newly disabled CRTC,
5210          * so we can put the GPU into runtime suspend if we're not driving any
5211          * displays anymore
5212          */
5213         for (i = 0; i < crtc_disable_count; i++)
5214                 pm_runtime_put_autosuspend(dev->dev);
5215         pm_runtime_mark_last_busy(dev->dev);
5216
5217         if (dc_state_temp)
5218                 dc_release_state(dc_state_temp);
5219 }
5220
5221
5222 static int dm_force_atomic_commit(struct drm_connector *connector)
5223 {
5224         int ret = 0;
5225         struct drm_device *ddev = connector->dev;
5226         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5227         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5228         struct drm_plane *plane = disconnected_acrtc->base.primary;
5229         struct drm_connector_state *conn_state;
5230         struct drm_crtc_state *crtc_state;
5231         struct drm_plane_state *plane_state;
5232
5233         if (!state)
5234                 return -ENOMEM;
5235
5236         state->acquire_ctx = ddev->mode_config.acquire_ctx;
5237
5238         /* Construct an atomic state to restore previous display setting */
5239
5240         /*
5241          * Attach connectors to drm_atomic_state
5242          */
5243         conn_state = drm_atomic_get_connector_state(state, connector);
5244
5245         ret = PTR_ERR_OR_ZERO(conn_state);
5246         if (ret)
5247                 goto err;
5248
5249         /* Attach crtc to drm_atomic_state*/
5250         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5251
5252         ret = PTR_ERR_OR_ZERO(crtc_state);
5253         if (ret)
5254                 goto err;
5255
5256         /* force a restore */
5257         crtc_state->mode_changed = true;
5258
5259         /* Attach plane to drm_atomic_state */
5260         plane_state = drm_atomic_get_plane_state(state, plane);
5261
5262         ret = PTR_ERR_OR_ZERO(plane_state);
5263         if (ret)
5264                 goto err;
5265
5266
5267         /* Call commit internally with the state we just constructed */
5268         ret = drm_atomic_commit(state);
5269         if (!ret)
5270                 return 0;
5271
5272 err:
5273         DRM_ERROR("Restoring old state failed with %i\n", ret);
5274         drm_atomic_state_put(state);
5275
5276         return ret;
5277 }
5278
5279 /*
5280  * This function handles all cases when set mode does not come upon hotplug.
5281  * This includes when a display is unplugged then plugged back into the
5282  * same port and when running without usermode desktop manager supprot
5283  */
5284 void dm_restore_drm_connector_state(struct drm_device *dev,
5285                                     struct drm_connector *connector)
5286 {
5287         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5288         struct amdgpu_crtc *disconnected_acrtc;
5289         struct dm_crtc_state *acrtc_state;
5290
5291         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5292                 return;
5293
5294         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5295         if (!disconnected_acrtc)
5296                 return;
5297
5298         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5299         if (!acrtc_state->stream)
5300                 return;
5301
5302         /*
5303          * If the previous sink is not released and different from the current,
5304          * we deduce we are in a state where we can not rely on usermode call
5305          * to turn on the display, so we do it here
5306          */
5307         if (acrtc_state->stream->sink != aconnector->dc_sink)
5308                 dm_force_atomic_commit(&aconnector->base);
5309 }
5310
5311 /*
5312  * Grabs all modesetting locks to serialize against any blocking commits,
5313  * Waits for completion of all non blocking commits.
5314  */
5315 static int do_aquire_global_lock(struct drm_device *dev,
5316                                  struct drm_atomic_state *state)
5317 {
5318         struct drm_crtc *crtc;
5319         struct drm_crtc_commit *commit;
5320         long ret;
5321
5322         /*
5323          * Adding all modeset locks to aquire_ctx will
5324          * ensure that when the framework release it the
5325          * extra locks we are locking here will get released to
5326          */
5327         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5328         if (ret)
5329                 return ret;
5330
5331         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5332                 spin_lock(&crtc->commit_lock);
5333                 commit = list_first_entry_or_null(&crtc->commit_list,
5334                                 struct drm_crtc_commit, commit_entry);
5335                 if (commit)
5336                         drm_crtc_commit_get(commit);
5337                 spin_unlock(&crtc->commit_lock);
5338
5339                 if (!commit)
5340                         continue;
5341
5342                 /*
5343                  * Make sure all pending HW programming completed and
5344                  * page flips done
5345                  */
5346                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5347
5348                 if (ret > 0)
5349                         ret = wait_for_completion_interruptible_timeout(
5350                                         &commit->flip_done, 10*HZ);
5351
5352                 if (ret == 0)
5353                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
5354                                   "timed out\n", crtc->base.id, crtc->name);
5355
5356                 drm_crtc_commit_put(commit);
5357         }
5358
5359         return ret < 0 ? ret : 0;
5360 }
5361
5362 static void get_freesync_config_for_crtc(
5363         struct dm_crtc_state *new_crtc_state,
5364         struct dm_connector_state *new_con_state)
5365 {
5366         struct mod_freesync_config config = {0};
5367         struct amdgpu_dm_connector *aconnector =
5368                         to_amdgpu_dm_connector(new_con_state->base.connector);
5369         struct drm_display_mode *mode = &new_crtc_state->base.mode;
5370
5371         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5372                 aconnector->min_vfreq <= drm_mode_vrefresh(mode);
5373
5374         if (new_crtc_state->vrr_supported) {
5375                 new_crtc_state->stream->ignore_msa_timing_param = true;
5376                 config.state = new_crtc_state->base.vrr_enabled ?
5377                                 VRR_STATE_ACTIVE_VARIABLE :
5378                                 VRR_STATE_INACTIVE;
5379                 config.min_refresh_in_uhz =
5380                                 aconnector->min_vfreq * 1000000;
5381                 config.max_refresh_in_uhz =
5382                                 aconnector->max_vfreq * 1000000;
5383                 config.vsif_supported = true;
5384                 config.btr = true;
5385         }
5386
5387         new_crtc_state->freesync_config = config;
5388 }
5389
5390 static void reset_freesync_config_for_crtc(
5391         struct dm_crtc_state *new_crtc_state)
5392 {
5393         new_crtc_state->vrr_supported = false;
5394
5395         memset(&new_crtc_state->vrr_params, 0,
5396                sizeof(new_crtc_state->vrr_params));
5397         memset(&new_crtc_state->vrr_infopacket, 0,
5398                sizeof(new_crtc_state->vrr_infopacket));
5399 }
5400
5401 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5402                                 struct drm_atomic_state *state,
5403                                 struct drm_crtc *crtc,
5404                                 struct drm_crtc_state *old_crtc_state,
5405                                 struct drm_crtc_state *new_crtc_state,
5406                                 bool enable,
5407                                 bool *lock_and_validation_needed)
5408 {
5409         struct dm_atomic_state *dm_state = NULL;
5410         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5411         struct dc_stream_state *new_stream;
5412         int ret = 0;
5413
5414         /*
5415          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5416          * update changed items
5417          */
5418         struct amdgpu_crtc *acrtc = NULL;
5419         struct amdgpu_dm_connector *aconnector = NULL;
5420         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5421         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5422         struct drm_plane_state *new_plane_state = NULL;
5423
5424         new_stream = NULL;
5425
5426         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5427         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5428         acrtc = to_amdgpu_crtc(crtc);
5429
5430         new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
5431
5432         if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5433                 ret = -EINVAL;
5434                 goto fail;
5435         }
5436
5437         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
5438
5439         /* TODO This hack should go away */
5440         if (aconnector && enable) {
5441                 /* Make sure fake sink is created in plug-in scenario */
5442                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5443                                                             &aconnector->base);
5444                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5445                                                             &aconnector->base);
5446
5447                 if (IS_ERR(drm_new_conn_state)) {
5448                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5449                         goto fail;
5450                 }
5451
5452                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5453                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
5454
5455                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5456                         goto skip_modeset;
5457
5458                 new_stream = create_stream_for_sink(aconnector,
5459                                                      &new_crtc_state->mode,
5460                                                     dm_new_conn_state,
5461                                                     dm_old_crtc_state->stream);
5462
5463                 /*
5464                  * we can have no stream on ACTION_SET if a display
5465                  * was disconnected during S3, in this case it is not an
5466                  * error, the OS will be updated after detection, and
5467                  * will do the right thing on next atomic commit
5468                  */
5469
5470                 if (!new_stream) {
5471                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5472                                         __func__, acrtc->base.base.id);
5473                         ret = -ENOMEM;
5474                         goto fail;
5475                 }
5476
5477                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
5478
5479                 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5480                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5481                         new_crtc_state->mode_changed = false;
5482                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5483                                          new_crtc_state->mode_changed);
5484                 }
5485         }
5486
5487         /* mode_changed flag may get updated above, need to check again */
5488         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5489                 goto skip_modeset;
5490
5491         DRM_DEBUG_DRIVER(
5492                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5493                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5494                 "connectors_changed:%d\n",
5495                 acrtc->crtc_id,
5496                 new_crtc_state->enable,
5497                 new_crtc_state->active,
5498                 new_crtc_state->planes_changed,
5499                 new_crtc_state->mode_changed,
5500                 new_crtc_state->active_changed,
5501                 new_crtc_state->connectors_changed);
5502
5503         /* Remove stream for any changed/disabled CRTC */
5504         if (!enable) {
5505
5506                 if (!dm_old_crtc_state->stream)
5507                         goto skip_modeset;
5508
5509                 ret = dm_atomic_get_state(state, &dm_state);
5510                 if (ret)
5511                         goto fail;
5512
5513                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5514                                 crtc->base.id);
5515
5516                 /* i.e. reset mode */
5517                 if (dc_remove_stream_from_ctx(
5518                                 dm->dc,
5519                                 dm_state->context,
5520                                 dm_old_crtc_state->stream) != DC_OK) {
5521                         ret = -EINVAL;
5522                         goto fail;
5523                 }
5524
5525                 dc_stream_release(dm_old_crtc_state->stream);
5526                 dm_new_crtc_state->stream = NULL;
5527
5528                 reset_freesync_config_for_crtc(dm_new_crtc_state);
5529
5530                 *lock_and_validation_needed = true;
5531
5532         } else {/* Add stream for any updated/enabled CRTC */
5533                 /*
5534                  * Quick fix to prevent NULL pointer on new_stream when
5535                  * added MST connectors not found in existing crtc_state in the chained mode
5536                  * TODO: need to dig out the root cause of that
5537                  */
5538                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5539                         goto skip_modeset;
5540
5541                 if (modereset_required(new_crtc_state))
5542                         goto skip_modeset;
5543
5544                 if (modeset_required(new_crtc_state, new_stream,
5545                                      dm_old_crtc_state->stream)) {
5546
5547                         WARN_ON(dm_new_crtc_state->stream);
5548
5549                         ret = dm_atomic_get_state(state, &dm_state);
5550                         if (ret)
5551                                 goto fail;
5552
5553                         dm_new_crtc_state->stream = new_stream;
5554
5555                         dc_stream_retain(new_stream);
5556
5557                         DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5558                                                 crtc->base.id);
5559
5560                         if (dc_add_stream_to_ctx(
5561                                         dm->dc,
5562                                         dm_state->context,
5563                                         dm_new_crtc_state->stream) != DC_OK) {
5564                                 ret = -EINVAL;
5565                                 goto fail;
5566                         }
5567
5568                         *lock_and_validation_needed = true;
5569                 }
5570         }
5571
5572 skip_modeset:
5573         /* Release extra reference */
5574         if (new_stream)
5575                  dc_stream_release(new_stream);
5576
5577         /*
5578          * We want to do dc stream updates that do not require a
5579          * full modeset below.
5580          */
5581         if (!(enable && aconnector && new_crtc_state->enable &&
5582               new_crtc_state->active))
5583                 return 0;
5584         /*
5585          * Given above conditions, the dc state cannot be NULL because:
5586          * 1. We're in the process of enabling CRTCs (just been added
5587          *    to the dc context, or already is on the context)
5588          * 2. Has a valid connector attached, and
5589          * 3. Is currently active and enabled.
5590          * => The dc stream state currently exists.
5591          */
5592         BUG_ON(dm_new_crtc_state->stream == NULL);
5593
5594         /* Scaling or underscan settings */
5595         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5596                 update_stream_scaling_settings(
5597                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5598
5599         /*
5600          * Color management settings. We also update color properties
5601          * when a modeset is needed, to ensure it gets reprogrammed.
5602          */
5603         if (dm_new_crtc_state->base.color_mgmt_changed ||
5604             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5605                 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5606                 if (ret)
5607                         goto fail;
5608                 amdgpu_dm_set_ctm(dm_new_crtc_state);
5609         }
5610
5611         /* Update Freesync settings. */
5612         get_freesync_config_for_crtc(dm_new_crtc_state,
5613                                      dm_new_conn_state);
5614
5615         return ret;
5616
5617 fail:
5618         if (new_stream)
5619                 dc_stream_release(new_stream);
5620         return ret;
5621 }
5622
5623 static int dm_update_plane_state(struct dc *dc,
5624                                  struct drm_atomic_state *state,
5625                                  struct drm_plane *plane,
5626                                  struct drm_plane_state *old_plane_state,
5627                                  struct drm_plane_state *new_plane_state,
5628                                  bool enable,
5629                                  bool *lock_and_validation_needed)
5630 {
5631
5632         struct dm_atomic_state *dm_state = NULL;
5633         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5634         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5635         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
5636         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
5637         /* TODO return page_flip_needed() function */
5638         bool pflip_needed  = !state->allow_modeset;
5639         int ret = 0;
5640
5641
5642         new_plane_crtc = new_plane_state->crtc;
5643         old_plane_crtc = old_plane_state->crtc;
5644         dm_new_plane_state = to_dm_plane_state(new_plane_state);
5645         dm_old_plane_state = to_dm_plane_state(old_plane_state);
5646
5647         /*TODO Implement atomic check for cursor plane */
5648         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5649                 return 0;
5650
5651         /* Remove any changed/removed planes */
5652         if (!enable) {
5653                 if (pflip_needed &&
5654                     plane->type != DRM_PLANE_TYPE_OVERLAY)
5655                         return 0;
5656
5657                 if (!old_plane_crtc)
5658                         return 0;
5659
5660                 old_crtc_state = drm_atomic_get_old_crtc_state(
5661                                 state, old_plane_crtc);
5662                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5663
5664                 if (!dm_old_crtc_state->stream)
5665                         return 0;
5666
5667                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5668                                 plane->base.id, old_plane_crtc->base.id);
5669
5670                 ret = dm_atomic_get_state(state, &dm_state);
5671                 if (ret)
5672                         return ret;
5673
5674                 if (!dc_remove_plane_from_context(
5675                                 dc,
5676                                 dm_old_crtc_state->stream,
5677                                 dm_old_plane_state->dc_state,
5678                                 dm_state->context)) {
5679
5680                         ret = EINVAL;
5681                         return ret;
5682                 }
5683
5684
5685                 dc_plane_state_release(dm_old_plane_state->dc_state);
5686                 dm_new_plane_state->dc_state = NULL;
5687
5688                 *lock_and_validation_needed = true;
5689
5690         } else { /* Add new planes */
5691                 struct dc_plane_state *dc_new_plane_state;
5692
5693                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5694                         return 0;
5695
5696                 if (!new_plane_crtc)
5697                         return 0;
5698
5699                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5700                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5701
5702                 if (!dm_new_crtc_state->stream)
5703                         return 0;
5704
5705                 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
5706                         return 0;
5707
5708                 WARN_ON(dm_new_plane_state->dc_state);
5709
5710                 dc_new_plane_state = dc_create_plane_state(dc);
5711                 if (!dc_new_plane_state)
5712                         return -ENOMEM;
5713
5714                 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5715                                 plane->base.id, new_plane_crtc->base.id);
5716
5717                 ret = fill_plane_attributes(
5718                         new_plane_crtc->dev->dev_private,
5719                         dc_new_plane_state,
5720                         new_plane_state,
5721                         new_crtc_state);
5722                 if (ret) {
5723                         dc_plane_state_release(dc_new_plane_state);
5724                         return ret;
5725                 }
5726
5727                 ret = dm_atomic_get_state(state, &dm_state);
5728                 if (ret) {
5729                         dc_plane_state_release(dc_new_plane_state);
5730                         return ret;
5731                 }
5732
5733                 /*
5734                  * Any atomic check errors that occur after this will
5735                  * not need a release. The plane state will be attached
5736                  * to the stream, and therefore part of the atomic
5737                  * state. It'll be released when the atomic state is
5738                  * cleaned.
5739                  */
5740                 if (!dc_add_plane_to_context(
5741                                 dc,
5742                                 dm_new_crtc_state->stream,
5743                                 dc_new_plane_state,
5744                                 dm_state->context)) {
5745
5746                         dc_plane_state_release(dc_new_plane_state);
5747                         return -EINVAL;
5748                 }
5749
5750                 dm_new_plane_state->dc_state = dc_new_plane_state;
5751
5752                 /* Tell DC to do a full surface update every time there
5753                  * is a plane change. Inefficient, but works for now.
5754                  */
5755                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5756
5757                 *lock_and_validation_needed = true;
5758         }
5759
5760
5761         return ret;
5762 }
5763
5764 static int
5765 dm_determine_update_type_for_commit(struct dc *dc,
5766                                     struct drm_atomic_state *state,
5767                                     enum surface_update_type *out_type)
5768 {
5769         struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5770         int i, j, num_plane, ret = 0;
5771         struct drm_plane_state *old_plane_state, *new_plane_state;
5772         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5773         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5774         struct drm_plane *plane;
5775
5776         struct drm_crtc *crtc;
5777         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5778         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5779         struct dc_stream_status *status = NULL;
5780
5781         struct dc_surface_update *updates;
5782         struct dc_plane_state *surface;
5783         enum surface_update_type update_type = UPDATE_TYPE_FAST;
5784
5785         updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
5786         surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
5787
5788         if (!updates || !surface) {
5789                 DRM_ERROR("Plane or surface update failed to allocate");
5790                 /* Set type to FULL to avoid crashing in DC*/
5791                 update_type = UPDATE_TYPE_FULL;
5792                 goto cleanup;
5793         }
5794
5795         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5796                 struct dc_stream_update stream_update = { 0 };
5797
5798                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5799                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5800                 num_plane = 0;
5801
5802                 if (!new_dm_crtc_state->stream) {
5803                         if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5804                                 update_type = UPDATE_TYPE_FULL;
5805                                 goto cleanup;
5806                         }
5807
5808                         continue;
5809                 }
5810
5811                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5812                         new_plane_crtc = new_plane_state->crtc;
5813                         old_plane_crtc = old_plane_state->crtc;
5814                         new_dm_plane_state = to_dm_plane_state(new_plane_state);
5815                         old_dm_plane_state = to_dm_plane_state(old_plane_state);
5816
5817                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5818                                 continue;
5819
5820                         if (!state->allow_modeset)
5821                                 continue;
5822
5823                         if (crtc != new_plane_crtc)
5824                                 continue;
5825
5826                         updates[num_plane].surface = &surface[num_plane];
5827
5828                         if (new_crtc_state->mode_changed) {
5829                                 updates[num_plane].surface->src_rect =
5830                                                 new_dm_plane_state->dc_state->src_rect;
5831                                 updates[num_plane].surface->dst_rect =
5832                                                 new_dm_plane_state->dc_state->dst_rect;
5833                                 updates[num_plane].surface->rotation =
5834                                                 new_dm_plane_state->dc_state->rotation;
5835                                 updates[num_plane].surface->in_transfer_func =
5836                                                 new_dm_plane_state->dc_state->in_transfer_func;
5837                                 stream_update.dst = new_dm_crtc_state->stream->dst;
5838                                 stream_update.src = new_dm_crtc_state->stream->src;
5839                         }
5840
5841                         if (new_crtc_state->color_mgmt_changed) {
5842                                 updates[num_plane].gamma =
5843                                                 new_dm_plane_state->dc_state->gamma_correction;
5844                                 updates[num_plane].in_transfer_func =
5845                                                 new_dm_plane_state->dc_state->in_transfer_func;
5846                                 stream_update.gamut_remap =
5847                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
5848                                 stream_update.out_transfer_func =
5849                                                 new_dm_crtc_state->stream->out_transfer_func;
5850                         }
5851
5852                         num_plane++;
5853                 }
5854
5855                 if (num_plane == 0)
5856                         continue;
5857
5858                 ret = dm_atomic_get_state(state, &dm_state);
5859                 if (ret)
5860                         goto cleanup;
5861
5862                 old_dm_state = dm_atomic_get_old_state(state);
5863                 if (!old_dm_state) {
5864                         ret = -EINVAL;
5865                         goto cleanup;
5866                 }
5867
5868                 status = dc_stream_get_status_from_state(old_dm_state->context,
5869                                                          new_dm_crtc_state->stream);
5870
5871                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5872                                                                   &stream_update, status);
5873
5874                 if (update_type > UPDATE_TYPE_MED) {
5875                         update_type = UPDATE_TYPE_FULL;
5876                         goto cleanup;
5877                 }
5878         }
5879
5880 cleanup:
5881         kfree(updates);
5882         kfree(surface);
5883
5884         *out_type = update_type;
5885         return ret;
5886 }
5887
5888 /**
5889  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5890  * @dev: The DRM device
5891  * @state: The atomic state to commit
5892  *
5893  * Validate that the given atomic state is programmable by DC into hardware.
5894  * This involves constructing a &struct dc_state reflecting the new hardware
5895  * state we wish to commit, then querying DC to see if it is programmable. It's
5896  * important not to modify the existing DC state. Otherwise, atomic_check
5897  * may unexpectedly commit hardware changes.
5898  *
5899  * When validating the DC state, it's important that the right locks are
5900  * acquired. For full updates case which removes/adds/updates streams on one
5901  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5902  * that any such full update commit will wait for completion of any outstanding
5903  * flip using DRMs synchronization events. See
5904  * dm_determine_update_type_for_commit()
5905  *
5906  * Note that DM adds the affected connectors for all CRTCs in state, when that
5907  * might not seem necessary. This is because DC stream creation requires the
5908  * DC sink, which is tied to the DRM connector state. Cleaning this up should
5909  * be possible but non-trivial - a possible TODO item.
5910  *
5911  * Return: -Error code if validation failed.
5912  */
5913 static int amdgpu_dm_atomic_check(struct drm_device *dev,
5914                                   struct drm_atomic_state *state)
5915 {
5916         struct amdgpu_device *adev = dev->dev_private;
5917         struct dm_atomic_state *dm_state = NULL;
5918         struct dc *dc = adev->dm.dc;
5919         struct drm_connector *connector;
5920         struct drm_connector_state *old_con_state, *new_con_state;
5921         struct drm_crtc *crtc;
5922         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5923         struct drm_plane *plane;
5924         struct drm_plane_state *old_plane_state, *new_plane_state;
5925         enum surface_update_type update_type = UPDATE_TYPE_FAST;
5926         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5927
5928         int ret, i;
5929
5930         /*
5931          * This bool will be set for true for any modeset/reset
5932          * or plane update which implies non fast surface update.
5933          */
5934         bool lock_and_validation_needed = false;
5935
5936         ret = drm_atomic_helper_check_modeset(dev, state);
5937         if (ret)
5938                 goto fail;
5939
5940         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5941                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
5942                     !new_crtc_state->color_mgmt_changed &&
5943                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
5944                         continue;
5945
5946                 if (!new_crtc_state->enable)
5947                         continue;
5948
5949                 ret = drm_atomic_add_affected_connectors(state, crtc);
5950                 if (ret)
5951                         return ret;
5952
5953                 ret = drm_atomic_add_affected_planes(state, crtc);
5954                 if (ret)
5955                         goto fail;
5956         }
5957
5958         /* Remove exiting planes if they are modified */
5959         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
5960                 ret = dm_update_plane_state(dc, state, plane,
5961                                             old_plane_state,
5962                                             new_plane_state,
5963                                             false,
5964                                             &lock_and_validation_needed);
5965                 if (ret)
5966                         goto fail;
5967         }
5968
5969         /* Disable all crtcs which require disable */
5970         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5971                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
5972                                            old_crtc_state,
5973                                            new_crtc_state,
5974                                            false,
5975                                            &lock_and_validation_needed);
5976                 if (ret)
5977                         goto fail;
5978         }
5979
5980         /* Enable all crtcs which require enable */
5981         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5982                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
5983                                            old_crtc_state,
5984                                            new_crtc_state,
5985                                            true,
5986                                            &lock_and_validation_needed);
5987                 if (ret)
5988                         goto fail;
5989         }
5990
5991         /* Add new/modified planes */
5992         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
5993                 ret = dm_update_plane_state(dc, state, plane,
5994                                             old_plane_state,
5995                                             new_plane_state,
5996                                             true,
5997                                             &lock_and_validation_needed);
5998                 if (ret)
5999                         goto fail;
6000         }
6001
6002         /* Run this here since we want to validate the streams we created */
6003         ret = drm_atomic_helper_check_planes(dev, state);
6004         if (ret)
6005                 goto fail;
6006
6007         /* Check scaling and underscan changes*/
6008         /* TODO Removed scaling changes validation due to inability to commit
6009          * new stream into context w\o causing full reset. Need to
6010          * decide how to handle.
6011          */
6012         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6013                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6014                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6015                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6016
6017                 /* Skip any modesets/resets */
6018                 if (!acrtc || drm_atomic_crtc_needs_modeset(
6019                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
6020                         continue;
6021
6022                 /* Skip any thing not scale or underscan changes */
6023                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
6024                         continue;
6025
6026                 overall_update_type = UPDATE_TYPE_FULL;
6027                 lock_and_validation_needed = true;
6028         }
6029
6030         ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6031         if (ret)
6032                 goto fail;
6033
6034         if (overall_update_type < update_type)
6035                 overall_update_type = update_type;
6036
6037         /*
6038          * lock_and_validation_needed was an old way to determine if we need to set
6039          * the global lock. Leaving it in to check if we broke any corner cases
6040          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6041          * lock_and_validation_needed false = UPDATE_TYPE_FAST
6042          */
6043         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6044                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6045         else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6046                 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
6047
6048
6049         if (overall_update_type > UPDATE_TYPE_FAST) {
6050                 ret = dm_atomic_get_state(state, &dm_state);
6051                 if (ret)
6052                         goto fail;
6053
6054                 ret = do_aquire_global_lock(dev, state);
6055                 if (ret)
6056                         goto fail;
6057
6058                 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
6059                         ret = -EINVAL;
6060                         goto fail;
6061                 }
6062         } else if (state->legacy_cursor_update) {
6063                 /*
6064                  * This is a fast cursor update coming from the plane update
6065                  * helper, check if it can be done asynchronously for better
6066                  * performance.
6067                  */
6068                 state->async_update = !drm_atomic_helper_async_check(dev, state);
6069         }
6070
6071         /* Must be success */
6072         WARN_ON(ret);
6073         return ret;
6074
6075 fail:
6076         if (ret == -EDEADLK)
6077                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
6078         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
6079                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
6080         else
6081                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
6082
6083         return ret;
6084 }
6085
6086 static bool is_dp_capable_without_timing_msa(struct dc *dc,
6087                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
6088 {
6089         uint8_t dpcd_data;
6090         bool capable = false;
6091
6092         if (amdgpu_dm_connector->dc_link &&
6093                 dm_helpers_dp_read_dpcd(
6094                                 NULL,
6095                                 amdgpu_dm_connector->dc_link,
6096                                 DP_DOWN_STREAM_PORT_COUNT,
6097                                 &dpcd_data,
6098                                 sizeof(dpcd_data))) {
6099                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6100         }
6101
6102         return capable;
6103 }
6104 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6105                                         struct edid *edid)
6106 {
6107         int i;
6108         bool edid_check_required;
6109         struct detailed_timing *timing;
6110         struct detailed_non_pixel *data;
6111         struct detailed_data_monitor_range *range;
6112         struct amdgpu_dm_connector *amdgpu_dm_connector =
6113                         to_amdgpu_dm_connector(connector);
6114         struct dm_connector_state *dm_con_state = NULL;
6115
6116         struct drm_device *dev = connector->dev;
6117         struct amdgpu_device *adev = dev->dev_private;
6118         bool freesync_capable = false;
6119
6120         if (!connector->state) {
6121                 DRM_ERROR("%s - Connector has no state", __func__);
6122                 goto update;
6123         }
6124
6125         if (!edid) {
6126                 dm_con_state = to_dm_connector_state(connector->state);
6127
6128                 amdgpu_dm_connector->min_vfreq = 0;
6129                 amdgpu_dm_connector->max_vfreq = 0;
6130                 amdgpu_dm_connector->pixel_clock_mhz = 0;
6131
6132                 goto update;
6133         }
6134
6135         dm_con_state = to_dm_connector_state(connector->state);
6136
6137         edid_check_required = false;
6138         if (!amdgpu_dm_connector->dc_sink) {
6139                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
6140                 goto update;
6141         }
6142         if (!adev->dm.freesync_module)
6143                 goto update;
6144         /*
6145          * if edid non zero restrict freesync only for dp and edp
6146          */
6147         if (edid) {
6148                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6149                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
6150                         edid_check_required = is_dp_capable_without_timing_msa(
6151                                                 adev->dm.dc,
6152                                                 amdgpu_dm_connector);
6153                 }
6154         }
6155         if (edid_check_required == true && (edid->version > 1 ||
6156            (edid->version == 1 && edid->revision > 1))) {
6157                 for (i = 0; i < 4; i++) {
6158
6159                         timing  = &edid->detailed_timings[i];
6160                         data    = &timing->data.other_data;
6161                         range   = &data->data.range;
6162                         /*
6163                          * Check if monitor has continuous frequency mode
6164                          */
6165                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
6166                                 continue;
6167                         /*
6168                          * Check for flag range limits only. If flag == 1 then
6169                          * no additional timing information provided.
6170                          * Default GTF, GTF Secondary curve and CVT are not
6171                          * supported
6172                          */
6173                         if (range->flags != 1)
6174                                 continue;
6175
6176                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6177                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6178                         amdgpu_dm_connector->pixel_clock_mhz =
6179                                 range->pixel_clock_mhz * 10;
6180                         break;
6181                 }
6182
6183                 if (amdgpu_dm_connector->max_vfreq -
6184                     amdgpu_dm_connector->min_vfreq > 10) {
6185
6186                         freesync_capable = true;
6187                 }
6188         }
6189
6190 update:
6191         if (dm_con_state)
6192                 dm_con_state->freesync_capable = freesync_capable;
6193
6194         if (connector->vrr_capable_property)
6195                 drm_connector_set_vrr_capable_property(connector,
6196                                                        freesync_capable);
6197 }
6198