drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "mp/mp_9_0_offset.h"
  45 #include "mp/mp_9_0_sh_mask.h"
  46 #include "smuio/smuio_9_0_offset.h"
  47 #include "smuio/smuio_9_0_sh_mask.h"
  48
  49 #include "soc15.h"
  50 #include "soc15_common.h"
  51 #include "gfx_v9_0.h"
  52 #include "gmc_v9_0.h"
  53 #include "gfxhub_v1_0.h"
  54 #include "mmhub_v1_0.h"
  55 #include "vega10_ih.h"
  56 #include "sdma_v4_0.h"
  57 #include "uvd_v7_0.h"
  58 #include "vce_v4_0.h"
  59 #include "vcn_v1_0.h"
  60 #include "amdgpu_powerplay.h"
  61 #include "dce_virtual.h"
  62 #include "mxgpu_ai.h"
  63
  64 #define mmFabricConfigAccessControl                                                                    0x0410
  65 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  66 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  67 //FabricConfigAccessControl
  68 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  69 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  70 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  71 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  72 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  73 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  74
  75
  76 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  77 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  78 //DF_PIE_AON0_DfGlobalClkGater
  79 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  80 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  81
  82 enum {
  83         DF_MGCG_DISABLE = 0,
  84         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  85         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  86         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  87         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  88         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  89 };
  90
  91 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  92 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  93 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  94 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  95
  96 /*
  97  * Indirect registers accessor
  98  */
  99 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 100 {
 101         unsigned long flags, address, data;
 102         u32 r;
 103         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 104         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 105
 106         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 107         WREG32(address, reg);
 108         (void)RREG32(address);
 109         r = RREG32(data);
 110         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 111         return r;
 112 }
 113
 114 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 115 {
 116         unsigned long flags, address, data;
 117
 118         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 119         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 120
 121         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 122         WREG32(address, reg);
 123         (void)RREG32(address);
 124         WREG32(data, v);
 125         (void)RREG32(data);
 126         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 127 }
 128
 129 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 130 {
 131         unsigned long flags, address, data;
 132         u32 r;
 133
 134         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 135         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 136
 137         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 138         WREG32(address, ((reg) & 0x1ff));
 139         r = RREG32(data);
 140         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 141         return r;
 142 }
 143
 144 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 145 {
 146         unsigned long flags, address, data;
 147
 148         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 149         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 150
 151         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 152         WREG32(address, ((reg) & 0x1ff));
 153         WREG32(data, (v));
 154         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 155 }
 156
 157 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 158 {
 159         unsigned long flags, address, data;
 160         u32 r;
 161
 162         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 163         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 164
 165         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 166         WREG32(address, (reg));
 167         r = RREG32(data);
 168         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 169         return r;
 170 }
 171
 172 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 173 {
 174         unsigned long flags, address, data;
 175
 176         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 177         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 178
 179         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 180         WREG32(address, (reg));
 181         WREG32(data, (v));
 182         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 183 }
 184
 185 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 186 {
 187         unsigned long flags;
 188         u32 r;
 189
 190         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 191         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 192         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 193         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 194         return r;
 195 }
 196
 197 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 198 {
 199         unsigned long flags;
 200
 201         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 202         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 203         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 204         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 205 }
 206
 207 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 208 {
 209         unsigned long flags;
 210         u32 r;
 211
 212         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 213         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 214         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 215         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 216         return r;
 217 }
 218
 219 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 220 {
 221         unsigned long flags;
 222
 223         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 224         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 225         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 226         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 227 }
 228
 229 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 230 {
 231         return adev->nbio_funcs->get_memsize(adev);
 232 }
 233
 234 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 235 {
 236         return adev->clock.spll.reference_freq;
 237 }
 238
 239
 240 void soc15_grbm_select(struct amdgpu_device *adev,
 241                      u32 me, u32 pipe, u32 queue, u32 vmid)
 242 {
 243         u32 grbm_gfx_cntl = 0;
 244         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 245         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 246         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 247         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 248
 249         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 250 }
 251
 252 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 253 {
 254         /* todo */
 255 }
 256
 257 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 258 {
 259         /* todo */
 260         return false;
 261 }
 262
 263 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 264                                      u8 *bios, u32 length_bytes)
 265 {
 266         u32 *dw_ptr;
 267         u32 i, length_dw;
 268
 269         if (bios == NULL)
 270                 return false;
 271         if (length_bytes == 0)
 272                 return false;
 273         /* APU vbios image is part of sbios image */
 274         if (adev->flags & AMD_IS_APU)
 275                 return false;
 276
 277         dw_ptr = (u32 *)bios;
 278         length_dw = ALIGN(length_bytes, 4) / 4;
 279
 280         /* set rom index to 0 */
 281         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 282         /* read out the rom data */
 283         for (i = 0; i < length_dw; i++)
 284                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 285
 286         return true;
 287 }
 288
 289 struct soc15_allowed_register_entry {
 290         uint32_t hwip;
 291         uint32_t inst;
 292         uint32_t seg;
 293         uint32_t reg_offset;
 294         bool grbm_indexed;
 295 };
 296
 297
 298 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 299         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 300         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 301         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 302         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 303         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 304         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 305         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 306         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 307         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 308         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 309         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 310         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 311         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 312         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 313         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 314         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 315         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 316         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 317 };
 318
 319 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 320                                          u32 sh_num, u32 reg_offset)
 321 {
 322         uint32_t val;
 323
 324         mutex_lock(&adev->grbm_idx_mutex);
 325         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 326                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 327
 328         val = RREG32(reg_offset);
 329
 330         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 331                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 332         mutex_unlock(&adev->grbm_idx_mutex);
 333         return val;
 334 }
 335
 336 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 337                                          bool indexed, u32 se_num,
 338                                          u32 sh_num, u32 reg_offset)
 339 {
 340         if (indexed) {
 341                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 342         } else {
 343                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 344                         return adev->gfx.config.gb_addr_config;
 345                 return RREG32(reg_offset);
 346         }
 347 }
 348
 349 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 350                             u32 sh_num, u32 reg_offset, u32 *value)
 351 {
 352         uint32_t i;
 353         struct soc15_allowed_register_entry  *en;
 354
 355         *value = 0;
 356         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 357                 en = &soc15_allowed_read_registers[i];
 358                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 359                                         + en->reg_offset))
 360                         continue;
 361
 362                 *value = soc15_get_register_value(adev,
 363                                                   soc15_allowed_read_registers[i].grbm_indexed,
 364                                                   se_num, sh_num, reg_offset);
 365                 return 0;
 366         }
 367         return -EINVAL;
 368 }
 369
 370
 371 /**
 372  * soc15_program_register_sequence - program an array of registers.
 373  *
 374  * @adev: amdgpu_device pointer
 375  * @regs: pointer to the register array
 376  * @array_size: size of the register array
 377  *
 378  * Programs an array or registers with and and or masks.
 379  * This is a helper for setting golden registers.
 380  */
 381
 382 void soc15_program_register_sequence(struct amdgpu_device *adev,
 383                                              const struct soc15_reg_golden *regs,
 384                                              const u32 array_size)
 385 {
 386         const struct soc15_reg_golden *entry;
 387         u32 tmp, reg;
 388         int i;
 389
 390         for (i = 0; i < array_size; ++i) {
 391                 entry = &regs[i];
 392                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 393
 394                 if (entry->and_mask == 0xffffffff) {
 395                         tmp = entry->or_mask;
 396                 } else {
 397                         tmp = RREG32(reg);
 398                         tmp &= ~(entry->and_mask);
 399                         tmp |= entry->or_mask;
 400                 }
 401                 WREG32(reg, tmp);
 402         }
 403
 404 }
 405
 406
 407 static int soc15_asic_reset(struct amdgpu_device *adev)
 408 {
 409         u32 i;
 410
 411         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 412
 413         dev_info(adev->dev, "GPU reset\n");
 414
 415         /* disable BM */
 416         pci_clear_master(adev->pdev);
 417
 418         pci_save_state(adev->pdev);
 419
 420         psp_gpu_reset(adev);
 421
 422         pci_restore_state(adev->pdev);
 423
 424         /* wait for asic to come out of reset */
 425         for (i = 0; i < adev->usec_timeout; i++) {
 426                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 427
 428                 if (memsize != 0xffffffff)
 429                         break;
 430                 udelay(1);
 431         }
 432
 433         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 434
 435         return 0;
 436 }
 437
 438 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 439                         u32 cntl_reg, u32 status_reg)
 440 {
 441         return 0;
 442 }*/
 443
 444 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 445 {
 446         /*int r;
 447
 448         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 449         if (r)
 450                 return r;
 451
 452         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 453         */
 454         return 0;
 455 }
 456
 457 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 458 {
 459         /* todo */
 460
 461         return 0;
 462 }
 463
 464 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 465 {
 466         if (pci_is_root_bus(adev->pdev->bus))
 467                 return;
 468
 469         if (amdgpu_pcie_gen2 == 0)
 470                 return;
 471
 472         if (adev->flags & AMD_IS_APU)
 473                 return;
 474
 475         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 476                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 477                 return;
 478
 479         /* todo */
 480 }
 481
 482 static void soc15_program_aspm(struct amdgpu_device *adev)
 483 {
 484
 485         if (amdgpu_aspm == 0)
 486                 return;
 487
 488         /* todo */
 489 }
 490
 491 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 492                                            bool enable)
 493 {
 494         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 495         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 496 }
 497
 498 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 499 {
 500         .type = AMD_IP_BLOCK_TYPE_COMMON,
 501         .major = 2,
 502         .minor = 0,
 503         .rev = 0,
 504         .funcs = &soc15_common_ip_funcs,
 505 };
 506
 507 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 508 {
 509         /* Set IP register base before any HW register access */
 510         switch (adev->asic_type) {
 511         case CHIP_VEGA10:
 512         case CHIP_RAVEN:
 513                 vega10_reg_base_init(adev);
 514                 break;
 515         default:
 516                 return -EINVAL;
 517         }
 518
 519         if (adev->flags & AMD_IS_APU)
 520                 adev->nbio_funcs = &nbio_v7_0_funcs;
 521         else
 522                 adev->nbio_funcs = &nbio_v6_1_funcs;
 523
 524         adev->nbio_funcs->detect_hw_virt(adev);
 525
 526         if (amdgpu_sriov_vf(adev))
 527                 adev->virt.ops = &xgpu_ai_virt_ops;
 528
 529         switch (adev->asic_type) {
 530         case CHIP_VEGA10:
 531                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 532                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 533                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 534                 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
 535                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 536                 if (!amdgpu_sriov_vf(adev))
 537                         amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
 538                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 539                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 540 #if defined(CONFIG_DRM_AMD_DC)
 541                 else if (amdgpu_device_has_dc_support(adev))
 542                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 543 #else
 544 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 545 #endif
 546                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 547                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 548                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 549                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 550                 break;
 551         case CHIP_RAVEN:
 552                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 553                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 554                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 555                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 556                 amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
 557                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 558                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 559 #if defined(CONFIG_DRM_AMD_DC)
 560                 else if (amdgpu_device_has_dc_support(adev))
 561                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 562 #else
 563 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 564 #endif
 565                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 566                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 567                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 568                 break;
 569         default:
 570                 return -EINVAL;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 577 {
 578         return adev->nbio_funcs->get_rev_id(adev);
 579 }
 580
 581 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 582 {
 583         adev->nbio_funcs->hdp_flush(adev, ring);
 584 }
 585
 586 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 587                                  struct amdgpu_ring *ring)
 588 {
 589         if (!ring || !ring->funcs->emit_wreg)
 590                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 591         else
 592                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 593                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 594 }
 595
 596 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 597 {
 598         .read_disabled_bios = &soc15_read_disabled_bios,
 599         .read_bios_from_rom = &soc15_read_bios_from_rom,
 600         .read_register = &soc15_read_register,
 601         .reset = &soc15_asic_reset,
 602         .set_vga_state = &soc15_vga_set_state,
 603         .get_xclk = &soc15_get_xclk,
 604         .set_uvd_clocks = &soc15_set_uvd_clocks,
 605         .set_vce_clocks = &soc15_set_vce_clocks,
 606         .get_config_memsize = &soc15_get_config_memsize,
 607         .flush_hdp = &soc15_flush_hdp,
 608         .invalidate_hdp = &soc15_invalidate_hdp,
 609 };
 610
 611 static int soc15_common_early_init(void *handle)
 612 {
 613         bool psp_enabled = false;
 614         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 615
 616         adev->smc_rreg = NULL;
 617         adev->smc_wreg = NULL;
 618         adev->pcie_rreg = &soc15_pcie_rreg;
 619         adev->pcie_wreg = &soc15_pcie_wreg;
 620         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 621         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 622         adev->didt_rreg = &soc15_didt_rreg;
 623         adev->didt_wreg = &soc15_didt_wreg;
 624         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 625         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 626         adev->se_cac_rreg = &soc15_se_cac_rreg;
 627         adev->se_cac_wreg = &soc15_se_cac_wreg;
 628
 629         adev->asic_funcs = &soc15_asic_funcs;
 630
 631         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
 632             (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
 633                 psp_enabled = true;
 634
 635         adev->rev_id = soc15_get_rev_id(adev);
 636         adev->external_rev_id = 0xFF;
 637         switch (adev->asic_type) {
 638         case CHIP_VEGA10:
 639                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 640                         AMD_CG_SUPPORT_GFX_MGLS |
 641                         AMD_CG_SUPPORT_GFX_RLC_LS |
 642                         AMD_CG_SUPPORT_GFX_CP_LS |
 643                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 644                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 645                         AMD_CG_SUPPORT_GFX_CGCG |
 646                         AMD_CG_SUPPORT_GFX_CGLS |
 647                         AMD_CG_SUPPORT_BIF_MGCG |
 648                         AMD_CG_SUPPORT_BIF_LS |
 649                         AMD_CG_SUPPORT_HDP_LS |
 650                         AMD_CG_SUPPORT_DRM_MGCG |
 651                         AMD_CG_SUPPORT_DRM_LS |
 652                         AMD_CG_SUPPORT_ROM_MGCG |
 653                         AMD_CG_SUPPORT_DF_MGCG |
 654                         AMD_CG_SUPPORT_SDMA_MGCG |
 655                         AMD_CG_SUPPORT_SDMA_LS |
 656                         AMD_CG_SUPPORT_MC_MGCG |
 657                         AMD_CG_SUPPORT_MC_LS;
 658                 adev->pg_flags = 0;
 659                 adev->external_rev_id = 0x1;
 660                 break;
 661         case CHIP_RAVEN:
 662                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 663                         AMD_CG_SUPPORT_GFX_MGLS |
 664                         AMD_CG_SUPPORT_GFX_RLC_LS |
 665                         AMD_CG_SUPPORT_GFX_CP_LS |
 666                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 667                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 668                         AMD_CG_SUPPORT_GFX_CGCG |
 669                         AMD_CG_SUPPORT_GFX_CGLS |
 670                         AMD_CG_SUPPORT_BIF_MGCG |
 671                         AMD_CG_SUPPORT_BIF_LS |
 672                         AMD_CG_SUPPORT_HDP_MGCG |
 673                         AMD_CG_SUPPORT_HDP_LS |
 674                         AMD_CG_SUPPORT_DRM_MGCG |
 675                         AMD_CG_SUPPORT_DRM_LS |
 676                         AMD_CG_SUPPORT_ROM_MGCG |
 677                         AMD_CG_SUPPORT_MC_MGCG |
 678                         AMD_CG_SUPPORT_MC_LS |
 679                         AMD_CG_SUPPORT_SDMA_MGCG |
 680                         AMD_CG_SUPPORT_SDMA_LS;
 681                 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
 682
 683                 adev->external_rev_id = 0x1;
 684                 break;
 685         default:
 686                 /* FIXME: not supported yet */
 687                 return -EINVAL;
 688         }
 689
 690         if (amdgpu_sriov_vf(adev)) {
 691                 amdgpu_virt_init_setting(adev);
 692                 xgpu_ai_mailbox_set_irq_funcs(adev);
 693         }
 694
 695         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 696
 697         amdgpu_device_get_pcie_info(adev);
 698
 699         return 0;
 700 }
 701
 702 static int soc15_common_late_init(void *handle)
 703 {
 704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 705
 706         if (amdgpu_sriov_vf(adev))
 707                 xgpu_ai_mailbox_get_irq(adev);
 708
 709         return 0;
 710 }
 711
 712 static int soc15_common_sw_init(void *handle)
 713 {
 714         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 715
 716         if (amdgpu_sriov_vf(adev))
 717                 xgpu_ai_mailbox_add_irq_id(adev);
 718
 719         return 0;
 720 }
 721
 722 static int soc15_common_sw_fini(void *handle)
 723 {
 724         return 0;
 725 }
 726
 727 static int soc15_common_hw_init(void *handle)
 728 {
 729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 730
 731         /* enable pcie gen2/3 link */
 732         soc15_pcie_gen3_enable(adev);
 733         /* enable aspm */
 734         soc15_program_aspm(adev);
 735         /* setup nbio registers */
 736         adev->nbio_funcs->init_registers(adev);
 737         /* enable the doorbell aperture */
 738         soc15_enable_doorbell_aperture(adev, true);
 739
 740         return 0;
 741 }
 742
 743 static int soc15_common_hw_fini(void *handle)
 744 {
 745         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 746
 747         /* disable the doorbell aperture */
 748         soc15_enable_doorbell_aperture(adev, false);
 749         if (amdgpu_sriov_vf(adev))
 750                 xgpu_ai_mailbox_put_irq(adev);
 751
 752         return 0;
 753 }
 754
 755 static int soc15_common_suspend(void *handle)
 756 {
 757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 758
 759         return soc15_common_hw_fini(adev);
 760 }
 761
 762 static int soc15_common_resume(void *handle)
 763 {
 764         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 765
 766         return soc15_common_hw_init(adev);
 767 }
 768
 769 static bool soc15_common_is_idle(void *handle)
 770 {
 771         return true;
 772 }
 773
 774 static int soc15_common_wait_for_idle(void *handle)
 775 {
 776         return 0;
 777 }
 778
 779 static int soc15_common_soft_reset(void *handle)
 780 {
 781         return 0;
 782 }
 783
 784 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 785 {
 786         uint32_t def, data;
 787
 788         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 789
 790         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 791                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 792         else
 793                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 794
 795         if (def != data)
 796                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 797 }
 798
 799 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 800 {
 801         uint32_t def, data;
 802
 803         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 804
 805         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 806                 data &= ~(0x01000000 |
 807                           0x02000000 |
 808                           0x04000000 |
 809                           0x08000000 |
 810                           0x10000000 |
 811                           0x20000000 |
 812                           0x40000000 |
 813                           0x80000000);
 814         else
 815                 data |= (0x01000000 |
 816                          0x02000000 |
 817                          0x04000000 |
 818                          0x08000000 |
 819                          0x10000000 |
 820                          0x20000000 |
 821                          0x40000000 |
 822                          0x80000000);
 823
 824         if (def != data)
 825                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 826 }
 827
 828 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 829 {
 830         uint32_t def, data;
 831
 832         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 833
 834         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 835                 data |= 1;
 836         else
 837                 data &= ~1;
 838
 839         if (def != data)
 840                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 841 }
 842
 843 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 844                                                        bool enable)
 845 {
 846         uint32_t def, data;
 847
 848         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 849
 850         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 851                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 852                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 853         else
 854                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 855                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 856
 857         if (def != data)
 858                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 859 }
 860
 861 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 862                                                        bool enable)
 863 {
 864         uint32_t data;
 865
 866         /* Put DF on broadcast mode */
 867         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 868         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 869         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 870
 871         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 872                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 873                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 874                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 875                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 876         } else {
 877                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 878                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 879                 data |= DF_MGCG_DISABLE;
 880                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 881         }
 882
 883         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 884                mmFabricConfigAccessControl_DEFAULT);
 885 }
 886
 887 static int soc15_common_set_clockgating_state(void *handle,
 888                                             enum amd_clockgating_state state)
 889 {
 890         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 891
 892         if (amdgpu_sriov_vf(adev))
 893                 return 0;
 894
 895         switch (adev->asic_type) {
 896         case CHIP_VEGA10:
 897                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 898                                 state == AMD_CG_STATE_GATE ? true : false);
 899                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 900                                 state == AMD_CG_STATE_GATE ? true : false);
 901                 soc15_update_hdp_light_sleep(adev,
 902                                 state == AMD_CG_STATE_GATE ? true : false);
 903                 soc15_update_drm_clock_gating(adev,
 904                                 state == AMD_CG_STATE_GATE ? true : false);
 905                 soc15_update_drm_light_sleep(adev,
 906                                 state == AMD_CG_STATE_GATE ? true : false);
 907                 soc15_update_rom_medium_grain_clock_gating(adev,
 908                                 state == AMD_CG_STATE_GATE ? true : false);
 909                 soc15_update_df_medium_grain_clock_gating(adev,
 910                                 state == AMD_CG_STATE_GATE ? true : false);
 911                 break;
 912         case CHIP_RAVEN:
 913                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 914                                 state == AMD_CG_STATE_GATE ? true : false);
 915                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 916                                 state == AMD_CG_STATE_GATE ? true : false);
 917                 soc15_update_hdp_light_sleep(adev,
 918                                 state == AMD_CG_STATE_GATE ? true : false);
 919                 soc15_update_drm_clock_gating(adev,
 920                                 state == AMD_CG_STATE_GATE ? true : false);
 921                 soc15_update_drm_light_sleep(adev,
 922                                 state == AMD_CG_STATE_GATE ? true : false);
 923                 soc15_update_rom_medium_grain_clock_gating(adev,
 924                                 state == AMD_CG_STATE_GATE ? true : false);
 925                 break;
 926         default:
 927                 break;
 928         }
 929         return 0;
 930 }
 931
 932 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 933 {
 934         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 935         int data;
 936
 937         if (amdgpu_sriov_vf(adev))
 938                 *flags = 0;
 939
 940         adev->nbio_funcs->get_clockgating_state(adev, flags);
 941
 942         /* AMD_CG_SUPPORT_HDP_LS */
 943         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 944         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 945                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 946
 947         /* AMD_CG_SUPPORT_DRM_MGCG */
 948         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 949         if (!(data & 0x01000000))
 950                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 951
 952         /* AMD_CG_SUPPORT_DRM_LS */
 953         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 954         if (data & 0x1)
 955                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 956
 957         /* AMD_CG_SUPPORT_ROM_MGCG */
 958         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 959         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 960                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 961
 962         /* AMD_CG_SUPPORT_DF_MGCG */
 963         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 964         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 965                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 966 }
 967
 968 static int soc15_common_set_powergating_state(void *handle,
 969                                             enum amd_powergating_state state)
 970 {
 971         /* todo */
 972         return 0;
 973 }
 974
 975 const struct amd_ip_funcs soc15_common_ip_funcs = {
 976         .name = "soc15_common",
 977         .early_init = soc15_common_early_init,
 978         .late_init = soc15_common_late_init,
 979         .sw_init = soc15_common_sw_init,
 980         .sw_fini = soc15_common_sw_fini,
 981         .hw_init = soc15_common_hw_init,
 982         .hw_fini = soc15_common_hw_fini,
 983         .suspend = soc15_common_suspend,
 984         .resume = soc15_common_resume,
 985         .is_idle = soc15_common_is_idle,
 986         .wait_for_idle = soc15_common_wait_for_idle,
 987         .soft_reset = soc15_common_soft_reset,
 988         .set_clockgating_state = soc15_common_set_clockgating_state,
 989         .set_powergating_state = soc15_common_set_powergating_state,
 990         .get_clockgating_state= soc15_common_get_clockgating_state,
 991 };