drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_4.h"
  26 #include "amdgpu_ras.h"
  27
  28 #include "nbio/nbio_7_4_offset.h"
  29 #include "nbio/nbio_7_4_sh_mask.h"
  30 #include "nbio/nbio_7_4_0_smn.h"
  31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  32 #include <uapi/linux/kfd_ioctl.h>
  33
  34 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
  35
  36 /*
  37  * These are nbio v7_4_1 registers mask. Temporarily define these here since
  38  * nbio v7_4_1 header is incomplete.
  39  */
  40 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK      0x00001000L
  41 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK      0x00002000L
  42 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK      0x00004000L
  43 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK      0x00008000L
  44 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK      0x00010000L
  45 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK      0x00020000L
  46
  47 #define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
  48 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
  49 //BIF_MMSCH1_DOORBELL_RANGE
  50 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
  51 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
  52 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
  53 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
  54
  55 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
  56 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
  57
  58 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE                0x01d8
  59 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX       2
  60 //BIF_MMSCH1_DOORBELL_ALDE_RANGE
  61 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT   0x2
  62 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT     0x10
  63 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK     0x00000FFCL
  64 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK       0x001F0000L
  65
  66 #define mmRCC_DEV0_EPF0_STRAP0_ALDE                     0x0015
  67 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX            2
  68
  69 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
  70                                         void *ras_error_status);
  71
  72 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
  73 {
  74         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
  75                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
  76         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
  77                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
  78 }
  79
  80 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
  81 {
  82         u32 tmp;
  83
  84         if (adev->asic_type == CHIP_ALDEBARAN)
  85                 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
  86         else
  87                 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  88
  89         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  90         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  91
  92         return tmp;
  93 }
  94
  95 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
  96 {
  97         if (enable)
  98                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  99                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 100         else
 101                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
 102 }
 103
 104 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
 105 {
 106         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
 107 }
 108
 109 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
 110                         bool use_doorbell, int doorbell_index, int doorbell_size)
 111 {
 112         u32 reg, doorbell_range;
 113
 114         if (instance < 2) {
 115                 reg = instance +
 116                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 117         } else {
 118                 /*
 119                  * These registers address of SDMA2~7 is not consecutive
 120                  * from SDMA0~1. Need plus 4 dwords offset.
 121                  *
 122                  *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
 123                  *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
 124                  *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
 125 +                *   BIF_SDMA4_DOORBELL_RANGE:
 126 +                *     ARCTURUS:  0x3be0
 127 +                *     ALDEBARAN: 0x3be4
 128                  */
 129                 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
 130                         reg = instance + 0x4 + 0x1 +
 131                                 SOC15_REG_OFFSET(NBIO, 0,
 132                                                  mmBIF_SDMA0_DOORBELL_RANGE);
 133                 else
 134                         reg = instance + 0x4 +
 135                                 SOC15_REG_OFFSET(NBIO, 0,
 136                                                  mmBIF_SDMA0_DOORBELL_RANGE);
 137         }
 138
 139         doorbell_range = RREG32(reg);
 140
 141         if (use_doorbell) {
 142                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
 143                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
 144         } else
 145                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 146
 147         WREG32(reg, doorbell_range);
 148 }
 149
 150 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
 151                                          int doorbell_index, int instance)
 152 {
 153         u32 reg;
 154         u32 doorbell_range;
 155
 156         if (instance) {
 157                 if (adev->asic_type == CHIP_ALDEBARAN)
 158                         reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
 159                 else
 160                         reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
 161         } else
 162                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
 163
 164         doorbell_range = RREG32(reg);
 165
 166         if (use_doorbell) {
 167                 doorbell_range = REG_SET_FIELD(doorbell_range,
 168                                                BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
 169                                                doorbell_index);
 170                 doorbell_range = REG_SET_FIELD(doorbell_range,
 171                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
 172         } else
 173                 doorbell_range = REG_SET_FIELD(doorbell_range,
 174                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
 175
 176         WREG32(reg, doorbell_range);
 177 }
 178
 179 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
 180                                                bool enable)
 181 {
 182         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 183 }
 184
 185 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 186                                                         bool enable)
 187 {
 188         u32 tmp = 0;
 189
 190         if (enable) {
 191                 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 192                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 193                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 194
 195                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
 196                              lower_32_bits(adev->doorbell.base));
 197                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 198                              upper_32_bits(adev->doorbell.base));
 199         }
 200
 201         WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 202 }
 203
 204 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
 205                                         bool use_doorbell, int doorbell_index)
 206 {
 207         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 208
 209         if (use_doorbell) {
 210                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 211                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
 212         } else
 213                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 214
 215         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 216 }
 217
 218
 219 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 220                                                        bool enable)
 221 {
 222         //TODO: Add support for v7.4
 223 }
 224
 225 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 226                                                       bool enable)
 227 {
 228         uint32_t def, data;
 229
 230         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 231         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 232                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 233                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 234                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 235         } else {
 236                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 237                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 238                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 239         }
 240
 241         if (def != data)
 242                 WREG32_PCIE(smnPCIE_CNTL2, data);
 243 }
 244
 245 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
 246                                             u32 *flags)
 247 {
 248         int data;
 249
 250         /* AMD_CG_SUPPORT_BIF_MGCG */
 251         data = RREG32_PCIE(smnCPM_CONTROL);
 252         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 253                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 254
 255         /* AMD_CG_SUPPORT_BIF_LS */
 256         data = RREG32_PCIE(smnPCIE_CNTL2);
 257         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 258                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 259 }
 260
 261 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
 262 {
 263         u32 interrupt_cntl;
 264
 265         /* setup interrupt control */
 266         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 267         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 268         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 269          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 270          */
 271         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 272         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 273         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 274         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 275 }
 276
 277 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 278 {
 279         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 280 }
 281
 282 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 283 {
 284         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 285 }
 286
 287 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
 288 {
 289         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 290 }
 291
 292 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 293 {
 294         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 295 }
 296
 297 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
 298         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 299         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 300         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 301         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 302         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 303         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 304         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 305         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 306         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 307         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 308         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 309         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 310         .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
 311         .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
 312         .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
 313         .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
 314         .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
 315         .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
 316 };
 317
 318 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 319 {
 320
 321 }
 322
 323 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
 324 {
 325         uint32_t bif_doorbell_intr_cntl;
 326         struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
 327         struct ras_err_data err_data = {0, 0, 0, NULL};
 328         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 329
 330         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 331         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 332                 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
 333                 /* driver has to clear the interrupt status when bif ring is disabled */
 334                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 335                                                 BIF_DOORBELL_INT_CNTL,
 336                                                 RAS_CNTLR_INTERRUPT_CLEAR, 1);
 337                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 338
 339                 if (!ras->disable_ras_err_cnt_harvest) {
 340                         /*
 341                          * clear error status after ras_controller_intr
 342                          * according to hw team and count ue number
 343                          * for query
 344                          */
 345                         nbio_v7_4_query_ras_error_count(adev, &err_data);
 346
 347                         /* logging on error cnt and printing for awareness */
 348                         obj->err_data.ue_count += err_data.ue_count;
 349                         obj->err_data.ce_count += err_data.ce_count;
 350
 351                         if (err_data.ce_count)
 352                                 dev_info(adev->dev, "%ld correctable hardware "
 353                                                 "errors detected in %s block, "
 354                                                 "no user action is needed.\n",
 355                                                 obj->err_data.ce_count,
 356                                                 adev->nbio.ras_if->name);
 357
 358                         if (err_data.ue_count)
 359                                 dev_info(adev->dev, "%ld uncorrectable hardware "
 360                                                 "errors detected in %s block\n",
 361                                                 obj->err_data.ue_count,
 362                                                 adev->nbio.ras_if->name);
 363                 }
 364
 365                 dev_info(adev->dev, "RAS controller interrupt triggered "
 366                                         "by NBIF error\n");
 367
 368                 /* ras_controller_int is dedicated for nbif ras error,
 369                  * not the global interrupt for sync flood
 370                  */
 371                 amdgpu_ras_reset_gpu(adev);
 372         }
 373 }
 374
 375 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
 376 {
 377         uint32_t bif_doorbell_intr_cntl;
 378
 379         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 380         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 381                 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
 382                 /* driver has to clear the interrupt status when bif ring is disabled */
 383                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 384                                                 BIF_DOORBELL_INT_CNTL,
 385                                                 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
 386                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 387
 388                 amdgpu_ras_global_ras_isr(adev);
 389         }
 390 }
 391
 392
 393 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
 394                                                   struct amdgpu_irq_src *src,
 395                                                   unsigned type,
 396                                                   enum amdgpu_interrupt_state state)
 397 {
 398         /* The ras_controller_irq enablement should be done in psp bl when it
 399          * tries to enable ras feature. Driver only need to set the correct interrupt
 400          * vector for bare-metal and sriov use case respectively
 401          */
 402         uint32_t bif_intr_cntl;
 403
 404         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 405         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 406                 /* set interrupt vector select bit to 0 to select
 407                  * vetcor 1 for bare metal case */
 408                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 409                                               BIF_INTR_CNTL,
 410                                               RAS_INTR_VEC_SEL, 0);
 411                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
 418                                                 struct amdgpu_irq_src *source,
 419                                                 struct amdgpu_iv_entry *entry)
 420 {
 421         /* By design, the ih cookie for ras_controller_irq should be written
 422          * to BIFring instead of general iv ring. However, due to known bif ring
 423          * hw bug, it has to be disabled. There is no chance the process function
 424          * will be involked. Just left it as a dummy one.
 425          */
 426         return 0;
 427 }
 428
 429 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
 430                                                        struct amdgpu_irq_src *src,
 431                                                        unsigned type,
 432                                                        enum amdgpu_interrupt_state state)
 433 {
 434         /* The ras_controller_irq enablement should be done in psp bl when it
 435          * tries to enable ras feature. Driver only need to set the correct interrupt
 436          * vector for bare-metal and sriov use case respectively
 437          */
 438         uint32_t bif_intr_cntl;
 439
 440         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 441         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 442                 /* set interrupt vector select bit to 0 to select
 443                  * vetcor 1 for bare metal case */
 444                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 445                                               BIF_INTR_CNTL,
 446                                               RAS_INTR_VEC_SEL, 0);
 447                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
 454                                                  struct amdgpu_irq_src *source,
 455                                                  struct amdgpu_iv_entry *entry)
 456 {
 457         /* By design, the ih cookie for err_event_athub_irq should be written
 458          * to BIFring instead of general iv ring. However, due to known bif ring
 459          * hw bug, it has to be disabled. There is no chance the process function
 460          * will be involked. Just left it as a dummy one.
 461          */
 462         return 0;
 463 }
 464
 465 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
 466         .set = nbio_v7_4_set_ras_controller_irq_state,
 467         .process = nbio_v7_4_process_ras_controller_irq,
 468 };
 469
 470 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
 471         .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
 472         .process = nbio_v7_4_process_err_event_athub_irq,
 473 };
 474
 475 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
 476 {
 477         int r;
 478
 479         /* init the irq funcs */
 480         adev->nbio.ras_controller_irq.funcs =
 481                 &nbio_v7_4_ras_controller_irq_funcs;
 482         adev->nbio.ras_controller_irq.num_types = 1;
 483
 484         /* register ras controller interrupt */
 485         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 486                               NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
 487                               &adev->nbio.ras_controller_irq);
 488
 489         return r;
 490 }
 491
 492 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
 493 {
 494
 495         int r;
 496
 497         /* init the irq funcs */
 498         adev->nbio.ras_err_event_athub_irq.funcs =
 499                 &nbio_v7_4_ras_err_event_athub_irq_funcs;
 500         adev->nbio.ras_err_event_athub_irq.num_types = 1;
 501
 502         /* register ras err event athub interrupt */
 503         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 504                               NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
 505                               &adev->nbio.ras_err_event_athub_irq);
 506
 507         return r;
 508 }
 509
 510 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2      0x13a20030
 511
 512 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
 513                                         void *ras_error_status)
 514 {
 515         uint32_t global_sts, central_sts, int_eoi, parity_sts;
 516         uint32_t corr, fatal, non_fatal;
 517         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 518
 519         global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
 520         corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
 521         fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
 522         non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
 523                                 ParityErrNonFatal);
 524         parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
 525
 526         if (corr)
 527                 err_data->ce_count++;
 528         if (fatal)
 529                 err_data->ue_count++;
 530
 531         if (corr || fatal || non_fatal) {
 532                 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
 533                 /* clear error status register */
 534                 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
 535
 536                 if (fatal)
 537                         /* clear parity fatal error indication field */
 538                         WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
 539                                     parity_sts);
 540
 541                 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
 542                                 BIFL_RasContller_Intr_Recv)) {
 543                         /* clear interrupt status register */
 544                         WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
 545                         int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
 546                         int_eoi = REG_SET_FIELD(int_eoi,
 547                                         IOHC_INTERRUPT_EOI, SMI_EOI, 1);
 548                         WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
 549                 }
 550         }
 551 }
 552
 553 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
 554                                                 bool enable)
 555 {
 556         WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
 557                        DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
 558 }
 559
 560 const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
 561         .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
 562         .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
 563         .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
 564         .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
 565         .query_ras_error_count = nbio_v7_4_query_ras_error_count,
 566         .ras_late_init = amdgpu_nbio_ras_late_init,
 567         .ras_fini = amdgpu_nbio_ras_fini,
 568 };
 569
 570 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 571         .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 572         .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
 573         .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
 574         .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
 575         .get_rev_id = nbio_v7_4_get_rev_id,
 576         .mc_access_enable = nbio_v7_4_mc_access_enable,
 577         .get_memsize = nbio_v7_4_get_memsize,
 578         .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
 579         .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
 580         .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
 581         .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
 582         .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
 583         .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
 584         .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
 585         .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
 586         .get_clockgating_state = nbio_v7_4_get_clockgating_state,
 587         .ih_control = nbio_v7_4_ih_control,
 588         .init_registers = nbio_v7_4_init_registers,
 589         .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 590 };