drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu_cs.h"
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38 #include "amdgpu_gmc.h"
  39 #include "amdgpu_gem.h"
  40 #include "amdgpu_ras.h"
  41
  42 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  43                                       struct drm_amdgpu_cs_chunk_fence *data,
  44                                       uint32_t *offset)
  45 {
  46         struct drm_gem_object *gobj;
  47         struct amdgpu_bo *bo;
  48         unsigned long size;
  49         int r;
  50
  51         gobj = drm_gem_object_lookup(p->filp, data->handle);
  52         if (gobj == NULL)
  53                 return -EINVAL;
  54
  55         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  56         p->uf_entry.priority = 0;
  57         p->uf_entry.tv.bo = &bo->tbo;
  58         /* One for TTM and one for the CS job */
  59         p->uf_entry.tv.num_shared = 2;
  60
  61         drm_gem_object_put(gobj);
  62
  63         size = amdgpu_bo_size(bo);
  64         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  65                 r = -EINVAL;
  66                 goto error_unref;
  67         }
  68
  69         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  70                 r = -EINVAL;
  71                 goto error_unref;
  72         }
  73
  74         *offset = data->offset;
  75
  76         return 0;
  77
  78 error_unref:
  79         amdgpu_bo_unref(&bo);
  80         return r;
  81 }
  82
  83 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  84                                       struct drm_amdgpu_bo_list_in *data)
  85 {
  86         int r;
  87         struct drm_amdgpu_bo_list_entry *info = NULL;
  88
  89         r = amdgpu_bo_create_list_entry_array(data, &info);
  90         if (r)
  91                 return r;
  92
  93         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  94                                   &p->bo_list);
  95         if (r)
  96                 goto error_free;
  97
  98         kvfree(info);
  99         return 0;
 100
 101 error_free:
 102         kvfree(info);
 103
 104         return r;
 105 }
 106
 107 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 108 {
 109         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 110         struct amdgpu_vm *vm = &fpriv->vm;
 111         uint64_t *chunk_array_user;
 112         uint64_t *chunk_array;
 113         unsigned size, num_ibs = 0;
 114         uint32_t uf_offset = 0;
 115         int i;
 116         int ret;
 117
 118         if (cs->in.num_chunks == 0)
 119                 return 0;
 120
 121         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 122         if (!chunk_array)
 123                 return -ENOMEM;
 124
 125         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 126         if (!p->ctx) {
 127                 ret = -EINVAL;
 128                 goto free_chunk;
 129         }
 130
 131         /* skip guilty context job */
 132         if (atomic_read(&p->ctx->guilty) == 1) {
 133                 ret = -ECANCELED;
 134                 goto free_chunk;
 135         }
 136
 137         /* get chunks */
 138         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 139         if (copy_from_user(chunk_array, chunk_array_user,
 140                            sizeof(uint64_t)*cs->in.num_chunks)) {
 141                 ret = -EFAULT;
 142                 goto free_chunk;
 143         }
 144
 145         p->nchunks = cs->in.num_chunks;
 146         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 147                             GFP_KERNEL);
 148         if (!p->chunks) {
 149                 ret = -ENOMEM;
 150                 goto free_chunk;
 151         }
 152
 153         for (i = 0; i < p->nchunks; i++) {
 154                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 155                 struct drm_amdgpu_cs_chunk user_chunk;
 156                 uint32_t __user *cdata;
 157
 158                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 159                 if (copy_from_user(&user_chunk, chunk_ptr,
 160                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 161                         ret = -EFAULT;
 162                         i--;
 163                         goto free_partial_kdata;
 164                 }
 165                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 166                 p->chunks[i].length_dw = user_chunk.length_dw;
 167
 168                 size = p->chunks[i].length_dw;
 169                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 170
 171                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 172                 if (p->chunks[i].kdata == NULL) {
 173                         ret = -ENOMEM;
 174                         i--;
 175                         goto free_partial_kdata;
 176                 }
 177                 size *= sizeof(uint32_t);
 178                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 179                         ret = -EFAULT;
 180                         goto free_partial_kdata;
 181                 }
 182
 183                 switch (p->chunks[i].chunk_id) {
 184                 case AMDGPU_CHUNK_ID_IB:
 185                         ++num_ibs;
 186                         break;
 187
 188                 case AMDGPU_CHUNK_ID_FENCE:
 189                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 190                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 191                                 ret = -EINVAL;
 192                                 goto free_partial_kdata;
 193                         }
 194
 195                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 196                                                          &uf_offset);
 197                         if (ret)
 198                                 goto free_partial_kdata;
 199
 200                         break;
 201
 202                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 203                         size = sizeof(struct drm_amdgpu_bo_list_in);
 204                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 205                                 ret = -EINVAL;
 206                                 goto free_partial_kdata;
 207                         }
 208
 209                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 210                         if (ret)
 211                                 goto free_partial_kdata;
 212
 213                         break;
 214
 215                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 216                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 218                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 219                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 221                         break;
 222
 223                 default:
 224                         ret = -EINVAL;
 225                         goto free_partial_kdata;
 226                 }
 227         }
 228
 229         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 230         if (ret)
 231                 goto free_all_kdata;
 232
 233         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 234                 ret = -ECANCELED;
 235                 goto free_all_kdata;
 236         }
 237
 238         if (p->uf_entry.tv.bo)
 239                 p->job->uf_addr = uf_offset;
 240         kvfree(chunk_array);
 241
 242         /* Use this opportunity to fill in task info for the vm */
 243         amdgpu_vm_set_task_info(vm);
 244
 245         return 0;
 246
 247 free_all_kdata:
 248         i = p->nchunks - 1;
 249 free_partial_kdata:
 250         for (; i >= 0; i--)
 251                 kvfree(p->chunks[i].kdata);
 252         kvfree(p->chunks);
 253         p->chunks = NULL;
 254         p->nchunks = 0;
 255 free_chunk:
 256         kvfree(chunk_array);
 257
 258         return ret;
 259 }
 260
 261 /* Convert microseconds to bytes. */
 262 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 263 {
 264         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 265                 return 0;
 266
 267         /* Since accum_us is incremented by a million per second, just
 268          * multiply it by the number of MB/s to get the number of bytes.
 269          */
 270         return us << adev->mm_stats.log2_max_MBps;
 271 }
 272
 273 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 274 {
 275         if (!adev->mm_stats.log2_max_MBps)
 276                 return 0;
 277
 278         return bytes >> adev->mm_stats.log2_max_MBps;
 279 }
 280
 281 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 282  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 283  * which means it can go over the threshold once. If that happens, the driver
 284  * will be in debt and no other buffer migrations can be done until that debt
 285  * is repaid.
 286  *
 287  * This approach allows moving a buffer of any size (it's important to allow
 288  * that).
 289  *
 290  * The currency is simply time in microseconds and it increases as the clock
 291  * ticks. The accumulated microseconds (us) are converted to bytes and
 292  * returned.
 293  */
 294 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 295                                               u64 *max_bytes,
 296                                               u64 *max_vis_bytes)
 297 {
 298         s64 time_us, increment_us;
 299         u64 free_vram, total_vram, used_vram;
 300         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 301          * throttling.
 302          *
 303          * It means that in order to get full max MBps, at least 5 IBs per
 304          * second must be submitted and not more than 200ms apart from each
 305          * other.
 306          */
 307         const s64 us_upper_bound = 200000;
 308
 309         if (!adev->mm_stats.log2_max_MBps) {
 310                 *max_bytes = 0;
 311                 *max_vis_bytes = 0;
 312                 return;
 313         }
 314
 315         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 316         used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 317         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 318
 319         spin_lock(&adev->mm_stats.lock);
 320
 321         /* Increase the amount of accumulated us. */
 322         time_us = ktime_to_us(ktime_get());
 323         increment_us = time_us - adev->mm_stats.last_update_us;
 324         adev->mm_stats.last_update_us = time_us;
 325         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 326                                       us_upper_bound);
 327
 328         /* This prevents the short period of low performance when the VRAM
 329          * usage is low and the driver is in debt or doesn't have enough
 330          * accumulated us to fill VRAM quickly.
 331          *
 332          * The situation can occur in these cases:
 333          * - a lot of VRAM is freed by userspace
 334          * - the presence of a big buffer causes a lot of evictions
 335          *   (solution: split buffers into smaller ones)
 336          *
 337          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 338          * accum_us to a positive number.
 339          */
 340         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 341                 s64 min_us;
 342
 343                 /* Be more aggressive on dGPUs. Try to fill a portion of free
 344                  * VRAM now.
 345                  */
 346                 if (!(adev->flags & AMD_IS_APU))
 347                         min_us = bytes_to_us(adev, free_vram / 4);
 348                 else
 349                         min_us = 0; /* Reset accum_us on APUs. */
 350
 351                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 352         }
 353
 354         /* This is set to 0 if the driver is in debt to disallow (optional)
 355          * buffer moves.
 356          */
 357         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 358
 359         /* Do the same for visible VRAM if half of it is free */
 360         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 361                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 362                 u64 used_vis_vram =
 363                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 364
 365                 if (used_vis_vram < total_vis_vram) {
 366                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 367                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 368                                                           increment_us, us_upper_bound);
 369
 370                         if (free_vis_vram >= total_vis_vram / 2)
 371                                 adev->mm_stats.accum_us_vis =
 372                                         max(bytes_to_us(adev, free_vis_vram / 2),
 373                                             adev->mm_stats.accum_us_vis);
 374                 }
 375
 376                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 377         } else {
 378                 *max_vis_bytes = 0;
 379         }
 380
 381         spin_unlock(&adev->mm_stats.lock);
 382 }
 383
 384 /* Report how many bytes have really been moved for the last command
 385  * submission. This can result in a debt that can stop buffer migrations
 386  * temporarily.
 387  */
 388 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 389                                   u64 num_vis_bytes)
 390 {
 391         spin_lock(&adev->mm_stats.lock);
 392         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 393         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 394         spin_unlock(&adev->mm_stats.lock);
 395 }
 396
 397 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 398 {
 399         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 400         struct amdgpu_cs_parser *p = param;
 401         struct ttm_operation_ctx ctx = {
 402                 .interruptible = true,
 403                 .no_wait_gpu = false,
 404                 .resv = bo->tbo.base.resv
 405         };
 406         uint32_t domain;
 407         int r;
 408
 409         if (bo->tbo.pin_count)
 410                 return 0;
 411
 412         /* Don't move this buffer if we have depleted our allowance
 413          * to move it. Don't move anything if the threshold is zero.
 414          */
 415         if (p->bytes_moved < p->bytes_moved_threshold &&
 416             (!bo->tbo.base.dma_buf ||
 417             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 418                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 419                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 420                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 421                          * visible VRAM if we've depleted our allowance to do
 422                          * that.
 423                          */
 424                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 425                                 domain = bo->preferred_domains;
 426                         else
 427                                 domain = bo->allowed_domains;
 428                 } else {
 429                         domain = bo->preferred_domains;
 430                 }
 431         } else {
 432                 domain = bo->allowed_domains;
 433         }
 434
 435 retry:
 436         amdgpu_bo_placement_from_domain(bo, domain);
 437         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 438
 439         p->bytes_moved += ctx.bytes_moved;
 440         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 441             amdgpu_bo_in_cpu_visible_vram(bo))
 442                 p->bytes_moved_vis += ctx.bytes_moved;
 443
 444         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 445                 domain = bo->allowed_domains;
 446                 goto retry;
 447         }
 448
 449         return r;
 450 }
 451
 452 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 453                             struct list_head *validated)
 454 {
 455         struct ttm_operation_ctx ctx = { true, false };
 456         struct amdgpu_bo_list_entry *lobj;
 457         int r;
 458
 459         list_for_each_entry(lobj, validated, tv.head) {
 460                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 461                 struct mm_struct *usermm;
 462
 463                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 464                 if (usermm && usermm != current->mm)
 465                         return -EPERM;
 466
 467                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 468                     lobj->user_invalidated && lobj->user_pages) {
 469                         amdgpu_bo_placement_from_domain(bo,
 470                                                         AMDGPU_GEM_DOMAIN_CPU);
 471                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 472                         if (r)
 473                                 return r;
 474
 475                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 476                                                      lobj->user_pages);
 477                 }
 478
 479                 r = amdgpu_cs_bo_validate(p, bo);
 480                 if (r)
 481                         return r;
 482
 483                 kvfree(lobj->user_pages);
 484                 lobj->user_pages = NULL;
 485         }
 486         return 0;
 487 }
 488
 489 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 490                                 union drm_amdgpu_cs *cs)
 491 {
 492         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 493         struct amdgpu_vm *vm = &fpriv->vm;
 494         struct amdgpu_bo_list_entry *e;
 495         struct list_head duplicates;
 496         struct amdgpu_bo *gds;
 497         struct amdgpu_bo *gws;
 498         struct amdgpu_bo *oa;
 499         int r;
 500
 501         INIT_LIST_HEAD(&p->validated);
 502
 503         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 504         if (cs->in.bo_list_handle) {
 505                 if (p->bo_list)
 506                         return -EINVAL;
 507
 508                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 509                                        &p->bo_list);
 510                 if (r)
 511                         return r;
 512         } else if (!p->bo_list) {
 513                 /* Create a empty bo_list when no handle is provided */
 514                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 515                                           &p->bo_list);
 516                 if (r)
 517                         return r;
 518         }
 519
 520         /* One for TTM and one for the CS job */
 521         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 522                 e->tv.num_shared = 2;
 523
 524         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 525
 526         INIT_LIST_HEAD(&duplicates);
 527         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 528
 529         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 530                 list_add(&p->uf_entry.tv.head, &p->validated);
 531
 532         /* Get userptr backing pages. If pages are updated after registered
 533          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 534          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 535          */
 536         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 537                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 538                 bool userpage_invalidated = false;
 539                 int i;
 540
 541                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 542                                         sizeof(struct page *),
 543                                         GFP_KERNEL | __GFP_ZERO);
 544                 if (!e->user_pages) {
 545                         DRM_ERROR("kvmalloc_array failure\n");
 546                         return -ENOMEM;
 547                 }
 548
 549                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 550                 if (r) {
 551                         kvfree(e->user_pages);
 552                         e->user_pages = NULL;
 553                         return r;
 554                 }
 555
 556                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 557                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 558                                 userpage_invalidated = true;
 559                                 break;
 560                         }
 561                 }
 562                 e->user_invalidated = userpage_invalidated;
 563         }
 564
 565         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 566                                    &duplicates);
 567         if (unlikely(r != 0)) {
 568                 if (r != -ERESTARTSYS)
 569                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 570                 goto out;
 571         }
 572
 573         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 574                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 575
 576                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 577
 578                 if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
 579                         e->chain = dma_fence_chain_alloc();
 580                         if (!e->chain) {
 581                                 r = -ENOMEM;
 582                                 goto error_validate;
 583                         }
 584                 }
 585         }
 586
 587         /* Move fence waiting after getting reservation lock of
 588          * PD root. Then there is no need on a ctx mutex lock.
 589          */
 590         r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);
 591         if (unlikely(r != 0)) {
 592                 if (r != -ERESTARTSYS)
 593                         DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
 594                 goto error_validate;
 595         }
 596
 597         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 598                                           &p->bytes_moved_vis_threshold);
 599         p->bytes_moved = 0;
 600         p->bytes_moved_vis = 0;
 601
 602         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 603                                       amdgpu_cs_bo_validate, p);
 604         if (r) {
 605                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 606                 goto error_validate;
 607         }
 608
 609         r = amdgpu_cs_list_validate(p, &duplicates);
 610         if (r)
 611                 goto error_validate;
 612
 613         r = amdgpu_cs_list_validate(p, &p->validated);
 614         if (r)
 615                 goto error_validate;
 616
 617         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 618                                      p->bytes_moved_vis);
 619
 620         gds = p->bo_list->gds_obj;
 621         gws = p->bo_list->gws_obj;
 622         oa = p->bo_list->oa_obj;
 623
 624         if (gds) {
 625                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 626                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 627         }
 628         if (gws) {
 629                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 630                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 631         }
 632         if (oa) {
 633                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 634                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 635         }
 636
 637         if (!r && p->uf_entry.tv.bo) {
 638                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 639
 640                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 641                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 642         }
 643
 644 error_validate:
 645         if (r) {
 646                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 647                         dma_fence_chain_free(e->chain);
 648                         e->chain = NULL;
 649                 }
 650                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 651         }
 652 out:
 653         return r;
 654 }
 655
 656 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 657 {
 658         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 659         struct amdgpu_bo_list_entry *e;
 660         int r;
 661
 662         list_for_each_entry(e, &p->validated, tv.head) {
 663                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 664                 struct dma_resv *resv = bo->tbo.base.resv;
 665                 enum amdgpu_sync_mode sync_mode;
 666
 667                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
 668                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
 669                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
 670                                      &fpriv->vm);
 671                 if (r)
 672                         return r;
 673         }
 674         return 0;
 675 }
 676
 677 /**
 678  * amdgpu_cs_parser_fini() - clean parser states
 679  * @parser:     parser structure holding parsing context.
 680  * @error:      error number
 681  * @backoff:    indicator to backoff the reservation
 682  *
 683  * If error is set then unvalidate buffer, otherwise just free memory
 684  * used by parsing context.
 685  **/
 686 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 687                                   bool backoff)
 688 {
 689         unsigned i;
 690
 691         if (error && backoff) {
 692                 struct amdgpu_bo_list_entry *e;
 693
 694                 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
 695                         dma_fence_chain_free(e->chain);
 696                         e->chain = NULL;
 697                 }
 698
 699                 ttm_eu_backoff_reservation(&parser->ticket,
 700                                            &parser->validated);
 701         }
 702
 703         for (i = 0; i < parser->num_post_deps; i++) {
 704                 drm_syncobj_put(parser->post_deps[i].syncobj);
 705                 kfree(parser->post_deps[i].chain);
 706         }
 707         kfree(parser->post_deps);
 708
 709         dma_fence_put(parser->fence);
 710
 711         if (parser->ctx) {
 712                 amdgpu_ctx_put(parser->ctx);
 713         }
 714         if (parser->bo_list)
 715                 amdgpu_bo_list_put(parser->bo_list);
 716
 717         for (i = 0; i < parser->nchunks; i++)
 718                 kvfree(parser->chunks[i].kdata);
 719         kvfree(parser->chunks);
 720         if (parser->job)
 721                 amdgpu_job_free(parser->job);
 722         if (parser->uf_entry.tv.bo) {
 723                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 724
 725                 amdgpu_bo_unref(&uf);
 726         }
 727 }
 728
 729 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 730 {
 731         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 732         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 733         struct amdgpu_device *adev = p->adev;
 734         struct amdgpu_vm *vm = &fpriv->vm;
 735         struct amdgpu_bo_list_entry *e;
 736         struct amdgpu_bo_va *bo_va;
 737         struct amdgpu_bo *bo;
 738         int r;
 739
 740         /* Only for UVD/VCE VM emulation */
 741         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 742                 unsigned i, j;
 743
 744                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 745                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 746                         struct amdgpu_bo_va_mapping *m;
 747                         struct amdgpu_bo *aobj = NULL;
 748                         struct amdgpu_cs_chunk *chunk;
 749                         uint64_t offset, va_start;
 750                         struct amdgpu_ib *ib;
 751                         uint8_t *kptr;
 752
 753                         chunk = &p->chunks[i];
 754                         ib = &p->job->ibs[j];
 755                         chunk_ib = chunk->kdata;
 756
 757                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 758                                 continue;
 759
 760                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 761                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 762                         if (r) {
 763                                 DRM_ERROR("IB va_start is invalid\n");
 764                                 return r;
 765                         }
 766
 767                         if ((va_start + chunk_ib->ib_bytes) >
 768                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 769                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 770                                 return -EINVAL;
 771                         }
 772
 773                         /* the IB should be reserved at this point */
 774                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 775                         if (r) {
 776                                 return r;
 777                         }
 778
 779                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 780                         kptr += va_start - offset;
 781
 782                         if (ring->funcs->parse_cs) {
 783                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 784                                 amdgpu_bo_kunmap(aobj);
 785
 786                                 r = amdgpu_ring_parse_cs(ring, p, p->job, ib);
 787                                 if (r)
 788                                         return r;
 789                         } else {
 790                                 ib->ptr = (uint32_t *)kptr;
 791                                 r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);
 792                                 amdgpu_bo_kunmap(aobj);
 793                                 if (r)
 794                                         return r;
 795                         }
 796
 797                         j++;
 798                 }
 799         }
 800
 801         if (!p->job->vm)
 802                 return amdgpu_cs_sync_rings(p);
 803
 804
 805         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 806         if (r)
 807                 return r;
 808
 809         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
 810         if (r)
 811                 return r;
 812
 813         r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
 814         if (r)
 815                 return r;
 816
 817         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 818                 bo_va = fpriv->csa_va;
 819                 BUG_ON(!bo_va);
 820                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 821                 if (r)
 822                         return r;
 823
 824                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 825                 if (r)
 826                         return r;
 827         }
 828
 829         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 830                 /* ignore duplicates */
 831                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 832                 if (!bo)
 833                         continue;
 834
 835                 bo_va = e->bo_va;
 836                 if (bo_va == NULL)
 837                         continue;
 838
 839                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 840                 if (r)
 841                         return r;
 842
 843                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 844                 if (r)
 845                         return r;
 846         }
 847
 848         r = amdgpu_vm_handle_moved(adev, vm);
 849         if (r)
 850                 return r;
 851
 852         r = amdgpu_vm_update_pdes(adev, vm, false);
 853         if (r)
 854                 return r;
 855
 856         r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
 857         if (r)
 858                 return r;
 859
 860         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 861
 862         if (amdgpu_vm_debug) {
 863                 /* Invalidate all BOs to test for userspace bugs */
 864                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 865                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 866
 867                         /* ignore duplicates */
 868                         if (!bo)
 869                                 continue;
 870
 871                         amdgpu_vm_bo_invalidate(adev, bo, false);
 872                 }
 873         }
 874
 875         return amdgpu_cs_sync_rings(p);
 876 }
 877
 878 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 879                              struct amdgpu_cs_parser *parser)
 880 {
 881         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 882         struct amdgpu_vm *vm = &fpriv->vm;
 883         int r, ce_preempt = 0, de_preempt = 0;
 884         struct amdgpu_ring *ring;
 885         int i, j;
 886
 887         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 888                 struct amdgpu_cs_chunk *chunk;
 889                 struct amdgpu_ib *ib;
 890                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 891                 struct drm_sched_entity *entity;
 892
 893                 chunk = &parser->chunks[i];
 894                 ib = &parser->job->ibs[j];
 895                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 896
 897                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 898                         continue;
 899
 900                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 901                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 902                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 903                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 904                                         ce_preempt++;
 905                                 else
 906                                         de_preempt++;
 907                         }
 908
 909                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 910                         if (ce_preempt > 1 || de_preempt > 1)
 911                                 return -EINVAL;
 912                 }
 913
 914                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 915                                           chunk_ib->ip_instance, chunk_ib->ring,
 916                                           &entity);
 917                 if (r)
 918                         return r;
 919
 920                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 921                         parser->job->preamble_status |=
 922                                 AMDGPU_PREAMBLE_IB_PRESENT;
 923
 924                 if (parser->entity && parser->entity != entity)
 925                         return -EINVAL;
 926
 927                 /* Return if there is no run queue associated with this entity.
 928                  * Possibly because of disabled HW IP*/
 929                 if (entity->rq == NULL)
 930                         return -EINVAL;
 931
 932                 parser->entity = entity;
 933
 934                 ring = to_amdgpu_ring(entity->rq->sched);
 935                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 936                                    chunk_ib->ib_bytes : 0,
 937                                    AMDGPU_IB_POOL_DELAYED, ib);
 938                 if (r) {
 939                         DRM_ERROR("Failed to get ib !\n");
 940                         return r;
 941                 }
 942
 943                 ib->gpu_addr = chunk_ib->va_start;
 944                 ib->length_dw = chunk_ib->ib_bytes / 4;
 945                 ib->flags = chunk_ib->flags;
 946
 947                 j++;
 948         }
 949
 950         /* MM engine doesn't support user fences */
 951         ring = to_amdgpu_ring(parser->entity->rq->sched);
 952         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 953                 return -EINVAL;
 954
 955         return 0;
 956 }
 957
 958 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 959                                        struct amdgpu_cs_chunk *chunk)
 960 {
 961         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 962         unsigned num_deps;
 963         int i, r;
 964         struct drm_amdgpu_cs_chunk_dep *deps;
 965
 966         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 967         num_deps = chunk->length_dw * 4 /
 968                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 969
 970         for (i = 0; i < num_deps; ++i) {
 971                 struct amdgpu_ctx *ctx;
 972                 struct drm_sched_entity *entity;
 973                 struct dma_fence *fence;
 974
 975                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 976                 if (ctx == NULL)
 977                         return -EINVAL;
 978
 979                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 980                                           deps[i].ip_instance,
 981                                           deps[i].ring, &entity);
 982                 if (r) {
 983                         amdgpu_ctx_put(ctx);
 984                         return r;
 985                 }
 986
 987                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 988                 amdgpu_ctx_put(ctx);
 989
 990                 if (IS_ERR(fence))
 991                         return PTR_ERR(fence);
 992                 else if (!fence)
 993                         continue;
 994
 995                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 996                         struct drm_sched_fence *s_fence;
 997                         struct dma_fence *old = fence;
 998
 999                         s_fence = to_drm_sched_fence(fence);
1000                         fence = dma_fence_get(&s_fence->scheduled);
1001                         dma_fence_put(old);
1002                 }
1003
1004                 r = amdgpu_sync_fence(&p->job->sync, fence);
1005                 dma_fence_put(fence);
1006                 if (r)
1007                         return r;
1008         }
1009         return 0;
1010 }
1011
1012 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1013                                                  uint32_t handle, u64 point,
1014                                                  u64 flags)
1015 {
1016         struct dma_fence *fence;
1017         int r;
1018
1019         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1020         if (r) {
1021                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1022                           handle, point, r);
1023                 return r;
1024         }
1025
1026         r = amdgpu_sync_fence(&p->job->sync, fence);
1027         dma_fence_put(fence);
1028
1029         return r;
1030 }
1031
1032 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1033                                             struct amdgpu_cs_chunk *chunk)
1034 {
1035         struct drm_amdgpu_cs_chunk_sem *deps;
1036         unsigned num_deps;
1037         int i, r;
1038
1039         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1040         num_deps = chunk->length_dw * 4 /
1041                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1042         for (i = 0; i < num_deps; ++i) {
1043                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1044                                                           0, 0);
1045                 if (r)
1046                         return r;
1047         }
1048
1049         return 0;
1050 }
1051
1052
1053 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1054                                                      struct amdgpu_cs_chunk *chunk)
1055 {
1056         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1057         unsigned num_deps;
1058         int i, r;
1059
1060         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1061         num_deps = chunk->length_dw * 4 /
1062                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1063         for (i = 0; i < num_deps; ++i) {
1064                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1065                                                           syncobj_deps[i].handle,
1066                                                           syncobj_deps[i].point,
1067                                                           syncobj_deps[i].flags);
1068                 if (r)
1069                         return r;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1076                                              struct amdgpu_cs_chunk *chunk)
1077 {
1078         struct drm_amdgpu_cs_chunk_sem *deps;
1079         unsigned num_deps;
1080         int i;
1081
1082         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1083         num_deps = chunk->length_dw * 4 /
1084                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1085
1086         if (p->post_deps)
1087                 return -EINVAL;
1088
1089         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1090                                      GFP_KERNEL);
1091         p->num_post_deps = 0;
1092
1093         if (!p->post_deps)
1094                 return -ENOMEM;
1095
1096
1097         for (i = 0; i < num_deps; ++i) {
1098                 p->post_deps[i].syncobj =
1099                         drm_syncobj_find(p->filp, deps[i].handle);
1100                 if (!p->post_deps[i].syncobj)
1101                         return -EINVAL;
1102                 p->post_deps[i].chain = NULL;
1103                 p->post_deps[i].point = 0;
1104                 p->num_post_deps++;
1105         }
1106
1107         return 0;
1108 }
1109
1110
1111 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1112                                                       struct amdgpu_cs_chunk *chunk)
1113 {
1114         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1115         unsigned num_deps;
1116         int i;
1117
1118         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1119         num_deps = chunk->length_dw * 4 /
1120                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1121
1122         if (p->post_deps)
1123                 return -EINVAL;
1124
1125         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1126                                      GFP_KERNEL);
1127         p->num_post_deps = 0;
1128
1129         if (!p->post_deps)
1130                 return -ENOMEM;
1131
1132         for (i = 0; i < num_deps; ++i) {
1133                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1134
1135                 dep->chain = NULL;
1136                 if (syncobj_deps[i].point) {
1137                         dep->chain = dma_fence_chain_alloc();
1138                         if (!dep->chain)
1139                                 return -ENOMEM;
1140                 }
1141
1142                 dep->syncobj = drm_syncobj_find(p->filp,
1143                                                 syncobj_deps[i].handle);
1144                 if (!dep->syncobj) {
1145                         dma_fence_chain_free(dep->chain);
1146                         return -EINVAL;
1147                 }
1148                 dep->point = syncobj_deps[i].point;
1149                 p->num_post_deps++;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1156                                   struct amdgpu_cs_parser *p)
1157 {
1158         int i, r;
1159
1160         for (i = 0; i < p->nchunks; ++i) {
1161                 struct amdgpu_cs_chunk *chunk;
1162
1163                 chunk = &p->chunks[i];
1164
1165                 switch (chunk->chunk_id) {
1166                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1167                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1168                         r = amdgpu_cs_process_fence_dep(p, chunk);
1169                         if (r)
1170                                 return r;
1171                         break;
1172                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1173                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1174                         if (r)
1175                                 return r;
1176                         break;
1177                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1178                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1179                         if (r)
1180                                 return r;
1181                         break;
1182                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1183                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1184                         if (r)
1185                                 return r;
1186                         break;
1187                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1188                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1189                         if (r)
1190                                 return r;
1191                         break;
1192                 }
1193         }
1194
1195         return 0;
1196 }
1197
1198 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1199 {
1200         int i;
1201
1202         for (i = 0; i < p->num_post_deps; ++i) {
1203                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1204                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1205                                               p->post_deps[i].chain,
1206                                               p->fence, p->post_deps[i].point);
1207                         p->post_deps[i].chain = NULL;
1208                 } else {
1209                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1210                                                   p->fence);
1211                 }
1212         }
1213 }
1214
1215 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1216                             union drm_amdgpu_cs *cs)
1217 {
1218         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1219         struct drm_sched_entity *entity = p->entity;
1220         struct amdgpu_bo_list_entry *e;
1221         struct amdgpu_job *job;
1222         uint64_t seq;
1223         int r;
1224
1225         job = p->job;
1226         p->job = NULL;
1227
1228         r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1229         if (r)
1230                 goto error_unlock;
1231
1232         drm_sched_job_arm(&job->base);
1233
1234         /* No memory allocation is allowed while holding the notifier lock.
1235          * The lock is held until amdgpu_cs_submit is finished and fence is
1236          * added to BOs.
1237          */
1238         mutex_lock(&p->adev->notifier_lock);
1239
1240         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1241          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1242          */
1243         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1244                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1245
1246                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1247         }
1248         if (r) {
1249                 r = -EAGAIN;
1250                 goto error_abort;
1251         }
1252
1253         p->fence = dma_fence_get(&job->base.s_fence->finished);
1254
1255         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1256         amdgpu_cs_post_dependencies(p);
1257
1258         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1259             !p->ctx->preamble_presented) {
1260                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1261                 p->ctx->preamble_presented = true;
1262         }
1263
1264         cs->out.handle = seq;
1265         job->uf_sequence = seq;
1266
1267         amdgpu_job_free_resources(job);
1268
1269         trace_amdgpu_cs_ioctl(job);
1270         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1271         drm_sched_entity_push_job(&job->base);
1272
1273         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1274
1275         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1276                 struct dma_resv *resv = e->tv.bo->base.resv;
1277                 struct dma_fence_chain *chain = e->chain;
1278
1279                 if (!chain)
1280                         continue;
1281
1282                 /*
1283                  * Work around dma_resv shortcomings by wrapping up the
1284                  * submission in a dma_fence_chain and add it as exclusive
1285                  * fence.
1286                  */
1287                 dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
1288                                      dma_fence_get(p->fence), 1);
1289
1290                 rcu_assign_pointer(resv->fence_excl, &chain->base);
1291                 e->chain = NULL;
1292         }
1293
1294         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1295         mutex_unlock(&p->adev->notifier_lock);
1296
1297         return 0;
1298
1299 error_abort:
1300         drm_sched_job_cleanup(&job->base);
1301         mutex_unlock(&p->adev->notifier_lock);
1302
1303 error_unlock:
1304         amdgpu_job_free(job);
1305         return r;
1306 }
1307
1308 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1309 {
1310         int i;
1311
1312         if (!trace_amdgpu_cs_enabled())
1313                 return;
1314
1315         for (i = 0; i < parser->job->num_ibs; i++)
1316                 trace_amdgpu_cs(parser, i);
1317 }
1318
1319 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1320 {
1321         struct amdgpu_device *adev = drm_to_adev(dev);
1322         union drm_amdgpu_cs *cs = data;
1323         struct amdgpu_cs_parser parser = {};
1324         bool reserved_buffers = false;
1325         int r;
1326
1327         if (amdgpu_ras_intr_triggered())
1328                 return -EHWPOISON;
1329
1330         if (!adev->accel_working)
1331                 return -EBUSY;
1332
1333         parser.adev = adev;
1334         parser.filp = filp;
1335
1336         r = amdgpu_cs_parser_init(&parser, data);
1337         if (r) {
1338                 if (printk_ratelimit())
1339                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1340                 goto out;
1341         }
1342
1343         r = amdgpu_cs_ib_fill(adev, &parser);
1344         if (r)
1345                 goto out;
1346
1347         r = amdgpu_cs_dependencies(adev, &parser);
1348         if (r) {
1349                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1350                 goto out;
1351         }
1352
1353         r = amdgpu_cs_parser_bos(&parser, data);
1354         if (r) {
1355                 if (r == -ENOMEM)
1356                         DRM_ERROR("Not enough memory for command submission!\n");
1357                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1358                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1359                 goto out;
1360         }
1361
1362         reserved_buffers = true;
1363
1364         trace_amdgpu_cs_ibs(&parser);
1365
1366         r = amdgpu_cs_vm_handling(&parser);
1367         if (r)
1368                 goto out;
1369
1370         r = amdgpu_cs_submit(&parser, cs);
1371 out:
1372         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1373
1374         return r;
1375 }
1376
1377 /**
1378  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1379  *
1380  * @dev: drm device
1381  * @data: data from userspace
1382  * @filp: file private
1383  *
1384  * Wait for the command submission identified by handle to finish.
1385  */
1386 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1387                          struct drm_file *filp)
1388 {
1389         union drm_amdgpu_wait_cs *wait = data;
1390         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1391         struct drm_sched_entity *entity;
1392         struct amdgpu_ctx *ctx;
1393         struct dma_fence *fence;
1394         long r;
1395
1396         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1397         if (ctx == NULL)
1398                 return -EINVAL;
1399
1400         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1401                                   wait->in.ring, &entity);
1402         if (r) {
1403                 amdgpu_ctx_put(ctx);
1404                 return r;
1405         }
1406
1407         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1408         if (IS_ERR(fence))
1409                 r = PTR_ERR(fence);
1410         else if (fence) {
1411                 r = dma_fence_wait_timeout(fence, true, timeout);
1412                 if (r > 0 && fence->error)
1413                         r = fence->error;
1414                 dma_fence_put(fence);
1415         } else
1416                 r = 1;
1417
1418         amdgpu_ctx_put(ctx);
1419         if (r < 0)
1420                 return r;
1421
1422         memset(wait, 0, sizeof(*wait));
1423         wait->out.status = (r == 0);
1424
1425         return 0;
1426 }
1427
1428 /**
1429  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1430  *
1431  * @adev: amdgpu device
1432  * @filp: file private
1433  * @user: drm_amdgpu_fence copied from user space
1434  */
1435 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1436                                              struct drm_file *filp,
1437                                              struct drm_amdgpu_fence *user)
1438 {
1439         struct drm_sched_entity *entity;
1440         struct amdgpu_ctx *ctx;
1441         struct dma_fence *fence;
1442         int r;
1443
1444         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1445         if (ctx == NULL)
1446                 return ERR_PTR(-EINVAL);
1447
1448         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1449                                   user->ring, &entity);
1450         if (r) {
1451                 amdgpu_ctx_put(ctx);
1452                 return ERR_PTR(r);
1453         }
1454
1455         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1456         amdgpu_ctx_put(ctx);
1457
1458         return fence;
1459 }
1460
1461 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1462                                     struct drm_file *filp)
1463 {
1464         struct amdgpu_device *adev = drm_to_adev(dev);
1465         union drm_amdgpu_fence_to_handle *info = data;
1466         struct dma_fence *fence;
1467         struct drm_syncobj *syncobj;
1468         struct sync_file *sync_file;
1469         int fd, r;
1470
1471         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1472         if (IS_ERR(fence))
1473                 return PTR_ERR(fence);
1474
1475         if (!fence)
1476                 fence = dma_fence_get_stub();
1477
1478         switch (info->in.what) {
1479         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1480                 r = drm_syncobj_create(&syncobj, 0, fence);
1481                 dma_fence_put(fence);
1482                 if (r)
1483                         return r;
1484                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1485                 drm_syncobj_put(syncobj);
1486                 return r;
1487
1488         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1489                 r = drm_syncobj_create(&syncobj, 0, fence);
1490                 dma_fence_put(fence);
1491                 if (r)
1492                         return r;
1493                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1494                 drm_syncobj_put(syncobj);
1495                 return r;
1496
1497         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1498                 fd = get_unused_fd_flags(O_CLOEXEC);
1499                 if (fd < 0) {
1500                         dma_fence_put(fence);
1501                         return fd;
1502                 }
1503
1504                 sync_file = sync_file_create(fence);
1505                 dma_fence_put(fence);
1506                 if (!sync_file) {
1507                         put_unused_fd(fd);
1508                         return -ENOMEM;
1509                 }
1510
1511                 fd_install(fd, sync_file->file);
1512                 info->out.handle = fd;
1513                 return 0;
1514
1515         default:
1516                 dma_fence_put(fence);
1517                 return -EINVAL;
1518         }
1519 }
1520
1521 /**
1522  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1523  *
1524  * @adev: amdgpu device
1525  * @filp: file private
1526  * @wait: wait parameters
1527  * @fences: array of drm_amdgpu_fence
1528  */
1529 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1530                                      struct drm_file *filp,
1531                                      union drm_amdgpu_wait_fences *wait,
1532                                      struct drm_amdgpu_fence *fences)
1533 {
1534         uint32_t fence_count = wait->in.fence_count;
1535         unsigned int i;
1536         long r = 1;
1537
1538         for (i = 0; i < fence_count; i++) {
1539                 struct dma_fence *fence;
1540                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1541
1542                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1543                 if (IS_ERR(fence))
1544                         return PTR_ERR(fence);
1545                 else if (!fence)
1546                         continue;
1547
1548                 r = dma_fence_wait_timeout(fence, true, timeout);
1549                 dma_fence_put(fence);
1550                 if (r < 0)
1551                         return r;
1552
1553                 if (r == 0)
1554                         break;
1555
1556                 if (fence->error)
1557                         return fence->error;
1558         }
1559
1560         memset(wait, 0, sizeof(*wait));
1561         wait->out.status = (r > 0);
1562
1563         return 0;
1564 }
1565
1566 /**
1567  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1568  *
1569  * @adev: amdgpu device
1570  * @filp: file private
1571  * @wait: wait parameters
1572  * @fences: array of drm_amdgpu_fence
1573  */
1574 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1575                                     struct drm_file *filp,
1576                                     union drm_amdgpu_wait_fences *wait,
1577                                     struct drm_amdgpu_fence *fences)
1578 {
1579         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1580         uint32_t fence_count = wait->in.fence_count;
1581         uint32_t first = ~0;
1582         struct dma_fence **array;
1583         unsigned int i;
1584         long r;
1585
1586         /* Prepare the fence array */
1587         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1588
1589         if (array == NULL)
1590                 return -ENOMEM;
1591
1592         for (i = 0; i < fence_count; i++) {
1593                 struct dma_fence *fence;
1594
1595                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1596                 if (IS_ERR(fence)) {
1597                         r = PTR_ERR(fence);
1598                         goto err_free_fence_array;
1599                 } else if (fence) {
1600                         array[i] = fence;
1601                 } else { /* NULL, the fence has been already signaled */
1602                         r = 1;
1603                         first = i;
1604                         goto out;
1605                 }
1606         }
1607
1608         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1609                                        &first);
1610         if (r < 0)
1611                 goto err_free_fence_array;
1612
1613 out:
1614         memset(wait, 0, sizeof(*wait));
1615         wait->out.status = (r > 0);
1616         wait->out.first_signaled = first;
1617
1618         if (first < fence_count && array[first])
1619                 r = array[first]->error;
1620         else
1621                 r = 0;
1622
1623 err_free_fence_array:
1624         for (i = 0; i < fence_count; i++)
1625                 dma_fence_put(array[i]);
1626         kfree(array);
1627
1628         return r;
1629 }
1630
1631 /**
1632  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1633  *
1634  * @dev: drm device
1635  * @data: data from userspace
1636  * @filp: file private
1637  */
1638 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1639                                 struct drm_file *filp)
1640 {
1641         struct amdgpu_device *adev = drm_to_adev(dev);
1642         union drm_amdgpu_wait_fences *wait = data;
1643         uint32_t fence_count = wait->in.fence_count;
1644         struct drm_amdgpu_fence *fences_user;
1645         struct drm_amdgpu_fence *fences;
1646         int r;
1647
1648         /* Get the fences from userspace */
1649         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1650                         GFP_KERNEL);
1651         if (fences == NULL)
1652                 return -ENOMEM;
1653
1654         fences_user = u64_to_user_ptr(wait->in.fences);
1655         if (copy_from_user(fences, fences_user,
1656                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1657                 r = -EFAULT;
1658                 goto err_free_fences;
1659         }
1660
1661         if (wait->in.wait_all)
1662                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1663         else
1664                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1665
1666 err_free_fences:
1667         kfree(fences);
1668
1669         return r;
1670 }
1671
1672 /**
1673  * amdgpu_cs_find_mapping - find bo_va for VM address
1674  *
1675  * @parser: command submission parser context
1676  * @addr: VM address
1677  * @bo: resulting BO of the mapping found
1678  * @map: Placeholder to return found BO mapping
1679  *
1680  * Search the buffer objects in the command submission context for a certain
1681  * virtual memory address. Returns allocation structure when found, NULL
1682  * otherwise.
1683  */
1684 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1685                            uint64_t addr, struct amdgpu_bo **bo,
1686                            struct amdgpu_bo_va_mapping **map)
1687 {
1688         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1689         struct ttm_operation_ctx ctx = { false, false };
1690         struct amdgpu_vm *vm = &fpriv->vm;
1691         struct amdgpu_bo_va_mapping *mapping;
1692         int r;
1693
1694         addr /= AMDGPU_GPU_PAGE_SIZE;
1695
1696         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1697         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1698                 return -EINVAL;
1699
1700         *bo = mapping->bo_va->base.bo;
1701         *map = mapping;
1702
1703         /* Double check that the BO is reserved by this CS */
1704         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1705                 return -EINVAL;
1706
1707         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1708                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1709                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1710                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1711                 if (r)
1712                         return r;
1713         }
1714
1715         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1716 }