drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include "hwmgr.h"
  41 #define WIDTH_4K 3840
  42
  43 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  44
  45 static const struct cg_flag_name clocks[] = {
  46         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  51         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  57         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  59         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  62         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  65         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  68         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  70
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  86 {
  87         if (adev->pm.dpm_enabled) {
  88                 mutex_lock(&adev->pm.mutex);
  89                 if (power_supply_is_system_supplied() > 0)
  90                         adev->pm.ac_power = true;
  91                 else
  92                         adev->pm.ac_power = false;
  93                 if (adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96         }
  97 }
  98
  99 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 100                            void *data, uint32_t *size)
 101 {
 102         int ret = 0;
 103
 104         if (!data || !size)
 105                 return -EINVAL;
 106
 107         if (is_support_sw_smu(adev))
 108                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 109         else {
 110                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 111                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 112                                                                     sensor, data, size);
 113                 else
 114                         ret = -EINVAL;
 115         }
 116
 117         return ret;
 118 }
 119
 120 /**
 121  * DOC: power_dpm_state
 122  *
 123  * The power_dpm_state file is a legacy interface and is only provided for
 124  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 125  * certain power related parameters.  The file power_dpm_state is used for this.
 126  * It accepts the following arguments:
 127  *
 128  * - battery
 129  *
 130  * - balanced
 131  *
 132  * - performance
 133  *
 134  * battery
 135  *
 136  * On older GPUs, the vbios provided a special power state for battery
 137  * operation.  Selecting battery switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  * balanced
 141  *
 142  * On older GPUs, the vbios provided a special power state for balanced
 143  * operation.  Selecting balanced switched to this state.  This is no
 144  * longer provided on newer GPUs so the option does nothing in that case.
 145  *
 146  * performance
 147  *
 148  * On older GPUs, the vbios provided a special power state for performance
 149  * operation.  Selecting performance switched to this state.  This is no
 150  * longer provided on newer GPUs so the option does nothing in that case.
 151  *
 152  */
 153
 154 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 155                                     struct device_attribute *attr,
 156                                     char *buf)
 157 {
 158         struct drm_device *ddev = dev_get_drvdata(dev);
 159         struct amdgpu_device *adev = ddev->dev_private;
 160         enum amd_pm_state_type pm;
 161
 162         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 163                 pm = amdgpu_smu_get_current_power_state(adev);
 164         else if (adev->powerplay.pp_funcs->get_current_power_state)
 165                 pm = amdgpu_dpm_get_current_power_state(adev);
 166         else
 167                 pm = adev->pm.dpm.user_state;
 168
 169         return snprintf(buf, PAGE_SIZE, "%s\n",
 170                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 171                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 172 }
 173
 174 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 175                                     struct device_attribute *attr,
 176                                     const char *buf,
 177                                     size_t count)
 178 {
 179         struct drm_device *ddev = dev_get_drvdata(dev);
 180         struct amdgpu_device *adev = ddev->dev_private;
 181         enum amd_pm_state_type  state;
 182
 183         if (strncmp("battery", buf, strlen("battery")) == 0)
 184                 state = POWER_STATE_TYPE_BATTERY;
 185         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 186                 state = POWER_STATE_TYPE_BALANCED;
 187         else if (strncmp("performance", buf, strlen("performance")) == 0)
 188                 state = POWER_STATE_TYPE_PERFORMANCE;
 189         else {
 190                 count = -EINVAL;
 191                 goto fail;
 192         }
 193
 194         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 195                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 196         } else {
 197                 mutex_lock(&adev->pm.mutex);
 198                 adev->pm.dpm.user_state = state;
 199                 mutex_unlock(&adev->pm.mutex);
 200
 201                 /* Can't set dpm state when the card is off */
 202                 if (!(adev->flags & AMD_IS_PX) ||
 203                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 204                         amdgpu_pm_compute_clocks(adev);
 205         }
 206 fail:
 207         return count;
 208 }
 209
 210
 211 /**
 212  * DOC: power_dpm_force_performance_level
 213  *
 214  * The amdgpu driver provides a sysfs API for adjusting certain power
 215  * related parameters.  The file power_dpm_force_performance_level is
 216  * used for this.  It accepts the following arguments:
 217  *
 218  * - auto
 219  *
 220  * - low
 221  *
 222  * - high
 223  *
 224  * - manual
 225  *
 226  * - profile_standard
 227  *
 228  * - profile_min_sclk
 229  *
 230  * - profile_min_mclk
 231  *
 232  * - profile_peak
 233  *
 234  * auto
 235  *
 236  * When auto is selected, the driver will attempt to dynamically select
 237  * the optimal power profile for current conditions in the driver.
 238  *
 239  * low
 240  *
 241  * When low is selected, the clocks are forced to the lowest power state.
 242  *
 243  * high
 244  *
 245  * When high is selected, the clocks are forced to the highest power state.
 246  *
 247  * manual
 248  *
 249  * When manual is selected, the user can manually adjust which power states
 250  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 251  * and pp_dpm_pcie files and adjust the power state transition heuristics
 252  * via the pp_power_profile_mode sysfs file.
 253  *
 254  * profile_standard
 255  * profile_min_sclk
 256  * profile_min_mclk
 257  * profile_peak
 258  *
 259  * When the profiling modes are selected, clock and power gating are
 260  * disabled and the clocks are set for different profiling cases. This
 261  * mode is recommended for profiling specific work loads where you do
 262  * not want clock or power gating for clock fluctuation to interfere
 263  * with your results. profile_standard sets the clocks to a fixed clock
 264  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 265  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 266  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 267  *
 268  */
 269
 270 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 271                                                 struct device_attribute *attr,
 272                                                                 char *buf)
 273 {
 274         struct drm_device *ddev = dev_get_drvdata(dev);
 275         struct amdgpu_device *adev = ddev->dev_private;
 276         enum amd_dpm_forced_level level = 0xff;
 277
 278         if (amdgpu_sriov_vf(adev))
 279                 return 0;
 280
 281         if ((adev->flags & AMD_IS_PX) &&
 282             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 283                 return snprintf(buf, PAGE_SIZE, "off\n");
 284
 285         if (is_support_sw_smu(adev))
 286                 level = smu_get_performance_level(&adev->smu);
 287         else if (adev->powerplay.pp_funcs->get_performance_level)
 288                 level = amdgpu_dpm_get_performance_level(adev);
 289         else
 290                 level = adev->pm.dpm.forced_level;
 291
 292         return snprintf(buf, PAGE_SIZE, "%s\n",
 293                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 294                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 295                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 296                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 297                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 298                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 299                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 300                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 301                         "unknown");
 302 }
 303
 304 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 305                                                        struct device_attribute *attr,
 306                                                        const char *buf,
 307                                                        size_t count)
 308 {
 309         struct drm_device *ddev = dev_get_drvdata(dev);
 310         struct amdgpu_device *adev = ddev->dev_private;
 311         enum amd_dpm_forced_level level;
 312         enum amd_dpm_forced_level current_level = 0xff;
 313         int ret = 0;
 314
 315         /* Can't force performance level when the card is off */
 316         if  ((adev->flags & AMD_IS_PX) &&
 317              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 318                 return -EINVAL;
 319
 320         if (!amdgpu_sriov_vf(adev)) {
 321                 if (is_support_sw_smu(adev))
 322                         current_level = smu_get_performance_level(&adev->smu);
 323                 else if (adev->powerplay.pp_funcs->get_performance_level)
 324                         current_level = amdgpu_dpm_get_performance_level(adev);
 325         }
 326
 327         if (strncmp("low", buf, strlen("low")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_LOW;
 329         } else if (strncmp("high", buf, strlen("high")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 331         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 333         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 335         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 337         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 339         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 340                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 341         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 342                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 343         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 344                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 345         }  else {
 346                 count = -EINVAL;
 347                 goto fail;
 348         }
 349
 350         if (amdgpu_sriov_vf(adev)) {
 351                 if (amdgim_is_hwperf(adev) &&
 352                     adev->virt.ops->force_dpm_level) {
 353                         mutex_lock(&adev->pm.mutex);
 354                         adev->virt.ops->force_dpm_level(adev, level);
 355                         mutex_unlock(&adev->pm.mutex);
 356                         return count;
 357                 } else {
 358                         return -EINVAL;
 359                 }
 360         }
 361
 362         if (current_level == level)
 363                 return count;
 364
 365         /* profile_exit setting is valid only when current mode is in profile mode */
 366         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 367             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 368             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 369             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 370             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 371                 pr_err("Currently not in any profile mode!\n");
 372                 return -EINVAL;
 373         }
 374
 375         if (is_support_sw_smu(adev)) {
 376                 ret = smu_force_performance_level(&adev->smu, level);
 377                 if (ret)
 378                         count = -EINVAL;
 379         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 380                 mutex_lock(&adev->pm.mutex);
 381                 if (adev->pm.dpm.thermal_active) {
 382                         count = -EINVAL;
 383                         mutex_unlock(&adev->pm.mutex);
 384                         goto fail;
 385                 }
 386                 ret = amdgpu_dpm_force_performance_level(adev, level);
 387                 if (ret)
 388                         count = -EINVAL;
 389                 else
 390                         adev->pm.dpm.forced_level = level;
 391                 mutex_unlock(&adev->pm.mutex);
 392         }
 393
 394 fail:
 395         return count;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = ddev->dev_private;
 404         struct pp_states_info data;
 405         int i, buf_len, ret;
 406
 407         if (is_support_sw_smu(adev)) {
 408                 ret = smu_get_power_num_states(&adev->smu, &data);
 409                 if (ret)
 410                         return ret;
 411         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 412                 amdgpu_dpm_get_pp_num_states(adev, &data);
 413
 414         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 415         for (i = 0; i < data.nums; i++)
 416                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 417                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 418                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 419                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 420                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 421
 422         return buf_len;
 423 }
 424
 425 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 426                 struct device_attribute *attr,
 427                 char *buf)
 428 {
 429         struct drm_device *ddev = dev_get_drvdata(dev);
 430         struct amdgpu_device *adev = ddev->dev_private;
 431         struct pp_states_info data;
 432         struct smu_context *smu = &adev->smu;
 433         enum amd_pm_state_type pm = 0;
 434         int i = 0, ret = 0;
 435
 436         if (is_support_sw_smu(adev)) {
 437                 pm = smu_get_current_power_state(smu);
 438                 ret = smu_get_power_num_states(smu, &data);
 439                 if (ret)
 440                         return ret;
 441         } else if (adev->powerplay.pp_funcs->get_current_power_state
 442                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 443                 pm = amdgpu_dpm_get_current_power_state(adev);
 444                 amdgpu_dpm_get_pp_num_states(adev, &data);
 445         }
 446
 447         for (i = 0; i < data.nums; i++) {
 448                 if (pm == data.states[i])
 449                         break;
 450         }
 451
 452         if (i == data.nums)
 453                 i = -EINVAL;
 454
 455         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 456 }
 457
 458 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 char *buf)
 461 {
 462         struct drm_device *ddev = dev_get_drvdata(dev);
 463         struct amdgpu_device *adev = ddev->dev_private;
 464
 465         if (adev->pp_force_state_enabled)
 466                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 467         else
 468                 return snprintf(buf, PAGE_SIZE, "\n");
 469 }
 470
 471 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 472                 struct device_attribute *attr,
 473                 const char *buf,
 474                 size_t count)
 475 {
 476         struct drm_device *ddev = dev_get_drvdata(dev);
 477         struct amdgpu_device *adev = ddev->dev_private;
 478         enum amd_pm_state_type state = 0;
 479         unsigned long idx;
 480         int ret;
 481
 482         if (strlen(buf) == 1)
 483                 adev->pp_force_state_enabled = false;
 484         else if (is_support_sw_smu(adev))
 485                 adev->pp_force_state_enabled = false;
 486         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 487                         adev->powerplay.pp_funcs->get_pp_num_states) {
 488                 struct pp_states_info data;
 489
 490                 ret = kstrtoul(buf, 0, &idx);
 491                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 492                         count = -EINVAL;
 493                         goto fail;
 494                 }
 495                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 496
 497                 amdgpu_dpm_get_pp_num_states(adev, &data);
 498                 state = data.states[idx];
 499                 /* only set user selected power states */
 500                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 501                     state != POWER_STATE_TYPE_DEFAULT) {
 502                         amdgpu_dpm_dispatch_task(adev,
 503                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 504                         adev->pp_force_state_enabled = true;
 505                 }
 506         }
 507 fail:
 508         return count;
 509 }
 510
 511 /**
 512  * DOC: pp_table
 513  *
 514  * The amdgpu driver provides a sysfs API for uploading new powerplay
 515  * tables.  The file pp_table is used for this.  Reading the file
 516  * will dump the current power play table.  Writing to the file
 517  * will attempt to upload a new powerplay table and re-initialize
 518  * powerplay using that new table.
 519  *
 520  */
 521
 522 static ssize_t amdgpu_get_pp_table(struct device *dev,
 523                 struct device_attribute *attr,
 524                 char *buf)
 525 {
 526         struct drm_device *ddev = dev_get_drvdata(dev);
 527         struct amdgpu_device *adev = ddev->dev_private;
 528         char *table = NULL;
 529         int size;
 530
 531         if (is_support_sw_smu(adev)) {
 532                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 533                 if (size < 0)
 534                         return size;
 535         }
 536         else if (adev->powerplay.pp_funcs->get_pp_table)
 537                 size = amdgpu_dpm_get_pp_table(adev, &table);
 538         else
 539                 return 0;
 540
 541         if (size >= PAGE_SIZE)
 542                 size = PAGE_SIZE - 1;
 543
 544         memcpy(buf, table, size);
 545
 546         return size;
 547 }
 548
 549 static ssize_t amdgpu_set_pp_table(struct device *dev,
 550                 struct device_attribute *attr,
 551                 const char *buf,
 552                 size_t count)
 553 {
 554         struct drm_device *ddev = dev_get_drvdata(dev);
 555         struct amdgpu_device *adev = ddev->dev_private;
 556         int ret = 0;
 557
 558         if (is_support_sw_smu(adev)) {
 559                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 560                 if (ret)
 561                         return ret;
 562         } else if (adev->powerplay.pp_funcs->set_pp_table)
 563                 amdgpu_dpm_set_pp_table(adev, buf, count);
 564
 565         return count;
 566 }
 567
 568 /**
 569  * DOC: pp_od_clk_voltage
 570  *
 571  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 572  * in each power level within a power state.  The pp_od_clk_voltage is used for
 573  * this.
 574  *
 575  * < For Vega10 and previous ASICs >
 576  *
 577  * Reading the file will display:
 578  *
 579  * - a list of engine clock levels and voltages labeled OD_SCLK
 580  *
 581  * - a list of memory clock levels and voltages labeled OD_MCLK
 582  *
 583  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 584  *
 585  * To manually adjust these settings, first select manual using
 586  * power_dpm_force_performance_level. Enter a new value for each
 587  * level by writing a string that contains "s/m level clock voltage" to
 588  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 589  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 590  * 810 mV.  When you have edited all of the states as needed, write
 591  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 592  * default power levels, write "r" (reset) to the file to reset them.
 593  *
 594  *
 595  * < For Vega20 >
 596  *
 597  * Reading the file will display:
 598  *
 599  * - minimum and maximum engine clock labeled OD_SCLK
 600  *
 601  * - maximum memory clock labeled OD_MCLK
 602  *
 603  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 604  *   They can be used to calibrate the sclk voltage curve.
 605  *
 606  * - a list of valid ranges for sclk, mclk, and voltage curve points
 607  *   labeled OD_RANGE
 608  *
 609  * To manually adjust these settings:
 610  *
 611  * - First select manual using power_dpm_force_performance_level
 612  *
 613  * - For clock frequency setting, enter a new value by writing a
 614  *   string that contains "s/m index clock" to the file. The index
 615  *   should be 0 if to set minimum clock. And 1 if to set maximum
 616  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 617  *   "m 1 800" will update maximum mclk to be 800Mhz.
 618  *
 619  *   For sclk voltage curve, enter the new values by writing a
 620  *   string that contains "vc point clock voltage" to the file. The
 621  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 622  *   update point1 with clock set as 300Mhz and voltage as
 623  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 624  *   as 1000Mhz and voltage 1000mV.
 625  *
 626  * - When you have edited all of the states as needed, write "c" (commit)
 627  *   to the file to commit your changes
 628  *
 629  * - If you want to reset to the default power levels, write "r" (reset)
 630  *   to the file to reset them
 631  *
 632  */
 633
 634 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 635                 struct device_attribute *attr,
 636                 const char *buf,
 637                 size_t count)
 638 {
 639         struct drm_device *ddev = dev_get_drvdata(dev);
 640         struct amdgpu_device *adev = ddev->dev_private;
 641         int ret;
 642         uint32_t parameter_size = 0;
 643         long parameter[64];
 644         char buf_cpy[128];
 645         char *tmp_str;
 646         char *sub_str;
 647         const char delimiter[3] = {' ', '\n', '\0'};
 648         uint32_t type;
 649
 650         if (count > 127)
 651                 return -EINVAL;
 652
 653         if (*buf == 's')
 654                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 655         else if (*buf == 'm')
 656                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 657         else if(*buf == 'r')
 658                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 659         else if (*buf == 'c')
 660                 type = PP_OD_COMMIT_DPM_TABLE;
 661         else if (!strncmp(buf, "vc", 2))
 662                 type = PP_OD_EDIT_VDDC_CURVE;
 663         else
 664                 return -EINVAL;
 665
 666         memcpy(buf_cpy, buf, count+1);
 667
 668         tmp_str = buf_cpy;
 669
 670         if (type == PP_OD_EDIT_VDDC_CURVE)
 671                 tmp_str++;
 672         while (isspace(*++tmp_str));
 673
 674         while (tmp_str[0]) {
 675                 sub_str = strsep(&tmp_str, delimiter);
 676                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 677                 if (ret)
 678                         return -EINVAL;
 679                 parameter_size++;
 680
 681                 while (isspace(*tmp_str))
 682                         tmp_str++;
 683         }
 684
 685         if (is_support_sw_smu(adev)) {
 686                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 687                                             parameter, parameter_size);
 688
 689                 if (ret)
 690                         return -EINVAL;
 691         } else {
 692                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 693                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 694                                                 parameter, parameter_size);
 695                         if (ret)
 696                                 return -EINVAL;
 697                 }
 698
 699                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 700                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 701                                 amdgpu_dpm_dispatch_task(adev,
 702                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 703                                                 NULL);
 704                                 return count;
 705                         } else {
 706                                 return -EINVAL;
 707                         }
 708                 }
 709         }
 710
 711         return count;
 712 }
 713
 714 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 715                 struct device_attribute *attr,
 716                 char *buf)
 717 {
 718         struct drm_device *ddev = dev_get_drvdata(dev);
 719         struct amdgpu_device *adev = ddev->dev_private;
 720         uint32_t size = 0;
 721
 722         if (is_support_sw_smu(adev)) {
 723                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 724                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 725                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 726                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 727                 return size;
 728         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 729                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 730                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 731                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 732                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 733                 return size;
 734         } else {
 735                 return snprintf(buf, PAGE_SIZE, "\n");
 736         }
 737
 738 }
 739
 740 /**
 741  * DOC: ppfeatures
 742  *
 743  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 744  * features to be enabled. The file ppfeatures is used for this. And
 745  * this is only available for Vega10 and later dGPUs.
 746  *
 747  * Reading back the file will show you the followings:
 748  * - Current ppfeature masks
 749  * - List of the all supported powerplay features with their naming,
 750  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 751  *
 752  * To manually enable or disable a specific feature, just set or clear
 753  * the corresponding bit from original ppfeature masks and input the
 754  * new ppfeature masks.
 755  */
 756 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 757                 struct device_attribute *attr,
 758                 const char *buf,
 759                 size_t count)
 760 {
 761         struct drm_device *ddev = dev_get_drvdata(dev);
 762         struct amdgpu_device *adev = ddev->dev_private;
 763         uint64_t featuremask;
 764         int ret;
 765
 766         ret = kstrtou64(buf, 0, &featuremask);
 767         if (ret)
 768                 return -EINVAL;
 769
 770         pr_debug("featuremask = 0x%llx\n", featuremask);
 771
 772         if (is_support_sw_smu(adev)) {
 773                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 774                 if (ret)
 775                         return -EINVAL;
 776         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 777                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 778                 if (ret)
 779                         return -EINVAL;
 780         }
 781
 782         return count;
 783 }
 784
 785 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 786                 struct device_attribute *attr,
 787                 char *buf)
 788 {
 789         struct drm_device *ddev = dev_get_drvdata(dev);
 790         struct amdgpu_device *adev = ddev->dev_private;
 791
 792         if (is_support_sw_smu(adev)) {
 793                 return smu_get_ppfeature_status(&adev->smu, buf);
 794         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 795                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 796
 797         return snprintf(buf, PAGE_SIZE, "\n");
 798 }
 799
 800 /**
 801  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 802  * pp_dpm_pcie
 803  *
 804  * The amdgpu driver provides a sysfs API for adjusting what power levels
 805  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 806  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 807  * this.
 808  *
 809  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 810  * Vega10 and later ASICs.
 811  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 812  *
 813  * Reading back the files will show you the available power levels within
 814  * the power state and the clock information for those levels.
 815  *
 816  * To manually adjust these states, first select manual using
 817  * power_dpm_force_performance_level.
 818  * Secondly,Enter a new value for each level by inputing a string that
 819  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 820  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 821  *
 822  * NOTE: change to the dcefclk max dpm level is not supported now
 823  */
 824
 825 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 826                 struct device_attribute *attr,
 827                 char *buf)
 828 {
 829         struct drm_device *ddev = dev_get_drvdata(dev);
 830         struct amdgpu_device *adev = ddev->dev_private;
 831
 832         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 833             adev->virt.ops->get_pp_clk)
 834                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 835
 836         if (is_support_sw_smu(adev))
 837                 return smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
 838         else if (adev->powerplay.pp_funcs->print_clock_levels)
 839                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 840         else
 841                 return snprintf(buf, PAGE_SIZE, "\n");
 842 }
 843
 844 /*
 845  * Worst case: 32 bits individually specified, in octal at 12 characters
 846  * per line (+1 for \n).
 847  */
 848 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 849
 850 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 851 {
 852         int ret;
 853         long level;
 854         char *sub_str = NULL;
 855         char *tmp;
 856         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 857         const char delimiter[3] = {' ', '\n', '\0'};
 858         size_t bytes;
 859
 860         *mask = 0;
 861
 862         bytes = min(count, sizeof(buf_cpy) - 1);
 863         memcpy(buf_cpy, buf, bytes);
 864         buf_cpy[bytes] = '\0';
 865         tmp = buf_cpy;
 866         while (tmp[0]) {
 867                 sub_str = strsep(&tmp, delimiter);
 868                 if (strlen(sub_str)) {
 869                         ret = kstrtol(sub_str, 0, &level);
 870                         if (ret)
 871                                 return -EINVAL;
 872                         *mask |= 1 << level;
 873                 } else
 874                         break;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 881                 struct device_attribute *attr,
 882                 const char *buf,
 883                 size_t count)
 884 {
 885         struct drm_device *ddev = dev_get_drvdata(dev);
 886         struct amdgpu_device *adev = ddev->dev_private;
 887         int ret;
 888         uint32_t mask = 0;
 889
 890         if (amdgpu_sriov_vf(adev))
 891                 return 0;
 892
 893         ret = amdgpu_read_mask(buf, count, &mask);
 894         if (ret)
 895                 return ret;
 896
 897         if (is_support_sw_smu(adev))
 898                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
 899         else if (adev->powerplay.pp_funcs->force_clock_level)
 900                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 901
 902         if (ret)
 903                 return -EINVAL;
 904
 905         return count;
 906 }
 907
 908 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 909                 struct device_attribute *attr,
 910                 char *buf)
 911 {
 912         struct drm_device *ddev = dev_get_drvdata(dev);
 913         struct amdgpu_device *adev = ddev->dev_private;
 914
 915         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 916             adev->virt.ops->get_pp_clk)
 917                 return adev->virt.ops->get_pp_clk(adev, PP_MCLK, buf);
 918
 919         if (is_support_sw_smu(adev))
 920                 return smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
 921         else if (adev->powerplay.pp_funcs->print_clock_levels)
 922                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 923         else
 924                 return snprintf(buf, PAGE_SIZE, "\n");
 925 }
 926
 927 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 928                 struct device_attribute *attr,
 929                 const char *buf,
 930                 size_t count)
 931 {
 932         struct drm_device *ddev = dev_get_drvdata(dev);
 933         struct amdgpu_device *adev = ddev->dev_private;
 934         int ret;
 935         uint32_t mask = 0;
 936
 937         if (amdgpu_sriov_vf(adev))
 938                 return 0;
 939
 940         ret = amdgpu_read_mask(buf, count, &mask);
 941         if (ret)
 942                 return ret;
 943
 944         if (is_support_sw_smu(adev))
 945                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
 946         else if (adev->powerplay.pp_funcs->force_clock_level)
 947                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 948
 949         if (ret)
 950                 return -EINVAL;
 951
 952         return count;
 953 }
 954
 955 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 956                 struct device_attribute *attr,
 957                 char *buf)
 958 {
 959         struct drm_device *ddev = dev_get_drvdata(dev);
 960         struct amdgpu_device *adev = ddev->dev_private;
 961
 962         if (is_support_sw_smu(adev))
 963                 return smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
 964         else if (adev->powerplay.pp_funcs->print_clock_levels)
 965                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 966         else
 967                 return snprintf(buf, PAGE_SIZE, "\n");
 968 }
 969
 970 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 971                 struct device_attribute *attr,
 972                 const char *buf,
 973                 size_t count)
 974 {
 975         struct drm_device *ddev = dev_get_drvdata(dev);
 976         struct amdgpu_device *adev = ddev->dev_private;
 977         int ret;
 978         uint32_t mask = 0;
 979
 980         ret = amdgpu_read_mask(buf, count, &mask);
 981         if (ret)
 982                 return ret;
 983
 984         if (is_support_sw_smu(adev))
 985                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
 986         else if (adev->powerplay.pp_funcs->force_clock_level)
 987                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 988
 989         if (ret)
 990                 return -EINVAL;
 991
 992         return count;
 993 }
 994
 995 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 996                 struct device_attribute *attr,
 997                 char *buf)
 998 {
 999         struct drm_device *ddev = dev_get_drvdata(dev);
1000         struct amdgpu_device *adev = ddev->dev_private;
1001
1002         if (is_support_sw_smu(adev))
1003                 return smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1004         else if (adev->powerplay.pp_funcs->print_clock_levels)
1005                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1006         else
1007                 return snprintf(buf, PAGE_SIZE, "\n");
1008 }
1009
1010 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1011                 struct device_attribute *attr,
1012                 const char *buf,
1013                 size_t count)
1014 {
1015         struct drm_device *ddev = dev_get_drvdata(dev);
1016         struct amdgpu_device *adev = ddev->dev_private;
1017         int ret;
1018         uint32_t mask = 0;
1019
1020         ret = amdgpu_read_mask(buf, count, &mask);
1021         if (ret)
1022                 return ret;
1023
1024         if (is_support_sw_smu(adev))
1025                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1026         else if (adev->powerplay.pp_funcs->force_clock_level)
1027                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1028
1029         if (ret)
1030                 return -EINVAL;
1031
1032         return count;
1033 }
1034
1035 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1036                 struct device_attribute *attr,
1037                 char *buf)
1038 {
1039         struct drm_device *ddev = dev_get_drvdata(dev);
1040         struct amdgpu_device *adev = ddev->dev_private;
1041
1042         if (is_support_sw_smu(adev))
1043                 return smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1044         else if (adev->powerplay.pp_funcs->print_clock_levels)
1045                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1046         else
1047                 return snprintf(buf, PAGE_SIZE, "\n");
1048 }
1049
1050 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1051                 struct device_attribute *attr,
1052                 const char *buf,
1053                 size_t count)
1054 {
1055         struct drm_device *ddev = dev_get_drvdata(dev);
1056         struct amdgpu_device *adev = ddev->dev_private;
1057         int ret;
1058         uint32_t mask = 0;
1059
1060         ret = amdgpu_read_mask(buf, count, &mask);
1061         if (ret)
1062                 return ret;
1063
1064         if (is_support_sw_smu(adev))
1065                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1066         else if (adev->powerplay.pp_funcs->force_clock_level)
1067                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1068
1069         if (ret)
1070                 return -EINVAL;
1071
1072         return count;
1073 }
1074
1075 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1076                 struct device_attribute *attr,
1077                 char *buf)
1078 {
1079         struct drm_device *ddev = dev_get_drvdata(dev);
1080         struct amdgpu_device *adev = ddev->dev_private;
1081
1082         if (is_support_sw_smu(adev))
1083                 return smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1084         else if (adev->powerplay.pp_funcs->print_clock_levels)
1085                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1086         else
1087                 return snprintf(buf, PAGE_SIZE, "\n");
1088 }
1089
1090 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1091                 struct device_attribute *attr,
1092                 const char *buf,
1093                 size_t count)
1094 {
1095         struct drm_device *ddev = dev_get_drvdata(dev);
1096         struct amdgpu_device *adev = ddev->dev_private;
1097         int ret;
1098         uint32_t mask = 0;
1099
1100         ret = amdgpu_read_mask(buf, count, &mask);
1101         if (ret)
1102                 return ret;
1103
1104         if (is_support_sw_smu(adev))
1105                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1106         else if (adev->powerplay.pp_funcs->force_clock_level)
1107                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1108
1109         if (ret)
1110                 return -EINVAL;
1111
1112         return count;
1113 }
1114
1115 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1116                 struct device_attribute *attr,
1117                 char *buf)
1118 {
1119         struct drm_device *ddev = dev_get_drvdata(dev);
1120         struct amdgpu_device *adev = ddev->dev_private;
1121         uint32_t value = 0;
1122
1123         if (is_support_sw_smu(adev))
1124                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1125         else if (adev->powerplay.pp_funcs->get_sclk_od)
1126                 value = amdgpu_dpm_get_sclk_od(adev);
1127
1128         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1129 }
1130
1131 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1132                 struct device_attribute *attr,
1133                 const char *buf,
1134                 size_t count)
1135 {
1136         struct drm_device *ddev = dev_get_drvdata(dev);
1137         struct amdgpu_device *adev = ddev->dev_private;
1138         int ret;
1139         long int value;
1140
1141         ret = kstrtol(buf, 0, &value);
1142
1143         if (ret) {
1144                 count = -EINVAL;
1145                 goto fail;
1146         }
1147
1148         if (is_support_sw_smu(adev)) {
1149                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1150         } else {
1151                 if (adev->powerplay.pp_funcs->set_sclk_od)
1152                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1153
1154                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1155                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1156                 } else {
1157                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1158                         amdgpu_pm_compute_clocks(adev);
1159                 }
1160         }
1161
1162 fail:
1163         return count;
1164 }
1165
1166 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1167                 struct device_attribute *attr,
1168                 char *buf)
1169 {
1170         struct drm_device *ddev = dev_get_drvdata(dev);
1171         struct amdgpu_device *adev = ddev->dev_private;
1172         uint32_t value = 0;
1173
1174         if (is_support_sw_smu(adev))
1175                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1176         else if (adev->powerplay.pp_funcs->get_mclk_od)
1177                 value = amdgpu_dpm_get_mclk_od(adev);
1178
1179         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1180 }
1181
1182 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1183                 struct device_attribute *attr,
1184                 const char *buf,
1185                 size_t count)
1186 {
1187         struct drm_device *ddev = dev_get_drvdata(dev);
1188         struct amdgpu_device *adev = ddev->dev_private;
1189         int ret;
1190         long int value;
1191
1192         ret = kstrtol(buf, 0, &value);
1193
1194         if (ret) {
1195                 count = -EINVAL;
1196                 goto fail;
1197         }
1198
1199         if (is_support_sw_smu(adev)) {
1200                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1201         } else {
1202                 if (adev->powerplay.pp_funcs->set_mclk_od)
1203                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1204
1205                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1206                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1207                 } else {
1208                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1209                         amdgpu_pm_compute_clocks(adev);
1210                 }
1211         }
1212
1213 fail:
1214         return count;
1215 }
1216
1217 /**
1218  * DOC: pp_power_profile_mode
1219  *
1220  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1221  * related to switching between power levels in a power state.  The file
1222  * pp_power_profile_mode is used for this.
1223  *
1224  * Reading this file outputs a list of all of the predefined power profiles
1225  * and the relevant heuristics settings for that profile.
1226  *
1227  * To select a profile or create a custom profile, first select manual using
1228  * power_dpm_force_performance_level.  Writing the number of a predefined
1229  * profile to pp_power_profile_mode will enable those heuristics.  To
1230  * create a custom set of heuristics, write a string of numbers to the file
1231  * starting with the number of the custom profile along with a setting
1232  * for each heuristic parameter.  Due to differences across asic families
1233  * the heuristic parameters vary from family to family.
1234  *
1235  */
1236
1237 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1238                 struct device_attribute *attr,
1239                 char *buf)
1240 {
1241         struct drm_device *ddev = dev_get_drvdata(dev);
1242         struct amdgpu_device *adev = ddev->dev_private;
1243
1244         if (is_support_sw_smu(adev))
1245                 return smu_get_power_profile_mode(&adev->smu, buf);
1246         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1247                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1248
1249         return snprintf(buf, PAGE_SIZE, "\n");
1250 }
1251
1252
1253 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1254                 struct device_attribute *attr,
1255                 const char *buf,
1256                 size_t count)
1257 {
1258         int ret = 0xff;
1259         struct drm_device *ddev = dev_get_drvdata(dev);
1260         struct amdgpu_device *adev = ddev->dev_private;
1261         uint32_t parameter_size = 0;
1262         long parameter[64];
1263         char *sub_str, buf_cpy[128];
1264         char *tmp_str;
1265         uint32_t i = 0;
1266         char tmp[2];
1267         long int profile_mode = 0;
1268         const char delimiter[3] = {' ', '\n', '\0'};
1269
1270         tmp[0] = *(buf);
1271         tmp[1] = '\0';
1272         ret = kstrtol(tmp, 0, &profile_mode);
1273         if (ret)
1274                 goto fail;
1275
1276         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1277                 if (count < 2 || count > 127)
1278                         return -EINVAL;
1279                 while (isspace(*++buf))
1280                         i++;
1281                 memcpy(buf_cpy, buf, count-i);
1282                 tmp_str = buf_cpy;
1283                 while (tmp_str[0]) {
1284                         sub_str = strsep(&tmp_str, delimiter);
1285                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1286                         if (ret) {
1287                                 count = -EINVAL;
1288                                 goto fail;
1289                         }
1290                         parameter_size++;
1291                         while (isspace(*tmp_str))
1292                                 tmp_str++;
1293                 }
1294         }
1295         parameter[parameter_size] = profile_mode;
1296         if (is_support_sw_smu(adev))
1297                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1298         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1299                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1300         if (!ret)
1301                 return count;
1302 fail:
1303         return -EINVAL;
1304 }
1305
1306 /**
1307  * DOC: busy_percent
1308  *
1309  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1310  * is as a percentage.  The file gpu_busy_percent is used for this.
1311  * The SMU firmware computes a percentage of load based on the
1312  * aggregate activity level in the IP cores.
1313  */
1314 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1315                 struct device_attribute *attr,
1316                 char *buf)
1317 {
1318         struct drm_device *ddev = dev_get_drvdata(dev);
1319         struct amdgpu_device *adev = ddev->dev_private;
1320         int r, value, size = sizeof(value);
1321
1322         /* read the IP busy sensor */
1323         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1324                                    (void *)&value, &size);
1325
1326         if (r)
1327                 return r;
1328
1329         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1330 }
1331
1332 /**
1333  * DOC: mem_busy_percent
1334  *
1335  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1336  * is as a percentage.  The file mem_busy_percent is used for this.
1337  * The SMU firmware computes a percentage of load based on the
1338  * aggregate activity level in the IP cores.
1339  */
1340 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1341                 struct device_attribute *attr,
1342                 char *buf)
1343 {
1344         struct drm_device *ddev = dev_get_drvdata(dev);
1345         struct amdgpu_device *adev = ddev->dev_private;
1346         int r, value, size = sizeof(value);
1347
1348         /* read the IP busy sensor */
1349         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1350                                    (void *)&value, &size);
1351
1352         if (r)
1353                 return r;
1354
1355         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1356 }
1357
1358 /**
1359  * DOC: pcie_bw
1360  *
1361  * The amdgpu driver provides a sysfs API for estimating how much data
1362  * has been received and sent by the GPU in the last second through PCIe.
1363  * The file pcie_bw is used for this.
1364  * The Perf counters count the number of received and sent messages and return
1365  * those values, as well as the maximum payload size of a PCIe packet (mps).
1366  * Note that it is not possible to easily and quickly obtain the size of each
1367  * packet transmitted, so we output the max payload size (mps) to allow for
1368  * quick estimation of the PCIe bandwidth usage
1369  */
1370 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1371                 struct device_attribute *attr,
1372                 char *buf)
1373 {
1374         struct drm_device *ddev = dev_get_drvdata(dev);
1375         struct amdgpu_device *adev = ddev->dev_private;
1376         uint64_t count0, count1;
1377
1378         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1379         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1380                         count0, count1, pcie_get_mps(adev->pdev));
1381 }
1382
1383 /**
1384  * DOC: unique_id
1385  *
1386  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1387  * The file unique_id is used for this.
1388  * This will provide a Unique ID that will persist from machine to machine
1389  *
1390  * NOTE: This will only work for GFX9 and newer. This file will be absent
1391  * on unsupported ASICs (GFX8 and older)
1392  */
1393 static ssize_t amdgpu_get_unique_id(struct device *dev,
1394                 struct device_attribute *attr,
1395                 char *buf)
1396 {
1397         struct drm_device *ddev = dev_get_drvdata(dev);
1398         struct amdgpu_device *adev = ddev->dev_private;
1399
1400         if (adev->unique_id)
1401                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1402
1403         return 0;
1404 }
1405
1406 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1407 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1408                    amdgpu_get_dpm_forced_performance_level,
1409                    amdgpu_set_dpm_forced_performance_level);
1410 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1411 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1412 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1413                 amdgpu_get_pp_force_state,
1414                 amdgpu_set_pp_force_state);
1415 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1416                 amdgpu_get_pp_table,
1417                 amdgpu_set_pp_table);
1418 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_pp_dpm_sclk,
1420                 amdgpu_set_pp_dpm_sclk);
1421 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1422                 amdgpu_get_pp_dpm_mclk,
1423                 amdgpu_set_pp_dpm_mclk);
1424 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_dpm_socclk,
1426                 amdgpu_set_pp_dpm_socclk);
1427 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_dpm_fclk,
1429                 amdgpu_set_pp_dpm_fclk);
1430 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_dpm_dcefclk,
1432                 amdgpu_set_pp_dpm_dcefclk);
1433 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_dpm_pcie,
1435                 amdgpu_set_pp_dpm_pcie);
1436 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1437                 amdgpu_get_pp_sclk_od,
1438                 amdgpu_set_pp_sclk_od);
1439 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1440                 amdgpu_get_pp_mclk_od,
1441                 amdgpu_set_pp_mclk_od);
1442 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1443                 amdgpu_get_pp_power_profile_mode,
1444                 amdgpu_set_pp_power_profile_mode);
1445 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1446                 amdgpu_get_pp_od_clk_voltage,
1447                 amdgpu_set_pp_od_clk_voltage);
1448 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1449                 amdgpu_get_busy_percent, NULL);
1450 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1451                 amdgpu_get_memory_busy_percent, NULL);
1452 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1453 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1454                 amdgpu_get_ppfeature_status,
1455                 amdgpu_set_ppfeature_status);
1456 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1457
1458 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1459                                       struct device_attribute *attr,
1460                                       char *buf)
1461 {
1462         struct amdgpu_device *adev = dev_get_drvdata(dev);
1463         struct drm_device *ddev = adev->ddev;
1464         int channel = to_sensor_dev_attr(attr)->index;
1465         int r, temp = 0, size = sizeof(temp);
1466
1467         /* Can't get temperature when the card is off */
1468         if  ((adev->flags & AMD_IS_PX) &&
1469              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1470                 return -EINVAL;
1471
1472         if (channel >= PP_TEMP_MAX)
1473                 return -EINVAL;
1474
1475         switch (channel) {
1476         case PP_TEMP_JUNCTION:
1477                 /* get current junction temperature */
1478                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1479                                            (void *)&temp, &size);
1480                 if (r)
1481                         return r;
1482                 break;
1483         case PP_TEMP_EDGE:
1484                 /* get current edge temperature */
1485                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1486                                            (void *)&temp, &size);
1487                 if (r)
1488                         return r;
1489                 break;
1490         case PP_TEMP_MEM:
1491                 /* get current memory temperature */
1492                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1493                                            (void *)&temp, &size);
1494                 if (r)
1495                         return r;
1496                 break;
1497         }
1498
1499         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1500 }
1501
1502 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1503                                              struct device_attribute *attr,
1504                                              char *buf)
1505 {
1506         struct amdgpu_device *adev = dev_get_drvdata(dev);
1507         int hyst = to_sensor_dev_attr(attr)->index;
1508         int temp;
1509
1510         if (hyst)
1511                 temp = adev->pm.dpm.thermal.min_temp;
1512         else
1513                 temp = adev->pm.dpm.thermal.max_temp;
1514
1515         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1516 }
1517
1518 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1519                                              struct device_attribute *attr,
1520                                              char *buf)
1521 {
1522         struct amdgpu_device *adev = dev_get_drvdata(dev);
1523         int hyst = to_sensor_dev_attr(attr)->index;
1524         int temp;
1525
1526         if (hyst)
1527                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1528         else
1529                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1530
1531         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1532 }
1533
1534 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1535                                              struct device_attribute *attr,
1536                                              char *buf)
1537 {
1538         struct amdgpu_device *adev = dev_get_drvdata(dev);
1539         int hyst = to_sensor_dev_attr(attr)->index;
1540         int temp;
1541
1542         if (hyst)
1543                 temp = adev->pm.dpm.thermal.min_mem_temp;
1544         else
1545                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1546
1547         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1548 }
1549
1550 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1551                                              struct device_attribute *attr,
1552                                              char *buf)
1553 {
1554         int channel = to_sensor_dev_attr(attr)->index;
1555
1556         if (channel >= PP_TEMP_MAX)
1557                 return -EINVAL;
1558
1559         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1560 }
1561
1562 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1563                                              struct device_attribute *attr,
1564                                              char *buf)
1565 {
1566         struct amdgpu_device *adev = dev_get_drvdata(dev);
1567         int channel = to_sensor_dev_attr(attr)->index;
1568         int temp = 0;
1569
1570         if (channel >= PP_TEMP_MAX)
1571                 return -EINVAL;
1572
1573         switch (channel) {
1574         case PP_TEMP_JUNCTION:
1575                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1576                 break;
1577         case PP_TEMP_EDGE:
1578                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1579                 break;
1580         case PP_TEMP_MEM:
1581                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1582                 break;
1583         }
1584
1585         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1586 }
1587
1588 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1589                                             struct device_attribute *attr,
1590                                             char *buf)
1591 {
1592         struct amdgpu_device *adev = dev_get_drvdata(dev);
1593         u32 pwm_mode = 0;
1594         if (is_support_sw_smu(adev)) {
1595                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1596         } else {
1597                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1598                         return -EINVAL;
1599
1600                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1601         }
1602
1603         return sprintf(buf, "%i\n", pwm_mode);
1604 }
1605
1606 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1607                                             struct device_attribute *attr,
1608                                             const char *buf,
1609                                             size_t count)
1610 {
1611         struct amdgpu_device *adev = dev_get_drvdata(dev);
1612         int err;
1613         int value;
1614
1615         /* Can't adjust fan when the card is off */
1616         if  ((adev->flags & AMD_IS_PX) &&
1617              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1618                 return -EINVAL;
1619
1620         if (is_support_sw_smu(adev)) {
1621                 err = kstrtoint(buf, 10, &value);
1622                 if (err)
1623                         return err;
1624
1625                 smu_set_fan_control_mode(&adev->smu, value);
1626         } else {
1627                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1628                         return -EINVAL;
1629
1630                 err = kstrtoint(buf, 10, &value);
1631                 if (err)
1632                         return err;
1633
1634                 amdgpu_dpm_set_fan_control_mode(adev, value);
1635         }
1636
1637         return count;
1638 }
1639
1640 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1641                                          struct device_attribute *attr,
1642                                          char *buf)
1643 {
1644         return sprintf(buf, "%i\n", 0);
1645 }
1646
1647 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1648                                          struct device_attribute *attr,
1649                                          char *buf)
1650 {
1651         return sprintf(buf, "%i\n", 255);
1652 }
1653
1654 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1655                                      struct device_attribute *attr,
1656                                      const char *buf, size_t count)
1657 {
1658         struct amdgpu_device *adev = dev_get_drvdata(dev);
1659         int err;
1660         u32 value;
1661         u32 pwm_mode;
1662
1663         /* Can't adjust fan when the card is off */
1664         if  ((adev->flags & AMD_IS_PX) &&
1665              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1666                 return -EINVAL;
1667         if (is_support_sw_smu(adev))
1668                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1669         else
1670                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1671         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1672                 pr_info("manual fan speed control should be enabled first\n");
1673                 return -EINVAL;
1674         }
1675
1676         err = kstrtou32(buf, 10, &value);
1677         if (err)
1678                 return err;
1679
1680         value = (value * 100) / 255;
1681
1682         if (is_support_sw_smu(adev)) {
1683                 err = smu_set_fan_speed_percent(&adev->smu, value);
1684                 if (err)
1685                         return err;
1686         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1687                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1688                 if (err)
1689                         return err;
1690         }
1691
1692         return count;
1693 }
1694
1695 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1696                                      struct device_attribute *attr,
1697                                      char *buf)
1698 {
1699         struct amdgpu_device *adev = dev_get_drvdata(dev);
1700         int err;
1701         u32 speed = 0;
1702
1703         /* Can't adjust fan when the card is off */
1704         if  ((adev->flags & AMD_IS_PX) &&
1705              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1706                 return -EINVAL;
1707
1708         if (is_support_sw_smu(adev)) {
1709                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1710                 if (err)
1711                         return err;
1712         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1713                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1714                 if (err)
1715                         return err;
1716         }
1717
1718         speed = (speed * 255) / 100;
1719
1720         return sprintf(buf, "%i\n", speed);
1721 }
1722
1723 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1724                                            struct device_attribute *attr,
1725                                            char *buf)
1726 {
1727         struct amdgpu_device *adev = dev_get_drvdata(dev);
1728         int err;
1729         u32 speed = 0;
1730
1731         /* Can't adjust fan when the card is off */
1732         if  ((adev->flags & AMD_IS_PX) &&
1733              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1734                 return -EINVAL;
1735
1736         if (is_support_sw_smu(adev)) {
1737                 err = smu_get_current_rpm(&adev->smu, &speed);
1738                 if (err)
1739                         return err;
1740         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1741                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1742                 if (err)
1743                         return err;
1744         }
1745
1746         return sprintf(buf, "%i\n", speed);
1747 }
1748
1749 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1750                                          struct device_attribute *attr,
1751                                          char *buf)
1752 {
1753         struct amdgpu_device *adev = dev_get_drvdata(dev);
1754         u32 min_rpm = 0;
1755         u32 size = sizeof(min_rpm);
1756         int r;
1757
1758         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1759                                    (void *)&min_rpm, &size);
1760         if (r)
1761                 return r;
1762
1763         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1764 }
1765
1766 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1767                                          struct device_attribute *attr,
1768                                          char *buf)
1769 {
1770         struct amdgpu_device *adev = dev_get_drvdata(dev);
1771         u32 max_rpm = 0;
1772         u32 size = sizeof(max_rpm);
1773         int r;
1774
1775         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1776                                    (void *)&max_rpm, &size);
1777         if (r)
1778                 return r;
1779
1780         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1781 }
1782
1783 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1784                                            struct device_attribute *attr,
1785                                            char *buf)
1786 {
1787         struct amdgpu_device *adev = dev_get_drvdata(dev);
1788         int err;
1789         u32 rpm = 0;
1790
1791         /* Can't adjust fan when the card is off */
1792         if  ((adev->flags & AMD_IS_PX) &&
1793              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1794                 return -EINVAL;
1795
1796         if (is_support_sw_smu(adev)) {
1797                 err = smu_get_current_rpm(&adev->smu, &rpm);
1798                 if (err)
1799                         return err;
1800         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1801                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1802                 if (err)
1803                         return err;
1804         }
1805
1806         return sprintf(buf, "%i\n", rpm);
1807 }
1808
1809 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1810                                      struct device_attribute *attr,
1811                                      const char *buf, size_t count)
1812 {
1813         struct amdgpu_device *adev = dev_get_drvdata(dev);
1814         int err;
1815         u32 value;
1816         u32 pwm_mode;
1817
1818         if (is_support_sw_smu(adev))
1819                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1820         else
1821                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1822
1823         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1824                 return -ENODATA;
1825
1826         /* Can't adjust fan when the card is off */
1827         if  ((adev->flags & AMD_IS_PX) &&
1828              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1829                 return -EINVAL;
1830
1831         err = kstrtou32(buf, 10, &value);
1832         if (err)
1833                 return err;
1834
1835         if (is_support_sw_smu(adev)) {
1836                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1837                 if (err)
1838                         return err;
1839         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1840                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1841                 if (err)
1842                         return err;
1843         }
1844
1845         return count;
1846 }
1847
1848 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1849                                             struct device_attribute *attr,
1850                                             char *buf)
1851 {
1852         struct amdgpu_device *adev = dev_get_drvdata(dev);
1853         u32 pwm_mode = 0;
1854
1855         if (is_support_sw_smu(adev)) {
1856                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1857         } else {
1858                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1859                         return -EINVAL;
1860
1861                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1862         }
1863         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1864 }
1865
1866 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1867                                             struct device_attribute *attr,
1868                                             const char *buf,
1869                                             size_t count)
1870 {
1871         struct amdgpu_device *adev = dev_get_drvdata(dev);
1872         int err;
1873         int value;
1874         u32 pwm_mode;
1875
1876         /* Can't adjust fan when the card is off */
1877         if  ((adev->flags & AMD_IS_PX) &&
1878              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1879                 return -EINVAL;
1880
1881
1882         err = kstrtoint(buf, 10, &value);
1883         if (err)
1884                 return err;
1885
1886         if (value == 0)
1887                 pwm_mode = AMD_FAN_CTRL_AUTO;
1888         else if (value == 1)
1889                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1890         else
1891                 return -EINVAL;
1892
1893         if (is_support_sw_smu(adev)) {
1894                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1895         } else {
1896                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1897                         return -EINVAL;
1898                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1899         }
1900
1901         return count;
1902 }
1903
1904 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1905                                         struct device_attribute *attr,
1906                                         char *buf)
1907 {
1908         struct amdgpu_device *adev = dev_get_drvdata(dev);
1909         struct drm_device *ddev = adev->ddev;
1910         u32 vddgfx;
1911         int r, size = sizeof(vddgfx);
1912
1913         /* Can't get voltage when the card is off */
1914         if  ((adev->flags & AMD_IS_PX) &&
1915              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1916                 return -EINVAL;
1917
1918         /* get the voltage */
1919         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1920                                    (void *)&vddgfx, &size);
1921         if (r)
1922                 return r;
1923
1924         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1925 }
1926
1927 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1928                                               struct device_attribute *attr,
1929                                               char *buf)
1930 {
1931         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1932 }
1933
1934 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1935                                        struct device_attribute *attr,
1936                                        char *buf)
1937 {
1938         struct amdgpu_device *adev = dev_get_drvdata(dev);
1939         struct drm_device *ddev = adev->ddev;
1940         u32 vddnb;
1941         int r, size = sizeof(vddnb);
1942
1943         /* only APUs have vddnb */
1944         if  (!(adev->flags & AMD_IS_APU))
1945                 return -EINVAL;
1946
1947         /* Can't get voltage when the card is off */
1948         if  ((adev->flags & AMD_IS_PX) &&
1949              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1950                 return -EINVAL;
1951
1952         /* get the voltage */
1953         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1954                                    (void *)&vddnb, &size);
1955         if (r)
1956                 return r;
1957
1958         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1959 }
1960
1961 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1962                                               struct device_attribute *attr,
1963                                               char *buf)
1964 {
1965         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1966 }
1967
1968 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1969                                            struct device_attribute *attr,
1970                                            char *buf)
1971 {
1972         struct amdgpu_device *adev = dev_get_drvdata(dev);
1973         struct drm_device *ddev = adev->ddev;
1974         u32 query = 0;
1975         int r, size = sizeof(u32);
1976         unsigned uw;
1977
1978         /* Can't get power when the card is off */
1979         if  ((adev->flags & AMD_IS_PX) &&
1980              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1981                 return -EINVAL;
1982
1983         /* get the voltage */
1984         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1985                                    (void *)&query, &size);
1986         if (r)
1987                 return r;
1988
1989         /* convert to microwatts */
1990         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1991
1992         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1993 }
1994
1995 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1996                                          struct device_attribute *attr,
1997                                          char *buf)
1998 {
1999         return sprintf(buf, "%i\n", 0);
2000 }
2001
2002 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2003                                          struct device_attribute *attr,
2004                                          char *buf)
2005 {
2006         struct amdgpu_device *adev = dev_get_drvdata(dev);
2007         uint32_t limit = 0;
2008
2009         if (is_support_sw_smu(adev)) {
2010                 smu_get_power_limit(&adev->smu, &limit, true);
2011                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2012         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2013                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2014                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2015         } else {
2016                 return snprintf(buf, PAGE_SIZE, "\n");
2017         }
2018 }
2019
2020 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2021                                          struct device_attribute *attr,
2022                                          char *buf)
2023 {
2024         struct amdgpu_device *adev = dev_get_drvdata(dev);
2025         uint32_t limit = 0;
2026
2027         if (is_support_sw_smu(adev)) {
2028                 smu_get_power_limit(&adev->smu, &limit, false);
2029                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2030         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2031                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2032                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2033         } else {
2034                 return snprintf(buf, PAGE_SIZE, "\n");
2035         }
2036 }
2037
2038
2039 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2040                 struct device_attribute *attr,
2041                 const char *buf,
2042                 size_t count)
2043 {
2044         struct amdgpu_device *adev = dev_get_drvdata(dev);
2045         int err;
2046         u32 value;
2047
2048         err = kstrtou32(buf, 10, &value);
2049         if (err)
2050                 return err;
2051
2052         value = value / 1000000; /* convert to Watt */
2053         if (is_support_sw_smu(adev)) {
2054                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2055         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2056                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2057                 if (err)
2058                         return err;
2059         } else {
2060                 return -EINVAL;
2061         }
2062
2063         return count;
2064 }
2065
2066 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2067                                       struct device_attribute *attr,
2068                                       char *buf)
2069 {
2070         struct amdgpu_device *adev = dev_get_drvdata(dev);
2071         struct drm_device *ddev = adev->ddev;
2072         uint32_t sclk;
2073         int r, size = sizeof(sclk);
2074
2075         /* Can't get voltage when the card is off */
2076         if  ((adev->flags & AMD_IS_PX) &&
2077              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2078                 return -EINVAL;
2079
2080         /* get the sclk */
2081         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2082                                    (void *)&sclk, &size);
2083         if (r)
2084                 return r;
2085
2086         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2087 }
2088
2089 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2090                                             struct device_attribute *attr,
2091                                             char *buf)
2092 {
2093         return snprintf(buf, PAGE_SIZE, "sclk\n");
2094 }
2095
2096 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2097                                       struct device_attribute *attr,
2098                                       char *buf)
2099 {
2100         struct amdgpu_device *adev = dev_get_drvdata(dev);
2101         struct drm_device *ddev = adev->ddev;
2102         uint32_t mclk;
2103         int r, size = sizeof(mclk);
2104
2105         /* Can't get voltage when the card is off */
2106         if  ((adev->flags & AMD_IS_PX) &&
2107              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2108                 return -EINVAL;
2109
2110         /* get the sclk */
2111         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2112                                    (void *)&mclk, &size);
2113         if (r)
2114                 return r;
2115
2116         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2117 }
2118
2119 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2120                                             struct device_attribute *attr,
2121                                             char *buf)
2122 {
2123         return snprintf(buf, PAGE_SIZE, "mclk\n");
2124 }
2125
2126 /**
2127  * DOC: hwmon
2128  *
2129  * The amdgpu driver exposes the following sensor interfaces:
2130  *
2131  * - GPU temperature (via the on-die sensor)
2132  *
2133  * - GPU voltage
2134  *
2135  * - Northbridge voltage (APUs only)
2136  *
2137  * - GPU power
2138  *
2139  * - GPU fan
2140  *
2141  * - GPU gfx/compute engine clock
2142  *
2143  * - GPU memory clock (dGPU only)
2144  *
2145  * hwmon interfaces for GPU temperature:
2146  *
2147  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2148  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2149  *
2150  * - temp[1-3]_label: temperature channel label
2151  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2152  *
2153  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2154  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2155  *
2156  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2157  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2158  *
2159  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2160  *   - these are supported on SOC15 dGPUs only
2161  *
2162  * hwmon interfaces for GPU voltage:
2163  *
2164  * - in0_input: the voltage on the GPU in millivolts
2165  *
2166  * - in1_input: the voltage on the Northbridge in millivolts
2167  *
2168  * hwmon interfaces for GPU power:
2169  *
2170  * - power1_average: average power used by the GPU in microWatts
2171  *
2172  * - power1_cap_min: minimum cap supported in microWatts
2173  *
2174  * - power1_cap_max: maximum cap supported in microWatts
2175  *
2176  * - power1_cap: selected power cap in microWatts
2177  *
2178  * hwmon interfaces for GPU fan:
2179  *
2180  * - pwm1: pulse width modulation fan level (0-255)
2181  *
2182  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2183  *
2184  * - pwm1_min: pulse width modulation fan control minimum level (0)
2185  *
2186  * - pwm1_max: pulse width modulation fan control maximum level (255)
2187  *
2188  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2189  *
2190  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2191  *
2192  * - fan1_input: fan speed in RPM
2193  *
2194  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2195  *
2196  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2197  *
2198  * hwmon interfaces for GPU clocks:
2199  *
2200  * - freq1_input: the gfx/compute clock in hertz
2201  *
2202  * - freq2_input: the memory clock in hertz
2203  *
2204  * You can use hwmon tools like sensors to view this information on your system.
2205  *
2206  */
2207
2208 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2209 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2210 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2211 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2212 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2213 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2214 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2215 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2216 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2217 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2218 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2219 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2220 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2221 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2222 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2223 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2224 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2225 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2226 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2227 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2228 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2229 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2230 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2231 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2232 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2233 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2234 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2235 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2236 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2237 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2238 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2239 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2240 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2241 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2242 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2243 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2244
2245 static struct attribute *hwmon_attributes[] = {
2246         &sensor_dev_attr_temp1_input.dev_attr.attr,
2247         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2248         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2249         &sensor_dev_attr_temp2_input.dev_attr.attr,
2250         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2251         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2252         &sensor_dev_attr_temp3_input.dev_attr.attr,
2253         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2254         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2255         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2256         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2257         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2258         &sensor_dev_attr_temp1_label.dev_attr.attr,
2259         &sensor_dev_attr_temp2_label.dev_attr.attr,
2260         &sensor_dev_attr_temp3_label.dev_attr.attr,
2261         &sensor_dev_attr_pwm1.dev_attr.attr,
2262         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2263         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2264         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2265         &sensor_dev_attr_fan1_input.dev_attr.attr,
2266         &sensor_dev_attr_fan1_min.dev_attr.attr,
2267         &sensor_dev_attr_fan1_max.dev_attr.attr,
2268         &sensor_dev_attr_fan1_target.dev_attr.attr,
2269         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2270         &sensor_dev_attr_in0_input.dev_attr.attr,
2271         &sensor_dev_attr_in0_label.dev_attr.attr,
2272         &sensor_dev_attr_in1_input.dev_attr.attr,
2273         &sensor_dev_attr_in1_label.dev_attr.attr,
2274         &sensor_dev_attr_power1_average.dev_attr.attr,
2275         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2276         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2277         &sensor_dev_attr_power1_cap.dev_attr.attr,
2278         &sensor_dev_attr_freq1_input.dev_attr.attr,
2279         &sensor_dev_attr_freq1_label.dev_attr.attr,
2280         &sensor_dev_attr_freq2_input.dev_attr.attr,
2281         &sensor_dev_attr_freq2_label.dev_attr.attr,
2282         NULL
2283 };
2284
2285 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2286                                         struct attribute *attr, int index)
2287 {
2288         struct device *dev = kobj_to_dev(kobj);
2289         struct amdgpu_device *adev = dev_get_drvdata(dev);
2290         umode_t effective_mode = attr->mode;
2291
2292         /* Skip fan attributes if fan is not present */
2293         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2294             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2295             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2296             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2297             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2298             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2299             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2300             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2301             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2302                 return 0;
2303
2304         /* Skip fan attributes on APU */
2305         if ((adev->flags & AMD_IS_APU) &&
2306             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2307              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2308              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2309              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2310              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2311              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2312              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2313              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2314              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2315                 return 0;
2316
2317         /* Skip limit attributes if DPM is not enabled */
2318         if (!adev->pm.dpm_enabled &&
2319             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2320              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2321              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2322              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2323              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2324              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2325              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2326              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2327              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2328              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2329              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2330                 return 0;
2331
2332         if (!is_support_sw_smu(adev)) {
2333                 /* mask fan attributes if we have no bindings for this asic to expose */
2334                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2335                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2336                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2337                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2338                         effective_mode &= ~S_IRUGO;
2339
2340                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2341                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2342                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2343                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2344                         effective_mode &= ~S_IWUSR;
2345         }
2346
2347         if ((adev->flags & AMD_IS_APU) &&
2348             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2349              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2350              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2351              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2352                 return 0;
2353
2354         if (!is_support_sw_smu(adev)) {
2355                 /* hide max/min values if we can't both query and manage the fan */
2356                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2357                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2358                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2359                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2360                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2361                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2362                         return 0;
2363
2364                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2365                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2366                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2367                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2368                         return 0;
2369         }
2370
2371         /* only APUs have vddnb */
2372         if (!(adev->flags & AMD_IS_APU) &&
2373             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2374              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2375                 return 0;
2376
2377         /* no mclk on APUs */
2378         if ((adev->flags & AMD_IS_APU) &&
2379             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2380              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2381                 return 0;
2382
2383         /* only SOC15 dGPUs support hotspot and mem temperatures */
2384         if (((adev->flags & AMD_IS_APU) ||
2385              adev->asic_type < CHIP_VEGA10) &&
2386             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2387              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2388              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2389              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2390              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2391              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2392              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2393              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2394              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2395              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2396              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2397                 return 0;
2398
2399         return effective_mode;
2400 }
2401
2402 static const struct attribute_group hwmon_attrgroup = {
2403         .attrs = hwmon_attributes,
2404         .is_visible = hwmon_attributes_visible,
2405 };
2406
2407 static const struct attribute_group *hwmon_groups[] = {
2408         &hwmon_attrgroup,
2409         NULL
2410 };
2411
2412 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2413 {
2414         struct amdgpu_device *adev =
2415                 container_of(work, struct amdgpu_device,
2416                              pm.dpm.thermal.work);
2417         /* switch to the thermal state */
2418         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2419         int temp, size = sizeof(temp);
2420
2421         if (!adev->pm.dpm_enabled)
2422                 return;
2423
2424         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2425                                     (void *)&temp, &size)) {
2426                 if (temp < adev->pm.dpm.thermal.min_temp)
2427                         /* switch back the user state */
2428                         dpm_state = adev->pm.dpm.user_state;
2429         } else {
2430                 if (adev->pm.dpm.thermal.high_to_low)
2431                         /* switch back the user state */
2432                         dpm_state = adev->pm.dpm.user_state;
2433         }
2434         mutex_lock(&adev->pm.mutex);
2435         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2436                 adev->pm.dpm.thermal_active = true;
2437         else
2438                 adev->pm.dpm.thermal_active = false;
2439         adev->pm.dpm.state = dpm_state;
2440         mutex_unlock(&adev->pm.mutex);
2441
2442         amdgpu_pm_compute_clocks(adev);
2443 }
2444
2445 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2446                                                      enum amd_pm_state_type dpm_state)
2447 {
2448         int i;
2449         struct amdgpu_ps *ps;
2450         u32 ui_class;
2451         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2452                 true : false;
2453
2454         /* check if the vblank period is too short to adjust the mclk */
2455         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2456                 if (amdgpu_dpm_vblank_too_short(adev))
2457                         single_display = false;
2458         }
2459
2460         /* certain older asics have a separare 3D performance state,
2461          * so try that first if the user selected performance
2462          */
2463         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2464                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2465         /* balanced states don't exist at the moment */
2466         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2467                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2468
2469 restart_search:
2470         /* Pick the best power state based on current conditions */
2471         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2472                 ps = &adev->pm.dpm.ps[i];
2473                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2474                 switch (dpm_state) {
2475                 /* user states */
2476                 case POWER_STATE_TYPE_BATTERY:
2477                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2478                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2479                                         if (single_display)
2480                                                 return ps;
2481                                 } else
2482                                         return ps;
2483                         }
2484                         break;
2485                 case POWER_STATE_TYPE_BALANCED:
2486                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2487                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2488                                         if (single_display)
2489                                                 return ps;
2490                                 } else
2491                                         return ps;
2492                         }
2493                         break;
2494                 case POWER_STATE_TYPE_PERFORMANCE:
2495                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2496                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2497                                         if (single_display)
2498                                                 return ps;
2499                                 } else
2500                                         return ps;
2501                         }
2502                         break;
2503                 /* internal states */
2504                 case POWER_STATE_TYPE_INTERNAL_UVD:
2505                         if (adev->pm.dpm.uvd_ps)
2506                                 return adev->pm.dpm.uvd_ps;
2507                         else
2508                                 break;
2509                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2510                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2511                                 return ps;
2512                         break;
2513                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2514                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2515                                 return ps;
2516                         break;
2517                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2518                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2519                                 return ps;
2520                         break;
2521                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2522                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2523                                 return ps;
2524                         break;
2525                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2526                         return adev->pm.dpm.boot_ps;
2527                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2528                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2529                                 return ps;
2530                         break;
2531                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2532                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2533                                 return ps;
2534                         break;
2535                 case POWER_STATE_TYPE_INTERNAL_ULV:
2536                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2537                                 return ps;
2538                         break;
2539                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2540                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2541                                 return ps;
2542                         break;
2543                 default:
2544                         break;
2545                 }
2546         }
2547         /* use a fallback state if we didn't match */
2548         switch (dpm_state) {
2549         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2550                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2551                 goto restart_search;
2552         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2553         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2554         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2555                 if (adev->pm.dpm.uvd_ps) {
2556                         return adev->pm.dpm.uvd_ps;
2557                 } else {
2558                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2559                         goto restart_search;
2560                 }
2561         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2562                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2563                 goto restart_search;
2564         case POWER_STATE_TYPE_INTERNAL_ACPI:
2565                 dpm_state = POWER_STATE_TYPE_BATTERY;
2566                 goto restart_search;
2567         case POWER_STATE_TYPE_BATTERY:
2568         case POWER_STATE_TYPE_BALANCED:
2569         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2570                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2571                 goto restart_search;
2572         default:
2573                 break;
2574         }
2575
2576         return NULL;
2577 }
2578
2579 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2580 {
2581         struct amdgpu_ps *ps;
2582         enum amd_pm_state_type dpm_state;
2583         int ret;
2584         bool equal = false;
2585
2586         /* if dpm init failed */
2587         if (!adev->pm.dpm_enabled)
2588                 return;
2589
2590         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2591                 /* add other state override checks here */
2592                 if ((!adev->pm.dpm.thermal_active) &&
2593                     (!adev->pm.dpm.uvd_active))
2594                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2595         }
2596         dpm_state = adev->pm.dpm.state;
2597
2598         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2599         if (ps)
2600                 adev->pm.dpm.requested_ps = ps;
2601         else
2602                 return;
2603
2604         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2605                 printk("switching from power state:\n");
2606                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2607                 printk("switching to power state:\n");
2608                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2609         }
2610
2611         /* update whether vce is active */
2612         ps->vce_active = adev->pm.dpm.vce_active;
2613         if (adev->powerplay.pp_funcs->display_configuration_changed)
2614                 amdgpu_dpm_display_configuration_changed(adev);
2615
2616         ret = amdgpu_dpm_pre_set_power_state(adev);
2617         if (ret)
2618                 return;
2619
2620         if (adev->powerplay.pp_funcs->check_state_equal) {
2621                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2622                         equal = false;
2623         }
2624
2625         if (equal)
2626                 return;
2627
2628         amdgpu_dpm_set_power_state(adev);
2629         amdgpu_dpm_post_set_power_state(adev);
2630
2631         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2632         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2633
2634         if (adev->powerplay.pp_funcs->force_performance_level) {
2635                 if (adev->pm.dpm.thermal_active) {
2636                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2637                         /* force low perf level for thermal */
2638                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2639                         /* save the user's level */
2640                         adev->pm.dpm.forced_level = level;
2641                 } else {
2642                         /* otherwise, user selected level */
2643                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2644                 }
2645         }
2646 }
2647
2648 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2649 {
2650         int ret = 0;
2651         if (is_support_sw_smu(adev)) {
2652             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2653             if (ret)
2654                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2655                           enable ? "true" : "false", ret);
2656         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2657                 /* enable/disable UVD */
2658                 mutex_lock(&adev->pm.mutex);
2659                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2660                 mutex_unlock(&adev->pm.mutex);
2661         }
2662         /* enable/disable Low Memory PState for UVD (4k videos) */
2663         if (adev->asic_type == CHIP_STONEY &&
2664                 adev->uvd.decode_image_width >= WIDTH_4K) {
2665                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2666
2667                 if (hwmgr && hwmgr->hwmgr_func &&
2668                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2669                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2670                                                                !enable,
2671                                                                true);
2672         }
2673 }
2674
2675 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2676 {
2677         int ret = 0;
2678         if (is_support_sw_smu(adev)) {
2679             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2680             if (ret)
2681                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2682                           enable ? "true" : "false", ret);
2683         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2684                 /* enable/disable VCE */
2685                 mutex_lock(&adev->pm.mutex);
2686                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2687                 mutex_unlock(&adev->pm.mutex);
2688         }
2689 }
2690
2691 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2692 {
2693         int i;
2694
2695         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2696                 return;
2697
2698         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2699                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2700
2701 }
2702
2703 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
2704 {
2705         int ret = 0;
2706
2707         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2708                 return ret;
2709
2710         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2711         if (ret) {
2712                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2713                 return ret;
2714         }
2715
2716         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2717         if (ret) {
2718                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2719                 return ret;
2720         }
2721
2722         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2723         if (ret) {
2724                 DRM_ERROR("failed to create device file for dpm state\n");
2725                 return ret;
2726         }
2727
2728         return ret;
2729 }
2730
2731 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev)
2732 {
2733         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2734                 return;
2735
2736         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2737         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2738         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2739 }
2740
2741 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2742 {
2743         int r;
2744
2745         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2746                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
2747                 if (r) {
2748                         pr_err("smu firmware loading failed\n");
2749                         return r;
2750                 }
2751                 *smu_version = adev->pm.fw_version;
2752         }
2753         return 0;
2754 }
2755
2756 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2757 {
2758         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2759         int ret;
2760
2761         if (adev->pm.sysfs_initialized)
2762                 return 0;
2763
2764         if (adev->pm.dpm_enabled == 0)
2765                 return 0;
2766
2767         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2768                                                                    DRIVER_NAME, adev,
2769                                                                    hwmon_groups);
2770         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2771                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2772                 dev_err(adev->dev,
2773                         "Unable to register hwmon device: %d\n", ret);
2774                 return ret;
2775         }
2776
2777         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2778         if (ret) {
2779                 DRM_ERROR("failed to create device file for dpm state\n");
2780                 return ret;
2781         }
2782         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2783         if (ret) {
2784                 DRM_ERROR("failed to create device file for dpm state\n");
2785                 return ret;
2786         }
2787
2788
2789         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2790         if (ret) {
2791                 DRM_ERROR("failed to create device file pp_num_states\n");
2792                 return ret;
2793         }
2794         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2795         if (ret) {
2796                 DRM_ERROR("failed to create device file pp_cur_state\n");
2797                 return ret;
2798         }
2799         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2800         if (ret) {
2801                 DRM_ERROR("failed to create device file pp_force_state\n");
2802                 return ret;
2803         }
2804         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2805         if (ret) {
2806                 DRM_ERROR("failed to create device file pp_table\n");
2807                 return ret;
2808         }
2809
2810         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2811         if (ret) {
2812                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2813                 return ret;
2814         }
2815         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2816         if (ret) {
2817                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2818                 return ret;
2819         }
2820         if (adev->asic_type >= CHIP_VEGA10) {
2821                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2822                 if (ret) {
2823                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2824                         return ret;
2825                 }
2826                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2827                 if (ret) {
2828                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2829                         return ret;
2830                 }
2831         }
2832         if (adev->asic_type >= CHIP_VEGA20) {
2833                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2834                 if (ret) {
2835                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2836                         return ret;
2837                 }
2838         }
2839         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2840         if (ret) {
2841                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2842                 return ret;
2843         }
2844         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2845         if (ret) {
2846                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2847                 return ret;
2848         }
2849         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2850         if (ret) {
2851                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2852                 return ret;
2853         }
2854         ret = device_create_file(adev->dev,
2855                         &dev_attr_pp_power_profile_mode);
2856         if (ret) {
2857                 DRM_ERROR("failed to create device file "
2858                                 "pp_power_profile_mode\n");
2859                 return ret;
2860         }
2861         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2862             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2863                 ret = device_create_file(adev->dev,
2864                                 &dev_attr_pp_od_clk_voltage);
2865                 if (ret) {
2866                         DRM_ERROR("failed to create device file "
2867                                         "pp_od_clk_voltage\n");
2868                         return ret;
2869                 }
2870         }
2871         ret = device_create_file(adev->dev,
2872                         &dev_attr_gpu_busy_percent);
2873         if (ret) {
2874                 DRM_ERROR("failed to create device file "
2875                                 "gpu_busy_level\n");
2876                 return ret;
2877         }
2878         /* APU does not have its own dedicated memory */
2879         if (!(adev->flags & AMD_IS_APU) &&
2880              (adev->asic_type != CHIP_VEGA10)) {
2881                 ret = device_create_file(adev->dev,
2882                                 &dev_attr_mem_busy_percent);
2883                 if (ret) {
2884                         DRM_ERROR("failed to create device file "
2885                                         "mem_busy_percent\n");
2886                         return ret;
2887                 }
2888         }
2889         /* PCIe Perf counters won't work on APU nodes */
2890         if (!(adev->flags & AMD_IS_APU)) {
2891                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2892                 if (ret) {
2893                         DRM_ERROR("failed to create device file pcie_bw\n");
2894                         return ret;
2895                 }
2896         }
2897         if (adev->unique_id)
2898                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2899         if (ret) {
2900                 DRM_ERROR("failed to create device file unique_id\n");
2901                 return ret;
2902         }
2903         ret = amdgpu_debugfs_pm_init(adev);
2904         if (ret) {
2905                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2906                 return ret;
2907         }
2908
2909         if ((adev->asic_type >= CHIP_VEGA10) &&
2910             !(adev->flags & AMD_IS_APU)) {
2911                 ret = device_create_file(adev->dev,
2912                                 &dev_attr_ppfeatures);
2913                 if (ret) {
2914                         DRM_ERROR("failed to create device file "
2915                                         "ppfeatures\n");
2916                         return ret;
2917                 }
2918         }
2919
2920         adev->pm.sysfs_initialized = true;
2921
2922         return 0;
2923 }
2924
2925 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2926 {
2927         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2928
2929         if (adev->pm.dpm_enabled == 0)
2930                 return;
2931
2932         if (adev->pm.int_hwmon_dev)
2933                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2934         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2935         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2936
2937         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2938         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2939         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2940         device_remove_file(adev->dev, &dev_attr_pp_table);
2941
2942         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2943         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2944         if (adev->asic_type >= CHIP_VEGA10) {
2945                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2946                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2947         }
2948         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2949         if (adev->asic_type >= CHIP_VEGA20)
2950                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2951         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2952         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2953         device_remove_file(adev->dev,
2954                         &dev_attr_pp_power_profile_mode);
2955         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2956             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2957                 device_remove_file(adev->dev,
2958                                 &dev_attr_pp_od_clk_voltage);
2959         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2960         if (!(adev->flags & AMD_IS_APU) &&
2961              (adev->asic_type != CHIP_VEGA10))
2962                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2963         if (!(adev->flags & AMD_IS_APU))
2964                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2965         if (adev->unique_id)
2966                 device_remove_file(adev->dev, &dev_attr_unique_id);
2967         if ((adev->asic_type >= CHIP_VEGA10) &&
2968             !(adev->flags & AMD_IS_APU))
2969                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2970 }
2971
2972 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2973 {
2974         int i = 0;
2975
2976         if (!adev->pm.dpm_enabled)
2977                 return;
2978
2979         if (adev->mode_info.num_crtc)
2980                 amdgpu_display_bandwidth_update(adev);
2981
2982         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2983                 struct amdgpu_ring *ring = adev->rings[i];
2984                 if (ring && ring->sched.ready)
2985                         amdgpu_fence_wait_empty(ring);
2986         }
2987
2988         if (is_support_sw_smu(adev)) {
2989                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2990                 smu_handle_task(&adev->smu,
2991                                 smu_dpm->dpm_level,
2992                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2993         } else {
2994                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2995                         if (!amdgpu_device_has_dc_support(adev)) {
2996                                 mutex_lock(&adev->pm.mutex);
2997                                 amdgpu_dpm_get_active_displays(adev);
2998                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2999                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3000                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3001                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3002                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3003                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3004                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3005                                         adev->powerplay.pp_funcs->display_configuration_change(
3006                                                                         adev->powerplay.pp_handle,
3007                                                                         &adev->pm.pm_display_cfg);
3008                                 mutex_unlock(&adev->pm.mutex);
3009                         }
3010                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3011                 } else {
3012                         mutex_lock(&adev->pm.mutex);
3013                         amdgpu_dpm_get_active_displays(adev);
3014                         amdgpu_dpm_change_power_state_locked(adev);
3015                         mutex_unlock(&adev->pm.mutex);
3016                 }
3017         }
3018 }
3019
3020 /*
3021  * Debugfs info
3022  */
3023 #if defined(CONFIG_DEBUG_FS)
3024
3025 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3026 {
3027         uint32_t value;
3028         uint64_t value64;
3029         uint32_t query = 0;
3030         int size;
3031
3032         /* GPU Clocks */
3033         size = sizeof(value);
3034         seq_printf(m, "GFX Clocks and Power:\n");
3035         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3036                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3037         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3038                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3039         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3040                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3041         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3042                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3043         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3044                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3045         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3046                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3047         size = sizeof(uint32_t);
3048         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3049                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3050         size = sizeof(value);
3051         seq_printf(m, "\n");
3052
3053         /* GPU Temp */
3054         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3055                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3056
3057         /* GPU Load */
3058         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3059                 seq_printf(m, "GPU Load: %u %%\n", value);
3060         /* MEM Load */
3061         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3062                 seq_printf(m, "MEM Load: %u %%\n", value);
3063
3064         seq_printf(m, "\n");
3065
3066         /* SMC feature mask */
3067         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3068                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3069
3070         /* UVD clocks */
3071         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3072                 if (!value) {
3073                         seq_printf(m, "UVD: Disabled\n");
3074                 } else {
3075                         seq_printf(m, "UVD: Enabled\n");
3076                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3077                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3078                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3079                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3080                 }
3081         }
3082         seq_printf(m, "\n");
3083
3084         /* VCE clocks */
3085         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3086                 if (!value) {
3087                         seq_printf(m, "VCE: Disabled\n");
3088                 } else {
3089                         seq_printf(m, "VCE: Enabled\n");
3090                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3091                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3092                 }
3093         }
3094
3095         return 0;
3096 }
3097
3098 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3099 {
3100         int i;
3101
3102         for (i = 0; clocks[i].flag; i++)
3103                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3104                            (flags & clocks[i].flag) ? "On" : "Off");
3105 }
3106
3107 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3108 {
3109         struct drm_info_node *node = (struct drm_info_node *) m->private;
3110         struct drm_device *dev = node->minor->dev;
3111         struct amdgpu_device *adev = dev->dev_private;
3112         struct drm_device *ddev = adev->ddev;
3113         u32 flags = 0;
3114
3115         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3116         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3117         amdgpu_parse_cg_state(m, flags);
3118         seq_printf(m, "\n");
3119
3120         if (!adev->pm.dpm_enabled) {
3121                 seq_printf(m, "dpm not enabled\n");
3122                 return 0;
3123         }
3124         if  ((adev->flags & AMD_IS_PX) &&
3125              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3126                 seq_printf(m, "PX asic powered off\n");
3127         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3128                 mutex_lock(&adev->pm.mutex);
3129                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3130                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3131                 else
3132                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3133                 mutex_unlock(&adev->pm.mutex);
3134         } else {
3135                 return amdgpu_debugfs_pm_info_pp(m, adev);
3136         }
3137
3138         return 0;
3139 }
3140
3141 static const struct drm_info_list amdgpu_pm_info_list[] = {
3142         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3143 };
3144 #endif
3145
3146 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3147 {
3148 #if defined(CONFIG_DEBUG_FS)
3149         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3150 #else
3151         return 0;
3152 #endif
3153 }