sound/soc/tegra/tegra_i2s.c

   1 /*
   2  * tegra_i2s.c - Tegra I2S driver
   3  *
   4  * Author: Stephen Warren <[email protected]>
   5  * Copyright (C) 2010 - NVIDIA, Inc.
   6  *
   7  * Based on code copyright/by:
   8  *
   9  * Copyright (c) 2009-2010, NVIDIA Corporation.
  10  * Scott Peterson <[email protected]>
  11  *
  12  * Copyright (C) 2010 Google, Inc.
  13  * Iliyan Malchev <[email protected]>
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * version 2 as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope that it will be useful, but
  20  * WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  22  * General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  27  * 02110-1301 USA
  28  *
  29  */
  30
  31 #include <linux/clk.h>
  32 #include <linux/module.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/device.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <mach/iomap.h>
  40 #include <sound/core.h>
  41 #include <sound/pcm.h>
  42 #include <sound/pcm_params.h>
  43 #include <sound/soc.h>
  44
  45 #include "tegra_i2s.h"
  46
  47 #define DRV_NAME "tegra-i2s"
  48
  49 static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
  50 {
  51         __raw_writel(val, i2s->regs + reg);
  52 }
  53
  54 static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
  55 {
  56         return __raw_readl(i2s->regs + reg);
  57 }
  58
  59 #ifdef CONFIG_DEBUG_FS
  60 static int tegra_i2s_show(struct seq_file *s, void *unused)
  61 {
  62 #define REG(r) { r, #r }
  63         static const struct {
  64                 int offset;
  65                 const char *name;
  66         } regs[] = {
  67                 REG(TEGRA_I2S_CTRL),
  68                 REG(TEGRA_I2S_STATUS),
  69                 REG(TEGRA_I2S_TIMING),
  70                 REG(TEGRA_I2S_FIFO_SCR),
  71                 REG(TEGRA_I2S_PCM_CTRL),
  72                 REG(TEGRA_I2S_NW_CTRL),
  73                 REG(TEGRA_I2S_TDM_CTRL),
  74                 REG(TEGRA_I2S_TDM_TX_RX_CTRL),
  75         };
  76 #undef REG
  77
  78         struct tegra_i2s *i2s = s->private;
  79         int i;
  80
  81         for (i = 0; i < ARRAY_SIZE(regs); i++) {
  82                 u32 val = tegra_i2s_read(i2s, regs[i].offset);
  83                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
  90 {
  91         return single_open(file, tegra_i2s_show, inode->i_private);
  92 }
  93
  94 static const struct file_operations tegra_i2s_debug_fops = {
  95         .open    = tegra_i2s_debug_open,
  96         .read    = seq_read,
  97         .llseek  = seq_lseek,
  98         .release = single_release,
  99 };
 100
 101 static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
 102 {
 103         char name[] = DRV_NAME ".0";
 104
 105         snprintf(name, sizeof(name), DRV_NAME".%1d", id);
 106         i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
 107                                                 i2s, &tegra_i2s_debug_fops);
 108 }
 109
 110 static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
 111 {
 112         if (i2s->debug)
 113                 debugfs_remove(i2s->debug);
 114 }
 115 #else
 116 static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
 117 {
 118 }
 119
 120 static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
 121 {
 122 }
 123 #endif
 124
 125 static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
 126                                 unsigned int fmt)
 127 {
 128         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 129
 130         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 131         case SND_SOC_DAIFMT_NB_NF:
 132                 break;
 133         default:
 134                 return -EINVAL;
 135         }
 136
 137         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
 138         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 139         case SND_SOC_DAIFMT_CBS_CFS:
 140                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
 141                 break;
 142         case SND_SOC_DAIFMT_CBM_CFM:
 143                 break;
 144         default:
 145                 return -EINVAL;
 146         }
 147
 148         i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
 149                                 TEGRA_I2S_CTRL_LRCK_MASK);
 150         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 151         case SND_SOC_DAIFMT_DSP_A:
 152                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
 153                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 154                 break;
 155         case SND_SOC_DAIFMT_DSP_B:
 156                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
 157                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
 158                 break;
 159         case SND_SOC_DAIFMT_I2S:
 160                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
 161                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 162                 break;
 163         case SND_SOC_DAIFMT_RIGHT_J:
 164                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
 165                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 166                 break;
 167         case SND_SOC_DAIFMT_LEFT_J:
 168                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
 169                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
 170                 break;
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
 179                                 struct snd_pcm_hw_params *params,
 180                                 struct snd_soc_dai *dai)
 181 {
 182         struct device *dev = substream->pcm->card->dev;
 183         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 184         u32 reg;
 185         int ret, sample_size, srate, i2sclock, bitcnt;
 186
 187         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
 188         switch (params_format(params)) {
 189         case SNDRV_PCM_FORMAT_S16_LE:
 190                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
 191                 sample_size = 16;
 192                 break;
 193         case SNDRV_PCM_FORMAT_S24_LE:
 194                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
 195                 sample_size = 24;
 196                 break;
 197         case SNDRV_PCM_FORMAT_S32_LE:
 198                 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
 199                 sample_size = 32;
 200                 break;
 201         default:
 202                 return -EINVAL;
 203         }
 204
 205         srate = params_rate(params);
 206
 207         /* Final "* 2" required by Tegra hardware */
 208         i2sclock = srate * params_channels(params) * sample_size * 2;
 209
 210         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
 211         if (ret) {
 212                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
 213                 return ret;
 214         }
 215
 216         bitcnt = (i2sclock / (2 * srate)) - 1;
 217         if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
 218                 return -EINVAL;
 219         reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 220
 221         if (i2sclock % (2 * srate))
 222                 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
 223
 224         if (!i2s->clk_refs)
 225                 clk_enable(i2s->clk_i2s);
 226
 227         tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
 228
 229         tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
 230                 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
 231                 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
 232
 233         if (!i2s->clk_refs)
 234                 clk_disable(i2s->clk_i2s);
 235
 236         return 0;
 237 }
 238
 239 static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
 240 {
 241         i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
 242         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 243 }
 244
 245 static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
 246 {
 247         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
 248         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 249 }
 250
 251 static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
 252 {
 253         i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
 254         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 255 }
 256
 257 static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
 258 {
 259         i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
 260         tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
 261 }
 262
 263 static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 264                                 struct snd_soc_dai *dai)
 265 {
 266         struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 267
 268         switch (cmd) {
 269         case SNDRV_PCM_TRIGGER_START:
 270         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 271         case SNDRV_PCM_TRIGGER_RESUME:
 272                 if (!i2s->clk_refs)
 273                         clk_enable(i2s->clk_i2s);
 274                 i2s->clk_refs++;
 275                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 276                         tegra_i2s_start_playback(i2s);
 277                 else
 278                         tegra_i2s_start_capture(i2s);
 279                 break;
 280         case SNDRV_PCM_TRIGGER_STOP:
 281         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 282         case SNDRV_PCM_TRIGGER_SUSPEND:
 283                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 284                         tegra_i2s_stop_playback(i2s);
 285                 else
 286                         tegra_i2s_stop_capture(i2s);
 287                 i2s->clk_refs--;
 288                 if (!i2s->clk_refs)
 289                         clk_disable(i2s->clk_i2s);
 290                 break;
 291         default:
 292                 return -EINVAL;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int tegra_i2s_probe(struct snd_soc_dai *dai)
 299 {
 300         struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
 301
 302         dai->capture_dma_data = &i2s->capture_dma_data;
 303         dai->playback_dma_data = &i2s->playback_dma_data;
 304
 305         return 0;
 306 }
 307
 308 static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
 309         .set_fmt        = tegra_i2s_set_fmt,
 310         .hw_params      = tegra_i2s_hw_params,
 311         .trigger        = tegra_i2s_trigger,
 312 };
 313
 314 static struct snd_soc_dai_driver tegra_i2s_dai[] = {
 315         {
 316                 .name = DRV_NAME ".0",
 317                 .probe = tegra_i2s_probe,
 318                 .playback = {
 319                         .channels_min = 2,
 320                         .channels_max = 2,
 321                         .rates = SNDRV_PCM_RATE_8000_96000,
 322                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 323                 },
 324                 .capture = {
 325                         .channels_min = 2,
 326                         .channels_max = 2,
 327                         .rates = SNDRV_PCM_RATE_8000_96000,
 328                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 329                 },
 330                 .ops = &tegra_i2s_dai_ops,
 331                 .symmetric_rates = 1,
 332         },
 333         {
 334                 .name = DRV_NAME ".1",
 335                 .probe = tegra_i2s_probe,
 336                 .playback = {
 337                         .channels_min = 2,
 338                         .channels_max = 2,
 339                         .rates = SNDRV_PCM_RATE_8000_96000,
 340                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 341                 },
 342                 .capture = {
 343                         .channels_min = 2,
 344                         .channels_max = 2,
 345                         .rates = SNDRV_PCM_RATE_8000_96000,
 346                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
 347                 },
 348                 .ops = &tegra_i2s_dai_ops,
 349                 .symmetric_rates = 1,
 350         },
 351 };
 352
 353 static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
 354 {
 355         struct tegra_i2s * i2s;
 356         struct resource *mem, *memregion, *dmareq;
 357         int ret;
 358
 359         if ((pdev->id < 0) ||
 360                 (pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
 361                 dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
 362                 return -EINVAL;
 363         }
 364
 365         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL);
 366         if (!i2s) {
 367                 dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
 368                 ret = -ENOMEM;
 369                 goto err;
 370         }
 371         dev_set_drvdata(&pdev->dev, i2s);
 372
 373         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
 374         if (IS_ERR(i2s->clk_i2s)) {
 375                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 376                 ret = PTR_ERR(i2s->clk_i2s);
 377                 goto err;
 378         }
 379
 380         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 381         if (!mem) {
 382                 dev_err(&pdev->dev, "No memory resource\n");
 383                 ret = -ENODEV;
 384                 goto err_clk_put;
 385         }
 386
 387         dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 388         if (!dmareq) {
 389                 dev_err(&pdev->dev, "No DMA resource\n");
 390                 ret = -ENODEV;
 391                 goto err_clk_put;
 392         }
 393
 394         memregion = devm_request_mem_region(&pdev->dev, mem->start,
 395                                             resource_size(mem), DRV_NAME);
 396         if (!memregion) {
 397                 dev_err(&pdev->dev, "Memory region already claimed\n");
 398                 ret = -EBUSY;
 399                 goto err_clk_put;
 400         }
 401
 402         i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 403         if (!i2s->regs) {
 404                 dev_err(&pdev->dev, "ioremap failed\n");
 405                 ret = -ENOMEM;
 406                 goto err_clk_put;
 407         }
 408
 409         i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
 410         i2s->capture_dma_data.wrap = 4;
 411         i2s->capture_dma_data.width = 32;
 412         i2s->capture_dma_data.req_sel = dmareq->start;
 413
 414         i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
 415         i2s->playback_dma_data.wrap = 4;
 416         i2s->playback_dma_data.width = 32;
 417         i2s->playback_dma_data.req_sel = dmareq->start;
 418
 419         i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
 420
 421         ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
 422         if (ret) {
 423                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 424                 ret = -ENOMEM;
 425                 goto err_clk_put;
 426         }
 427
 428         tegra_i2s_debug_add(i2s, pdev->id);
 429
 430         return 0;
 431
 432 err_clk_put:
 433         clk_put(i2s->clk_i2s);
 434 err:
 435         return ret;
 436 }
 437
 438 static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
 439 {
 440         struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
 441
 442         snd_soc_unregister_dai(&pdev->dev);
 443
 444         tegra_i2s_debug_remove(i2s);
 445
 446         clk_put(i2s->clk_i2s);
 447
 448         return 0;
 449 }
 450
 451 static struct platform_driver tegra_i2s_driver = {
 452         .driver = {
 453                 .name = DRV_NAME,
 454                 .owner = THIS_MODULE,
 455         },
 456         .probe = tegra_i2s_platform_probe,
 457         .remove = __devexit_p(tegra_i2s_platform_remove),
 458 };
 459 module_platform_driver(tegra_i2s_driver);
 460
 461 MODULE_AUTHOR("Stephen Warren <[email protected]>");
 462 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
 463 MODULE_LICENSE("GPL");
 464 MODULE_ALIAS("platform:" DRV_NAME);