drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31
  32 /* delay 0.1 second to enable gfx off feature */
  33 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  34
  35 #define GFX_OFF_NO_DELAY 0
  36
  37 /*
  38  * GPU GFX IP block helpers function.
  39  */
  40
  41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  42                                 int pipe, int queue)
  43 {
  44         int bit = 0;
  45
  46         bit += mec * adev->gfx.mec.num_pipe_per_mec
  47                 * adev->gfx.mec.num_queue_per_pipe;
  48         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  49         bit += queue;
  50
  51         return bit;
  52 }
  53
  54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  55                                  int *mec, int *pipe, int *queue)
  56 {
  57         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  58         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  59                 % adev->gfx.mec.num_pipe_per_mec;
  60         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                / adev->gfx.mec.num_pipe_per_mec;
  62
  63 }
  64
  65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  66                                      int xcc_id, int mec, int pipe, int queue)
  67 {
  68         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  69                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  70 }
  71
  72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  73                                int me, int pipe, int queue)
  74 {
  75         int bit = 0;
  76
  77         bit += me * adev->gfx.me.num_pipe_per_me
  78                 * adev->gfx.me.num_queue_per_pipe;
  79         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  80         bit += queue;
  81
  82         return bit;
  83 }
  84
  85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  86                                 int *me, int *pipe, int *queue)
  87 {
  88         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  89         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  90                 % adev->gfx.me.num_pipe_per_me;
  91         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 / adev->gfx.me.num_pipe_per_me;
  93 }
  94
  95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  96                                     int me, int pipe, int queue)
  97 {
  98         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  99                         adev->gfx.me.queue_bitmap);
 100 }
 101
 102 /**
 103  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 104  *
 105  * @mask: array in which the per-shader array disable masks will be stored
 106  * @max_se: number of SEs
 107  * @max_sh: number of SHs
 108  *
 109  * The bitmask of CUs to be disabled in the shader array determined by se and
 110  * sh is stored in mask[se * max_sh + sh].
 111  */
 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 113 {
 114         unsigned se, sh, cu;
 115         const char *p;
 116
 117         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 118
 119         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 120                 return;
 121
 122         p = amdgpu_disable_cu;
 123         for (;;) {
 124                 char *next;
 125                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 126                 if (ret < 3) {
 127                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 128                         return;
 129                 }
 130
 131                 if (se < max_se && sh < max_sh && cu < 16) {
 132                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 133                         mask[se * max_sh + sh] |= 1u << cu;
 134                 } else {
 135                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 136                                   se, sh, cu);
 137                 }
 138
 139                 next = strchr(p, ',');
 140                 if (!next)
 141                         break;
 142                 p = next + 1;
 143         }
 144 }
 145
 146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 147 {
 148         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 149 }
 150
 151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 152 {
 153         if (amdgpu_compute_multipipe != -1) {
 154                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 155                          amdgpu_compute_multipipe);
 156                 return amdgpu_compute_multipipe == 1;
 157         }
 158
 159         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 160                 return true;
 161
 162         /* FIXME: spreading the queues across pipes causes perf regressions
 163          * on POLARIS11 compute workloads */
 164         if (adev->asic_type == CHIP_POLARIS11)
 165                 return false;
 166
 167         return adev->gfx.mec.num_mec > 1;
 168 }
 169
 170 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 171                                                 struct amdgpu_ring *ring)
 172 {
 173         int queue = ring->queue;
 174         int pipe = ring->pipe;
 175
 176         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 177          * have more than one gfx pipe.
 178          */
 179         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 180             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 181                 int me = ring->me;
 182                 int bit;
 183
 184                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 185                 if (ring == &adev->gfx.gfx_ring[bit])
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 193                                                struct amdgpu_ring *ring)
 194 {
 195         /* Policy: use 1st queue as high priority compute queue if we
 196          * have more than one compute queue.
 197          */
 198         if (adev->gfx.num_compute_rings > 1 &&
 199             ring == &adev->gfx.compute_ring[0])
 200                 return true;
 201
 202         return false;
 203 }
 204
 205 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 206 {
 207         int i, j, queue, pipe;
 208         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 209         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 210                                      adev->gfx.mec.num_queue_per_pipe,
 211                                      adev->gfx.num_compute_rings);
 212         int num_xcd = (adev->gfx.num_xcd > 1) ? adev->gfx.num_xcd : 1;
 213
 214         if (multipipe_policy) {
 215                 /* policy: make queues evenly cross all pipes on MEC1 only
 216                  * for multiple xcc, just use the original policy for simplicity */
 217                 for (j = 0; j < num_xcd; j++) {
 218                         for (i = 0; i < max_queues_per_mec; i++) {
 219                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 220                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 221                                          adev->gfx.mec.num_queue_per_pipe;
 222
 223                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 224                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 225                         }
 226                 }
 227         } else {
 228                 /* policy: amdgpu owns all queues in the given pipe */
 229                 for (j = 0; j < num_xcd; j++) {
 230                         for (i = 0; i < max_queues_per_mec; ++i)
 231                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 232                 }
 233         }
 234
 235         for (j = 0; j < num_xcd; j++) {
 236                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 237                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 238         }
 239 }
 240
 241 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 242 {
 243         int i, queue, pipe;
 244         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 245         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 246                                         adev->gfx.me.num_queue_per_pipe;
 247
 248         if (multipipe_policy) {
 249                 /* policy: amdgpu owns the first queue per pipe at this stage
 250                  * will extend to mulitple queues per pipe later */
 251                 for (i = 0; i < max_queues_per_me; i++) {
 252                         pipe = i % adev->gfx.me.num_pipe_per_me;
 253                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 254                                 adev->gfx.me.num_queue_per_pipe;
 255
 256                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 257                                 adev->gfx.me.queue_bitmap);
 258                 }
 259         } else {
 260                 for (i = 0; i < max_queues_per_me; ++i)
 261                         set_bit(i, adev->gfx.me.queue_bitmap);
 262         }
 263
 264         /* update the number of active graphics rings */
 265         adev->gfx.num_gfx_rings =
 266                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 267 }
 268
 269 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 270                                   struct amdgpu_ring *ring)
 271 {
 272         int queue_bit;
 273         int mec, pipe, queue;
 274
 275         queue_bit = adev->gfx.mec.num_mec
 276                     * adev->gfx.mec.num_pipe_per_mec
 277                     * adev->gfx.mec.num_queue_per_pipe;
 278
 279         while (--queue_bit >= 0) {
 280                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[0].queue_bitmap))
 281                         continue;
 282
 283                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 284
 285                 /*
 286                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 287                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 288                  * only can be issued on queue 0.
 289                  */
 290                 if ((mec == 1 && pipe > 1) || queue != 0)
 291                         continue;
 292
 293                 ring->me = mec + 1;
 294                 ring->pipe = pipe;
 295                 ring->queue = queue;
 296
 297                 return 0;
 298         }
 299
 300         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 301         return -EINVAL;
 302 }
 303
 304 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 305                              struct amdgpu_ring *ring,
 306                              struct amdgpu_irq_src *irq)
 307 {
 308         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 309         int r = 0;
 310
 311         spin_lock_init(&kiq->ring_lock);
 312
 313         ring->adev = NULL;
 314         ring->ring_obj = NULL;
 315         ring->use_doorbell = true;
 316         ring->doorbell_index = adev->doorbell_index.kiq;
 317         ring->vm_hub = AMDGPU_GFXHUB_0;
 318
 319         r = amdgpu_gfx_kiq_acquire(adev, ring);
 320         if (r)
 321                 return r;
 322
 323         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 324         ring->no_scheduler = true;
 325         sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 326         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 327                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 328         if (r)
 329                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 330
 331         return r;
 332 }
 333
 334 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 335 {
 336         amdgpu_ring_fini(ring);
 337 }
 338
 339 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
 340 {
 341         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 342
 343         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 344 }
 345
 346 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 347                         unsigned hpd_size)
 348 {
 349         int r;
 350         u32 *hpd;
 351         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 352
 353         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 354                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 355                                     &kiq->eop_gpu_addr, (void **)&hpd);
 356         if (r) {
 357                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 358                 return r;
 359         }
 360
 361         memset(hpd, 0, hpd_size);
 362
 363         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 364         if (unlikely(r != 0))
 365                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 366         amdgpu_bo_kunmap(kiq->eop_obj);
 367         amdgpu_bo_unreserve(kiq->eop_obj);
 368
 369         return 0;
 370 }
 371
 372 /* create MQD for each compute/gfx queue */
 373 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 374                            unsigned mqd_size)
 375 {
 376         struct amdgpu_ring *ring = NULL;
 377         int r, i;
 378
 379         /* create MQD for KIQ */
 380         ring = &adev->gfx.kiq[0].ring;
 381         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 382                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 383                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 384                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 385                  * KIQ MQD no matter SRIOV or Bare-metal
 386                  */
 387                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 388                                             AMDGPU_GEM_DOMAIN_VRAM |
 389                                             AMDGPU_GEM_DOMAIN_GTT,
 390                                             &ring->mqd_obj,
 391                                             &ring->mqd_gpu_addr,
 392                                             &ring->mqd_ptr);
 393                 if (r) {
 394                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 395                         return r;
 396                 }
 397
 398                 /* prepare MQD backup */
 399                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
 400                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
 401                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 402         }
 403
 404         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 405                 /* create MQD for each KGQ */
 406                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 407                         ring = &adev->gfx.gfx_ring[i];
 408                         if (!ring->mqd_obj) {
 409                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 410                                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 411                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 412                                 if (r) {
 413                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 414                                         return r;
 415                                 }
 416
 417                                 /* prepare MQD backup */
 418                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 419                                 if (!adev->gfx.me.mqd_backup[i])
 420                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 421                         }
 422                 }
 423         }
 424
 425         /* create MQD for each KCQ */
 426         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 427                 ring = &adev->gfx.compute_ring[i];
 428                 if (!ring->mqd_obj) {
 429                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 430                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 431                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 432                         if (r) {
 433                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 434                                 return r;
 435                         }
 436
 437                         /* prepare MQD backup */
 438                         adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 439                         if (!adev->gfx.mec.mqd_backup[i])
 440                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 441                 }
 442         }
 443
 444         return 0;
 445 }
 446
 447 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
 448 {
 449         struct amdgpu_ring *ring = NULL;
 450         int i;
 451
 452         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 453                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 454                         ring = &adev->gfx.gfx_ring[i];
 455                         kfree(adev->gfx.me.mqd_backup[i]);
 456                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 457                                               &ring->mqd_gpu_addr,
 458                                               &ring->mqd_ptr);
 459                 }
 460         }
 461
 462         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 463                 ring = &adev->gfx.compute_ring[i];
 464                 kfree(adev->gfx.mec.mqd_backup[i]);
 465                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 466                                       &ring->mqd_gpu_addr,
 467                                       &ring->mqd_ptr);
 468         }
 469
 470         ring = &adev->gfx.kiq[0].ring;
 471         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 472         amdgpu_bo_free_kernel(&ring->mqd_obj,
 473                               &ring->mqd_gpu_addr,
 474                               &ring->mqd_ptr);
 475 }
 476
 477 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
 478 {
 479         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 480         struct amdgpu_ring *kiq_ring = &kiq->ring;
 481         int i, r = 0;
 482
 483         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 484                 return -EINVAL;
 485
 486         spin_lock(&adev->gfx.kiq[0].ring_lock);
 487         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 488                                         adev->gfx.num_compute_rings)) {
 489                 spin_unlock(&adev->gfx.kiq[0].ring_lock);
 490                 return -ENOMEM;
 491         }
 492
 493         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 494                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
 495                                            RESET_QUEUES, 0, 0);
 496
 497         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 498                 r = amdgpu_ring_test_helper(kiq_ring);
 499         spin_unlock(&adev->gfx.kiq[0].ring_lock);
 500
 501         return r;
 502 }
 503
 504 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 505                                         int queue_bit)
 506 {
 507         int mec, pipe, queue;
 508         int set_resource_bit = 0;
 509
 510         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 511
 512         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 513
 514         return set_resource_bit;
 515 }
 516
 517 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
 518 {
 519         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 520         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
 521         uint64_t queue_mask = 0;
 522         int r, i;
 523
 524         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 525                 return -EINVAL;
 526
 527         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 528                 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))
 529                         continue;
 530
 531                 /* This situation may be hit in the future if a new HW
 532                  * generation exposes more than 64 queues. If so, the
 533                  * definition of queue_mask needs updating */
 534                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 535                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 536                         break;
 537                 }
 538
 539                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 540         }
 541
 542         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 543                                                         kiq_ring->queue);
 544         spin_lock(&adev->gfx.kiq[0].ring_lock);
 545         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 546                                         adev->gfx.num_compute_rings +
 547                                         kiq->pmf->set_resources_size);
 548         if (r) {
 549                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 550                 spin_unlock(&adev->gfx.kiq[0].ring_lock);
 551                 return r;
 552         }
 553
 554         if (adev->enable_mes)
 555                 queue_mask = ~0ULL;
 556
 557         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 558         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 559                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
 560
 561         r = amdgpu_ring_test_helper(kiq_ring);
 562         spin_unlock(&adev->gfx.kiq[0].ring_lock);
 563         if (r)
 564                 DRM_ERROR("KCQ enable failed\n");
 565
 566         return r;
 567 }
 568
 569 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 570  *
 571  * @adev: amdgpu_device pointer
 572  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 573  *
 574  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 575  * 2. other client can send request to disable gfx off feature, the request should be honored.
 576  * 3. other client can cancel their request of disable gfx off feature
 577  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 578  */
 579
 580 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 581 {
 582         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 583
 584         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 585                 return;
 586
 587         mutex_lock(&adev->gfx.gfx_off_mutex);
 588
 589         if (enable) {
 590                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 591                  * Note that the bug may be in a different caller than the one which triggers the
 592                  * WARN_ON_ONCE.
 593                  */
 594                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 595                         goto unlock;
 596
 597                 adev->gfx.gfx_off_req_count--;
 598
 599                 if (adev->gfx.gfx_off_req_count == 0 &&
 600                     !adev->gfx.gfx_off_state) {
 601                         /* If going to s2idle, no need to wait */
 602                         if (adev->in_s0ix) {
 603                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 604                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 605                                         adev->gfx.gfx_off_state = true;
 606                         } else {
 607                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 608                                               delay);
 609                         }
 610                 }
 611         } else {
 612                 if (adev->gfx.gfx_off_req_count == 0) {
 613                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 614
 615                         if (adev->gfx.gfx_off_state &&
 616                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 617                                 adev->gfx.gfx_off_state = false;
 618
 619                                 if (adev->gfx.funcs->init_spm_golden) {
 620                                         dev_dbg(adev->dev,
 621                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 622                                         amdgpu_gfx_init_spm_golden(adev);
 623                                 }
 624                         }
 625                 }
 626
 627                 adev->gfx.gfx_off_req_count++;
 628         }
 629
 630 unlock:
 631         mutex_unlock(&adev->gfx.gfx_off_mutex);
 632 }
 633
 634 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 635 {
 636         int r = 0;
 637
 638         mutex_lock(&adev->gfx.gfx_off_mutex);
 639
 640         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 641
 642         mutex_unlock(&adev->gfx.gfx_off_mutex);
 643
 644         return r;
 645 }
 646
 647 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 648 {
 649         int r = 0;
 650
 651         mutex_lock(&adev->gfx.gfx_off_mutex);
 652
 653         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 654
 655         mutex_unlock(&adev->gfx.gfx_off_mutex);
 656
 657         return r;
 658 }
 659
 660 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 661 {
 662         int r = 0;
 663
 664         mutex_lock(&adev->gfx.gfx_off_mutex);
 665
 666         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 667
 668         mutex_unlock(&adev->gfx.gfx_off_mutex);
 669
 670         return r;
 671 }
 672
 673 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 674 {
 675
 676         int r = 0;
 677
 678         mutex_lock(&adev->gfx.gfx_off_mutex);
 679
 680         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 681
 682         mutex_unlock(&adev->gfx.gfx_off_mutex);
 683
 684         return r;
 685 }
 686
 687 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 688 {
 689         int r;
 690
 691         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 692                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 693                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 694
 695                 r = amdgpu_ras_block_late_init(adev, ras_block);
 696                 if (r)
 697                         return r;
 698
 699                 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 700                 if (r)
 701                         goto late_fini;
 702         } else {
 703                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 704         }
 705
 706         return 0;
 707 late_fini:
 708         amdgpu_ras_block_late_fini(adev, ras_block);
 709         return r;
 710 }
 711
 712 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 713 {
 714         int err = 0;
 715         struct amdgpu_gfx_ras *ras = NULL;
 716
 717         /* adev->gfx.ras is NULL, which means gfx does not
 718          * support ras function, then do nothing here.
 719          */
 720         if (!adev->gfx.ras)
 721                 return 0;
 722
 723         ras = adev->gfx.ras;
 724
 725         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 726         if (err) {
 727                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 728                 return err;
 729         }
 730
 731         strcpy(ras->ras_block.ras_comm.name, "gfx");
 732         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 733         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 734         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 735
 736         /* If not define special ras_late_init function, use gfx default ras_late_init */
 737         if (!ras->ras_block.ras_late_init)
 738                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 739
 740         /* If not defined special ras_cb function, use default ras_cb */
 741         if (!ras->ras_block.ras_cb)
 742                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 743
 744         return 0;
 745 }
 746
 747 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 748                                                 struct amdgpu_iv_entry *entry)
 749 {
 750         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 751                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 752
 753         return 0;
 754 }
 755
 756 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 757                 void *err_data,
 758                 struct amdgpu_iv_entry *entry)
 759 {
 760         /* TODO ue will trigger an interrupt.
 761          *
 762          * When “Full RAS” is enabled, the per-IP interrupt sources should
 763          * be disabled and the driver should only look for the aggregated
 764          * interrupt via sync flood
 765          */
 766         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 767                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 768                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 769                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 770                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 771                 amdgpu_ras_reset_gpu(adev);
 772         }
 773         return AMDGPU_RAS_SUCCESS;
 774 }
 775
 776 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 777                                   struct amdgpu_irq_src *source,
 778                                   struct amdgpu_iv_entry *entry)
 779 {
 780         struct ras_common_if *ras_if = adev->gfx.ras_if;
 781         struct ras_dispatch_if ih_data = {
 782                 .entry = entry,
 783         };
 784
 785         if (!ras_if)
 786                 return 0;
 787
 788         ih_data.head = *ras_if;
 789
 790         DRM_ERROR("CP ECC ERROR IRQ\n");
 791         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 792         return 0;
 793 }
 794
 795 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 796 {
 797         signed long r, cnt = 0;
 798         unsigned long flags;
 799         uint32_t seq, reg_val_offs = 0, value = 0;
 800         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 801         struct amdgpu_ring *ring = &kiq->ring;
 802
 803         if (amdgpu_device_skip_hw_access(adev))
 804                 return 0;
 805
 806         if (adev->mes.ring.sched.ready)
 807                 return amdgpu_mes_rreg(adev, reg);
 808
 809         BUG_ON(!ring->funcs->emit_rreg);
 810
 811         spin_lock_irqsave(&kiq->ring_lock, flags);
 812         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 813                 pr_err("critical bug! too many kiq readers\n");
 814                 goto failed_unlock;
 815         }
 816         amdgpu_ring_alloc(ring, 32);
 817         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 818         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 819         if (r)
 820                 goto failed_undo;
 821
 822         amdgpu_ring_commit(ring);
 823         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 824
 825         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 826
 827         /* don't wait anymore for gpu reset case because this way may
 828          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 829          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 830          * never return if we keep waiting in virt_kiq_rreg, which cause
 831          * gpu_recover() hang there.
 832          *
 833          * also don't wait anymore for IRQ context
 834          * */
 835         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 836                 goto failed_kiq_read;
 837
 838         might_sleep();
 839         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 840                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 841                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 842         }
 843
 844         if (cnt > MAX_KIQ_REG_TRY)
 845                 goto failed_kiq_read;
 846
 847         mb();
 848         value = adev->wb.wb[reg_val_offs];
 849         amdgpu_device_wb_free(adev, reg_val_offs);
 850         return value;
 851
 852 failed_undo:
 853         amdgpu_ring_undo(ring);
 854 failed_unlock:
 855         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 856 failed_kiq_read:
 857         if (reg_val_offs)
 858                 amdgpu_device_wb_free(adev, reg_val_offs);
 859         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 860         return ~0;
 861 }
 862
 863 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 864 {
 865         signed long r, cnt = 0;
 866         unsigned long flags;
 867         uint32_t seq;
 868         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 869         struct amdgpu_ring *ring = &kiq->ring;
 870
 871         BUG_ON(!ring->funcs->emit_wreg);
 872
 873         if (amdgpu_device_skip_hw_access(adev))
 874                 return;
 875
 876         if (adev->mes.ring.sched.ready) {
 877                 amdgpu_mes_wreg(adev, reg, v);
 878                 return;
 879         }
 880
 881         spin_lock_irqsave(&kiq->ring_lock, flags);
 882         amdgpu_ring_alloc(ring, 32);
 883         amdgpu_ring_emit_wreg(ring, reg, v);
 884         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 885         if (r)
 886                 goto failed_undo;
 887
 888         amdgpu_ring_commit(ring);
 889         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 890
 891         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 892
 893         /* don't wait anymore for gpu reset case because this way may
 894          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 895          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 896          * never return if we keep waiting in virt_kiq_rreg, which cause
 897          * gpu_recover() hang there.
 898          *
 899          * also don't wait anymore for IRQ context
 900          * */
 901         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 902                 goto failed_kiq_write;
 903
 904         might_sleep();
 905         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 906
 907                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 908                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 909         }
 910
 911         if (cnt > MAX_KIQ_REG_TRY)
 912                 goto failed_kiq_write;
 913
 914         return;
 915
 916 failed_undo:
 917         amdgpu_ring_undo(ring);
 918         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 919 failed_kiq_write:
 920         dev_err(adev->dev, "failed to write reg:%x\n", reg);
 921 }
 922
 923 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
 924 {
 925         if (amdgpu_num_kcq == -1) {
 926                 return 8;
 927         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
 928                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
 929                 return 8;
 930         }
 931         return amdgpu_num_kcq;
 932 }
 933
 934 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
 935                                   uint32_t ucode_id)
 936 {
 937         const struct gfx_firmware_header_v1_0 *cp_hdr;
 938         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
 939         struct amdgpu_firmware_info *info = NULL;
 940         const struct firmware *ucode_fw;
 941         unsigned int fw_size;
 942
 943         switch (ucode_id) {
 944         case AMDGPU_UCODE_ID_CP_PFP:
 945                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 946                         adev->gfx.pfp_fw->data;
 947                 adev->gfx.pfp_fw_version =
 948                         le32_to_cpu(cp_hdr->header.ucode_version);
 949                 adev->gfx.pfp_feature_version =
 950                         le32_to_cpu(cp_hdr->ucode_feature_version);
 951                 ucode_fw = adev->gfx.pfp_fw;
 952                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 953                 break;
 954         case AMDGPU_UCODE_ID_CP_RS64_PFP:
 955                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 956                         adev->gfx.pfp_fw->data;
 957                 adev->gfx.pfp_fw_version =
 958                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
 959                 adev->gfx.pfp_feature_version =
 960                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
 961                 ucode_fw = adev->gfx.pfp_fw;
 962                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
 963                 break;
 964         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
 965         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
 966                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 967                         adev->gfx.pfp_fw->data;
 968                 ucode_fw = adev->gfx.pfp_fw;
 969                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
 970                 break;
 971         case AMDGPU_UCODE_ID_CP_ME:
 972                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 973                         adev->gfx.me_fw->data;
 974                 adev->gfx.me_fw_version =
 975                         le32_to_cpu(cp_hdr->header.ucode_version);
 976                 adev->gfx.me_feature_version =
 977                         le32_to_cpu(cp_hdr->ucode_feature_version);
 978                 ucode_fw = adev->gfx.me_fw;
 979                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 980                 break;
 981         case AMDGPU_UCODE_ID_CP_RS64_ME:
 982                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 983                         adev->gfx.me_fw->data;
 984                 adev->gfx.me_fw_version =
 985                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
 986                 adev->gfx.me_feature_version =
 987                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
 988                 ucode_fw = adev->gfx.me_fw;
 989                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
 990                 break;
 991         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
 992         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
 993                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 994                         adev->gfx.me_fw->data;
 995                 ucode_fw = adev->gfx.me_fw;
 996                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
 997                 break;
 998         case AMDGPU_UCODE_ID_CP_CE:
 999                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1000                         adev->gfx.ce_fw->data;
1001                 adev->gfx.ce_fw_version =
1002                         le32_to_cpu(cp_hdr->header.ucode_version);
1003                 adev->gfx.ce_feature_version =
1004                         le32_to_cpu(cp_hdr->ucode_feature_version);
1005                 ucode_fw = adev->gfx.ce_fw;
1006                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1007                 break;
1008         case AMDGPU_UCODE_ID_CP_MEC1:
1009                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1010                         adev->gfx.mec_fw->data;
1011                 adev->gfx.mec_fw_version =
1012                         le32_to_cpu(cp_hdr->header.ucode_version);
1013                 adev->gfx.mec_feature_version =
1014                         le32_to_cpu(cp_hdr->ucode_feature_version);
1015                 ucode_fw = adev->gfx.mec_fw;
1016                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1017                           le32_to_cpu(cp_hdr->jt_size) * 4;
1018                 break;
1019         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1020                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1021                         adev->gfx.mec_fw->data;
1022                 ucode_fw = adev->gfx.mec_fw;
1023                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1024                 break;
1025         case AMDGPU_UCODE_ID_CP_MEC2:
1026                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1027                         adev->gfx.mec2_fw->data;
1028                 adev->gfx.mec2_fw_version =
1029                         le32_to_cpu(cp_hdr->header.ucode_version);
1030                 adev->gfx.mec2_feature_version =
1031                         le32_to_cpu(cp_hdr->ucode_feature_version);
1032                 ucode_fw = adev->gfx.mec2_fw;
1033                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1034                           le32_to_cpu(cp_hdr->jt_size) * 4;
1035                 break;
1036         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1037                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1038                         adev->gfx.mec2_fw->data;
1039                 ucode_fw = adev->gfx.mec2_fw;
1040                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1041                 break;
1042         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1043                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1044                         adev->gfx.mec_fw->data;
1045                 adev->gfx.mec_fw_version =
1046                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1047                 adev->gfx.mec_feature_version =
1048                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1049                 ucode_fw = adev->gfx.mec_fw;
1050                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1051                 break;
1052         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1053         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1054         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1055         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1056                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1057                         adev->gfx.mec_fw->data;
1058                 ucode_fw = adev->gfx.mec_fw;
1059                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1060                 break;
1061         default:
1062                 break;
1063         }
1064
1065         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1066                 info = &adev->firmware.ucode[ucode_id];
1067                 info->ucode_id = ucode_id;
1068                 info->fw = ucode_fw;
1069                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1070         }
1071 }