drivers/gpu/drm/udl/udl_modeset.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Red Hat
   4  *
   5  * based in parts on udlfb.c:
   6  * Copyright (C) 2009 Roberto De Ioris <[email protected]>
   7  * Copyright (C) 2009 Jaya Kumar <[email protected]>
   8  * Copyright (C) 2009 Bernie Thompson <[email protected]>
   9  */
  10
  11 #include <drm/drm_atomic_helper.h>
  12 #include <drm/drm_crtc_helper.h>
  13 #include <drm/drm_damage_helper.h>
  14 #include <drm/drm_fourcc.h>
  15 #include <drm/drm_gem_atomic_helper.h>
  16 #include <drm/drm_gem_framebuffer_helper.h>
  17 #include <drm/drm_gem_shmem_helper.h>
  18 #include <drm/drm_modeset_helper_vtables.h>
  19 #include <drm/drm_vblank.h>
  20
  21 #include "udl_drv.h"
  22
  23 #define UDL_COLOR_DEPTH_16BPP   0
  24
  25 /*
  26  * All DisplayLink bulk operations start with 0xAF, followed by specific code
  27  * All operations are written to buffers which then later get sent to device
  28  */
  29 static char *udl_set_register(char *buf, u8 reg, u8 val)
  30 {
  31         *buf++ = 0xAF;
  32         *buf++ = 0x20;
  33         *buf++ = reg;
  34         *buf++ = val;
  35         return buf;
  36 }
  37
  38 static char *udl_vidreg_lock(char *buf)
  39 {
  40         return udl_set_register(buf, 0xFF, 0x00);
  41 }
  42
  43 static char *udl_vidreg_unlock(char *buf)
  44 {
  45         return udl_set_register(buf, 0xFF, 0xFF);
  46 }
  47
  48 static char *udl_set_blank_mode(char *buf, u8 mode)
  49 {
  50         return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
  51 }
  52
  53 static char *udl_set_color_depth(char *buf, u8 selection)
  54 {
  55         return udl_set_register(buf, 0x00, selection);
  56 }
  57
  58 static char *udl_set_base16bpp(char *wrptr, u32 base)
  59 {
  60         /* the base pointer is 16 bits wide, 0x20 is hi byte. */
  61         wrptr = udl_set_register(wrptr, 0x20, base >> 16);
  62         wrptr = udl_set_register(wrptr, 0x21, base >> 8);
  63         return udl_set_register(wrptr, 0x22, base);
  64 }
  65
  66 /*
  67  * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
  68  * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
  69  */
  70 static char *udl_set_base8bpp(char *wrptr, u32 base)
  71 {
  72         wrptr = udl_set_register(wrptr, 0x26, base >> 16);
  73         wrptr = udl_set_register(wrptr, 0x27, base >> 8);
  74         return udl_set_register(wrptr, 0x28, base);
  75 }
  76
  77 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
  78 {
  79         wrptr = udl_set_register(wrptr, reg, value >> 8);
  80         return udl_set_register(wrptr, reg+1, value);
  81 }
  82
  83 /*
  84  * This is kind of weird because the controller takes some
  85  * register values in a different byte order than other registers.
  86  */
  87 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
  88 {
  89         wrptr = udl_set_register(wrptr, reg, value);
  90         return udl_set_register(wrptr, reg+1, value >> 8);
  91 }
  92
  93 /*
  94  * LFSR is linear feedback shift register. The reason we have this is
  95  * because the display controller needs to minimize the clock depth of
  96  * various counters used in the display path. So this code reverses the
  97  * provided value into the lfsr16 value by counting backwards to get
  98  * the value that needs to be set in the hardware comparator to get the
  99  * same actual count. This makes sense once you read above a couple of
 100  * times and think about it from a hardware perspective.
 101  */
 102 static u16 udl_lfsr16(u16 actual_count)
 103 {
 104         u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
 105
 106         while (actual_count--) {
 107                 lv =     ((lv << 1) |
 108                         (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
 109                         & 0xFFFF;
 110         }
 111
 112         return (u16) lv;
 113 }
 114
 115 /*
 116  * This does LFSR conversion on the value that is to be written.
 117  * See LFSR explanation above for more detail.
 118  */
 119 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
 120 {
 121         return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
 122 }
 123
 124 /*
 125  * This takes a standard fbdev screeninfo struct and all of its monitor mode
 126  * details and converts them into the DisplayLink equivalent register commands.
 127   ERR(vreg(dev,               0x00, (color_depth == 16) ? 0 : 1));
 128   ERR(vreg_lfsr16(dev,        0x01, xDisplayStart));
 129   ERR(vreg_lfsr16(dev,        0x03, xDisplayEnd));
 130   ERR(vreg_lfsr16(dev,        0x05, yDisplayStart));
 131   ERR(vreg_lfsr16(dev,        0x07, yDisplayEnd));
 132   ERR(vreg_lfsr16(dev,        0x09, xEndCount));
 133   ERR(vreg_lfsr16(dev,        0x0B, hSyncStart));
 134   ERR(vreg_lfsr16(dev,        0x0D, hSyncEnd));
 135   ERR(vreg_big_endian(dev,    0x0F, hPixels));
 136   ERR(vreg_lfsr16(dev,        0x11, yEndCount));
 137   ERR(vreg_lfsr16(dev,        0x13, vSyncStart));
 138   ERR(vreg_lfsr16(dev,        0x15, vSyncEnd));
 139   ERR(vreg_big_endian(dev,    0x17, vPixels));
 140   ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
 141
 142   ERR(vreg(dev,               0x1F, 0));
 143
 144   ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
 145  */
 146 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
 147 {
 148         u16 xds, yds;
 149         u16 xde, yde;
 150         u16 yec;
 151
 152         /* x display start */
 153         xds = mode->crtc_htotal - mode->crtc_hsync_start;
 154         wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
 155         /* x display end */
 156         xde = xds + mode->crtc_hdisplay;
 157         wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
 158
 159         /* y display start */
 160         yds = mode->crtc_vtotal - mode->crtc_vsync_start;
 161         wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
 162         /* y display end */
 163         yde = yds + mode->crtc_vdisplay;
 164         wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
 165
 166         /* x end count is active + blanking - 1 */
 167         wrptr = udl_set_register_lfsr16(wrptr, 0x09,
 168                                         mode->crtc_htotal - 1);
 169
 170         /* libdlo hardcodes hsync start to 1 */
 171         wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
 172
 173         /* hsync end is width of sync pulse + 1 */
 174         wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
 175                                         mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
 176
 177         /* hpixels is active pixels */
 178         wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
 179
 180         /* yendcount is vertical active + vertical blanking */
 181         yec = mode->crtc_vtotal;
 182         wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
 183
 184         /* libdlo hardcodes vsync start to 0 */
 185         wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
 186
 187         /* vsync end is width of vsync pulse */
 188         wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
 189
 190         /* vpixels is active pixels */
 191         wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
 192
 193         wrptr = udl_set_register_16be(wrptr, 0x1B,
 194                                       mode->clock / 5);
 195
 196         return wrptr;
 197 }
 198
 199 static char *udl_dummy_render(char *wrptr)
 200 {
 201         *wrptr++ = 0xAF;
 202         *wrptr++ = 0x6A; /* copy */
 203         *wrptr++ = 0x00; /* from addr */
 204         *wrptr++ = 0x00;
 205         *wrptr++ = 0x00;
 206         *wrptr++ = 0x01; /* one pixel */
 207         *wrptr++ = 0x00; /* to address */
 208         *wrptr++ = 0x00;
 209         *wrptr++ = 0x00;
 210         return wrptr;
 211 }
 212
 213 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
 214 {
 215         struct drm_device *dev = crtc->dev;
 216         struct udl_device *udl = to_udl(dev);
 217         struct urb *urb;
 218         char *buf;
 219         int retval;
 220
 221         if (udl->mode_buf_len == 0) {
 222                 DRM_ERROR("No mode set\n");
 223                 return -EINVAL;
 224         }
 225
 226         urb = udl_get_urb(dev);
 227         if (!urb)
 228                 return -ENOMEM;
 229
 230         buf = (char *)urb->transfer_buffer;
 231
 232         memcpy(buf, udl->mode_buf, udl->mode_buf_len);
 233         retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
 234         DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
 235         return retval;
 236 }
 237
 238 static long udl_log_cpp(unsigned int cpp)
 239 {
 240         if (WARN_ON(!is_power_of_2(cpp)))
 241                 return -EINVAL;
 242         return __ffs(cpp);
 243 }
 244
 245 static int udl_handle_damage(struct drm_framebuffer *fb,
 246                              const struct iosys_map *map,
 247                              const struct drm_rect *clip)
 248 {
 249         struct drm_device *dev = fb->dev;
 250         void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */
 251         int i, ret;
 252         char *cmd;
 253         struct urb *urb;
 254         int log_bpp;
 255
 256         ret = udl_log_cpp(fb->format->cpp[0]);
 257         if (ret < 0)
 258                 return ret;
 259         log_bpp = ret;
 260
 261         ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
 262         if (ret)
 263                 return ret;
 264
 265         urb = udl_get_urb(dev);
 266         if (!urb) {
 267                 ret = -ENOMEM;
 268                 goto out_drm_gem_fb_end_cpu_access;
 269         }
 270         cmd = urb->transfer_buffer;
 271
 272         for (i = clip->y1; i < clip->y2; i++) {
 273                 const int line_offset = fb->pitches[0] * i;
 274                 const int byte_offset = line_offset + (clip->x1 << log_bpp);
 275                 const int dev_byte_offset = (fb->width * i + clip->x1) << log_bpp;
 276                 const int byte_width = drm_rect_width(clip) << log_bpp;
 277                 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
 278                                        &cmd, byte_offset, dev_byte_offset,
 279                                        byte_width);
 280                 if (ret)
 281                         goto out_drm_gem_fb_end_cpu_access;
 282         }
 283
 284         if (cmd > (char *)urb->transfer_buffer) {
 285                 /* Send partial buffer remaining before exiting */
 286                 int len;
 287                 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
 288                         *cmd++ = 0xAF;
 289                 len = cmd - (char *)urb->transfer_buffer;
 290                 ret = udl_submit_urb(dev, urb, len);
 291         } else {
 292                 udl_urb_completion(urb);
 293         }
 294
 295         ret = 0;
 296
 297 out_drm_gem_fb_end_cpu_access:
 298         drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
 299         return ret;
 300 }
 301
 302 /*
 303  * Simple display pipeline
 304  */
 305
 306 static const uint32_t udl_simple_display_pipe_formats[] = {
 307         DRM_FORMAT_RGB565,
 308         DRM_FORMAT_XRGB8888,
 309 };
 310
 311 static enum drm_mode_status
 312 udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
 313                                    const struct drm_display_mode *mode)
 314 {
 315         return MODE_OK;
 316 }
 317
 318 static void
 319 udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
 320                                struct drm_crtc_state *crtc_state,
 321                                struct drm_plane_state *plane_state)
 322 {
 323         struct drm_crtc *crtc = &pipe->crtc;
 324         struct drm_device *dev = crtc->dev;
 325         struct drm_framebuffer *fb = plane_state->fb;
 326         struct udl_device *udl = to_udl(dev);
 327         struct drm_display_mode *mode = &crtc_state->mode;
 328         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
 329         struct drm_rect clip = DRM_RECT_INIT(0, 0, fb->width, fb->height);
 330         char *buf;
 331         char *wrptr;
 332         int color_depth = UDL_COLOR_DEPTH_16BPP;
 333
 334         buf = (char *)udl->mode_buf;
 335
 336         /* This first section has to do with setting the base address on the
 337          * controller associated with the display. There are 2 base
 338          * pointers, currently, we only use the 16 bpp segment.
 339          */
 340         wrptr = udl_vidreg_lock(buf);
 341         wrptr = udl_set_color_depth(wrptr, color_depth);
 342         /* set base for 16bpp segment to 0 */
 343         wrptr = udl_set_base16bpp(wrptr, 0);
 344         /* set base for 8bpp segment to end of fb */
 345         wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
 346
 347         wrptr = udl_set_vid_cmds(wrptr, mode);
 348         wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
 349         wrptr = udl_vidreg_unlock(wrptr);
 350
 351         wrptr = udl_dummy_render(wrptr);
 352
 353         udl->mode_buf_len = wrptr - buf;
 354
 355         udl_handle_damage(fb, &shadow_plane_state->data[0], &clip);
 356
 357         /* enable display */
 358         udl_crtc_write_mode_to_hw(crtc);
 359 }
 360
 361 static void
 362 udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
 363 {
 364         struct drm_crtc *crtc = &pipe->crtc;
 365         struct drm_device *dev = crtc->dev;
 366         struct urb *urb;
 367         char *buf;
 368
 369         urb = udl_get_urb(dev);
 370         if (!urb)
 371                 return;
 372
 373         buf = (char *)urb->transfer_buffer;
 374         buf = udl_vidreg_lock(buf);
 375         buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
 376         buf = udl_vidreg_unlock(buf);
 377         buf = udl_dummy_render(buf);
 378
 379         udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
 380 }
 381
 382 static void
 383 udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
 384                                struct drm_plane_state *old_plane_state)
 385 {
 386         struct drm_plane_state *state = pipe->plane.state;
 387         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
 388         struct drm_framebuffer *fb = state->fb;
 389         struct drm_rect rect;
 390
 391         if (!fb)
 392                 return;
 393
 394         if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
 395                 udl_handle_damage(fb, &shadow_plane_state->data[0], &rect);
 396 }
 397
 398 static const struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
 399         .mode_valid = udl_simple_display_pipe_mode_valid,
 400         .enable = udl_simple_display_pipe_enable,
 401         .disable = udl_simple_display_pipe_disable,
 402         .update = udl_simple_display_pipe_update,
 403         DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS,
 404 };
 405
 406 /*
 407  * Modesetting
 408  */
 409
 410 static const struct drm_mode_config_funcs udl_mode_funcs = {
 411         .fb_create = drm_gem_fb_create_with_dirty,
 412         .atomic_check  = drm_atomic_helper_check,
 413         .atomic_commit = drm_atomic_helper_commit,
 414 };
 415
 416 int udl_modeset_init(struct drm_device *dev)
 417 {
 418         size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 419         struct udl_device *udl = to_udl(dev);
 420         struct drm_connector *connector;
 421         int ret;
 422
 423         ret = drmm_mode_config_init(dev);
 424         if (ret)
 425                 return ret;
 426
 427         dev->mode_config.min_width = 640;
 428         dev->mode_config.min_height = 480;
 429
 430         dev->mode_config.max_width = 2048;
 431         dev->mode_config.max_height = 2048;
 432
 433         dev->mode_config.prefer_shadow = 0;
 434         dev->mode_config.preferred_depth = 16;
 435
 436         dev->mode_config.funcs = &udl_mode_funcs;
 437
 438         connector = udl_connector_init(dev);
 439         if (IS_ERR(connector))
 440                 return PTR_ERR(connector);
 441
 442         format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
 443
 444         ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
 445                                            &udl_simple_display_pipe_funcs,
 446                                            udl_simple_display_pipe_formats,
 447                                            format_count, NULL, connector);
 448         if (ret)
 449                 return ret;
 450         drm_plane_enable_fb_damage_clips(&udl->display_pipe.plane);
 451
 452         drm_mode_config_reset(dev);
 453
 454         return 0;
 455 }