drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67
  68         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  70         {0, NULL},
  71 };
  72
  73 static const struct hwmon_temp_label {
  74         enum PP_HWMON_TEMP channel;
  75         const char *label;
  76 } temp_label[] = {
  77         {PP_TEMP_EDGE, "edge"},
  78         {PP_TEMP_JUNCTION, "junction"},
  79         {PP_TEMP_MEM, "mem"},
  80 };
  81
  82 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  83 {
  84         if (adev->pm.dpm_enabled) {
  85                 mutex_lock(&adev->pm.mutex);
  86                 if (power_supply_is_system_supplied() > 0)
  87                         adev->pm.ac_power = true;
  88                 else
  89                         adev->pm.ac_power = false;
  90                 if (adev->powerplay.pp_funcs->enable_bapm)
  91                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  92                 mutex_unlock(&adev->pm.mutex);
  93         }
  94 }
  95
  96 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  97                            void *data, uint32_t *size)
  98 {
  99         int ret = 0;
 100
 101         if (!data || !size)
 102                 return -EINVAL;
 103
 104         if (is_support_sw_smu(adev))
 105                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 106         else {
 107                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 108                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 109                                                                     sensor, data, size);
 110                 else
 111                         ret = -EINVAL;
 112         }
 113
 114         return ret;
 115 }
 116
 117 /**
 118  * DOC: power_dpm_state
 119  *
 120  * The power_dpm_state file is a legacy interface and is only provided for
 121  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 122  * certain power related parameters.  The file power_dpm_state is used for this.
 123  * It accepts the following arguments:
 124  *
 125  * - battery
 126  *
 127  * - balanced
 128  *
 129  * - performance
 130  *
 131  * battery
 132  *
 133  * On older GPUs, the vbios provided a special power state for battery
 134  * operation.  Selecting battery switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  * balanced
 138  *
 139  * On older GPUs, the vbios provided a special power state for balanced
 140  * operation.  Selecting balanced switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * performance
 144  *
 145  * On older GPUs, the vbios provided a special power state for performance
 146  * operation.  Selecting performance switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  */
 150
 151 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 152                                     struct device_attribute *attr,
 153                                     char *buf)
 154 {
 155         struct drm_device *ddev = dev_get_drvdata(dev);
 156         struct amdgpu_device *adev = ddev->dev_private;
 157         enum amd_pm_state_type pm;
 158
 159         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 160                 pm = amdgpu_smu_get_current_power_state(adev);
 161         else if (adev->powerplay.pp_funcs->get_current_power_state)
 162                 pm = amdgpu_dpm_get_current_power_state(adev);
 163         else
 164                 pm = adev->pm.dpm.user_state;
 165
 166         return snprintf(buf, PAGE_SIZE, "%s\n",
 167                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 168                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 169 }
 170
 171 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 172                                     struct device_attribute *attr,
 173                                     const char *buf,
 174                                     size_t count)
 175 {
 176         struct drm_device *ddev = dev_get_drvdata(dev);
 177         struct amdgpu_device *adev = ddev->dev_private;
 178         enum amd_pm_state_type  state;
 179
 180         if (strncmp("battery", buf, strlen("battery")) == 0)
 181                 state = POWER_STATE_TYPE_BATTERY;
 182         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 183                 state = POWER_STATE_TYPE_BALANCED;
 184         else if (strncmp("performance", buf, strlen("performance")) == 0)
 185                 state = POWER_STATE_TYPE_PERFORMANCE;
 186         else {
 187                 count = -EINVAL;
 188                 goto fail;
 189         }
 190
 191         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 192                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 193         } else {
 194                 mutex_lock(&adev->pm.mutex);
 195                 adev->pm.dpm.user_state = state;
 196                 mutex_unlock(&adev->pm.mutex);
 197
 198                 /* Can't set dpm state when the card is off */
 199                 if (!(adev->flags & AMD_IS_PX) ||
 200                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 201                         amdgpu_pm_compute_clocks(adev);
 202         }
 203 fail:
 204         return count;
 205 }
 206
 207
 208 /**
 209  * DOC: power_dpm_force_performance_level
 210  *
 211  * The amdgpu driver provides a sysfs API for adjusting certain power
 212  * related parameters.  The file power_dpm_force_performance_level is
 213  * used for this.  It accepts the following arguments:
 214  *
 215  * - auto
 216  *
 217  * - low
 218  *
 219  * - high
 220  *
 221  * - manual
 222  *
 223  * - profile_standard
 224  *
 225  * - profile_min_sclk
 226  *
 227  * - profile_min_mclk
 228  *
 229  * - profile_peak
 230  *
 231  * auto
 232  *
 233  * When auto is selected, the driver will attempt to dynamically select
 234  * the optimal power profile for current conditions in the driver.
 235  *
 236  * low
 237  *
 238  * When low is selected, the clocks are forced to the lowest power state.
 239  *
 240  * high
 241  *
 242  * When high is selected, the clocks are forced to the highest power state.
 243  *
 244  * manual
 245  *
 246  * When manual is selected, the user can manually adjust which power states
 247  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 248  * and pp_dpm_pcie files and adjust the power state transition heuristics
 249  * via the pp_power_profile_mode sysfs file.
 250  *
 251  * profile_standard
 252  * profile_min_sclk
 253  * profile_min_mclk
 254  * profile_peak
 255  *
 256  * When the profiling modes are selected, clock and power gating are
 257  * disabled and the clocks are set for different profiling cases. This
 258  * mode is recommended for profiling specific work loads where you do
 259  * not want clock or power gating for clock fluctuation to interfere
 260  * with your results. profile_standard sets the clocks to a fixed clock
 261  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 262  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 263  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 264  *
 265  */
 266
 267 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 268                                                 struct device_attribute *attr,
 269                                                                 char *buf)
 270 {
 271         struct drm_device *ddev = dev_get_drvdata(dev);
 272         struct amdgpu_device *adev = ddev->dev_private;
 273         enum amd_dpm_forced_level level = 0xff;
 274
 275         if (amdgpu_sriov_vf(adev))
 276                 return 0;
 277
 278         if ((adev->flags & AMD_IS_PX) &&
 279             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 280                 return snprintf(buf, PAGE_SIZE, "off\n");
 281
 282         if (is_support_sw_smu(adev))
 283                 level = smu_get_performance_level(&adev->smu);
 284         else if (adev->powerplay.pp_funcs->get_performance_level)
 285                 level = amdgpu_dpm_get_performance_level(adev);
 286         else
 287                 level = adev->pm.dpm.forced_level;
 288
 289         return snprintf(buf, PAGE_SIZE, "%s\n",
 290                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 291                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 292                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 293                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 294                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 295                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 296                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 297                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 298                         "unknown");
 299 }
 300
 301 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 302                                                        struct device_attribute *attr,
 303                                                        const char *buf,
 304                                                        size_t count)
 305 {
 306         struct drm_device *ddev = dev_get_drvdata(dev);
 307         struct amdgpu_device *adev = ddev->dev_private;
 308         enum amd_dpm_forced_level level;
 309         enum amd_dpm_forced_level current_level = 0xff;
 310         int ret = 0;
 311
 312         /* Can't force performance level when the card is off */
 313         if  ((adev->flags & AMD_IS_PX) &&
 314              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 315                 return -EINVAL;
 316
 317         if (!amdgpu_sriov_vf(adev)) {
 318                 if (is_support_sw_smu(adev))
 319                         current_level = smu_get_performance_level(&adev->smu);
 320                 else if (adev->powerplay.pp_funcs->get_performance_level)
 321                         current_level = amdgpu_dpm_get_performance_level(adev);
 322         }
 323
 324         if (strncmp("low", buf, strlen("low")) == 0) {
 325                 level = AMD_DPM_FORCED_LEVEL_LOW;
 326         } else if (strncmp("high", buf, strlen("high")) == 0) {
 327                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 328         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 329                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 330         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 331                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 332         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 333                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 334         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 335                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 336         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 337                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 338         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 339                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 340         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 341                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 342         }  else {
 343                 count = -EINVAL;
 344                 goto fail;
 345         }
 346
 347         if (amdgpu_sriov_vf(adev)) {
 348                 if (amdgim_is_hwperf(adev) &&
 349                     adev->virt.ops->force_dpm_level) {
 350                         mutex_lock(&adev->pm.mutex);
 351                         adev->virt.ops->force_dpm_level(adev, level);
 352                         mutex_unlock(&adev->pm.mutex);
 353                         return count;
 354                 } else {
 355                         return -EINVAL;
 356                 }
 357         }
 358
 359         if (current_level == level)
 360                 return count;
 361
 362         /* profile_exit setting is valid only when current mode is in profile mode */
 363         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 364             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 365             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 366             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 367             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 368                 pr_err("Currently not in any profile mode!\n");
 369                 return -EINVAL;
 370         }
 371
 372         if (is_support_sw_smu(adev)) {
 373                 mutex_lock(&adev->pm.mutex);
 374                 if (adev->pm.dpm.thermal_active) {
 375                         count = -EINVAL;
 376                         mutex_unlock(&adev->pm.mutex);
 377                         goto fail;
 378                 }
 379                 ret = smu_force_performance_level(&adev->smu, level);
 380                 if (ret)
 381                         count = -EINVAL;
 382                 else
 383                         adev->pm.dpm.forced_level = level;
 384                 mutex_unlock(&adev->pm.mutex);
 385         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 386                 mutex_lock(&adev->pm.mutex);
 387                 if (adev->pm.dpm.thermal_active) {
 388                         count = -EINVAL;
 389                         mutex_unlock(&adev->pm.mutex);
 390                         goto fail;
 391                 }
 392                 ret = amdgpu_dpm_force_performance_level(adev, level);
 393                 if (ret)
 394                         count = -EINVAL;
 395                 else
 396                         adev->pm.dpm.forced_level = level;
 397                 mutex_unlock(&adev->pm.mutex);
 398         }
 399
 400 fail:
 401         return count;
 402 }
 403
 404 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 405                 struct device_attribute *attr,
 406                 char *buf)
 407 {
 408         struct drm_device *ddev = dev_get_drvdata(dev);
 409         struct amdgpu_device *adev = ddev->dev_private;
 410         struct pp_states_info data;
 411         int i, buf_len, ret;
 412
 413         if (is_support_sw_smu(adev)) {
 414                 ret = smu_get_power_num_states(&adev->smu, &data);
 415                 if (ret)
 416                         return ret;
 417         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 418                 amdgpu_dpm_get_pp_num_states(adev, &data);
 419
 420         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 421         for (i = 0; i < data.nums; i++)
 422                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 423                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 424                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 425                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 426                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 427
 428         return buf_len;
 429 }
 430
 431 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 432                 struct device_attribute *attr,
 433                 char *buf)
 434 {
 435         struct drm_device *ddev = dev_get_drvdata(dev);
 436         struct amdgpu_device *adev = ddev->dev_private;
 437         struct pp_states_info data;
 438         struct smu_context *smu = &adev->smu;
 439         enum amd_pm_state_type pm = 0;
 440         int i = 0, ret = 0;
 441
 442         if (is_support_sw_smu(adev)) {
 443                 pm = smu_get_current_power_state(smu);
 444                 ret = smu_get_power_num_states(smu, &data);
 445                 if (ret)
 446                         return ret;
 447         } else if (adev->powerplay.pp_funcs->get_current_power_state
 448                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 449                 pm = amdgpu_dpm_get_current_power_state(adev);
 450                 amdgpu_dpm_get_pp_num_states(adev, &data);
 451         }
 452
 453         for (i = 0; i < data.nums; i++) {
 454                 if (pm == data.states[i])
 455                         break;
 456         }
 457
 458         if (i == data.nums)
 459                 i = -EINVAL;
 460
 461         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 462 }
 463
 464 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 465                 struct device_attribute *attr,
 466                 char *buf)
 467 {
 468         struct drm_device *ddev = dev_get_drvdata(dev);
 469         struct amdgpu_device *adev = ddev->dev_private;
 470
 471         if (adev->pp_force_state_enabled)
 472                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 473         else
 474                 return snprintf(buf, PAGE_SIZE, "\n");
 475 }
 476
 477 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 478                 struct device_attribute *attr,
 479                 const char *buf,
 480                 size_t count)
 481 {
 482         struct drm_device *ddev = dev_get_drvdata(dev);
 483         struct amdgpu_device *adev = ddev->dev_private;
 484         enum amd_pm_state_type state = 0;
 485         unsigned long idx;
 486         int ret;
 487
 488         if (strlen(buf) == 1)
 489                 adev->pp_force_state_enabled = false;
 490         else if (is_support_sw_smu(adev))
 491                 adev->pp_force_state_enabled = false;
 492         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 493                         adev->powerplay.pp_funcs->get_pp_num_states) {
 494                 struct pp_states_info data;
 495
 496                 ret = kstrtoul(buf, 0, &idx);
 497                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 498                         count = -EINVAL;
 499                         goto fail;
 500                 }
 501                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 502
 503                 amdgpu_dpm_get_pp_num_states(adev, &data);
 504                 state = data.states[idx];
 505                 /* only set user selected power states */
 506                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 507                     state != POWER_STATE_TYPE_DEFAULT) {
 508                         amdgpu_dpm_dispatch_task(adev,
 509                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 510                         adev->pp_force_state_enabled = true;
 511                 }
 512         }
 513 fail:
 514         return count;
 515 }
 516
 517 /**
 518  * DOC: pp_table
 519  *
 520  * The amdgpu driver provides a sysfs API for uploading new powerplay
 521  * tables.  The file pp_table is used for this.  Reading the file
 522  * will dump the current power play table.  Writing to the file
 523  * will attempt to upload a new powerplay table and re-initialize
 524  * powerplay using that new table.
 525  *
 526  */
 527
 528 static ssize_t amdgpu_get_pp_table(struct device *dev,
 529                 struct device_attribute *attr,
 530                 char *buf)
 531 {
 532         struct drm_device *ddev = dev_get_drvdata(dev);
 533         struct amdgpu_device *adev = ddev->dev_private;
 534         char *table = NULL;
 535         int size;
 536
 537         if (is_support_sw_smu(adev)) {
 538                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 539                 if (size < 0)
 540                         return size;
 541         }
 542         else if (adev->powerplay.pp_funcs->get_pp_table)
 543                 size = amdgpu_dpm_get_pp_table(adev, &table);
 544         else
 545                 return 0;
 546
 547         if (size >= PAGE_SIZE)
 548                 size = PAGE_SIZE - 1;
 549
 550         memcpy(buf, table, size);
 551
 552         return size;
 553 }
 554
 555 static ssize_t amdgpu_set_pp_table(struct device *dev,
 556                 struct device_attribute *attr,
 557                 const char *buf,
 558                 size_t count)
 559 {
 560         struct drm_device *ddev = dev_get_drvdata(dev);
 561         struct amdgpu_device *adev = ddev->dev_private;
 562         int ret = 0;
 563
 564         if (is_support_sw_smu(adev)) {
 565                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 566                 if (ret)
 567                         return ret;
 568         } else if (adev->powerplay.pp_funcs->set_pp_table)
 569                 amdgpu_dpm_set_pp_table(adev, buf, count);
 570
 571         return count;
 572 }
 573
 574 /**
 575  * DOC: pp_od_clk_voltage
 576  *
 577  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 578  * in each power level within a power state.  The pp_od_clk_voltage is used for
 579  * this.
 580  *
 581  * < For Vega10 and previous ASICs >
 582  *
 583  * Reading the file will display:
 584  *
 585  * - a list of engine clock levels and voltages labeled OD_SCLK
 586  *
 587  * - a list of memory clock levels and voltages labeled OD_MCLK
 588  *
 589  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 590  *
 591  * To manually adjust these settings, first select manual using
 592  * power_dpm_force_performance_level. Enter a new value for each
 593  * level by writing a string that contains "s/m level clock voltage" to
 594  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 595  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 596  * 810 mV.  When you have edited all of the states as needed, write
 597  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 598  * default power levels, write "r" (reset) to the file to reset them.
 599  *
 600  *
 601  * < For Vega20 >
 602  *
 603  * Reading the file will display:
 604  *
 605  * - minimum and maximum engine clock labeled OD_SCLK
 606  *
 607  * - maximum memory clock labeled OD_MCLK
 608  *
 609  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 610  *   They can be used to calibrate the sclk voltage curve.
 611  *
 612  * - a list of valid ranges for sclk, mclk, and voltage curve points
 613  *   labeled OD_RANGE
 614  *
 615  * To manually adjust these settings:
 616  *
 617  * - First select manual using power_dpm_force_performance_level
 618  *
 619  * - For clock frequency setting, enter a new value by writing a
 620  *   string that contains "s/m index clock" to the file. The index
 621  *   should be 0 if to set minimum clock. And 1 if to set maximum
 622  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 623  *   "m 1 800" will update maximum mclk to be 800Mhz.
 624  *
 625  *   For sclk voltage curve, enter the new values by writing a
 626  *   string that contains "vc point clock voltage" to the file. The
 627  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 628  *   update point1 with clock set as 300Mhz and voltage as
 629  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 630  *   as 1000Mhz and voltage 1000mV.
 631  *
 632  * - When you have edited all of the states as needed, write "c" (commit)
 633  *   to the file to commit your changes
 634  *
 635  * - If you want to reset to the default power levels, write "r" (reset)
 636  *   to the file to reset them
 637  *
 638  */
 639
 640 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 641                 struct device_attribute *attr,
 642                 const char *buf,
 643                 size_t count)
 644 {
 645         struct drm_device *ddev = dev_get_drvdata(dev);
 646         struct amdgpu_device *adev = ddev->dev_private;
 647         int ret;
 648         uint32_t parameter_size = 0;
 649         long parameter[64];
 650         char buf_cpy[128];
 651         char *tmp_str;
 652         char *sub_str;
 653         const char delimiter[3] = {' ', '\n', '\0'};
 654         uint32_t type;
 655
 656         if (count > 127)
 657                 return -EINVAL;
 658
 659         if (*buf == 's')
 660                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 661         else if (*buf == 'm')
 662                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 663         else if(*buf == 'r')
 664                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 665         else if (*buf == 'c')
 666                 type = PP_OD_COMMIT_DPM_TABLE;
 667         else if (!strncmp(buf, "vc", 2))
 668                 type = PP_OD_EDIT_VDDC_CURVE;
 669         else
 670                 return -EINVAL;
 671
 672         memcpy(buf_cpy, buf, count+1);
 673
 674         tmp_str = buf_cpy;
 675
 676         if (type == PP_OD_EDIT_VDDC_CURVE)
 677                 tmp_str++;
 678         while (isspace(*++tmp_str));
 679
 680         while (tmp_str[0]) {
 681                 sub_str = strsep(&tmp_str, delimiter);
 682                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 683                 if (ret)
 684                         return -EINVAL;
 685                 parameter_size++;
 686
 687                 while (isspace(*tmp_str))
 688                         tmp_str++;
 689         }
 690
 691         if (is_support_sw_smu(adev)) {
 692                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 693                                             parameter, parameter_size);
 694
 695                 if (ret)
 696                         return -EINVAL;
 697         } else {
 698                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 699                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 700                                                 parameter, parameter_size);
 701
 702                 if (ret)
 703                         return -EINVAL;
 704
 705                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 706                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 707                                 amdgpu_dpm_dispatch_task(adev,
 708                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 709                                                 NULL);
 710                                 return count;
 711                         } else {
 712                                 return -EINVAL;
 713                         }
 714                 }
 715         }
 716
 717         return count;
 718 }
 719
 720 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 721                 struct device_attribute *attr,
 722                 char *buf)
 723 {
 724         struct drm_device *ddev = dev_get_drvdata(dev);
 725         struct amdgpu_device *adev = ddev->dev_private;
 726         uint32_t size = 0;
 727
 728         if (is_support_sw_smu(adev)) {
 729                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 730                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 731                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 732                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 733                 return size;
 734         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 735                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 736                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 737                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 738                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 739                 return size;
 740         } else {
 741                 return snprintf(buf, PAGE_SIZE, "\n");
 742         }
 743
 744 }
 745
 746 /**
 747  * DOC: ppfeatures
 748  *
 749  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 750  * features to be enabled. The file ppfeatures is used for this. And
 751  * this is only available for Vega10 and later dGPUs.
 752  *
 753  * Reading back the file will show you the followings:
 754  * - Current ppfeature masks
 755  * - List of the all supported powerplay features with their naming,
 756  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 757  *
 758  * To manually enable or disable a specific feature, just set or clear
 759  * the corresponding bit from original ppfeature masks and input the
 760  * new ppfeature masks.
 761  */
 762 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 763                 struct device_attribute *attr,
 764                 const char *buf,
 765                 size_t count)
 766 {
 767         struct drm_device *ddev = dev_get_drvdata(dev);
 768         struct amdgpu_device *adev = ddev->dev_private;
 769         uint64_t featuremask;
 770         int ret;
 771
 772         ret = kstrtou64(buf, 0, &featuremask);
 773         if (ret)
 774                 return -EINVAL;
 775
 776         pr_debug("featuremask = 0x%llx\n", featuremask);
 777
 778         if (is_support_sw_smu(adev)) {
 779                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 780                 if (ret)
 781                         return -EINVAL;
 782         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 783                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 784                 if (ret)
 785                         return -EINVAL;
 786         }
 787
 788         return count;
 789 }
 790
 791 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 792                 struct device_attribute *attr,
 793                 char *buf)
 794 {
 795         struct drm_device *ddev = dev_get_drvdata(dev);
 796         struct amdgpu_device *adev = ddev->dev_private;
 797
 798         if (is_support_sw_smu(adev)) {
 799                 return smu_get_ppfeature_status(&adev->smu, buf);
 800         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 801                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 802
 803         return snprintf(buf, PAGE_SIZE, "\n");
 804 }
 805
 806 /**
 807  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 808  * pp_dpm_pcie
 809  *
 810  * The amdgpu driver provides a sysfs API for adjusting what power levels
 811  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 812  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 813  * this.
 814  *
 815  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 816  * Vega10 and later ASICs.
 817  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 818  *
 819  * Reading back the files will show you the available power levels within
 820  * the power state and the clock information for those levels.
 821  *
 822  * To manually adjust these states, first select manual using
 823  * power_dpm_force_performance_level.
 824  * Secondly,Enter a new value for each level by inputing a string that
 825  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 826  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 827  *
 828  * NOTE: change to the dcefclk max dpm level is not supported now
 829  */
 830
 831 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 832                 struct device_attribute *attr,
 833                 char *buf)
 834 {
 835         struct drm_device *ddev = dev_get_drvdata(dev);
 836         struct amdgpu_device *adev = ddev->dev_private;
 837
 838         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 839             adev->virt.ops->get_pp_clk)
 840                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 841
 842         if (is_support_sw_smu(adev))
 843                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 844         else if (adev->powerplay.pp_funcs->print_clock_levels)
 845                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 846         else
 847                 return snprintf(buf, PAGE_SIZE, "\n");
 848 }
 849
 850 /*
 851  * Worst case: 32 bits individually specified, in octal at 12 characters
 852  * per line (+1 for \n).
 853  */
 854 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 855
 856 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 857 {
 858         int ret;
 859         long level;
 860         char *sub_str = NULL;
 861         char *tmp;
 862         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 863         const char delimiter[3] = {' ', '\n', '\0'};
 864         size_t bytes;
 865
 866         *mask = 0;
 867
 868         bytes = min(count, sizeof(buf_cpy) - 1);
 869         memcpy(buf_cpy, buf, bytes);
 870         buf_cpy[bytes] = '\0';
 871         tmp = buf_cpy;
 872         while (tmp[0]) {
 873                 sub_str = strsep(&tmp, delimiter);
 874                 if (strlen(sub_str)) {
 875                         ret = kstrtol(sub_str, 0, &level);
 876                         if (ret)
 877                                 return -EINVAL;
 878                         *mask |= 1 << level;
 879                 } else
 880                         break;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 887                 struct device_attribute *attr,
 888                 const char *buf,
 889                 size_t count)
 890 {
 891         struct drm_device *ddev = dev_get_drvdata(dev);
 892         struct amdgpu_device *adev = ddev->dev_private;
 893         int ret;
 894         uint32_t mask = 0;
 895
 896         if (amdgpu_sriov_vf(adev))
 897                 return 0;
 898
 899         ret = amdgpu_read_mask(buf, count, &mask);
 900         if (ret)
 901                 return ret;
 902
 903         if (is_support_sw_smu(adev))
 904                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 905         else if (adev->powerplay.pp_funcs->force_clock_level)
 906                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 907
 908         if (ret)
 909                 return -EINVAL;
 910
 911         return count;
 912 }
 913
 914 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 915                 struct device_attribute *attr,
 916                 char *buf)
 917 {
 918         struct drm_device *ddev = dev_get_drvdata(dev);
 919         struct amdgpu_device *adev = ddev->dev_private;
 920
 921         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 922             adev->virt.ops->get_pp_clk)
 923                 return adev->virt.ops->get_pp_clk(adev, PP_MCLK, buf);
 924
 925         if (is_support_sw_smu(adev))
 926                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 927         else if (adev->powerplay.pp_funcs->print_clock_levels)
 928                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 929         else
 930                 return snprintf(buf, PAGE_SIZE, "\n");
 931 }
 932
 933 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 934                 struct device_attribute *attr,
 935                 const char *buf,
 936                 size_t count)
 937 {
 938         struct drm_device *ddev = dev_get_drvdata(dev);
 939         struct amdgpu_device *adev = ddev->dev_private;
 940         int ret;
 941         uint32_t mask = 0;
 942
 943         if (amdgpu_sriov_vf(adev))
 944                 return 0;
 945
 946         ret = amdgpu_read_mask(buf, count, &mask);
 947         if (ret)
 948                 return ret;
 949
 950         if (is_support_sw_smu(adev))
 951                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 952         else if (adev->powerplay.pp_funcs->force_clock_level)
 953                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 954
 955         if (ret)
 956                 return -EINVAL;
 957
 958         return count;
 959 }
 960
 961 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 962                 struct device_attribute *attr,
 963                 char *buf)
 964 {
 965         struct drm_device *ddev = dev_get_drvdata(dev);
 966         struct amdgpu_device *adev = ddev->dev_private;
 967
 968         if (is_support_sw_smu(adev))
 969                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 970         else if (adev->powerplay.pp_funcs->print_clock_levels)
 971                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 972         else
 973                 return snprintf(buf, PAGE_SIZE, "\n");
 974 }
 975
 976 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 977                 struct device_attribute *attr,
 978                 const char *buf,
 979                 size_t count)
 980 {
 981         struct drm_device *ddev = dev_get_drvdata(dev);
 982         struct amdgpu_device *adev = ddev->dev_private;
 983         int ret;
 984         uint32_t mask = 0;
 985
 986         ret = amdgpu_read_mask(buf, count, &mask);
 987         if (ret)
 988                 return ret;
 989
 990         if (is_support_sw_smu(adev))
 991                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 992         else if (adev->powerplay.pp_funcs->force_clock_level)
 993                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 994
 995         if (ret)
 996                 return -EINVAL;
 997
 998         return count;
 999 }
1000
1001 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1002                 struct device_attribute *attr,
1003                 char *buf)
1004 {
1005         struct drm_device *ddev = dev_get_drvdata(dev);
1006         struct amdgpu_device *adev = ddev->dev_private;
1007
1008         if (is_support_sw_smu(adev))
1009                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
1010         else if (adev->powerplay.pp_funcs->print_clock_levels)
1011                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1012         else
1013                 return snprintf(buf, PAGE_SIZE, "\n");
1014 }
1015
1016 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1017                 struct device_attribute *attr,
1018                 const char *buf,
1019                 size_t count)
1020 {
1021         struct drm_device *ddev = dev_get_drvdata(dev);
1022         struct amdgpu_device *adev = ddev->dev_private;
1023         int ret;
1024         uint32_t mask = 0;
1025
1026         ret = amdgpu_read_mask(buf, count, &mask);
1027         if (ret)
1028                 return ret;
1029
1030         if (is_support_sw_smu(adev))
1031                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1032         else if (adev->powerplay.pp_funcs->force_clock_level)
1033                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1034
1035         if (ret)
1036                 return -EINVAL;
1037
1038         return count;
1039 }
1040
1041 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1042                 struct device_attribute *attr,
1043                 char *buf)
1044 {
1045         struct drm_device *ddev = dev_get_drvdata(dev);
1046         struct amdgpu_device *adev = ddev->dev_private;
1047
1048         if (is_support_sw_smu(adev))
1049                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1050         else if (adev->powerplay.pp_funcs->print_clock_levels)
1051                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1052         else
1053                 return snprintf(buf, PAGE_SIZE, "\n");
1054 }
1055
1056 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1057                 struct device_attribute *attr,
1058                 const char *buf,
1059                 size_t count)
1060 {
1061         struct drm_device *ddev = dev_get_drvdata(dev);
1062         struct amdgpu_device *adev = ddev->dev_private;
1063         int ret;
1064         uint32_t mask = 0;
1065
1066         ret = amdgpu_read_mask(buf, count, &mask);
1067         if (ret)
1068                 return ret;
1069
1070         if (is_support_sw_smu(adev))
1071                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1072         else if (adev->powerplay.pp_funcs->force_clock_level)
1073                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1074
1075         if (ret)
1076                 return -EINVAL;
1077
1078         return count;
1079 }
1080
1081 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1082                 struct device_attribute *attr,
1083                 char *buf)
1084 {
1085         struct drm_device *ddev = dev_get_drvdata(dev);
1086         struct amdgpu_device *adev = ddev->dev_private;
1087
1088         if (is_support_sw_smu(adev))
1089                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1090         else if (adev->powerplay.pp_funcs->print_clock_levels)
1091                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1092         else
1093                 return snprintf(buf, PAGE_SIZE, "\n");
1094 }
1095
1096 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1097                 struct device_attribute *attr,
1098                 const char *buf,
1099                 size_t count)
1100 {
1101         struct drm_device *ddev = dev_get_drvdata(dev);
1102         struct amdgpu_device *adev = ddev->dev_private;
1103         int ret;
1104         uint32_t mask = 0;
1105
1106         ret = amdgpu_read_mask(buf, count, &mask);
1107         if (ret)
1108                 return ret;
1109
1110         if (is_support_sw_smu(adev))
1111                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1112         else if (adev->powerplay.pp_funcs->force_clock_level)
1113                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1114
1115         if (ret)
1116                 return -EINVAL;
1117
1118         return count;
1119 }
1120
1121 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1122                 struct device_attribute *attr,
1123                 char *buf)
1124 {
1125         struct drm_device *ddev = dev_get_drvdata(dev);
1126         struct amdgpu_device *adev = ddev->dev_private;
1127         uint32_t value = 0;
1128
1129         if (is_support_sw_smu(adev))
1130                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1131         else if (adev->powerplay.pp_funcs->get_sclk_od)
1132                 value = amdgpu_dpm_get_sclk_od(adev);
1133
1134         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1135 }
1136
1137 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1138                 struct device_attribute *attr,
1139                 const char *buf,
1140                 size_t count)
1141 {
1142         struct drm_device *ddev = dev_get_drvdata(dev);
1143         struct amdgpu_device *adev = ddev->dev_private;
1144         int ret;
1145         long int value;
1146
1147         ret = kstrtol(buf, 0, &value);
1148
1149         if (ret) {
1150                 count = -EINVAL;
1151                 goto fail;
1152         }
1153
1154         if (is_support_sw_smu(adev)) {
1155                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1156         } else {
1157                 if (adev->powerplay.pp_funcs->set_sclk_od)
1158                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1159
1160                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1161                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1162                 } else {
1163                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1164                         amdgpu_pm_compute_clocks(adev);
1165                 }
1166         }
1167
1168 fail:
1169         return count;
1170 }
1171
1172 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1173                 struct device_attribute *attr,
1174                 char *buf)
1175 {
1176         struct drm_device *ddev = dev_get_drvdata(dev);
1177         struct amdgpu_device *adev = ddev->dev_private;
1178         uint32_t value = 0;
1179
1180         if (is_support_sw_smu(adev))
1181                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1182         else if (adev->powerplay.pp_funcs->get_mclk_od)
1183                 value = amdgpu_dpm_get_mclk_od(adev);
1184
1185         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1186 }
1187
1188 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1189                 struct device_attribute *attr,
1190                 const char *buf,
1191                 size_t count)
1192 {
1193         struct drm_device *ddev = dev_get_drvdata(dev);
1194         struct amdgpu_device *adev = ddev->dev_private;
1195         int ret;
1196         long int value;
1197
1198         ret = kstrtol(buf, 0, &value);
1199
1200         if (ret) {
1201                 count = -EINVAL;
1202                 goto fail;
1203         }
1204
1205         if (is_support_sw_smu(adev)) {
1206                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1207         } else {
1208                 if (adev->powerplay.pp_funcs->set_mclk_od)
1209                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1210
1211                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1212                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1213                 } else {
1214                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1215                         amdgpu_pm_compute_clocks(adev);
1216                 }
1217         }
1218
1219 fail:
1220         return count;
1221 }
1222
1223 /**
1224  * DOC: pp_power_profile_mode
1225  *
1226  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1227  * related to switching between power levels in a power state.  The file
1228  * pp_power_profile_mode is used for this.
1229  *
1230  * Reading this file outputs a list of all of the predefined power profiles
1231  * and the relevant heuristics settings for that profile.
1232  *
1233  * To select a profile or create a custom profile, first select manual using
1234  * power_dpm_force_performance_level.  Writing the number of a predefined
1235  * profile to pp_power_profile_mode will enable those heuristics.  To
1236  * create a custom set of heuristics, write a string of numbers to the file
1237  * starting with the number of the custom profile along with a setting
1238  * for each heuristic parameter.  Due to differences across asic families
1239  * the heuristic parameters vary from family to family.
1240  *
1241  */
1242
1243 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1244                 struct device_attribute *attr,
1245                 char *buf)
1246 {
1247         struct drm_device *ddev = dev_get_drvdata(dev);
1248         struct amdgpu_device *adev = ddev->dev_private;
1249
1250         if (is_support_sw_smu(adev))
1251                 return smu_get_power_profile_mode(&adev->smu, buf);
1252         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1253                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1254
1255         return snprintf(buf, PAGE_SIZE, "\n");
1256 }
1257
1258
1259 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1260                 struct device_attribute *attr,
1261                 const char *buf,
1262                 size_t count)
1263 {
1264         int ret = 0xff;
1265         struct drm_device *ddev = dev_get_drvdata(dev);
1266         struct amdgpu_device *adev = ddev->dev_private;
1267         uint32_t parameter_size = 0;
1268         long parameter[64];
1269         char *sub_str, buf_cpy[128];
1270         char *tmp_str;
1271         uint32_t i = 0;
1272         char tmp[2];
1273         long int profile_mode = 0;
1274         const char delimiter[3] = {' ', '\n', '\0'};
1275
1276         tmp[0] = *(buf);
1277         tmp[1] = '\0';
1278         ret = kstrtol(tmp, 0, &profile_mode);
1279         if (ret)
1280                 goto fail;
1281
1282         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1283                 if (count < 2 || count > 127)
1284                         return -EINVAL;
1285                 while (isspace(*++buf))
1286                         i++;
1287                 memcpy(buf_cpy, buf, count-i);
1288                 tmp_str = buf_cpy;
1289                 while (tmp_str[0]) {
1290                         sub_str = strsep(&tmp_str, delimiter);
1291                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1292                         if (ret) {
1293                                 count = -EINVAL;
1294                                 goto fail;
1295                         }
1296                         parameter_size++;
1297                         while (isspace(*tmp_str))
1298                                 tmp_str++;
1299                 }
1300         }
1301         parameter[parameter_size] = profile_mode;
1302         if (is_support_sw_smu(adev))
1303                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1304         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1305                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1306         if (!ret)
1307                 return count;
1308 fail:
1309         return -EINVAL;
1310 }
1311
1312 /**
1313  * DOC: busy_percent
1314  *
1315  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1316  * is as a percentage.  The file gpu_busy_percent is used for this.
1317  * The SMU firmware computes a percentage of load based on the
1318  * aggregate activity level in the IP cores.
1319  */
1320 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1321                 struct device_attribute *attr,
1322                 char *buf)
1323 {
1324         struct drm_device *ddev = dev_get_drvdata(dev);
1325         struct amdgpu_device *adev = ddev->dev_private;
1326         int r, value, size = sizeof(value);
1327
1328         /* read the IP busy sensor */
1329         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1330                                    (void *)&value, &size);
1331
1332         if (r)
1333                 return r;
1334
1335         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1336 }
1337
1338 /**
1339  * DOC: mem_busy_percent
1340  *
1341  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1342  * is as a percentage.  The file mem_busy_percent is used for this.
1343  * The SMU firmware computes a percentage of load based on the
1344  * aggregate activity level in the IP cores.
1345  */
1346 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1347                 struct device_attribute *attr,
1348                 char *buf)
1349 {
1350         struct drm_device *ddev = dev_get_drvdata(dev);
1351         struct amdgpu_device *adev = ddev->dev_private;
1352         int r, value, size = sizeof(value);
1353
1354         /* read the IP busy sensor */
1355         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1356                                    (void *)&value, &size);
1357
1358         if (r)
1359                 return r;
1360
1361         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1362 }
1363
1364 /**
1365  * DOC: pcie_bw
1366  *
1367  * The amdgpu driver provides a sysfs API for estimating how much data
1368  * has been received and sent by the GPU in the last second through PCIe.
1369  * The file pcie_bw is used for this.
1370  * The Perf counters count the number of received and sent messages and return
1371  * those values, as well as the maximum payload size of a PCIe packet (mps).
1372  * Note that it is not possible to easily and quickly obtain the size of each
1373  * packet transmitted, so we output the max payload size (mps) to allow for
1374  * quick estimation of the PCIe bandwidth usage
1375  */
1376 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1377                 struct device_attribute *attr,
1378                 char *buf)
1379 {
1380         struct drm_device *ddev = dev_get_drvdata(dev);
1381         struct amdgpu_device *adev = ddev->dev_private;
1382         uint64_t count0, count1;
1383
1384         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1385         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1386                         count0, count1, pcie_get_mps(adev->pdev));
1387 }
1388
1389 /**
1390  * DOC: unique_id
1391  *
1392  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1393  * The file unique_id is used for this.
1394  * This will provide a Unique ID that will persist from machine to machine
1395  *
1396  * NOTE: This will only work for GFX9 and newer. This file will be absent
1397  * on unsupported ASICs (GFX8 and older)
1398  */
1399 static ssize_t amdgpu_get_unique_id(struct device *dev,
1400                 struct device_attribute *attr,
1401                 char *buf)
1402 {
1403         struct drm_device *ddev = dev_get_drvdata(dev);
1404         struct amdgpu_device *adev = ddev->dev_private;
1405
1406         if (adev->unique_id)
1407                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1408
1409         return 0;
1410 }
1411
1412 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1413 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1414                    amdgpu_get_dpm_forced_performance_level,
1415                    amdgpu_set_dpm_forced_performance_level);
1416 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1417 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1418 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_pp_force_state,
1420                 amdgpu_set_pp_force_state);
1421 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1422                 amdgpu_get_pp_table,
1423                 amdgpu_set_pp_table);
1424 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_dpm_sclk,
1426                 amdgpu_set_pp_dpm_sclk);
1427 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_dpm_mclk,
1429                 amdgpu_set_pp_dpm_mclk);
1430 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_dpm_socclk,
1432                 amdgpu_set_pp_dpm_socclk);
1433 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_dpm_fclk,
1435                 amdgpu_set_pp_dpm_fclk);
1436 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1437                 amdgpu_get_pp_dpm_dcefclk,
1438                 amdgpu_set_pp_dpm_dcefclk);
1439 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1440                 amdgpu_get_pp_dpm_pcie,
1441                 amdgpu_set_pp_dpm_pcie);
1442 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1443                 amdgpu_get_pp_sclk_od,
1444                 amdgpu_set_pp_sclk_od);
1445 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1446                 amdgpu_get_pp_mclk_od,
1447                 amdgpu_set_pp_mclk_od);
1448 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1449                 amdgpu_get_pp_power_profile_mode,
1450                 amdgpu_set_pp_power_profile_mode);
1451 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1452                 amdgpu_get_pp_od_clk_voltage,
1453                 amdgpu_set_pp_od_clk_voltage);
1454 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1455                 amdgpu_get_busy_percent, NULL);
1456 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1457                 amdgpu_get_memory_busy_percent, NULL);
1458 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1459 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1460                 amdgpu_get_ppfeature_status,
1461                 amdgpu_set_ppfeature_status);
1462 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1463
1464 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1465                                       struct device_attribute *attr,
1466                                       char *buf)
1467 {
1468         struct amdgpu_device *adev = dev_get_drvdata(dev);
1469         struct drm_device *ddev = adev->ddev;
1470         int channel = to_sensor_dev_attr(attr)->index;
1471         int r, temp, size = sizeof(temp);
1472
1473         /* Can't get temperature when the card is off */
1474         if  ((adev->flags & AMD_IS_PX) &&
1475              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1476                 return -EINVAL;
1477
1478         if (channel >= PP_TEMP_MAX)
1479                 return -EINVAL;
1480
1481         switch (channel) {
1482         case PP_TEMP_JUNCTION:
1483                 /* get current junction temperature */
1484                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1485                                            (void *)&temp, &size);
1486                 if (r)
1487                         return r;
1488                 break;
1489         case PP_TEMP_EDGE:
1490                 /* get current edge temperature */
1491                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1492                                            (void *)&temp, &size);
1493                 if (r)
1494                         return r;
1495                 break;
1496         case PP_TEMP_MEM:
1497                 /* get current memory temperature */
1498                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1499                                            (void *)&temp, &size);
1500                 if (r)
1501                         return r;
1502                 break;
1503         }
1504
1505         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1506 }
1507
1508 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1509                                              struct device_attribute *attr,
1510                                              char *buf)
1511 {
1512         struct amdgpu_device *adev = dev_get_drvdata(dev);
1513         int hyst = to_sensor_dev_attr(attr)->index;
1514         int temp;
1515
1516         if (hyst)
1517                 temp = adev->pm.dpm.thermal.min_temp;
1518         else
1519                 temp = adev->pm.dpm.thermal.max_temp;
1520
1521         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1522 }
1523
1524 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1525                                              struct device_attribute *attr,
1526                                              char *buf)
1527 {
1528         struct amdgpu_device *adev = dev_get_drvdata(dev);
1529         int hyst = to_sensor_dev_attr(attr)->index;
1530         int temp;
1531
1532         if (hyst)
1533                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1534         else
1535                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1536
1537         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1538 }
1539
1540 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1541                                              struct device_attribute *attr,
1542                                              char *buf)
1543 {
1544         struct amdgpu_device *adev = dev_get_drvdata(dev);
1545         int hyst = to_sensor_dev_attr(attr)->index;
1546         int temp;
1547
1548         if (hyst)
1549                 temp = adev->pm.dpm.thermal.min_mem_temp;
1550         else
1551                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1552
1553         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1554 }
1555
1556 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1557                                              struct device_attribute *attr,
1558                                              char *buf)
1559 {
1560         int channel = to_sensor_dev_attr(attr)->index;
1561
1562         if (channel >= PP_TEMP_MAX)
1563                 return -EINVAL;
1564
1565         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1566 }
1567
1568 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1569                                              struct device_attribute *attr,
1570                                              char *buf)
1571 {
1572         struct amdgpu_device *adev = dev_get_drvdata(dev);
1573         int channel = to_sensor_dev_attr(attr)->index;
1574         int temp = 0;
1575
1576         if (channel >= PP_TEMP_MAX)
1577                 return -EINVAL;
1578
1579         switch (channel) {
1580         case PP_TEMP_JUNCTION:
1581                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1582                 break;
1583         case PP_TEMP_EDGE:
1584                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1585                 break;
1586         case PP_TEMP_MEM:
1587                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1588                 break;
1589         }
1590
1591         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1592 }
1593
1594 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1595                                             struct device_attribute *attr,
1596                                             char *buf)
1597 {
1598         struct amdgpu_device *adev = dev_get_drvdata(dev);
1599         u32 pwm_mode = 0;
1600         if (is_support_sw_smu(adev)) {
1601                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1602         } else {
1603                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1604                         return -EINVAL;
1605
1606                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1607         }
1608
1609         return sprintf(buf, "%i\n", pwm_mode);
1610 }
1611
1612 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1613                                             struct device_attribute *attr,
1614                                             const char *buf,
1615                                             size_t count)
1616 {
1617         struct amdgpu_device *adev = dev_get_drvdata(dev);
1618         int err;
1619         int value;
1620
1621         /* Can't adjust fan when the card is off */
1622         if  ((adev->flags & AMD_IS_PX) &&
1623              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1624                 return -EINVAL;
1625
1626         if (is_support_sw_smu(adev)) {
1627                 err = kstrtoint(buf, 10, &value);
1628                 if (err)
1629                         return err;
1630
1631                 smu_set_fan_control_mode(&adev->smu, value);
1632         } else {
1633                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1634                         return -EINVAL;
1635
1636                 err = kstrtoint(buf, 10, &value);
1637                 if (err)
1638                         return err;
1639
1640                 amdgpu_dpm_set_fan_control_mode(adev, value);
1641         }
1642
1643         return count;
1644 }
1645
1646 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1647                                          struct device_attribute *attr,
1648                                          char *buf)
1649 {
1650         return sprintf(buf, "%i\n", 0);
1651 }
1652
1653 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1654                                          struct device_attribute *attr,
1655                                          char *buf)
1656 {
1657         return sprintf(buf, "%i\n", 255);
1658 }
1659
1660 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1661                                      struct device_attribute *attr,
1662                                      const char *buf, size_t count)
1663 {
1664         struct amdgpu_device *adev = dev_get_drvdata(dev);
1665         int err;
1666         u32 value;
1667         u32 pwm_mode;
1668
1669         /* Can't adjust fan when the card is off */
1670         if  ((adev->flags & AMD_IS_PX) &&
1671              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1672                 return -EINVAL;
1673         if (is_support_sw_smu(adev))
1674                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1675         else
1676                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1677         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1678                 pr_info("manual fan speed control should be enabled first\n");
1679                 return -EINVAL;
1680         }
1681
1682         err = kstrtou32(buf, 10, &value);
1683         if (err)
1684                 return err;
1685
1686         value = (value * 100) / 255;
1687
1688         if (is_support_sw_smu(adev)) {
1689                 err = smu_set_fan_speed_percent(&adev->smu, value);
1690                 if (err)
1691                         return err;
1692         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1693                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1694                 if (err)
1695                         return err;
1696         }
1697
1698         return count;
1699 }
1700
1701 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1702                                      struct device_attribute *attr,
1703                                      char *buf)
1704 {
1705         struct amdgpu_device *adev = dev_get_drvdata(dev);
1706         int err;
1707         u32 speed = 0;
1708
1709         /* Can't adjust fan when the card is off */
1710         if  ((adev->flags & AMD_IS_PX) &&
1711              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1712                 return -EINVAL;
1713
1714         if (is_support_sw_smu(adev)) {
1715                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1716                 if (err)
1717                         return err;
1718         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1719                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1720                 if (err)
1721                         return err;
1722         }
1723
1724         speed = (speed * 255) / 100;
1725
1726         return sprintf(buf, "%i\n", speed);
1727 }
1728
1729 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1730                                            struct device_attribute *attr,
1731                                            char *buf)
1732 {
1733         struct amdgpu_device *adev = dev_get_drvdata(dev);
1734         int err;
1735         u32 speed = 0;
1736
1737         /* Can't adjust fan when the card is off */
1738         if  ((adev->flags & AMD_IS_PX) &&
1739              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1740                 return -EINVAL;
1741
1742         if (is_support_sw_smu(adev)) {
1743                 err = smu_get_current_rpm(&adev->smu, &speed);
1744                 if (err)
1745                         return err;
1746         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1747                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1748                 if (err)
1749                         return err;
1750         }
1751
1752         return sprintf(buf, "%i\n", speed);
1753 }
1754
1755 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1756                                          struct device_attribute *attr,
1757                                          char *buf)
1758 {
1759         struct amdgpu_device *adev = dev_get_drvdata(dev);
1760         u32 min_rpm = 0;
1761         u32 size = sizeof(min_rpm);
1762         int r;
1763
1764         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1765                                    (void *)&min_rpm, &size);
1766         if (r)
1767                 return r;
1768
1769         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1770 }
1771
1772 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1773                                          struct device_attribute *attr,
1774                                          char *buf)
1775 {
1776         struct amdgpu_device *adev = dev_get_drvdata(dev);
1777         u32 max_rpm = 0;
1778         u32 size = sizeof(max_rpm);
1779         int r;
1780
1781         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1782                                    (void *)&max_rpm, &size);
1783         if (r)
1784                 return r;
1785
1786         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1787 }
1788
1789 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1790                                            struct device_attribute *attr,
1791                                            char *buf)
1792 {
1793         struct amdgpu_device *adev = dev_get_drvdata(dev);
1794         int err;
1795         u32 rpm = 0;
1796
1797         /* Can't adjust fan when the card is off */
1798         if  ((adev->flags & AMD_IS_PX) &&
1799              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1800                 return -EINVAL;
1801
1802         if (is_support_sw_smu(adev)) {
1803                 err = smu_get_current_rpm(&adev->smu, &rpm);
1804                 if (err)
1805                         return err;
1806         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1807                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1808                 if (err)
1809                         return err;
1810         }
1811
1812         return sprintf(buf, "%i\n", rpm);
1813 }
1814
1815 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1816                                      struct device_attribute *attr,
1817                                      const char *buf, size_t count)
1818 {
1819         struct amdgpu_device *adev = dev_get_drvdata(dev);
1820         int err;
1821         u32 value;
1822         u32 pwm_mode;
1823
1824         if (is_support_sw_smu(adev))
1825                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1826         else
1827                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1828
1829         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1830                 return -ENODATA;
1831
1832         /* Can't adjust fan when the card is off */
1833         if  ((adev->flags & AMD_IS_PX) &&
1834              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1835                 return -EINVAL;
1836
1837         err = kstrtou32(buf, 10, &value);
1838         if (err)
1839                 return err;
1840
1841         if (is_support_sw_smu(adev)) {
1842                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1843                 if (err)
1844                         return err;
1845         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1846                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1847                 if (err)
1848                         return err;
1849         }
1850
1851         return count;
1852 }
1853
1854 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1855                                             struct device_attribute *attr,
1856                                             char *buf)
1857 {
1858         struct amdgpu_device *adev = dev_get_drvdata(dev);
1859         u32 pwm_mode = 0;
1860
1861         if (is_support_sw_smu(adev)) {
1862                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1863         } else {
1864                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1865                         return -EINVAL;
1866
1867                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1868         }
1869         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1870 }
1871
1872 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1873                                             struct device_attribute *attr,
1874                                             const char *buf,
1875                                             size_t count)
1876 {
1877         struct amdgpu_device *adev = dev_get_drvdata(dev);
1878         int err;
1879         int value;
1880         u32 pwm_mode;
1881
1882         /* Can't adjust fan when the card is off */
1883         if  ((adev->flags & AMD_IS_PX) &&
1884              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1885                 return -EINVAL;
1886
1887
1888         err = kstrtoint(buf, 10, &value);
1889         if (err)
1890                 return err;
1891
1892         if (value == 0)
1893                 pwm_mode = AMD_FAN_CTRL_AUTO;
1894         else if (value == 1)
1895                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1896         else
1897                 return -EINVAL;
1898
1899         if (is_support_sw_smu(adev)) {
1900                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1901         } else {
1902                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1903                         return -EINVAL;
1904                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1905         }
1906
1907         return count;
1908 }
1909
1910 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1911                                         struct device_attribute *attr,
1912                                         char *buf)
1913 {
1914         struct amdgpu_device *adev = dev_get_drvdata(dev);
1915         struct drm_device *ddev = adev->ddev;
1916         u32 vddgfx;
1917         int r, size = sizeof(vddgfx);
1918
1919         /* Can't get voltage when the card is off */
1920         if  ((adev->flags & AMD_IS_PX) &&
1921              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1922                 return -EINVAL;
1923
1924         /* get the voltage */
1925         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1926                                    (void *)&vddgfx, &size);
1927         if (r)
1928                 return r;
1929
1930         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1931 }
1932
1933 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1934                                               struct device_attribute *attr,
1935                                               char *buf)
1936 {
1937         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1938 }
1939
1940 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1941                                        struct device_attribute *attr,
1942                                        char *buf)
1943 {
1944         struct amdgpu_device *adev = dev_get_drvdata(dev);
1945         struct drm_device *ddev = adev->ddev;
1946         u32 vddnb;
1947         int r, size = sizeof(vddnb);
1948
1949         /* only APUs have vddnb */
1950         if  (!(adev->flags & AMD_IS_APU))
1951                 return -EINVAL;
1952
1953         /* Can't get voltage when the card is off */
1954         if  ((adev->flags & AMD_IS_PX) &&
1955              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1956                 return -EINVAL;
1957
1958         /* get the voltage */
1959         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1960                                    (void *)&vddnb, &size);
1961         if (r)
1962                 return r;
1963
1964         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1965 }
1966
1967 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1968                                               struct device_attribute *attr,
1969                                               char *buf)
1970 {
1971         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1972 }
1973
1974 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1975                                            struct device_attribute *attr,
1976                                            char *buf)
1977 {
1978         struct amdgpu_device *adev = dev_get_drvdata(dev);
1979         struct drm_device *ddev = adev->ddev;
1980         u32 query = 0;
1981         int r, size = sizeof(u32);
1982         unsigned uw;
1983
1984         /* Can't get power when the card is off */
1985         if  ((adev->flags & AMD_IS_PX) &&
1986              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1987                 return -EINVAL;
1988
1989         /* get the voltage */
1990         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1991                                    (void *)&query, &size);
1992         if (r)
1993                 return r;
1994
1995         /* convert to microwatts */
1996         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1997
1998         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1999 }
2000
2001 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2002                                          struct device_attribute *attr,
2003                                          char *buf)
2004 {
2005         return sprintf(buf, "%i\n", 0);
2006 }
2007
2008 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2009                                          struct device_attribute *attr,
2010                                          char *buf)
2011 {
2012         struct amdgpu_device *adev = dev_get_drvdata(dev);
2013         uint32_t limit = 0;
2014
2015         if (is_support_sw_smu(adev)) {
2016                 smu_get_power_limit(&adev->smu, &limit, true);
2017                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2018         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2019                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2020                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2021         } else {
2022                 return snprintf(buf, PAGE_SIZE, "\n");
2023         }
2024 }
2025
2026 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2027                                          struct device_attribute *attr,
2028                                          char *buf)
2029 {
2030         struct amdgpu_device *adev = dev_get_drvdata(dev);
2031         uint32_t limit = 0;
2032
2033         if (is_support_sw_smu(adev)) {
2034                 smu_get_power_limit(&adev->smu, &limit, false);
2035                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2036         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2037                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2038                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2039         } else {
2040                 return snprintf(buf, PAGE_SIZE, "\n");
2041         }
2042 }
2043
2044
2045 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2046                 struct device_attribute *attr,
2047                 const char *buf,
2048                 size_t count)
2049 {
2050         struct amdgpu_device *adev = dev_get_drvdata(dev);
2051         int err;
2052         u32 value;
2053
2054         err = kstrtou32(buf, 10, &value);
2055         if (err)
2056                 return err;
2057
2058         value = value / 1000000; /* convert to Watt */
2059         if (is_support_sw_smu(adev)) {
2060                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2061         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2062                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2063                 if (err)
2064                         return err;
2065         } else {
2066                 return -EINVAL;
2067         }
2068
2069         return count;
2070 }
2071
2072 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2073                                       struct device_attribute *attr,
2074                                       char *buf)
2075 {
2076         struct amdgpu_device *adev = dev_get_drvdata(dev);
2077         struct drm_device *ddev = adev->ddev;
2078         uint32_t sclk;
2079         int r, size = sizeof(sclk);
2080
2081         /* Can't get voltage when the card is off */
2082         if  ((adev->flags & AMD_IS_PX) &&
2083              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2084                 return -EINVAL;
2085
2086         /* sanity check PP is enabled */
2087         if (!(adev->powerplay.pp_funcs &&
2088               adev->powerplay.pp_funcs->read_sensor))
2089               return -EINVAL;
2090
2091         /* get the sclk */
2092         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2093                                    (void *)&sclk, &size);
2094         if (r)
2095                 return r;
2096
2097         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2098 }
2099
2100 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2101                                             struct device_attribute *attr,
2102                                             char *buf)
2103 {
2104         return snprintf(buf, PAGE_SIZE, "sclk\n");
2105 }
2106
2107 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2108                                       struct device_attribute *attr,
2109                                       char *buf)
2110 {
2111         struct amdgpu_device *adev = dev_get_drvdata(dev);
2112         struct drm_device *ddev = adev->ddev;
2113         uint32_t mclk;
2114         int r, size = sizeof(mclk);
2115
2116         /* Can't get voltage when the card is off */
2117         if  ((adev->flags & AMD_IS_PX) &&
2118              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2119                 return -EINVAL;
2120
2121         /* sanity check PP is enabled */
2122         if (!(adev->powerplay.pp_funcs &&
2123               adev->powerplay.pp_funcs->read_sensor))
2124               return -EINVAL;
2125
2126         /* get the sclk */
2127         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2128                                    (void *)&mclk, &size);
2129         if (r)
2130                 return r;
2131
2132         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2133 }
2134
2135 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2136                                             struct device_attribute *attr,
2137                                             char *buf)
2138 {
2139         return snprintf(buf, PAGE_SIZE, "mclk\n");
2140 }
2141
2142 /**
2143  * DOC: hwmon
2144  *
2145  * The amdgpu driver exposes the following sensor interfaces:
2146  *
2147  * - GPU temperature (via the on-die sensor)
2148  *
2149  * - GPU voltage
2150  *
2151  * - Northbridge voltage (APUs only)
2152  *
2153  * - GPU power
2154  *
2155  * - GPU fan
2156  *
2157  * - GPU gfx/compute engine clock
2158  *
2159  * - GPU memory clock (dGPU only)
2160  *
2161  * hwmon interfaces for GPU temperature:
2162  *
2163  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2164  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2165  *
2166  * - temp[1-3]_label: temperature channel label
2167  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2168  *
2169  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2170  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2171  *
2172  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2173  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2174  *
2175  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2176  *   - these are supported on SOC15 dGPUs only
2177  *
2178  * hwmon interfaces for GPU voltage:
2179  *
2180  * - in0_input: the voltage on the GPU in millivolts
2181  *
2182  * - in1_input: the voltage on the Northbridge in millivolts
2183  *
2184  * hwmon interfaces for GPU power:
2185  *
2186  * - power1_average: average power used by the GPU in microWatts
2187  *
2188  * - power1_cap_min: minimum cap supported in microWatts
2189  *
2190  * - power1_cap_max: maximum cap supported in microWatts
2191  *
2192  * - power1_cap: selected power cap in microWatts
2193  *
2194  * hwmon interfaces for GPU fan:
2195  *
2196  * - pwm1: pulse width modulation fan level (0-255)
2197  *
2198  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2199  *
2200  * - pwm1_min: pulse width modulation fan control minimum level (0)
2201  *
2202  * - pwm1_max: pulse width modulation fan control maximum level (255)
2203  *
2204  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2205  *
2206  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2207  *
2208  * - fan1_input: fan speed in RPM
2209  *
2210  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2211  *
2212  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2213  *
2214  * hwmon interfaces for GPU clocks:
2215  *
2216  * - freq1_input: the gfx/compute clock in hertz
2217  *
2218  * - freq2_input: the memory clock in hertz
2219  *
2220  * You can use hwmon tools like sensors to view this information on your system.
2221  *
2222  */
2223
2224 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2225 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2226 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2227 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2228 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2229 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2230 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2231 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2232 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2233 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2234 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2235 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2236 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2237 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2238 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2239 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2240 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2241 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2242 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2243 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2244 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2245 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2246 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2247 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2248 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2249 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2250 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2251 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2252 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2253 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2254 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2255 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2256 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2257 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2258 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2259 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2260
2261 static struct attribute *hwmon_attributes[] = {
2262         &sensor_dev_attr_temp1_input.dev_attr.attr,
2263         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2264         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2265         &sensor_dev_attr_temp2_input.dev_attr.attr,
2266         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2267         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2268         &sensor_dev_attr_temp3_input.dev_attr.attr,
2269         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2270         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2271         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2272         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2273         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2274         &sensor_dev_attr_temp1_label.dev_attr.attr,
2275         &sensor_dev_attr_temp2_label.dev_attr.attr,
2276         &sensor_dev_attr_temp3_label.dev_attr.attr,
2277         &sensor_dev_attr_pwm1.dev_attr.attr,
2278         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2279         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2280         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2281         &sensor_dev_attr_fan1_input.dev_attr.attr,
2282         &sensor_dev_attr_fan1_min.dev_attr.attr,
2283         &sensor_dev_attr_fan1_max.dev_attr.attr,
2284         &sensor_dev_attr_fan1_target.dev_attr.attr,
2285         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2286         &sensor_dev_attr_in0_input.dev_attr.attr,
2287         &sensor_dev_attr_in0_label.dev_attr.attr,
2288         &sensor_dev_attr_in1_input.dev_attr.attr,
2289         &sensor_dev_attr_in1_label.dev_attr.attr,
2290         &sensor_dev_attr_power1_average.dev_attr.attr,
2291         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2292         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2293         &sensor_dev_attr_power1_cap.dev_attr.attr,
2294         &sensor_dev_attr_freq1_input.dev_attr.attr,
2295         &sensor_dev_attr_freq1_label.dev_attr.attr,
2296         &sensor_dev_attr_freq2_input.dev_attr.attr,
2297         &sensor_dev_attr_freq2_label.dev_attr.attr,
2298         NULL
2299 };
2300
2301 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2302                                         struct attribute *attr, int index)
2303 {
2304         struct device *dev = kobj_to_dev(kobj);
2305         struct amdgpu_device *adev = dev_get_drvdata(dev);
2306         umode_t effective_mode = attr->mode;
2307
2308         /* Skip fan attributes if fan is not present */
2309         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2310             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2311             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2312             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2313             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2314             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2315             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2316             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2317             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2318                 return 0;
2319
2320         /* Skip fan attributes on APU */
2321         if ((adev->flags & AMD_IS_APU) &&
2322             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2323              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2324              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2325              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2326              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2327              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2328              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2329              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2330              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2331                 return 0;
2332
2333         /* Skip limit attributes if DPM is not enabled */
2334         if (!adev->pm.dpm_enabled &&
2335             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2336              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2337              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2338              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2339              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2340              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2341              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2342              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2343              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2344              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2345              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2346                 return 0;
2347
2348         if (!is_support_sw_smu(adev)) {
2349                 /* mask fan attributes if we have no bindings for this asic to expose */
2350                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2351                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2352                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2353                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2354                         effective_mode &= ~S_IRUGO;
2355
2356                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2357                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2358                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2359                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2360                         effective_mode &= ~S_IWUSR;
2361         }
2362
2363         if ((adev->flags & AMD_IS_APU) &&
2364             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2365              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2366              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2367              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2368                 return 0;
2369
2370         if (!is_support_sw_smu(adev)) {
2371                 /* hide max/min values if we can't both query and manage the fan */
2372                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2373                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2374                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2375                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2376                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2377                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2378                         return 0;
2379
2380                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2381                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2382                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2383                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2384                         return 0;
2385         }
2386
2387         /* only APUs have vddnb */
2388         if (!(adev->flags & AMD_IS_APU) &&
2389             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2390              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2391                 return 0;
2392
2393         /* no mclk on APUs */
2394         if ((adev->flags & AMD_IS_APU) &&
2395             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2396              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2397                 return 0;
2398
2399         /* only SOC15 dGPUs support hotspot and mem temperatures */
2400         if (((adev->flags & AMD_IS_APU) ||
2401              adev->asic_type < CHIP_VEGA10) &&
2402             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2403              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2404              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2405              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2406              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2407              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2408              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2409              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2410              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2411              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2412              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2413                 return 0;
2414
2415         return effective_mode;
2416 }
2417
2418 static const struct attribute_group hwmon_attrgroup = {
2419         .attrs = hwmon_attributes,
2420         .is_visible = hwmon_attributes_visible,
2421 };
2422
2423 static const struct attribute_group *hwmon_groups[] = {
2424         &hwmon_attrgroup,
2425         NULL
2426 };
2427
2428 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2429 {
2430         struct amdgpu_device *adev =
2431                 container_of(work, struct amdgpu_device,
2432                              pm.dpm.thermal.work);
2433         /* switch to the thermal state */
2434         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2435         int temp, size = sizeof(temp);
2436
2437         if (!adev->pm.dpm_enabled)
2438                 return;
2439
2440         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2441                                     (void *)&temp, &size)) {
2442                 if (temp < adev->pm.dpm.thermal.min_temp)
2443                         /* switch back the user state */
2444                         dpm_state = adev->pm.dpm.user_state;
2445         } else {
2446                 if (adev->pm.dpm.thermal.high_to_low)
2447                         /* switch back the user state */
2448                         dpm_state = adev->pm.dpm.user_state;
2449         }
2450         mutex_lock(&adev->pm.mutex);
2451         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2452                 adev->pm.dpm.thermal_active = true;
2453         else
2454                 adev->pm.dpm.thermal_active = false;
2455         adev->pm.dpm.state = dpm_state;
2456         mutex_unlock(&adev->pm.mutex);
2457
2458         amdgpu_pm_compute_clocks(adev);
2459 }
2460
2461 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2462                                                      enum amd_pm_state_type dpm_state)
2463 {
2464         int i;
2465         struct amdgpu_ps *ps;
2466         u32 ui_class;
2467         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2468                 true : false;
2469
2470         /* check if the vblank period is too short to adjust the mclk */
2471         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2472                 if (amdgpu_dpm_vblank_too_short(adev))
2473                         single_display = false;
2474         }
2475
2476         /* certain older asics have a separare 3D performance state,
2477          * so try that first if the user selected performance
2478          */
2479         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2480                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2481         /* balanced states don't exist at the moment */
2482         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2483                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2484
2485 restart_search:
2486         /* Pick the best power state based on current conditions */
2487         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2488                 ps = &adev->pm.dpm.ps[i];
2489                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2490                 switch (dpm_state) {
2491                 /* user states */
2492                 case POWER_STATE_TYPE_BATTERY:
2493                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2494                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2495                                         if (single_display)
2496                                                 return ps;
2497                                 } else
2498                                         return ps;
2499                         }
2500                         break;
2501                 case POWER_STATE_TYPE_BALANCED:
2502                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2503                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2504                                         if (single_display)
2505                                                 return ps;
2506                                 } else
2507                                         return ps;
2508                         }
2509                         break;
2510                 case POWER_STATE_TYPE_PERFORMANCE:
2511                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2512                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2513                                         if (single_display)
2514                                                 return ps;
2515                                 } else
2516                                         return ps;
2517                         }
2518                         break;
2519                 /* internal states */
2520                 case POWER_STATE_TYPE_INTERNAL_UVD:
2521                         if (adev->pm.dpm.uvd_ps)
2522                                 return adev->pm.dpm.uvd_ps;
2523                         else
2524                                 break;
2525                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2526                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2527                                 return ps;
2528                         break;
2529                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2530                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2531                                 return ps;
2532                         break;
2533                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2534                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2535                                 return ps;
2536                         break;
2537                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2538                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2539                                 return ps;
2540                         break;
2541                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2542                         return adev->pm.dpm.boot_ps;
2543                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2544                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2545                                 return ps;
2546                         break;
2547                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2548                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2549                                 return ps;
2550                         break;
2551                 case POWER_STATE_TYPE_INTERNAL_ULV:
2552                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2553                                 return ps;
2554                         break;
2555                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2556                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2557                                 return ps;
2558                         break;
2559                 default:
2560                         break;
2561                 }
2562         }
2563         /* use a fallback state if we didn't match */
2564         switch (dpm_state) {
2565         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2566                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2567                 goto restart_search;
2568         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2569         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2570         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2571                 if (adev->pm.dpm.uvd_ps) {
2572                         return adev->pm.dpm.uvd_ps;
2573                 } else {
2574                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2575                         goto restart_search;
2576                 }
2577         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2578                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2579                 goto restart_search;
2580         case POWER_STATE_TYPE_INTERNAL_ACPI:
2581                 dpm_state = POWER_STATE_TYPE_BATTERY;
2582                 goto restart_search;
2583         case POWER_STATE_TYPE_BATTERY:
2584         case POWER_STATE_TYPE_BALANCED:
2585         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2586                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2587                 goto restart_search;
2588         default:
2589                 break;
2590         }
2591
2592         return NULL;
2593 }
2594
2595 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2596 {
2597         struct amdgpu_ps *ps;
2598         enum amd_pm_state_type dpm_state;
2599         int ret;
2600         bool equal = false;
2601
2602         /* if dpm init failed */
2603         if (!adev->pm.dpm_enabled)
2604                 return;
2605
2606         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2607                 /* add other state override checks here */
2608                 if ((!adev->pm.dpm.thermal_active) &&
2609                     (!adev->pm.dpm.uvd_active))
2610                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2611         }
2612         dpm_state = adev->pm.dpm.state;
2613
2614         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2615         if (ps)
2616                 adev->pm.dpm.requested_ps = ps;
2617         else
2618                 return;
2619
2620         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2621                 printk("switching from power state:\n");
2622                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2623                 printk("switching to power state:\n");
2624                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2625         }
2626
2627         /* update whether vce is active */
2628         ps->vce_active = adev->pm.dpm.vce_active;
2629         if (adev->powerplay.pp_funcs->display_configuration_changed)
2630                 amdgpu_dpm_display_configuration_changed(adev);
2631
2632         ret = amdgpu_dpm_pre_set_power_state(adev);
2633         if (ret)
2634                 return;
2635
2636         if (adev->powerplay.pp_funcs->check_state_equal) {
2637                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2638                         equal = false;
2639         }
2640
2641         if (equal)
2642                 return;
2643
2644         amdgpu_dpm_set_power_state(adev);
2645         amdgpu_dpm_post_set_power_state(adev);
2646
2647         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2648         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2649
2650         if (adev->powerplay.pp_funcs->force_performance_level) {
2651                 if (adev->pm.dpm.thermal_active) {
2652                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2653                         /* force low perf level for thermal */
2654                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2655                         /* save the user's level */
2656                         adev->pm.dpm.forced_level = level;
2657                 } else {
2658                         /* otherwise, user selected level */
2659                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2660                 }
2661         }
2662 }
2663
2664 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2665 {
2666         int ret = 0;
2667         if (is_support_sw_smu(adev)) {
2668             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2669             if (ret)
2670                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2671                           enable ? "true" : "false", ret);
2672         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2673                 /* enable/disable UVD */
2674                 mutex_lock(&adev->pm.mutex);
2675                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2676                 mutex_unlock(&adev->pm.mutex);
2677         }
2678         /* enable/disable Low Memory PState for UVD (4k videos) */
2679         if (adev->asic_type == CHIP_STONEY &&
2680                 adev->uvd.decode_image_width >= WIDTH_4K) {
2681                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2682
2683                 if (hwmgr && hwmgr->hwmgr_func &&
2684                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2685                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2686                                                                !enable,
2687                                                                true);
2688         }
2689 }
2690
2691 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2692 {
2693         int ret = 0;
2694         if (is_support_sw_smu(adev)) {
2695             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2696             if (ret)
2697                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2698                           enable ? "true" : "false", ret);
2699         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2700                 /* enable/disable VCE */
2701                 mutex_lock(&adev->pm.mutex);
2702                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2703                 mutex_unlock(&adev->pm.mutex);
2704         }
2705 }
2706
2707 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2708 {
2709         int i;
2710
2711         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2712                 return;
2713
2714         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2715                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2716
2717 }
2718
2719 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
2720 {
2721         int ret = 0;
2722
2723         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2724                 return ret;
2725
2726         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2727         if (ret) {
2728                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2729                 return ret;
2730         }
2731
2732         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2733         if (ret) {
2734                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2735                 return ret;
2736         }
2737
2738         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2739         if (ret) {
2740                 DRM_ERROR("failed to create device file for dpm state\n");
2741                 return ret;
2742         }
2743
2744         return ret;
2745 }
2746
2747 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev)
2748 {
2749         if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
2750                 return;
2751
2752         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2753         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2754         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2755 }
2756
2757 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2758 {
2759         int r;
2760
2761
2762         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2763                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
2764                 if (r) {
2765                         pr_err("smu firmware loading failed\n");
2766                         return r;
2767                 }
2768                 *smu_version = adev->pm.fw_version;
2769         }
2770         return 0;
2771 }
2772
2773 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2774 {
2775         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2776         int ret;
2777
2778         if (adev->pm.sysfs_initialized)
2779                 return 0;
2780
2781         if (adev->pm.dpm_enabled == 0)
2782                 return 0;
2783
2784         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2785                                                                    DRIVER_NAME, adev,
2786                                                                    hwmon_groups);
2787         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2788                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2789                 dev_err(adev->dev,
2790                         "Unable to register hwmon device: %d\n", ret);
2791                 return ret;
2792         }
2793
2794         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2795         if (ret) {
2796                 DRM_ERROR("failed to create device file for dpm state\n");
2797                 return ret;
2798         }
2799         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2800         if (ret) {
2801                 DRM_ERROR("failed to create device file for dpm state\n");
2802                 return ret;
2803         }
2804
2805
2806         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2807         if (ret) {
2808                 DRM_ERROR("failed to create device file pp_num_states\n");
2809                 return ret;
2810         }
2811         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2812         if (ret) {
2813                 DRM_ERROR("failed to create device file pp_cur_state\n");
2814                 return ret;
2815         }
2816         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2817         if (ret) {
2818                 DRM_ERROR("failed to create device file pp_force_state\n");
2819                 return ret;
2820         }
2821         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2822         if (ret) {
2823                 DRM_ERROR("failed to create device file pp_table\n");
2824                 return ret;
2825         }
2826
2827         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2828         if (ret) {
2829                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2830                 return ret;
2831         }
2832         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2833         if (ret) {
2834                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2835                 return ret;
2836         }
2837         if (adev->asic_type >= CHIP_VEGA10) {
2838                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2839                 if (ret) {
2840                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2841                         return ret;
2842                 }
2843                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2844                 if (ret) {
2845                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2846                         return ret;
2847                 }
2848         }
2849         if (adev->asic_type >= CHIP_VEGA20) {
2850                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2851                 if (ret) {
2852                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2853                         return ret;
2854                 }
2855         }
2856         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2857         if (ret) {
2858                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2859                 return ret;
2860         }
2861         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2862         if (ret) {
2863                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2864                 return ret;
2865         }
2866         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2867         if (ret) {
2868                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2869                 return ret;
2870         }
2871         ret = device_create_file(adev->dev,
2872                         &dev_attr_pp_power_profile_mode);
2873         if (ret) {
2874                 DRM_ERROR("failed to create device file "
2875                                 "pp_power_profile_mode\n");
2876                 return ret;
2877         }
2878         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2879             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2880                 ret = device_create_file(adev->dev,
2881                                 &dev_attr_pp_od_clk_voltage);
2882                 if (ret) {
2883                         DRM_ERROR("failed to create device file "
2884                                         "pp_od_clk_voltage\n");
2885                         return ret;
2886                 }
2887         }
2888         ret = device_create_file(adev->dev,
2889                         &dev_attr_gpu_busy_percent);
2890         if (ret) {
2891                 DRM_ERROR("failed to create device file "
2892                                 "gpu_busy_level\n");
2893                 return ret;
2894         }
2895         /* APU does not have its own dedicated memory */
2896         if (!(adev->flags & AMD_IS_APU)) {
2897                 ret = device_create_file(adev->dev,
2898                                 &dev_attr_mem_busy_percent);
2899                 if (ret) {
2900                         DRM_ERROR("failed to create device file "
2901                                         "mem_busy_percent\n");
2902                         return ret;
2903                 }
2904         }
2905         /* PCIe Perf counters won't work on APU nodes */
2906         if (!(adev->flags & AMD_IS_APU)) {
2907                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2908                 if (ret) {
2909                         DRM_ERROR("failed to create device file pcie_bw\n");
2910                         return ret;
2911                 }
2912         }
2913         if (adev->unique_id)
2914                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2915         if (ret) {
2916                 DRM_ERROR("failed to create device file unique_id\n");
2917                 return ret;
2918         }
2919         ret = amdgpu_debugfs_pm_init(adev);
2920         if (ret) {
2921                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2922                 return ret;
2923         }
2924
2925         if ((adev->asic_type >= CHIP_VEGA10) &&
2926             !(adev->flags & AMD_IS_APU)) {
2927                 ret = device_create_file(adev->dev,
2928                                 &dev_attr_ppfeatures);
2929                 if (ret) {
2930                         DRM_ERROR("failed to create device file "
2931                                         "ppfeatures\n");
2932                         return ret;
2933                 }
2934         }
2935
2936         adev->pm.sysfs_initialized = true;
2937
2938         return 0;
2939 }
2940
2941 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2942 {
2943         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2944
2945         if (adev->pm.dpm_enabled == 0)
2946                 return;
2947
2948         if (adev->pm.int_hwmon_dev)
2949                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2950         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2951         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2952
2953         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2954         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2955         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2956         device_remove_file(adev->dev, &dev_attr_pp_table);
2957
2958         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2959         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2960         if (adev->asic_type >= CHIP_VEGA10) {
2961                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2962                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2963         }
2964         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2965         if (adev->asic_type >= CHIP_VEGA20)
2966                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2967         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2968         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2969         device_remove_file(adev->dev,
2970                         &dev_attr_pp_power_profile_mode);
2971         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2972             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2973                 device_remove_file(adev->dev,
2974                                 &dev_attr_pp_od_clk_voltage);
2975         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2976         if (!(adev->flags & AMD_IS_APU))
2977                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2978         if (!(adev->flags & AMD_IS_APU))
2979                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2980         if (adev->unique_id)
2981                 device_remove_file(adev->dev, &dev_attr_unique_id);
2982         if ((adev->asic_type >= CHIP_VEGA10) &&
2983             !(adev->flags & AMD_IS_APU))
2984                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2985 }
2986
2987 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2988 {
2989         int i = 0;
2990
2991         if (!adev->pm.dpm_enabled)
2992                 return;
2993
2994         if (adev->mode_info.num_crtc)
2995                 amdgpu_display_bandwidth_update(adev);
2996
2997         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2998                 struct amdgpu_ring *ring = adev->rings[i];
2999                 if (ring && ring->sched.ready)
3000                         amdgpu_fence_wait_empty(ring);
3001         }
3002
3003         if (is_support_sw_smu(adev)) {
3004                 struct smu_context *smu = &adev->smu;
3005                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3006                 mutex_lock(&(smu->mutex));
3007                 smu_handle_task(&adev->smu,
3008                                 smu_dpm->dpm_level,
3009                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
3010                 mutex_unlock(&(smu->mutex));
3011         } else {
3012                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3013                         if (!amdgpu_device_has_dc_support(adev)) {
3014                                 mutex_lock(&adev->pm.mutex);
3015                                 amdgpu_dpm_get_active_displays(adev);
3016                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3017                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3018                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3019                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3020                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3021                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3022                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3023                                         adev->powerplay.pp_funcs->display_configuration_change(
3024                                                                         adev->powerplay.pp_handle,
3025                                                                         &adev->pm.pm_display_cfg);
3026                                 mutex_unlock(&adev->pm.mutex);
3027                         }
3028                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3029                 } else {
3030                         mutex_lock(&adev->pm.mutex);
3031                         amdgpu_dpm_get_active_displays(adev);
3032                         amdgpu_dpm_change_power_state_locked(adev);
3033                         mutex_unlock(&adev->pm.mutex);
3034                 }
3035         }
3036 }
3037
3038 /*
3039  * Debugfs info
3040  */
3041 #if defined(CONFIG_DEBUG_FS)
3042
3043 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3044 {
3045         uint32_t value;
3046         uint64_t value64;
3047         uint32_t query = 0;
3048         int size;
3049
3050         /* GPU Clocks */
3051         size = sizeof(value);
3052         seq_printf(m, "GFX Clocks and Power:\n");
3053         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3054                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3055         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3056                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3057         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3058                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3059         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3060                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3061         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3062                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3063         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3064                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3065         size = sizeof(uint32_t);
3066         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3067                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3068         size = sizeof(value);
3069         seq_printf(m, "\n");
3070
3071         /* GPU Temp */
3072         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3073                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3074
3075         /* GPU Load */
3076         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3077                 seq_printf(m, "GPU Load: %u %%\n", value);
3078         /* MEM Load */
3079         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3080                 seq_printf(m, "MEM Load: %u %%\n", value);
3081
3082         seq_printf(m, "\n");
3083
3084         /* SMC feature mask */
3085         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3086                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3087
3088         /* UVD clocks */
3089         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3090                 if (!value) {
3091                         seq_printf(m, "UVD: Disabled\n");
3092                 } else {
3093                         seq_printf(m, "UVD: Enabled\n");
3094                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3095                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3096                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3097                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3098                 }
3099         }
3100         seq_printf(m, "\n");
3101
3102         /* VCE clocks */
3103         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3104                 if (!value) {
3105                         seq_printf(m, "VCE: Disabled\n");
3106                 } else {
3107                         seq_printf(m, "VCE: Enabled\n");
3108                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3109                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3110                 }
3111         }
3112
3113         return 0;
3114 }
3115
3116 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3117 {
3118         int i;
3119
3120         for (i = 0; clocks[i].flag; i++)
3121                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3122                            (flags & clocks[i].flag) ? "On" : "Off");
3123 }
3124
3125 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3126 {
3127         struct drm_info_node *node = (struct drm_info_node *) m->private;
3128         struct drm_device *dev = node->minor->dev;
3129         struct amdgpu_device *adev = dev->dev_private;
3130         struct drm_device *ddev = adev->ddev;
3131         u32 flags = 0;
3132
3133         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3134         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3135         amdgpu_parse_cg_state(m, flags);
3136         seq_printf(m, "\n");
3137
3138         if (!adev->pm.dpm_enabled) {
3139                 seq_printf(m, "dpm not enabled\n");
3140                 return 0;
3141         }
3142         if  ((adev->flags & AMD_IS_PX) &&
3143              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3144                 seq_printf(m, "PX asic powered off\n");
3145         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3146                 mutex_lock(&adev->pm.mutex);
3147                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3148                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3149                 else
3150                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3151                 mutex_unlock(&adev->pm.mutex);
3152         } else {
3153                 return amdgpu_debugfs_pm_info_pp(m, adev);
3154         }
3155
3156         return 0;
3157 }
3158
3159 static const struct drm_info_list amdgpu_pm_info_list[] = {
3160         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3161 };
3162 #endif
3163
3164 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3165 {
3166 #if defined(CONFIG_DEBUG_FS)
3167         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3168 #else
3169         return 0;
3170 #endif
3171 }