drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "nv.h"
  55 #include "bif/bif_4_1_d.h"
  56 #include <linux/pci.h>
  57 #include <linux/firmware.h>
  58 #include "amdgpu_vf_error.h"
  59
  60 #include "amdgpu_amdkfd.h"
  61 #include "amdgpu_pm.h"
  62
  63 #include "amdgpu_xgmi.h"
  64 #include "amdgpu_ras.h"
  65 #include "amdgpu_pmu.h"
  66
  67 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  68 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  69 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  70 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  71 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  72 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
  73
  74 #define AMDGPU_RESUME_MS                2000
  75
  76 static const char *amdgpu_asic_name[] = {
  77         "TAHITI",
  78         "PITCAIRN",
  79         "VERDE",
  80         "OLAND",
  81         "HAINAN",
  82         "BONAIRE",
  83         "KAVERI",
  84         "KABINI",
  85         "HAWAII",
  86         "MULLINS",
  87         "TOPAZ",
  88         "TONGA",
  89         "FIJI",
  90         "CARRIZO",
  91         "STONEY",
  92         "POLARIS10",
  93         "POLARIS11",
  94         "POLARIS12",
  95         "VEGAM",
  96         "VEGA10",
  97         "VEGA12",
  98         "VEGA20",
  99         "RAVEN",
 100         "NAVI10",
 101         "LAST",
 102 };
 103
 104 /**
 105  * DOC: pcie_replay_count
 106  *
 107  * The amdgpu driver provides a sysfs API for reporting the total number
 108  * of PCIe replays (NAKs)
 109  * The file pcie_replay_count is used for this and returns the total
 110  * number of replays as a sum of the NAKs generated and NAKs received
 111  */
 112
 113 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
 114                 struct device_attribute *attr, char *buf)
 115 {
 116         struct drm_device *ddev = dev_get_drvdata(dev);
 117         struct amdgpu_device *adev = ddev->dev_private;
 118         uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
 119
 120         return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
 121 }
 122
 123 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 124                 amdgpu_device_get_pcie_replay_count, NULL);
 125
 126 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 127
 128 /**
 129  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 130  *
 131  * @dev: drm_device pointer
 132  *
 133  * Returns true if the device is a dGPU with HG/PX power control,
 134  * otherwise return false.
 135  */
 136 bool amdgpu_device_is_px(struct drm_device *dev)
 137 {
 138         struct amdgpu_device *adev = dev->dev_private;
 139
 140         if (adev->flags & AMD_IS_PX)
 141                 return true;
 142         return false;
 143 }
 144
 145 /*
 146  * MMIO register access helper functions.
 147  */
 148 /**
 149  * amdgpu_mm_rreg - read a memory mapped IO register
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @reg: dword aligned register offset
 153  * @acc_flags: access flags which require special behavior
 154  *
 155  * Returns the 32 bit value from the offset specified.
 156  */
 157 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 158                         uint32_t acc_flags)
 159 {
 160         uint32_t ret;
 161
 162         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 163                 return amdgpu_virt_kiq_rreg(adev, reg);
 164
 165         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 166                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 167         else {
 168                 unsigned long flags;
 169
 170                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 171                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 172                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 173                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 174         }
 175         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 176         return ret;
 177 }
 178
 179 /*
 180  * MMIO register read with bytes helper functions
 181  * @offset:bytes offset from MMIO start
 182  *
 183 */
 184
 185 /**
 186  * amdgpu_mm_rreg8 - read a memory mapped IO register
 187  *
 188  * @adev: amdgpu_device pointer
 189  * @offset: byte aligned register offset
 190  *
 191  * Returns the 8 bit value from the offset specified.
 192  */
 193 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 194         if (offset < adev->rmmio_size)
 195                 return (readb(adev->rmmio + offset));
 196         BUG();
 197 }
 198
 199 /*
 200  * MMIO register write with bytes helper functions
 201  * @offset:bytes offset from MMIO start
 202  * @value: the value want to be written to the register
 203  *
 204 */
 205 /**
 206  * amdgpu_mm_wreg8 - read a memory mapped IO register
 207  *
 208  * @adev: amdgpu_device pointer
 209  * @offset: byte aligned register offset
 210  * @value: 8 bit value to write
 211  *
 212  * Writes the value specified to the offset specified.
 213  */
 214 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 215         if (offset < adev->rmmio_size)
 216                 writeb(value, adev->rmmio + offset);
 217         else
 218                 BUG();
 219 }
 220
 221 /**
 222  * amdgpu_mm_wreg - write to a memory mapped IO register
 223  *
 224  * @adev: amdgpu_device pointer
 225  * @reg: dword aligned register offset
 226  * @v: 32 bit value to write to the register
 227  * @acc_flags: access flags which require special behavior
 228  *
 229  * Writes the value specified to the offset specified.
 230  */
 231 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 232                     uint32_t acc_flags)
 233 {
 234         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 235
 236         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 237                 adev->last_mm_index = v;
 238         }
 239
 240         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 241                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 242
 243         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 244                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 245         else {
 246                 unsigned long flags;
 247
 248                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 249                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 250                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 251                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 252         }
 253
 254         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 255                 udelay(500);
 256         }
 257 }
 258
 259 /**
 260  * amdgpu_io_rreg - read an IO register
 261  *
 262  * @adev: amdgpu_device pointer
 263  * @reg: dword aligned register offset
 264  *
 265  * Returns the 32 bit value from the offset specified.
 266  */
 267 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 268 {
 269         if ((reg * 4) < adev->rio_mem_size)
 270                 return ioread32(adev->rio_mem + (reg * 4));
 271         else {
 272                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 273                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 274         }
 275 }
 276
 277 /**
 278  * amdgpu_io_wreg - write to an IO register
 279  *
 280  * @adev: amdgpu_device pointer
 281  * @reg: dword aligned register offset
 282  * @v: 32 bit value to write to the register
 283  *
 284  * Writes the value specified to the offset specified.
 285  */
 286 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 287 {
 288         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 289                 adev->last_mm_index = v;
 290         }
 291
 292         if ((reg * 4) < adev->rio_mem_size)
 293                 iowrite32(v, adev->rio_mem + (reg * 4));
 294         else {
 295                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 296                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 297         }
 298
 299         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 300                 udelay(500);
 301         }
 302 }
 303
 304 /**
 305  * amdgpu_mm_rdoorbell - read a doorbell dword
 306  *
 307  * @adev: amdgpu_device pointer
 308  * @index: doorbell index
 309  *
 310  * Returns the value in the doorbell aperture at the
 311  * requested doorbell index (CIK).
 312  */
 313 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 314 {
 315         if (index < adev->doorbell.num_doorbells) {
 316                 return readl(adev->doorbell.ptr + index);
 317         } else {
 318                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 319                 return 0;
 320         }
 321 }
 322
 323 /**
 324  * amdgpu_mm_wdoorbell - write a doorbell dword
 325  *
 326  * @adev: amdgpu_device pointer
 327  * @index: doorbell index
 328  * @v: value to write
 329  *
 330  * Writes @v to the doorbell aperture at the
 331  * requested doorbell index (CIK).
 332  */
 333 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 334 {
 335         if (index < adev->doorbell.num_doorbells) {
 336                 writel(v, adev->doorbell.ptr + index);
 337         } else {
 338                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 339         }
 340 }
 341
 342 /**
 343  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 344  *
 345  * @adev: amdgpu_device pointer
 346  * @index: doorbell index
 347  *
 348  * Returns the value in the doorbell aperture at the
 349  * requested doorbell index (VEGA10+).
 350  */
 351 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 352 {
 353         if (index < adev->doorbell.num_doorbells) {
 354                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 355         } else {
 356                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 363  *
 364  * @adev: amdgpu_device pointer
 365  * @index: doorbell index
 366  * @v: value to write
 367  *
 368  * Writes @v to the doorbell aperture at the
 369  * requested doorbell index (VEGA10+).
 370  */
 371 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 372 {
 373         if (index < adev->doorbell.num_doorbells) {
 374                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 375         } else {
 376                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 377         }
 378 }
 379
 380 /**
 381  * amdgpu_invalid_rreg - dummy reg read function
 382  *
 383  * @adev: amdgpu device pointer
 384  * @reg: offset of register
 385  *
 386  * Dummy register read function.  Used for register blocks
 387  * that certain asics don't have (all asics).
 388  * Returns the value in the register.
 389  */
 390 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 391 {
 392         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 393         BUG();
 394         return 0;
 395 }
 396
 397 /**
 398  * amdgpu_invalid_wreg - dummy reg write function
 399  *
 400  * @adev: amdgpu device pointer
 401  * @reg: offset of register
 402  * @v: value to write to the register
 403  *
 404  * Dummy register read function.  Used for register blocks
 405  * that certain asics don't have (all asics).
 406  */
 407 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 408 {
 409         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 410                   reg, v);
 411         BUG();
 412 }
 413
 414 /**
 415  * amdgpu_block_invalid_rreg - dummy reg read function
 416  *
 417  * @adev: amdgpu device pointer
 418  * @block: offset of instance
 419  * @reg: offset of register
 420  *
 421  * Dummy register read function.  Used for register blocks
 422  * that certain asics don't have (all asics).
 423  * Returns the value in the register.
 424  */
 425 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 426                                           uint32_t block, uint32_t reg)
 427 {
 428         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 429                   reg, block);
 430         BUG();
 431         return 0;
 432 }
 433
 434 /**
 435  * amdgpu_block_invalid_wreg - dummy reg write function
 436  *
 437  * @adev: amdgpu device pointer
 438  * @block: offset of instance
 439  * @reg: offset of register
 440  * @v: value to write to the register
 441  *
 442  * Dummy register read function.  Used for register blocks
 443  * that certain asics don't have (all asics).
 444  */
 445 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 446                                       uint32_t block,
 447                                       uint32_t reg, uint32_t v)
 448 {
 449         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 450                   reg, block, v);
 451         BUG();
 452 }
 453
 454 /**
 455  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 456  *
 457  * @adev: amdgpu device pointer
 458  *
 459  * Allocates a scratch page of VRAM for use by various things in the
 460  * driver.
 461  */
 462 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 463 {
 464         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 465                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 466                                        &adev->vram_scratch.robj,
 467                                        &adev->vram_scratch.gpu_addr,
 468                                        (void **)&adev->vram_scratch.ptr);
 469 }
 470
 471 /**
 472  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 473  *
 474  * @adev: amdgpu device pointer
 475  *
 476  * Frees the VRAM scratch page.
 477  */
 478 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 479 {
 480         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 481 }
 482
 483 /**
 484  * amdgpu_device_program_register_sequence - program an array of registers.
 485  *
 486  * @adev: amdgpu_device pointer
 487  * @registers: pointer to the register array
 488  * @array_size: size of the register array
 489  *
 490  * Programs an array or registers with and and or masks.
 491  * This is a helper for setting golden registers.
 492  */
 493 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 494                                              const u32 *registers,
 495                                              const u32 array_size)
 496 {
 497         u32 tmp, reg, and_mask, or_mask;
 498         int i;
 499
 500         if (array_size % 3)
 501                 return;
 502
 503         for (i = 0; i < array_size; i +=3) {
 504                 reg = registers[i + 0];
 505                 and_mask = registers[i + 1];
 506                 or_mask = registers[i + 2];
 507
 508                 if (and_mask == 0xffffffff) {
 509                         tmp = or_mask;
 510                 } else {
 511                         tmp = RREG32(reg);
 512                         tmp &= ~and_mask;
 513                         if (adev->family >= AMDGPU_FAMILY_AI)
 514                                 tmp |= (or_mask & and_mask);
 515                         else
 516                                 tmp |= or_mask;
 517                 }
 518                 WREG32(reg, tmp);
 519         }
 520 }
 521
 522 /**
 523  * amdgpu_device_pci_config_reset - reset the GPU
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Resets the GPU using the pci config reset sequence.
 528  * Only applicable to asics prior to vega10.
 529  */
 530 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 531 {
 532         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 533 }
 534
 535 /*
 536  * GPU doorbell aperture helpers function.
 537  */
 538 /**
 539  * amdgpu_device_doorbell_init - Init doorbell driver information.
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * Init doorbell driver information (CIK)
 544  * Returns 0 on success, error on failure.
 545  */
 546 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 547 {
 548
 549         /* No doorbell on SI hardware generation */
 550         if (adev->asic_type < CHIP_BONAIRE) {
 551                 adev->doorbell.base = 0;
 552                 adev->doorbell.size = 0;
 553                 adev->doorbell.num_doorbells = 0;
 554                 adev->doorbell.ptr = NULL;
 555                 return 0;
 556         }
 557
 558         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 559                 return -EINVAL;
 560
 561         amdgpu_asic_init_doorbell_index(adev);
 562
 563         /* doorbell bar mapping */
 564         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 565         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 566
 567         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 568                                              adev->doorbell_index.max_assignment+1);
 569         if (adev->doorbell.num_doorbells == 0)
 570                 return -EINVAL;
 571
 572         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 573          * paging queue doorbell use the second page. The
 574          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 575          * doorbells are in the first page. So with paging queue enabled,
 576          * the max num_doorbells should + 1 page (0x400 in dword)
 577          */
 578         if (adev->asic_type >= CHIP_VEGA10)
 579                 adev->doorbell.num_doorbells += 0x400;
 580
 581         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 582                                      adev->doorbell.num_doorbells *
 583                                      sizeof(u32));
 584         if (adev->doorbell.ptr == NULL)
 585                 return -ENOMEM;
 586
 587         return 0;
 588 }
 589
 590 /**
 591  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 592  *
 593  * @adev: amdgpu_device pointer
 594  *
 595  * Tear down doorbell driver information (CIK)
 596  */
 597 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 598 {
 599         iounmap(adev->doorbell.ptr);
 600         adev->doorbell.ptr = NULL;
 601 }
 602
 603
 604
 605 /*
 606  * amdgpu_device_wb_*()
 607  * Writeback is the method by which the GPU updates special pages in memory
 608  * with the status of certain GPU events (fences, ring pointers,etc.).
 609  */
 610
 611 /**
 612  * amdgpu_device_wb_fini - Disable Writeback and free memory
 613  *
 614  * @adev: amdgpu_device pointer
 615  *
 616  * Disables Writeback and frees the Writeback memory (all asics).
 617  * Used at driver shutdown.
 618  */
 619 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 620 {
 621         if (adev->wb.wb_obj) {
 622                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 623                                       &adev->wb.gpu_addr,
 624                                       (void **)&adev->wb.wb);
 625                 adev->wb.wb_obj = NULL;
 626         }
 627 }
 628
 629 /**
 630  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 631  *
 632  * @adev: amdgpu_device pointer
 633  *
 634  * Initializes writeback and allocates writeback memory (all asics).
 635  * Used at driver startup.
 636  * Returns 0 on success or an -error on failure.
 637  */
 638 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 639 {
 640         int r;
 641
 642         if (adev->wb.wb_obj == NULL) {
 643                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 644                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 645                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 646                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 647                                             (void **)&adev->wb.wb);
 648                 if (r) {
 649                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 650                         return r;
 651                 }
 652
 653                 adev->wb.num_wb = AMDGPU_MAX_WB;
 654                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 655
 656                 /* clear wb memory */
 657                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 658         }
 659
 660         return 0;
 661 }
 662
 663 /**
 664  * amdgpu_device_wb_get - Allocate a wb entry
 665  *
 666  * @adev: amdgpu_device pointer
 667  * @wb: wb index
 668  *
 669  * Allocate a wb slot for use by the driver (all asics).
 670  * Returns 0 on success or -EINVAL on failure.
 671  */
 672 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 673 {
 674         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 675
 676         if (offset < adev->wb.num_wb) {
 677                 __set_bit(offset, adev->wb.used);
 678                 *wb = offset << 3; /* convert to dw offset */
 679                 return 0;
 680         } else {
 681                 return -EINVAL;
 682         }
 683 }
 684
 685 /**
 686  * amdgpu_device_wb_free - Free a wb entry
 687  *
 688  * @adev: amdgpu_device pointer
 689  * @wb: wb index
 690  *
 691  * Free a wb slot allocated for use by the driver (all asics)
 692  */
 693 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 694 {
 695         wb >>= 3;
 696         if (wb < adev->wb.num_wb)
 697                 __clear_bit(wb, adev->wb.used);
 698 }
 699
 700 /**
 701  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 702  *
 703  * @adev: amdgpu_device pointer
 704  *
 705  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 706  * to fail, but if any of the BARs is not accessible after the size we abort
 707  * driver loading by returning -ENODEV.
 708  */
 709 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 710 {
 711         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 712         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 713         struct pci_bus *root;
 714         struct resource *res;
 715         unsigned i;
 716         u16 cmd;
 717         int r;
 718
 719         /* Bypass for VF */
 720         if (amdgpu_sriov_vf(adev))
 721                 return 0;
 722
 723         /* Check if the root BUS has 64bit memory resources */
 724         root = adev->pdev->bus;
 725         while (root->parent)
 726                 root = root->parent;
 727
 728         pci_bus_for_each_resource(root, res, i) {
 729                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 730                     res->start > 0x100000000ull)
 731                         break;
 732         }
 733
 734         /* Trying to resize is pointless without a root hub window above 4GB */
 735         if (!res)
 736                 return 0;
 737
 738         /* Disable memory decoding while we change the BAR addresses and size */
 739         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 740         pci_write_config_word(adev->pdev, PCI_COMMAND,
 741                               cmd & ~PCI_COMMAND_MEMORY);
 742
 743         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 744         amdgpu_device_doorbell_fini(adev);
 745         if (adev->asic_type >= CHIP_BONAIRE)
 746                 pci_release_resource(adev->pdev, 2);
 747
 748         pci_release_resource(adev->pdev, 0);
 749
 750         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 751         if (r == -ENOSPC)
 752                 DRM_INFO("Not enough PCI address space for a large BAR.");
 753         else if (r && r != -ENOTSUPP)
 754                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 755
 756         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 757
 758         /* When the doorbell or fb BAR isn't available we have no chance of
 759          * using the device.
 760          */
 761         r = amdgpu_device_doorbell_init(adev);
 762         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 763                 return -ENODEV;
 764
 765         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 766
 767         return 0;
 768 }
 769
 770 /*
 771  * GPU helpers function.
 772  */
 773 /**
 774  * amdgpu_device_need_post - check if the hw need post or not
 775  *
 776  * @adev: amdgpu_device pointer
 777  *
 778  * Check if the asic has been initialized (all asics) at driver startup
 779  * or post is needed if  hw reset is performed.
 780  * Returns true if need or false if not.
 781  */
 782 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 783 {
 784         uint32_t reg;
 785
 786         if (amdgpu_sriov_vf(adev))
 787                 return false;
 788
 789         if (amdgpu_passthrough(adev)) {
 790                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 791                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 792                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 793                  * vpost executed for smc version below 22.15
 794                  */
 795                 if (adev->asic_type == CHIP_FIJI) {
 796                         int err;
 797                         uint32_t fw_ver;
 798                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 799                         /* force vPost if error occured */
 800                         if (err)
 801                                 return true;
 802
 803                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 804                         if (fw_ver < 0x00160e00)
 805                                 return true;
 806                 }
 807         }
 808
 809         if (adev->has_hw_reset) {
 810                 adev->has_hw_reset = false;
 811                 return true;
 812         }
 813
 814         /* bios scratch used on CIK+ */
 815         if (adev->asic_type >= CHIP_BONAIRE)
 816                 return amdgpu_atombios_scratch_need_asic_init(adev);
 817
 818         /* check MEM_SIZE for older asics */
 819         reg = amdgpu_asic_get_config_memsize(adev);
 820
 821         if ((reg != 0) && (reg != 0xffffffff))
 822                 return false;
 823
 824         return true;
 825 }
 826
 827 /* if we get transitioned to only one device, take VGA back */
 828 /**
 829  * amdgpu_device_vga_set_decode - enable/disable vga decode
 830  *
 831  * @cookie: amdgpu_device pointer
 832  * @state: enable/disable vga decode
 833  *
 834  * Enable/disable vga decode (all asics).
 835  * Returns VGA resource flags.
 836  */
 837 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 838 {
 839         struct amdgpu_device *adev = cookie;
 840         amdgpu_asic_set_vga_state(adev, state);
 841         if (state)
 842                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 843                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 844         else
 845                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 846 }
 847
 848 /**
 849  * amdgpu_device_check_block_size - validate the vm block size
 850  *
 851  * @adev: amdgpu_device pointer
 852  *
 853  * Validates the vm block size specified via module parameter.
 854  * The vm block size defines number of bits in page table versus page directory,
 855  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 856  * page table and the remaining bits are in the page directory.
 857  */
 858 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 859 {
 860         /* defines number of bits in page table versus page directory,
 861          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 862          * page table and the remaining bits are in the page directory */
 863         if (amdgpu_vm_block_size == -1)
 864                 return;
 865
 866         if (amdgpu_vm_block_size < 9) {
 867                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 868                          amdgpu_vm_block_size);
 869                 amdgpu_vm_block_size = -1;
 870         }
 871 }
 872
 873 /**
 874  * amdgpu_device_check_vm_size - validate the vm size
 875  *
 876  * @adev: amdgpu_device pointer
 877  *
 878  * Validates the vm size in GB specified via module parameter.
 879  * The VM size is the size of the GPU virtual memory space in GB.
 880  */
 881 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 882 {
 883         /* no need to check the default value */
 884         if (amdgpu_vm_size == -1)
 885                 return;
 886
 887         if (amdgpu_vm_size < 1) {
 888                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 889                          amdgpu_vm_size);
 890                 amdgpu_vm_size = -1;
 891         }
 892 }
 893
 894 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 895 {
 896         struct sysinfo si;
 897         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 898         uint64_t total_memory;
 899         uint64_t dram_size_seven_GB = 0x1B8000000;
 900         uint64_t dram_size_three_GB = 0xB8000000;
 901
 902         if (amdgpu_smu_memory_pool_size == 0)
 903                 return;
 904
 905         if (!is_os_64) {
 906                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 907                 goto def_value;
 908         }
 909         si_meminfo(&si);
 910         total_memory = (uint64_t)si.totalram * si.mem_unit;
 911
 912         if ((amdgpu_smu_memory_pool_size == 1) ||
 913                 (amdgpu_smu_memory_pool_size == 2)) {
 914                 if (total_memory < dram_size_three_GB)
 915                         goto def_value1;
 916         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 917                 (amdgpu_smu_memory_pool_size == 8)) {
 918                 if (total_memory < dram_size_seven_GB)
 919                         goto def_value1;
 920         } else {
 921                 DRM_WARN("Smu memory pool size not supported\n");
 922                 goto def_value;
 923         }
 924         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 925
 926         return;
 927
 928 def_value1:
 929         DRM_WARN("No enough system memory\n");
 930 def_value:
 931         adev->pm.smu_prv_buffer_size = 0;
 932 }
 933
 934 /**
 935  * amdgpu_device_check_arguments - validate module params
 936  *
 937  * @adev: amdgpu_device pointer
 938  *
 939  * Validates certain module parameters and updates
 940  * the associated values used by the driver (all asics).
 941  */
 942 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
 943 {
 944         int ret = 0;
 945
 946         if (amdgpu_sched_jobs < 4) {
 947                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 948                          amdgpu_sched_jobs);
 949                 amdgpu_sched_jobs = 4;
 950         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 951                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 952                          amdgpu_sched_jobs);
 953                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 954         }
 955
 956         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 957                 /* gart size must be greater or equal to 32M */
 958                 dev_warn(adev->dev, "gart size (%d) too small\n",
 959                          amdgpu_gart_size);
 960                 amdgpu_gart_size = -1;
 961         }
 962
 963         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 964                 /* gtt size must be greater or equal to 32M */
 965                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 966                                  amdgpu_gtt_size);
 967                 amdgpu_gtt_size = -1;
 968         }
 969
 970         /* valid range is between 4 and 9 inclusive */
 971         if (amdgpu_vm_fragment_size != -1 &&
 972             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 973                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 974                 amdgpu_vm_fragment_size = -1;
 975         }
 976
 977         amdgpu_device_check_smu_prv_buffer_size(adev);
 978
 979         amdgpu_device_check_vm_size(adev);
 980
 981         amdgpu_device_check_block_size(adev);
 982
 983         ret = amdgpu_device_get_job_timeout_settings(adev);
 984         if (ret) {
 985                 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
 986                 return ret;
 987         }
 988
 989         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 990
 991         return ret;
 992 }
 993
 994 /**
 995  * amdgpu_switcheroo_set_state - set switcheroo state
 996  *
 997  * @pdev: pci dev pointer
 998  * @state: vga_switcheroo state
 999  *
1000  * Callback for the switcheroo driver.  Suspends or resumes the
1001  * the asics before or after it is powered up using ACPI methods.
1002  */
1003 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1004 {
1005         struct drm_device *dev = pci_get_drvdata(pdev);
1006
1007         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1008                 return;
1009
1010         if (state == VGA_SWITCHEROO_ON) {
1011                 pr_info("amdgpu: switched on\n");
1012                 /* don't suspend or resume card normally */
1013                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1014
1015                 amdgpu_device_resume(dev, true, true);
1016
1017                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1018                 drm_kms_helper_poll_enable(dev);
1019         } else {
1020                 pr_info("amdgpu: switched off\n");
1021                 drm_kms_helper_poll_disable(dev);
1022                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1023                 amdgpu_device_suspend(dev, true, true);
1024                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1025         }
1026 }
1027
1028 /**
1029  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1030  *
1031  * @pdev: pci dev pointer
1032  *
1033  * Callback for the switcheroo driver.  Check of the switcheroo
1034  * state can be changed.
1035  * Returns true if the state can be changed, false if not.
1036  */
1037 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1038 {
1039         struct drm_device *dev = pci_get_drvdata(pdev);
1040
1041         /*
1042         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1043         * locking inversion with the driver load path. And the access here is
1044         * completely racy anyway. So don't bother with locking for now.
1045         */
1046         return dev->open_count == 0;
1047 }
1048
1049 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1050         .set_gpu_state = amdgpu_switcheroo_set_state,
1051         .reprobe = NULL,
1052         .can_switch = amdgpu_switcheroo_can_switch,
1053 };
1054
1055 /**
1056  * amdgpu_device_ip_set_clockgating_state - set the CG state
1057  *
1058  * @dev: amdgpu_device pointer
1059  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1060  * @state: clockgating state (gate or ungate)
1061  *
1062  * Sets the requested clockgating state for all instances of
1063  * the hardware IP specified.
1064  * Returns the error code from the last instance.
1065  */
1066 int amdgpu_device_ip_set_clockgating_state(void *dev,
1067                                            enum amd_ip_block_type block_type,
1068                                            enum amd_clockgating_state state)
1069 {
1070         struct amdgpu_device *adev = dev;
1071         int i, r = 0;
1072
1073         for (i = 0; i < adev->num_ip_blocks; i++) {
1074                 if (!adev->ip_blocks[i].status.valid)
1075                         continue;
1076                 if (adev->ip_blocks[i].version->type != block_type)
1077                         continue;
1078                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1079                         continue;
1080                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1081                         (void *)adev, state);
1082                 if (r)
1083                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1084                                   adev->ip_blocks[i].version->funcs->name, r);
1085         }
1086         return r;
1087 }
1088
1089 /**
1090  * amdgpu_device_ip_set_powergating_state - set the PG state
1091  *
1092  * @dev: amdgpu_device pointer
1093  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1094  * @state: powergating state (gate or ungate)
1095  *
1096  * Sets the requested powergating state for all instances of
1097  * the hardware IP specified.
1098  * Returns the error code from the last instance.
1099  */
1100 int amdgpu_device_ip_set_powergating_state(void *dev,
1101                                            enum amd_ip_block_type block_type,
1102                                            enum amd_powergating_state state)
1103 {
1104         struct amdgpu_device *adev = dev;
1105         int i, r = 0;
1106
1107         for (i = 0; i < adev->num_ip_blocks; i++) {
1108                 if (!adev->ip_blocks[i].status.valid)
1109                         continue;
1110                 if (adev->ip_blocks[i].version->type != block_type)
1111                         continue;
1112                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1113                         continue;
1114                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1115                         (void *)adev, state);
1116                 if (r)
1117                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1118                                   adev->ip_blocks[i].version->funcs->name, r);
1119         }
1120         return r;
1121 }
1122
1123 /**
1124  * amdgpu_device_ip_get_clockgating_state - get the CG state
1125  *
1126  * @adev: amdgpu_device pointer
1127  * @flags: clockgating feature flags
1128  *
1129  * Walks the list of IPs on the device and updates the clockgating
1130  * flags for each IP.
1131  * Updates @flags with the feature flags for each hardware IP where
1132  * clockgating is enabled.
1133  */
1134 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1135                                             u32 *flags)
1136 {
1137         int i;
1138
1139         for (i = 0; i < adev->num_ip_blocks; i++) {
1140                 if (!adev->ip_blocks[i].status.valid)
1141                         continue;
1142                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1143                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1144         }
1145 }
1146
1147 /**
1148  * amdgpu_device_ip_wait_for_idle - wait for idle
1149  *
1150  * @adev: amdgpu_device pointer
1151  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1152  *
1153  * Waits for the request hardware IP to be idle.
1154  * Returns 0 for success or a negative error code on failure.
1155  */
1156 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1157                                    enum amd_ip_block_type block_type)
1158 {
1159         int i, r;
1160
1161         for (i = 0; i < adev->num_ip_blocks; i++) {
1162                 if (!adev->ip_blocks[i].status.valid)
1163                         continue;
1164                 if (adev->ip_blocks[i].version->type == block_type) {
1165                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1166                         if (r)
1167                                 return r;
1168                         break;
1169                 }
1170         }
1171         return 0;
1172
1173 }
1174
1175 /**
1176  * amdgpu_device_ip_is_idle - is the hardware IP idle
1177  *
1178  * @adev: amdgpu_device pointer
1179  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1180  *
1181  * Check if the hardware IP is idle or not.
1182  * Returns true if it the IP is idle, false if not.
1183  */
1184 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1185                               enum amd_ip_block_type block_type)
1186 {
1187         int i;
1188
1189         for (i = 0; i < adev->num_ip_blocks; i++) {
1190                 if (!adev->ip_blocks[i].status.valid)
1191                         continue;
1192                 if (adev->ip_blocks[i].version->type == block_type)
1193                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1194         }
1195         return true;
1196
1197 }
1198
1199 /**
1200  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1201  *
1202  * @adev: amdgpu_device pointer
1203  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1204  *
1205  * Returns a pointer to the hardware IP block structure
1206  * if it exists for the asic, otherwise NULL.
1207  */
1208 struct amdgpu_ip_block *
1209 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1210                               enum amd_ip_block_type type)
1211 {
1212         int i;
1213
1214         for (i = 0; i < adev->num_ip_blocks; i++)
1215                 if (adev->ip_blocks[i].version->type == type)
1216                         return &adev->ip_blocks[i];
1217
1218         return NULL;
1219 }
1220
1221 /**
1222  * amdgpu_device_ip_block_version_cmp
1223  *
1224  * @adev: amdgpu_device pointer
1225  * @type: enum amd_ip_block_type
1226  * @major: major version
1227  * @minor: minor version
1228  *
1229  * return 0 if equal or greater
1230  * return 1 if smaller or the ip_block doesn't exist
1231  */
1232 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1233                                        enum amd_ip_block_type type,
1234                                        u32 major, u32 minor)
1235 {
1236         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1237
1238         if (ip_block && ((ip_block->version->major > major) ||
1239                         ((ip_block->version->major == major) &&
1240                         (ip_block->version->minor >= minor))))
1241                 return 0;
1242
1243         return 1;
1244 }
1245
1246 /**
1247  * amdgpu_device_ip_block_add
1248  *
1249  * @adev: amdgpu_device pointer
1250  * @ip_block_version: pointer to the IP to add
1251  *
1252  * Adds the IP block driver information to the collection of IPs
1253  * on the asic.
1254  */
1255 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1256                                const struct amdgpu_ip_block_version *ip_block_version)
1257 {
1258         if (!ip_block_version)
1259                 return -EINVAL;
1260
1261         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1262                   ip_block_version->funcs->name);
1263
1264         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1265
1266         return 0;
1267 }
1268
1269 /**
1270  * amdgpu_device_enable_virtual_display - enable virtual display feature
1271  *
1272  * @adev: amdgpu_device pointer
1273  *
1274  * Enabled the virtual display feature if the user has enabled it via
1275  * the module parameter virtual_display.  This feature provides a virtual
1276  * display hardware on headless boards or in virtualized environments.
1277  * This function parses and validates the configuration string specified by
1278  * the user and configues the virtual display configuration (number of
1279  * virtual connectors, crtcs, etc.) specified.
1280  */
1281 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1282 {
1283         adev->enable_virtual_display = false;
1284
1285         if (amdgpu_virtual_display) {
1286                 struct drm_device *ddev = adev->ddev;
1287                 const char *pci_address_name = pci_name(ddev->pdev);
1288                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1289
1290                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1291                 pciaddstr_tmp = pciaddstr;
1292                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1293                         pciaddname = strsep(&pciaddname_tmp, ",");
1294                         if (!strcmp("all", pciaddname)
1295                             || !strcmp(pci_address_name, pciaddname)) {
1296                                 long num_crtc;
1297                                 int res = -1;
1298
1299                                 adev->enable_virtual_display = true;
1300
1301                                 if (pciaddname_tmp)
1302                                         res = kstrtol(pciaddname_tmp, 10,
1303                                                       &num_crtc);
1304
1305                                 if (!res) {
1306                                         if (num_crtc < 1)
1307                                                 num_crtc = 1;
1308                                         if (num_crtc > 6)
1309                                                 num_crtc = 6;
1310                                         adev->mode_info.num_crtc = num_crtc;
1311                                 } else {
1312                                         adev->mode_info.num_crtc = 1;
1313                                 }
1314                                 break;
1315                         }
1316                 }
1317
1318                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1319                          amdgpu_virtual_display, pci_address_name,
1320                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1321
1322                 kfree(pciaddstr);
1323         }
1324 }
1325
1326 /**
1327  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1328  *
1329  * @adev: amdgpu_device pointer
1330  *
1331  * Parses the asic configuration parameters specified in the gpu info
1332  * firmware and makes them availale to the driver for use in configuring
1333  * the asic.
1334  * Returns 0 on success, -EINVAL on failure.
1335  */
1336 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1337 {
1338         const char *chip_name;
1339         char fw_name[30];
1340         int err;
1341         const struct gpu_info_firmware_header_v1_0 *hdr;
1342
1343         adev->firmware.gpu_info_fw = NULL;
1344
1345         switch (adev->asic_type) {
1346         case CHIP_TOPAZ:
1347         case CHIP_TONGA:
1348         case CHIP_FIJI:
1349         case CHIP_POLARIS10:
1350         case CHIP_POLARIS11:
1351         case CHIP_POLARIS12:
1352         case CHIP_VEGAM:
1353         case CHIP_CARRIZO:
1354         case CHIP_STONEY:
1355 #ifdef CONFIG_DRM_AMDGPU_SI
1356         case CHIP_VERDE:
1357         case CHIP_TAHITI:
1358         case CHIP_PITCAIRN:
1359         case CHIP_OLAND:
1360         case CHIP_HAINAN:
1361 #endif
1362 #ifdef CONFIG_DRM_AMDGPU_CIK
1363         case CHIP_BONAIRE:
1364         case CHIP_HAWAII:
1365         case CHIP_KAVERI:
1366         case CHIP_KABINI:
1367         case CHIP_MULLINS:
1368 #endif
1369         case CHIP_VEGA20:
1370         default:
1371                 return 0;
1372         case CHIP_VEGA10:
1373                 chip_name = "vega10";
1374                 break;
1375         case CHIP_VEGA12:
1376                 chip_name = "vega12";
1377                 break;
1378         case CHIP_RAVEN:
1379                 if (adev->rev_id >= 8)
1380                         chip_name = "raven2";
1381                 else if (adev->pdev->device == 0x15d8)
1382                         chip_name = "picasso";
1383                 else
1384                         chip_name = "raven";
1385                 break;
1386         case CHIP_NAVI10:
1387                 chip_name = "navi10";
1388                 break;
1389         }
1390
1391         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1392         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1393         if (err) {
1394                 dev_err(adev->dev,
1395                         "Failed to load gpu_info firmware \"%s\"\n",
1396                         fw_name);
1397                 goto out;
1398         }
1399         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1400         if (err) {
1401                 dev_err(adev->dev,
1402                         "Failed to validate gpu_info firmware \"%s\"\n",
1403                         fw_name);
1404                 goto out;
1405         }
1406
1407         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1408         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1409
1410         switch (hdr->version_major) {
1411         case 1:
1412         {
1413                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1414                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1415                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1416
1417                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1418                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1419                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1420                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1421                 adev->gfx.config.max_texture_channel_caches =
1422                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1423                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1424                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1425                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1426                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1427                 adev->gfx.config.double_offchip_lds_buf =
1428                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1429                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1430                 adev->gfx.cu_info.max_waves_per_simd =
1431                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1432                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1433                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1434                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1435                 if (hdr->version_minor == 1) {
1436                         const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1437                                 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1438                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1439                         adev->gfx.config.num_sc_per_sh =
1440                                 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1441                         adev->gfx.config.num_packer_per_sc =
1442                                 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1443                 }
1444                 break;
1445         }
1446         default:
1447                 dev_err(adev->dev,
1448                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1449                 err = -EINVAL;
1450                 goto out;
1451         }
1452 out:
1453         return err;
1454 }
1455
1456 /**
1457  * amdgpu_device_ip_early_init - run early init for hardware IPs
1458  *
1459  * @adev: amdgpu_device pointer
1460  *
1461  * Early initialization pass for hardware IPs.  The hardware IPs that make
1462  * up each asic are discovered each IP's early_init callback is run.  This
1463  * is the first stage in initializing the asic.
1464  * Returns 0 on success, negative error code on failure.
1465  */
1466 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1467 {
1468         int i, r;
1469
1470         amdgpu_device_enable_virtual_display(adev);
1471
1472         switch (adev->asic_type) {
1473         case CHIP_TOPAZ:
1474         case CHIP_TONGA:
1475         case CHIP_FIJI:
1476         case CHIP_POLARIS10:
1477         case CHIP_POLARIS11:
1478         case CHIP_POLARIS12:
1479         case CHIP_VEGAM:
1480         case CHIP_CARRIZO:
1481         case CHIP_STONEY:
1482                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1483                         adev->family = AMDGPU_FAMILY_CZ;
1484                 else
1485                         adev->family = AMDGPU_FAMILY_VI;
1486
1487                 r = vi_set_ip_blocks(adev);
1488                 if (r)
1489                         return r;
1490                 break;
1491 #ifdef CONFIG_DRM_AMDGPU_SI
1492         case CHIP_VERDE:
1493         case CHIP_TAHITI:
1494         case CHIP_PITCAIRN:
1495         case CHIP_OLAND:
1496         case CHIP_HAINAN:
1497                 adev->family = AMDGPU_FAMILY_SI;
1498                 r = si_set_ip_blocks(adev);
1499                 if (r)
1500                         return r;
1501                 break;
1502 #endif
1503 #ifdef CONFIG_DRM_AMDGPU_CIK
1504         case CHIP_BONAIRE:
1505         case CHIP_HAWAII:
1506         case CHIP_KAVERI:
1507         case CHIP_KABINI:
1508         case CHIP_MULLINS:
1509                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1510                         adev->family = AMDGPU_FAMILY_CI;
1511                 else
1512                         adev->family = AMDGPU_FAMILY_KV;
1513
1514                 r = cik_set_ip_blocks(adev);
1515                 if (r)
1516                         return r;
1517                 break;
1518 #endif
1519         case CHIP_VEGA10:
1520         case CHIP_VEGA12:
1521         case CHIP_VEGA20:
1522         case CHIP_RAVEN:
1523                 if (adev->asic_type == CHIP_RAVEN)
1524                         adev->family = AMDGPU_FAMILY_RV;
1525                 else
1526                         adev->family = AMDGPU_FAMILY_AI;
1527
1528                 r = soc15_set_ip_blocks(adev);
1529                 if (r)
1530                         return r;
1531                 break;
1532         case  CHIP_NAVI10:
1533                 adev->family = AMDGPU_FAMILY_NV;
1534
1535                 r = nv_set_ip_blocks(adev);
1536                 if (r)
1537                         return r;
1538                 break;
1539         default:
1540                 /* FIXME: not supported yet */
1541                 return -EINVAL;
1542         }
1543
1544         r = amdgpu_device_parse_gpu_info_fw(adev);
1545         if (r)
1546                 return r;
1547
1548         amdgpu_amdkfd_device_probe(adev);
1549
1550         if (amdgpu_sriov_vf(adev)) {
1551                 r = amdgpu_virt_request_full_gpu(adev, true);
1552                 if (r)
1553                         return -EAGAIN;
1554
1555                 /* query the reg access mode at the very beginning */
1556                 amdgpu_virt_init_reg_access_mode(adev);
1557         }
1558
1559         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1560         if (amdgpu_sriov_vf(adev))
1561                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1562
1563         for (i = 0; i < adev->num_ip_blocks; i++) {
1564                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1565                         DRM_ERROR("disabled ip block: %d <%s>\n",
1566                                   i, adev->ip_blocks[i].version->funcs->name);
1567                         adev->ip_blocks[i].status.valid = false;
1568                 } else {
1569                         if (adev->ip_blocks[i].version->funcs->early_init) {
1570                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1571                                 if (r == -ENOENT) {
1572                                         adev->ip_blocks[i].status.valid = false;
1573                                 } else if (r) {
1574                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1575                                                   adev->ip_blocks[i].version->funcs->name, r);
1576                                         return r;
1577                                 } else {
1578                                         adev->ip_blocks[i].status.valid = true;
1579                                 }
1580                         } else {
1581                                 adev->ip_blocks[i].status.valid = true;
1582                         }
1583                 }
1584                 /* get the vbios after the asic_funcs are set up */
1585                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1586                         /* Read BIOS */
1587                         if (!amdgpu_get_bios(adev))
1588                                 return -EINVAL;
1589
1590                         r = amdgpu_atombios_init(adev);
1591                         if (r) {
1592                                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1593                                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1594                                 return r;
1595                         }
1596                 }
1597         }
1598
1599         adev->cg_flags &= amdgpu_cg_mask;
1600         adev->pg_flags &= amdgpu_pg_mask;
1601
1602         return 0;
1603 }
1604
1605 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1606 {
1607         int i, r;
1608
1609         for (i = 0; i < adev->num_ip_blocks; i++) {
1610                 if (!adev->ip_blocks[i].status.sw)
1611                         continue;
1612                 if (adev->ip_blocks[i].status.hw)
1613                         continue;
1614                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1615                     (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1616                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1617                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1618                         if (r) {
1619                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1620                                           adev->ip_blocks[i].version->funcs->name, r);
1621                                 return r;
1622                         }
1623                         adev->ip_blocks[i].status.hw = true;
1624                 }
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1631 {
1632         int i, r;
1633
1634         for (i = 0; i < adev->num_ip_blocks; i++) {
1635                 if (!adev->ip_blocks[i].status.sw)
1636                         continue;
1637                 if (adev->ip_blocks[i].status.hw)
1638                         continue;
1639                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1640                 if (r) {
1641                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1642                                   adev->ip_blocks[i].version->funcs->name, r);
1643                         return r;
1644                 }
1645                 adev->ip_blocks[i].status.hw = true;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1652 {
1653         int r = 0;
1654         int i;
1655         uint32_t smu_version;
1656
1657         if (adev->asic_type >= CHIP_VEGA10) {
1658                 for (i = 0; i < adev->num_ip_blocks; i++) {
1659                         if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1660                                 if (adev->in_gpu_reset || adev->in_suspend) {
1661                                         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1662                                                 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1663                                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1664                                         if (r) {
1665                                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1666                                                           adev->ip_blocks[i].version->funcs->name, r);
1667                                                 return r;
1668                                         }
1669                                 } else {
1670                                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1671                                         if (r) {
1672                                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1673                                                   adev->ip_blocks[i].version->funcs->name, r);
1674                                                 return r;
1675                                         }
1676                                 }
1677                                 adev->ip_blocks[i].status.hw = true;
1678                         }
1679                 }
1680         }
1681         r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1682
1683         return r;
1684 }
1685
1686 /**
1687  * amdgpu_device_ip_init - run init for hardware IPs
1688  *
1689  * @adev: amdgpu_device pointer
1690  *
1691  * Main initialization pass for hardware IPs.  The list of all the hardware
1692  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1693  * are run.  sw_init initializes the software state associated with each IP
1694  * and hw_init initializes the hardware associated with each IP.
1695  * Returns 0 on success, negative error code on failure.
1696  */
1697 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1698 {
1699         int i, r;
1700
1701         r = amdgpu_ras_init(adev);
1702         if (r)
1703                 return r;
1704
1705         for (i = 0; i < adev->num_ip_blocks; i++) {
1706                 if (!adev->ip_blocks[i].status.valid)
1707                         continue;
1708                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1709                 if (r) {
1710                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1711                                   adev->ip_blocks[i].version->funcs->name, r);
1712                         goto init_failed;
1713                 }
1714                 adev->ip_blocks[i].status.sw = true;
1715
1716                 /* need to do gmc hw init early so we can allocate gpu mem */
1717                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1718                         r = amdgpu_device_vram_scratch_init(adev);
1719                         if (r) {
1720                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1721                                 goto init_failed;
1722                         }
1723                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1724                         if (r) {
1725                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1726                                 goto init_failed;
1727                         }
1728                         r = amdgpu_device_wb_init(adev);
1729                         if (r) {
1730                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1731                                 goto init_failed;
1732                         }
1733                         adev->ip_blocks[i].status.hw = true;
1734
1735                         /* right after GMC hw init, we create CSA */
1736                         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1737                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1738                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1739                                                                 AMDGPU_CSA_SIZE);
1740                                 if (r) {
1741                                         DRM_ERROR("allocate CSA failed %d\n", r);
1742                                         goto init_failed;
1743                                 }
1744                         }
1745                 }
1746         }
1747
1748         r = amdgpu_ib_pool_init(adev);
1749         if (r) {
1750                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1751                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1752                 goto init_failed;
1753         }
1754
1755         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1756         if (r)
1757                 goto init_failed;
1758
1759         r = amdgpu_device_ip_hw_init_phase1(adev);
1760         if (r)
1761                 goto init_failed;
1762
1763         r = amdgpu_device_fw_loading(adev);
1764         if (r)
1765                 goto init_failed;
1766
1767         r = amdgpu_device_ip_hw_init_phase2(adev);
1768         if (r)
1769                 goto init_failed;
1770
1771         if (adev->gmc.xgmi.num_physical_nodes > 1)
1772                 amdgpu_xgmi_add_device(adev);
1773         amdgpu_amdkfd_device_init(adev);
1774
1775 init_failed:
1776         if (amdgpu_sriov_vf(adev)) {
1777                 if (!r)
1778                         amdgpu_virt_init_data_exchange(adev);
1779                 amdgpu_virt_release_full_gpu(adev, true);
1780         }
1781
1782         return r;
1783 }
1784
1785 /**
1786  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1787  *
1788  * @adev: amdgpu_device pointer
1789  *
1790  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1791  * this function before a GPU reset.  If the value is retained after a
1792  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1793  */
1794 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1795 {
1796         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1797 }
1798
1799 /**
1800  * amdgpu_device_check_vram_lost - check if vram is valid
1801  *
1802  * @adev: amdgpu_device pointer
1803  *
1804  * Checks the reset magic value written to the gart pointer in VRAM.
1805  * The driver calls this after a GPU reset to see if the contents of
1806  * VRAM is lost or now.
1807  * returns true if vram is lost, false if not.
1808  */
1809 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1810 {
1811         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1812                         AMDGPU_RESET_MAGIC_NUM);
1813 }
1814
1815 /**
1816  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1817  *
1818  * @adev: amdgpu_device pointer
1819  *
1820  * The list of all the hardware IPs that make up the asic is walked and the
1821  * set_clockgating_state callbacks are run.
1822  * Late initialization pass enabling clockgating for hardware IPs.
1823  * Fini or suspend, pass disabling clockgating for hardware IPs.
1824  * Returns 0 on success, negative error code on failure.
1825  */
1826
1827 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1828                                                 enum amd_clockgating_state state)
1829 {
1830         int i, j, r;
1831
1832         if (amdgpu_emu_mode == 1)
1833                 return 0;
1834
1835         for (j = 0; j < adev->num_ip_blocks; j++) {
1836                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1837                 if (!adev->ip_blocks[i].status.late_initialized)
1838                         continue;
1839                 /* skip CG for VCE/UVD, it's handled specially */
1840                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1841                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1842                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1843                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1844                         /* enable clockgating to save power */
1845                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1846                                                                                      state);
1847                         if (r) {
1848                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1849                                           adev->ip_blocks[i].version->funcs->name, r);
1850                                 return r;
1851                         }
1852                 }
1853         }
1854
1855         return 0;
1856 }
1857
1858 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1859 {
1860         int i, j, r;
1861
1862         if (amdgpu_emu_mode == 1)
1863                 return 0;
1864
1865         for (j = 0; j < adev->num_ip_blocks; j++) {
1866                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1867                 if (!adev->ip_blocks[i].status.late_initialized)
1868                         continue;
1869                 /* skip CG for VCE/UVD, it's handled specially */
1870                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1871                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1872                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1873                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1874                         /* enable powergating to save power */
1875                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1876                                                                                         state);
1877                         if (r) {
1878                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1879                                           adev->ip_blocks[i].version->funcs->name, r);
1880                                 return r;
1881                         }
1882                 }
1883         }
1884         return 0;
1885 }
1886
1887 static int amdgpu_device_enable_mgpu_fan_boost(void)
1888 {
1889         struct amdgpu_gpu_instance *gpu_ins;
1890         struct amdgpu_device *adev;
1891         int i, ret = 0;
1892
1893         mutex_lock(&mgpu_info.mutex);
1894
1895         /*
1896          * MGPU fan boost feature should be enabled
1897          * only when there are two or more dGPUs in
1898          * the system
1899          */
1900         if (mgpu_info.num_dgpu < 2)
1901                 goto out;
1902
1903         for (i = 0; i < mgpu_info.num_dgpu; i++) {
1904                 gpu_ins = &(mgpu_info.gpu_ins[i]);
1905                 adev = gpu_ins->adev;
1906                 if (!(adev->flags & AMD_IS_APU) &&
1907                     !gpu_ins->mgpu_fan_enabled &&
1908                     adev->powerplay.pp_funcs &&
1909                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1910                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1911                         if (ret)
1912                                 break;
1913
1914                         gpu_ins->mgpu_fan_enabled = 1;
1915                 }
1916         }
1917
1918 out:
1919         mutex_unlock(&mgpu_info.mutex);
1920
1921         return ret;
1922 }
1923
1924 /**
1925  * amdgpu_device_ip_late_init - run late init for hardware IPs
1926  *
1927  * @adev: amdgpu_device pointer
1928  *
1929  * Late initialization pass for hardware IPs.  The list of all the hardware
1930  * IPs that make up the asic is walked and the late_init callbacks are run.
1931  * late_init covers any special initialization that an IP requires
1932  * after all of the have been initialized or something that needs to happen
1933  * late in the init process.
1934  * Returns 0 on success, negative error code on failure.
1935  */
1936 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1937 {
1938         int i = 0, r;
1939
1940         for (i = 0; i < adev->num_ip_blocks; i++) {
1941                 if (!adev->ip_blocks[i].status.hw)
1942                         continue;
1943                 if (adev->ip_blocks[i].version->funcs->late_init) {
1944                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1945                         if (r) {
1946                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1947                                           adev->ip_blocks[i].version->funcs->name, r);
1948                                 return r;
1949                         }
1950                 }
1951                 adev->ip_blocks[i].status.late_initialized = true;
1952         }
1953
1954         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1955         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1956
1957         amdgpu_device_fill_reset_magic(adev);
1958
1959         r = amdgpu_device_enable_mgpu_fan_boost();
1960         if (r)
1961                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
1962
1963         /* set to low pstate by default */
1964         amdgpu_xgmi_set_pstate(adev, 0);
1965
1966         return 0;
1967 }
1968
1969 /**
1970  * amdgpu_device_ip_fini - run fini for hardware IPs
1971  *
1972  * @adev: amdgpu_device pointer
1973  *
1974  * Main teardown pass for hardware IPs.  The list of all the hardware
1975  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1976  * are run.  hw_fini tears down the hardware associated with each IP
1977  * and sw_fini tears down any software state associated with each IP.
1978  * Returns 0 on success, negative error code on failure.
1979  */
1980 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1981 {
1982         int i, r;
1983
1984         amdgpu_ras_pre_fini(adev);
1985
1986         if (adev->gmc.xgmi.num_physical_nodes > 1)
1987                 amdgpu_xgmi_remove_device(adev);
1988
1989         amdgpu_amdkfd_device_fini(adev);
1990
1991         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1992         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1993
1994         /* need to disable SMC first */
1995         for (i = 0; i < adev->num_ip_blocks; i++) {
1996                 if (!adev->ip_blocks[i].status.hw)
1997                         continue;
1998                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1999                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2000                         /* XXX handle errors */
2001                         if (r) {
2002                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2003                                           adev->ip_blocks[i].version->funcs->name, r);
2004                         }
2005                         adev->ip_blocks[i].status.hw = false;
2006                         break;
2007                 }
2008         }
2009
2010         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2011                 if (!adev->ip_blocks[i].status.hw)
2012                         continue;
2013
2014                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2015                 /* XXX handle errors */
2016                 if (r) {
2017                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2018                                   adev->ip_blocks[i].version->funcs->name, r);
2019                 }
2020
2021                 adev->ip_blocks[i].status.hw = false;
2022         }
2023
2024
2025         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2026                 if (!adev->ip_blocks[i].status.sw)
2027                         continue;
2028
2029                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2030                         amdgpu_ucode_free_bo(adev);
2031                         amdgpu_free_static_csa(&adev->virt.csa_obj);
2032                         amdgpu_device_wb_fini(adev);
2033                         amdgpu_device_vram_scratch_fini(adev);
2034                         amdgpu_ib_pool_fini(adev);
2035                 }
2036
2037                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2038                 /* XXX handle errors */
2039                 if (r) {
2040                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2041                                   adev->ip_blocks[i].version->funcs->name, r);
2042                 }
2043                 adev->ip_blocks[i].status.sw = false;
2044                 adev->ip_blocks[i].status.valid = false;
2045         }
2046
2047         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2048                 if (!adev->ip_blocks[i].status.late_initialized)
2049                         continue;
2050                 if (adev->ip_blocks[i].version->funcs->late_fini)
2051                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2052                 adev->ip_blocks[i].status.late_initialized = false;
2053         }
2054
2055         amdgpu_ras_fini(adev);
2056
2057         if (amdgpu_sriov_vf(adev))
2058                 if (amdgpu_virt_release_full_gpu(adev, false))
2059                         DRM_ERROR("failed to release exclusive mode on fini\n");
2060
2061         return 0;
2062 }
2063
2064 /**
2065  * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2066  *
2067  * @work: work_struct.
2068  */
2069 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2070 {
2071         struct amdgpu_device *adev =
2072                 container_of(work, struct amdgpu_device, delayed_init_work.work);
2073         int r;
2074
2075         r = amdgpu_ib_ring_tests(adev);
2076         if (r)
2077                 DRM_ERROR("ib ring test failed (%d).\n", r);
2078 }
2079
2080 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2081 {
2082         struct amdgpu_device *adev =
2083                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2084
2085         mutex_lock(&adev->gfx.gfx_off_mutex);
2086         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2087                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2088                         adev->gfx.gfx_off_state = true;
2089         }
2090         mutex_unlock(&adev->gfx.gfx_off_mutex);
2091 }
2092
2093 /**
2094  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2095  *
2096  * @adev: amdgpu_device pointer
2097  *
2098  * Main suspend function for hardware IPs.  The list of all the hardware
2099  * IPs that make up the asic is walked, clockgating is disabled and the
2100  * suspend callbacks are run.  suspend puts the hardware and software state
2101  * in each IP into a state suitable for suspend.
2102  * Returns 0 on success, negative error code on failure.
2103  */
2104 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2105 {
2106         int i, r;
2107
2108         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2109         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2110
2111         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2112                 if (!adev->ip_blocks[i].status.valid)
2113                         continue;
2114                 /* displays are handled separately */
2115                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2116                         /* XXX handle errors */
2117                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2118                         /* XXX handle errors */
2119                         if (r) {
2120                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2121                                           adev->ip_blocks[i].version->funcs->name, r);
2122                         }
2123                 }
2124         }
2125
2126         return 0;
2127 }
2128
2129 /**
2130  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2131  *
2132  * @adev: amdgpu_device pointer
2133  *
2134  * Main suspend function for hardware IPs.  The list of all the hardware
2135  * IPs that make up the asic is walked, clockgating is disabled and the
2136  * suspend callbacks are run.  suspend puts the hardware and software state
2137  * in each IP into a state suitable for suspend.
2138  * Returns 0 on success, negative error code on failure.
2139  */
2140 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2141 {
2142         int i, r;
2143
2144         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2145                 if (!adev->ip_blocks[i].status.valid)
2146                         continue;
2147                 /* displays are handled in phase1 */
2148                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2149                         continue;
2150                 /* XXX handle errors */
2151                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2152                 /* XXX handle errors */
2153                 if (r) {
2154                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2155                                   adev->ip_blocks[i].version->funcs->name, r);
2156                 }
2157         }
2158
2159         return 0;
2160 }
2161
2162 /**
2163  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2164  *
2165  * @adev: amdgpu_device pointer
2166  *
2167  * Main suspend function for hardware IPs.  The list of all the hardware
2168  * IPs that make up the asic is walked, clockgating is disabled and the
2169  * suspend callbacks are run.  suspend puts the hardware and software state
2170  * in each IP into a state suitable for suspend.
2171  * Returns 0 on success, negative error code on failure.
2172  */
2173 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2174 {
2175         int r;
2176
2177         if (amdgpu_sriov_vf(adev))
2178                 amdgpu_virt_request_full_gpu(adev, false);
2179
2180         r = amdgpu_device_ip_suspend_phase1(adev);
2181         if (r)
2182                 return r;
2183         r = amdgpu_device_ip_suspend_phase2(adev);
2184
2185         if (amdgpu_sriov_vf(adev))
2186                 amdgpu_virt_release_full_gpu(adev, false);
2187
2188         return r;
2189 }
2190
2191 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2192 {
2193         int i, r;
2194
2195         static enum amd_ip_block_type ip_order[] = {
2196                 AMD_IP_BLOCK_TYPE_GMC,
2197                 AMD_IP_BLOCK_TYPE_COMMON,
2198                 AMD_IP_BLOCK_TYPE_PSP,
2199                 AMD_IP_BLOCK_TYPE_IH,
2200         };
2201
2202         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2203                 int j;
2204                 struct amdgpu_ip_block *block;
2205
2206                 for (j = 0; j < adev->num_ip_blocks; j++) {
2207                         block = &adev->ip_blocks[j];
2208
2209                         if (block->version->type != ip_order[i] ||
2210                                 !block->status.valid)
2211                                 continue;
2212
2213                         r = block->version->funcs->hw_init(adev);
2214                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2215                         if (r)
2216                                 return r;
2217                 }
2218         }
2219
2220         return 0;
2221 }
2222
2223 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2224 {
2225         int i, r;
2226
2227         static enum amd_ip_block_type ip_order[] = {
2228                 AMD_IP_BLOCK_TYPE_SMC,
2229                 AMD_IP_BLOCK_TYPE_DCE,
2230                 AMD_IP_BLOCK_TYPE_GFX,
2231                 AMD_IP_BLOCK_TYPE_SDMA,
2232                 AMD_IP_BLOCK_TYPE_UVD,
2233                 AMD_IP_BLOCK_TYPE_VCE
2234         };
2235
2236         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2237                 int j;
2238                 struct amdgpu_ip_block *block;
2239
2240                 for (j = 0; j < adev->num_ip_blocks; j++) {
2241                         block = &adev->ip_blocks[j];
2242
2243                         if (block->version->type != ip_order[i] ||
2244                                 !block->status.valid)
2245                                 continue;
2246
2247                         r = block->version->funcs->hw_init(adev);
2248                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2249                         if (r)
2250                                 return r;
2251                 }
2252         }
2253
2254         return 0;
2255 }
2256
2257 /**
2258  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2259  *
2260  * @adev: amdgpu_device pointer
2261  *
2262  * First resume function for hardware IPs.  The list of all the hardware
2263  * IPs that make up the asic is walked and the resume callbacks are run for
2264  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2265  * after a suspend and updates the software state as necessary.  This
2266  * function is also used for restoring the GPU after a GPU reset.
2267  * Returns 0 on success, negative error code on failure.
2268  */
2269 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2270 {
2271         int i, r;
2272
2273         for (i = 0; i < adev->num_ip_blocks; i++) {
2274                 if (!adev->ip_blocks[i].status.valid)
2275                         continue;
2276                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2277                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2278                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2279                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2280                         if (r) {
2281                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2282                                           adev->ip_blocks[i].version->funcs->name, r);
2283                                 return r;
2284                         }
2285                 }
2286         }
2287
2288         return 0;
2289 }
2290
2291 /**
2292  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2293  *
2294  * @adev: amdgpu_device pointer
2295  *
2296  * First resume function for hardware IPs.  The list of all the hardware
2297  * IPs that make up the asic is walked and the resume callbacks are run for
2298  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2299  * functional state after a suspend and updates the software state as
2300  * necessary.  This function is also used for restoring the GPU after a GPU
2301  * reset.
2302  * Returns 0 on success, negative error code on failure.
2303  */
2304 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2305 {
2306         int i, r;
2307
2308         for (i = 0; i < adev->num_ip_blocks; i++) {
2309                 if (!adev->ip_blocks[i].status.valid)
2310                         continue;
2311                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2312                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2313                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2314                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2315                         continue;
2316                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2317                 if (r) {
2318                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2319                                   adev->ip_blocks[i].version->funcs->name, r);
2320                         return r;
2321                 }
2322         }
2323
2324         return 0;
2325 }
2326
2327 /**
2328  * amdgpu_device_ip_resume - run resume for hardware IPs
2329  *
2330  * @adev: amdgpu_device pointer
2331  *
2332  * Main resume function for hardware IPs.  The hardware IPs
2333  * are split into two resume functions because they are
2334  * are also used in in recovering from a GPU reset and some additional
2335  * steps need to be take between them.  In this case (S3/S4) they are
2336  * run sequentially.
2337  * Returns 0 on success, negative error code on failure.
2338  */
2339 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2340 {
2341         int r;
2342
2343         r = amdgpu_device_ip_resume_phase1(adev);
2344         if (r)
2345                 return r;
2346
2347         r = amdgpu_device_fw_loading(adev);
2348         if (r)
2349                 return r;
2350
2351         r = amdgpu_device_ip_resume_phase2(adev);
2352
2353         return r;
2354 }
2355
2356 /**
2357  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2358  *
2359  * @adev: amdgpu_device pointer
2360  *
2361  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2362  */
2363 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2364 {
2365         if (amdgpu_sriov_vf(adev)) {
2366                 if (adev->is_atom_fw) {
2367                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2368                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2369                 } else {
2370                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2371                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2372                 }
2373
2374                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2375                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2376         }
2377 }
2378
2379 /**
2380  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2381  *
2382  * @asic_type: AMD asic type
2383  *
2384  * Check if there is DC (new modesetting infrastructre) support for an asic.
2385  * returns true if DC has support, false if not.
2386  */
2387 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2388 {
2389         switch (asic_type) {
2390 #if defined(CONFIG_DRM_AMD_DC)
2391         case CHIP_BONAIRE:
2392         case CHIP_KAVERI:
2393         case CHIP_KABINI:
2394         case CHIP_MULLINS:
2395                 /*
2396                  * We have systems in the wild with these ASICs that require
2397                  * LVDS and VGA support which is not supported with DC.
2398                  *
2399                  * Fallback to the non-DC driver here by default so as not to
2400                  * cause regressions.
2401                  */
2402                 return amdgpu_dc > 0;
2403         case CHIP_HAWAII:
2404         case CHIP_CARRIZO:
2405         case CHIP_STONEY:
2406         case CHIP_POLARIS10:
2407         case CHIP_POLARIS11:
2408         case CHIP_POLARIS12:
2409         case CHIP_VEGAM:
2410         case CHIP_TONGA:
2411         case CHIP_FIJI:
2412         case CHIP_VEGA10:
2413         case CHIP_VEGA12:
2414         case CHIP_VEGA20:
2415 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2416         case CHIP_RAVEN:
2417 #endif
2418                 return amdgpu_dc != 0;
2419 #endif
2420         default:
2421                 return false;
2422         }
2423 }
2424
2425 /**
2426  * amdgpu_device_has_dc_support - check if dc is supported
2427  *
2428  * @adev: amdgpu_device_pointer
2429  *
2430  * Returns true for supported, false for not supported
2431  */
2432 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2433 {
2434         if (amdgpu_sriov_vf(adev))
2435                 return false;
2436
2437         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2438 }
2439
2440
2441 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2442 {
2443         struct amdgpu_device *adev =
2444                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2445
2446         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2447         if (adev->asic_reset_res)
2448                 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2449                          adev->asic_reset_res, adev->ddev->unique);
2450 }
2451
2452
2453 /**
2454  * amdgpu_device_init - initialize the driver
2455  *
2456  * @adev: amdgpu_device pointer
2457  * @ddev: drm dev pointer
2458  * @pdev: pci dev pointer
2459  * @flags: driver flags
2460  *
2461  * Initializes the driver info and hw (all asics).
2462  * Returns 0 for success or an error on failure.
2463  * Called at driver startup.
2464  */
2465 int amdgpu_device_init(struct amdgpu_device *adev,
2466                        struct drm_device *ddev,
2467                        struct pci_dev *pdev,
2468                        uint32_t flags)
2469 {
2470         int r, i;
2471         bool runtime = false;
2472         u32 max_MBps;
2473
2474         adev->shutdown = false;
2475         adev->dev = &pdev->dev;
2476         adev->ddev = ddev;
2477         adev->pdev = pdev;
2478         adev->flags = flags;
2479         adev->asic_type = flags & AMD_ASIC_MASK;
2480         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2481         if (amdgpu_emu_mode == 1)
2482                 adev->usec_timeout *= 2;
2483         adev->gmc.gart_size = 512 * 1024 * 1024;
2484         adev->accel_working = false;
2485         adev->num_rings = 0;
2486         adev->mman.buffer_funcs = NULL;
2487         adev->mman.buffer_funcs_ring = NULL;
2488         adev->vm_manager.vm_pte_funcs = NULL;
2489         adev->vm_manager.vm_pte_num_rqs = 0;
2490         adev->gmc.gmc_funcs = NULL;
2491         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2492         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2493
2494         adev->smc_rreg = &amdgpu_invalid_rreg;
2495         adev->smc_wreg = &amdgpu_invalid_wreg;
2496         adev->pcie_rreg = &amdgpu_invalid_rreg;
2497         adev->pcie_wreg = &amdgpu_invalid_wreg;
2498         adev->pciep_rreg = &amdgpu_invalid_rreg;
2499         adev->pciep_wreg = &amdgpu_invalid_wreg;
2500         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2501         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2502         adev->didt_rreg = &amdgpu_invalid_rreg;
2503         adev->didt_wreg = &amdgpu_invalid_wreg;
2504         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2505         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2506         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2507         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2508
2509         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2510                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2511                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2512
2513         /* mutex initialization are all done here so we
2514          * can recall function without having locking issues */
2515         atomic_set(&adev->irq.ih.lock, 0);
2516         mutex_init(&adev->firmware.mutex);
2517         mutex_init(&adev->pm.mutex);
2518         mutex_init(&adev->gfx.gpu_clock_mutex);
2519         mutex_init(&adev->srbm_mutex);
2520         mutex_init(&adev->gfx.pipe_reserve_mutex);
2521         mutex_init(&adev->gfx.gfx_off_mutex);
2522         mutex_init(&adev->grbm_idx_mutex);
2523         mutex_init(&adev->mn_lock);
2524         mutex_init(&adev->virt.vf_errors.lock);
2525         hash_init(adev->mn_hash);
2526         mutex_init(&adev->lock_reset);
2527         mutex_init(&adev->virt.dpm_mutex);
2528
2529         r = amdgpu_device_check_arguments(adev);
2530         if (r)
2531                 return r;
2532
2533         spin_lock_init(&adev->mmio_idx_lock);
2534         spin_lock_init(&adev->smc_idx_lock);
2535         spin_lock_init(&adev->pcie_idx_lock);
2536         spin_lock_init(&adev->uvd_ctx_idx_lock);
2537         spin_lock_init(&adev->didt_idx_lock);
2538         spin_lock_init(&adev->gc_cac_idx_lock);
2539         spin_lock_init(&adev->se_cac_idx_lock);
2540         spin_lock_init(&adev->audio_endpt_idx_lock);
2541         spin_lock_init(&adev->mm_stats.lock);
2542
2543         INIT_LIST_HEAD(&adev->shadow_list);
2544         mutex_init(&adev->shadow_list_lock);
2545
2546         INIT_LIST_HEAD(&adev->ring_lru_list);
2547         spin_lock_init(&adev->ring_lru_list_lock);
2548
2549         INIT_DELAYED_WORK(&adev->delayed_init_work,
2550                           amdgpu_device_delayed_init_work_handler);
2551         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2552                           amdgpu_device_delay_enable_gfx_off);
2553
2554         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2555
2556         adev->gfx.gfx_off_req_count = 1;
2557         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2558
2559         /* Registers mapping */
2560         /* TODO: block userspace mapping of io register */
2561         if (adev->asic_type >= CHIP_BONAIRE) {
2562                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2563                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2564         } else {
2565                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2566                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2567         }
2568
2569         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2570         if (adev->rmmio == NULL) {
2571                 return -ENOMEM;
2572         }
2573         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2574         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2575
2576         /* io port mapping */
2577         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2578                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2579                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2580                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2581                         break;
2582                 }
2583         }
2584         if (adev->rio_mem == NULL)
2585                 DRM_INFO("PCI I/O BAR is not found.\n");
2586
2587         amdgpu_device_get_pcie_info(adev);
2588
2589         if (amdgpu_mcbp)
2590                 DRM_INFO("MCBP is enabled\n");
2591
2592         if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
2593                 adev->enable_mes = true;
2594
2595         if (amdgpu_discovery) {
2596                 r = amdgpu_discovery_init(adev);
2597                 if (r) {
2598                         dev_err(adev->dev, "amdgpu_discovery_init failed\n");
2599                         return r;
2600                 }
2601         }
2602
2603         /* early init functions */
2604         r = amdgpu_device_ip_early_init(adev);
2605         if (r)
2606                 return r;
2607
2608         /* doorbell bar mapping and doorbell index init*/
2609         amdgpu_device_doorbell_init(adev);
2610
2611         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2612         /* this will fail for cards that aren't VGA class devices, just
2613          * ignore it */
2614         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2615
2616         if (amdgpu_device_is_px(ddev))
2617                 runtime = true;
2618         if (!pci_is_thunderbolt_attached(adev->pdev))
2619                 vga_switcheroo_register_client(adev->pdev,
2620                                                &amdgpu_switcheroo_ops, runtime);
2621         if (runtime)
2622                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2623
2624         if (amdgpu_emu_mode == 1) {
2625                 /* post the asic on emulation mode */
2626                 emu_soc_asic_init(adev);
2627                 goto fence_driver_init;
2628         }
2629
2630         /* detect if we are with an SRIOV vbios */
2631         amdgpu_device_detect_sriov_bios(adev);
2632
2633         /* check if we need to reset the asic
2634          *  E.g., driver was not cleanly unloaded previously, etc.
2635          */
2636         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2637                 r = amdgpu_asic_reset(adev);
2638                 if (r) {
2639                         dev_err(adev->dev, "asic reset on init failed\n");
2640                         goto failed;
2641                 }
2642         }
2643
2644         /* Post card if necessary */
2645         if (amdgpu_device_need_post(adev)) {
2646                 if (!adev->bios) {
2647                         dev_err(adev->dev, "no vBIOS found\n");
2648                         r = -EINVAL;
2649                         goto failed;
2650                 }
2651                 DRM_INFO("GPU posting now...\n");
2652                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2653                 if (r) {
2654                         dev_err(adev->dev, "gpu post error!\n");
2655                         goto failed;
2656                 }
2657         }
2658
2659         if (adev->is_atom_fw) {
2660                 /* Initialize clocks */
2661                 r = amdgpu_atomfirmware_get_clock_info(adev);
2662                 if (r) {
2663                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2664                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2665                         goto failed;
2666                 }
2667         } else {
2668                 /* Initialize clocks */
2669                 r = amdgpu_atombios_get_clock_info(adev);
2670                 if (r) {
2671                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2672                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2673                         goto failed;
2674                 }
2675                 /* init i2c buses */
2676                 if (!amdgpu_device_has_dc_support(adev))
2677                         amdgpu_atombios_i2c_init(adev);
2678         }
2679
2680 fence_driver_init:
2681         /* Fence driver */
2682         r = amdgpu_fence_driver_init(adev);
2683         if (r) {
2684                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2685                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2686                 goto failed;
2687         }
2688
2689         /* init the mode config */
2690         drm_mode_config_init(adev->ddev);
2691
2692         r = amdgpu_device_ip_init(adev);
2693         if (r) {
2694                 /* failed in exclusive mode due to timeout */
2695                 if (amdgpu_sriov_vf(adev) &&
2696                     !amdgpu_sriov_runtime(adev) &&
2697                     amdgpu_virt_mmio_blocked(adev) &&
2698                     !amdgpu_virt_wait_reset(adev)) {
2699                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2700                         /* Don't send request since VF is inactive. */
2701                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2702                         adev->virt.ops = NULL;
2703                         r = -EAGAIN;
2704                         goto failed;
2705                 }
2706                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2707                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2708                 if (amdgpu_virt_request_full_gpu(adev, false))
2709                         amdgpu_virt_release_full_gpu(adev, false);
2710                 goto failed;
2711         }
2712
2713         adev->accel_working = true;
2714
2715         amdgpu_vm_check_compute_bug(adev);
2716
2717         /* Initialize the buffer migration limit. */
2718         if (amdgpu_moverate >= 0)
2719                 max_MBps = amdgpu_moverate;
2720         else
2721                 max_MBps = 8; /* Allow 8 MB/s. */
2722         /* Get a log2 for easy divisions. */
2723         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2724
2725         amdgpu_fbdev_init(adev);
2726
2727         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2728                 amdgpu_pm_virt_sysfs_init(adev);
2729
2730         r = amdgpu_pm_sysfs_init(adev);
2731         if (r)
2732                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2733
2734         r = amdgpu_ucode_sysfs_init(adev);
2735         if (r)
2736                 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2737
2738         r = amdgpu_debugfs_gem_init(adev);
2739         if (r)
2740                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2741
2742         r = amdgpu_debugfs_regs_init(adev);
2743         if (r)
2744                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2745
2746         r = amdgpu_debugfs_firmware_init(adev);
2747         if (r)
2748                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2749
2750         r = amdgpu_debugfs_init(adev);
2751         if (r)
2752                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2753
2754         if ((amdgpu_testing & 1)) {
2755                 if (adev->accel_working)
2756                         amdgpu_test_moves(adev);
2757                 else
2758                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2759         }
2760         if (amdgpu_benchmarking) {
2761                 if (adev->accel_working)
2762                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2763                 else
2764                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2765         }
2766
2767         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2768          * explicit gating rather than handling it automatically.
2769          */
2770         r = amdgpu_device_ip_late_init(adev);
2771         if (r) {
2772                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2773                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2774                 goto failed;
2775         }
2776
2777         /* must succeed. */
2778         amdgpu_ras_resume(adev);
2779
2780         queue_delayed_work(system_wq, &adev->delayed_init_work,
2781                            msecs_to_jiffies(AMDGPU_RESUME_MS));
2782
2783         r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2784         if (r) {
2785                 dev_err(adev->dev, "Could not create pcie_replay_count");
2786                 return r;
2787         }
2788
2789         r = amdgpu_pmu_init(adev);
2790         if (r)
2791                 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
2792
2793         return 0;
2794
2795 failed:
2796         amdgpu_vf_error_trans_all(adev);
2797         if (runtime)
2798                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2799
2800         return r;
2801 }
2802
2803 /**
2804  * amdgpu_device_fini - tear down the driver
2805  *
2806  * @adev: amdgpu_device pointer
2807  *
2808  * Tear down the driver info (all asics).
2809  * Called at driver shutdown.
2810  */
2811 void amdgpu_device_fini(struct amdgpu_device *adev)
2812 {
2813         int r;
2814
2815         DRM_INFO("amdgpu: finishing device.\n");
2816         adev->shutdown = true;
2817         /* disable all interrupts */
2818         amdgpu_irq_disable_all(adev);
2819         if (adev->mode_info.mode_config_initialized){
2820                 if (!amdgpu_device_has_dc_support(adev))
2821                         drm_helper_force_disable_all(adev->ddev);
2822                 else
2823                         drm_atomic_helper_shutdown(adev->ddev);
2824         }
2825         amdgpu_fence_driver_fini(adev);
2826         amdgpu_pm_sysfs_fini(adev);
2827         amdgpu_fbdev_fini(adev);
2828         r = amdgpu_device_ip_fini(adev);
2829         if (adev->firmware.gpu_info_fw) {
2830                 release_firmware(adev->firmware.gpu_info_fw);
2831                 adev->firmware.gpu_info_fw = NULL;
2832         }
2833         adev->accel_working = false;
2834         cancel_delayed_work_sync(&adev->delayed_init_work);
2835         /* free i2c buses */
2836         if (!amdgpu_device_has_dc_support(adev))
2837                 amdgpu_i2c_fini(adev);
2838
2839         if (amdgpu_emu_mode != 1)
2840                 amdgpu_atombios_fini(adev);
2841
2842         kfree(adev->bios);
2843         adev->bios = NULL;
2844         if (!pci_is_thunderbolt_attached(adev->pdev))
2845                 vga_switcheroo_unregister_client(adev->pdev);
2846         if (adev->flags & AMD_IS_PX)
2847                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2848         vga_client_register(adev->pdev, NULL, NULL, NULL);
2849         if (adev->rio_mem)
2850                 pci_iounmap(adev->pdev, adev->rio_mem);
2851         adev->rio_mem = NULL;
2852         iounmap(adev->rmmio);
2853         adev->rmmio = NULL;
2854         amdgpu_device_doorbell_fini(adev);
2855         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2856                 amdgpu_pm_virt_sysfs_fini(adev);
2857
2858         amdgpu_debugfs_regs_cleanup(adev);
2859         device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
2860         amdgpu_ucode_sysfs_fini(adev);
2861         amdgpu_pmu_fini(adev);
2862         amdgpu_debugfs_preempt_cleanup(adev);
2863         if (amdgpu_discovery)
2864                 amdgpu_discovery_fini(adev);
2865 }
2866
2867
2868 /*
2869  * Suspend & resume.
2870  */
2871 /**
2872  * amdgpu_device_suspend - initiate device suspend
2873  *
2874  * @dev: drm dev pointer
2875  * @suspend: suspend state
2876  * @fbcon : notify the fbdev of suspend
2877  *
2878  * Puts the hw in the suspend state (all asics).
2879  * Returns 0 for success or an error on failure.
2880  * Called at driver suspend.
2881  */
2882 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2883 {
2884         struct amdgpu_device *adev;
2885         struct drm_crtc *crtc;
2886         struct drm_connector *connector;
2887         int r;
2888
2889         if (dev == NULL || dev->dev_private == NULL) {
2890                 return -ENODEV;
2891         }
2892
2893         adev = dev->dev_private;
2894
2895         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2896                 return 0;
2897
2898         adev->in_suspend = true;
2899         drm_kms_helper_poll_disable(dev);
2900
2901         if (fbcon)
2902                 amdgpu_fbdev_set_suspend(adev, 1);
2903
2904         cancel_delayed_work_sync(&adev->delayed_init_work);
2905
2906         if (!amdgpu_device_has_dc_support(adev)) {
2907                 /* turn off display hw */
2908                 drm_modeset_lock_all(dev);
2909                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2910                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2911                 }
2912                 drm_modeset_unlock_all(dev);
2913                         /* unpin the front buffers and cursors */
2914                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2915                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2916                         struct drm_framebuffer *fb = crtc->primary->fb;
2917                         struct amdgpu_bo *robj;
2918
2919                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2920                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2921                                 r = amdgpu_bo_reserve(aobj, true);
2922                                 if (r == 0) {
2923                                         amdgpu_bo_unpin(aobj);
2924                                         amdgpu_bo_unreserve(aobj);
2925                                 }
2926                         }
2927
2928                         if (fb == NULL || fb->obj[0] == NULL) {
2929                                 continue;
2930                         }
2931                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2932                         /* don't unpin kernel fb objects */
2933                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2934                                 r = amdgpu_bo_reserve(robj, true);
2935                                 if (r == 0) {
2936                                         amdgpu_bo_unpin(robj);
2937                                         amdgpu_bo_unreserve(robj);
2938                                 }
2939                         }
2940                 }
2941         }
2942
2943         amdgpu_amdkfd_suspend(adev);
2944
2945         amdgpu_ras_suspend(adev);
2946
2947         r = amdgpu_device_ip_suspend_phase1(adev);
2948
2949         /* evict vram memory */
2950         amdgpu_bo_evict_vram(adev);
2951
2952         amdgpu_fence_driver_suspend(adev);
2953
2954         r = amdgpu_device_ip_suspend_phase2(adev);
2955
2956         /* evict remaining vram memory
2957          * This second call to evict vram is to evict the gart page table
2958          * using the CPU.
2959          */
2960         amdgpu_bo_evict_vram(adev);
2961
2962         pci_save_state(dev->pdev);
2963         if (suspend) {
2964                 /* Shut down the device */
2965                 pci_disable_device(dev->pdev);
2966                 pci_set_power_state(dev->pdev, PCI_D3hot);
2967         } else {
2968                 r = amdgpu_asic_reset(adev);
2969                 if (r)
2970                         DRM_ERROR("amdgpu asic reset failed\n");
2971         }
2972
2973         return 0;
2974 }
2975
2976 /**
2977  * amdgpu_device_resume - initiate device resume
2978  *
2979  * @dev: drm dev pointer
2980  * @resume: resume state
2981  * @fbcon : notify the fbdev of resume
2982  *
2983  * Bring the hw back to operating state (all asics).
2984  * Returns 0 for success or an error on failure.
2985  * Called at driver resume.
2986  */
2987 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2988 {
2989         struct drm_connector *connector;
2990         struct amdgpu_device *adev = dev->dev_private;
2991         struct drm_crtc *crtc;
2992         int r = 0;
2993
2994         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2995                 return 0;
2996
2997         if (resume) {
2998                 pci_set_power_state(dev->pdev, PCI_D0);
2999                 pci_restore_state(dev->pdev);
3000                 r = pci_enable_device(dev->pdev);
3001                 if (r)
3002                         return r;
3003         }
3004
3005         /* post card */
3006         if (amdgpu_device_need_post(adev)) {
3007                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3008                 if (r)
3009                         DRM_ERROR("amdgpu asic init failed\n");
3010         }
3011
3012         r = amdgpu_device_ip_resume(adev);
3013         if (r) {
3014                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3015                 return r;
3016         }
3017         amdgpu_fence_driver_resume(adev);
3018
3019
3020         r = amdgpu_device_ip_late_init(adev);
3021         if (r)
3022                 return r;
3023
3024         queue_delayed_work(system_wq, &adev->delayed_init_work,
3025                            msecs_to_jiffies(AMDGPU_RESUME_MS));
3026
3027         if (!amdgpu_device_has_dc_support(adev)) {
3028                 /* pin cursors */
3029                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3030                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3031
3032                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3033                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3034                                 r = amdgpu_bo_reserve(aobj, true);
3035                                 if (r == 0) {
3036                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3037                                         if (r != 0)
3038                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3039                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3040                                         amdgpu_bo_unreserve(aobj);
3041                                 }
3042                         }
3043                 }
3044         }
3045         r = amdgpu_amdkfd_resume(adev);
3046         if (r)
3047                 return r;
3048
3049         /* Make sure IB tests flushed */
3050         flush_delayed_work(&adev->delayed_init_work);
3051
3052         /* blat the mode back in */
3053         if (fbcon) {
3054                 if (!amdgpu_device_has_dc_support(adev)) {
3055                         /* pre DCE11 */
3056                         drm_helper_resume_force_mode(dev);
3057
3058                         /* turn on display hw */
3059                         drm_modeset_lock_all(dev);
3060                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3061                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3062                         }
3063                         drm_modeset_unlock_all(dev);
3064                 }
3065                 amdgpu_fbdev_set_suspend(adev, 0);
3066         }
3067
3068         drm_kms_helper_poll_enable(dev);
3069
3070         amdgpu_ras_resume(adev);
3071
3072         /*
3073          * Most of the connector probing functions try to acquire runtime pm
3074          * refs to ensure that the GPU is powered on when connector polling is
3075          * performed. Since we're calling this from a runtime PM callback,
3076          * trying to acquire rpm refs will cause us to deadlock.
3077          *
3078          * Since we're guaranteed to be holding the rpm lock, it's safe to
3079          * temporarily disable the rpm helpers so this doesn't deadlock us.
3080          */
3081 #ifdef CONFIG_PM
3082         dev->dev->power.disable_depth++;
3083 #endif
3084         if (!amdgpu_device_has_dc_support(adev))
3085                 drm_helper_hpd_irq_event(dev);
3086         else
3087                 drm_kms_helper_hotplug_event(dev);
3088 #ifdef CONFIG_PM
3089         dev->dev->power.disable_depth--;
3090 #endif
3091         adev->in_suspend = false;
3092
3093         return 0;
3094 }
3095
3096 /**
3097  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3098  *
3099  * @adev: amdgpu_device pointer
3100  *
3101  * The list of all the hardware IPs that make up the asic is walked and
3102  * the check_soft_reset callbacks are run.  check_soft_reset determines
3103  * if the asic is still hung or not.
3104  * Returns true if any of the IPs are still in a hung state, false if not.
3105  */
3106 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3107 {
3108         int i;
3109         bool asic_hang = false;
3110
3111         if (amdgpu_sriov_vf(adev))
3112                 return true;
3113
3114         if (amdgpu_asic_need_full_reset(adev))
3115                 return true;
3116
3117         for (i = 0; i < adev->num_ip_blocks; i++) {
3118                 if (!adev->ip_blocks[i].status.valid)
3119                         continue;
3120                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3121                         adev->ip_blocks[i].status.hang =
3122                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3123                 if (adev->ip_blocks[i].status.hang) {
3124                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3125                         asic_hang = true;
3126                 }
3127         }
3128         return asic_hang;
3129 }
3130
3131 /**
3132  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3133  *
3134  * @adev: amdgpu_device pointer
3135  *
3136  * The list of all the hardware IPs that make up the asic is walked and the
3137  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3138  * handles any IP specific hardware or software state changes that are
3139  * necessary for a soft reset to succeed.
3140  * Returns 0 on success, negative error code on failure.
3141  */
3142 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3143 {
3144         int i, r = 0;
3145
3146         for (i = 0; i < adev->num_ip_blocks; i++) {
3147                 if (!adev->ip_blocks[i].status.valid)
3148                         continue;
3149                 if (adev->ip_blocks[i].status.hang &&
3150                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3151                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3152                         if (r)
3153                                 return r;
3154                 }
3155         }
3156
3157         return 0;
3158 }
3159
3160 /**
3161  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3162  *
3163  * @adev: amdgpu_device pointer
3164  *
3165  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3166  * reset is necessary to recover.
3167  * Returns true if a full asic reset is required, false if not.
3168  */
3169 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3170 {
3171         int i;
3172
3173         if (amdgpu_asic_need_full_reset(adev))
3174                 return true;
3175
3176         for (i = 0; i < adev->num_ip_blocks; i++) {
3177                 if (!adev->ip_blocks[i].status.valid)
3178                         continue;
3179                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3180                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3181                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3182                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3183                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3184                         if (adev->ip_blocks[i].status.hang) {
3185                                 DRM_INFO("Some block need full reset!\n");
3186                                 return true;
3187                         }
3188                 }
3189         }
3190         return false;
3191 }
3192
3193 /**
3194  * amdgpu_device_ip_soft_reset - do a soft reset
3195  *
3196  * @adev: amdgpu_device pointer
3197  *
3198  * The list of all the hardware IPs that make up the asic is walked and the
3199  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3200  * IP specific hardware or software state changes that are necessary to soft
3201  * reset the IP.
3202  * Returns 0 on success, negative error code on failure.
3203  */
3204 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3205 {
3206         int i, r = 0;
3207
3208         for (i = 0; i < adev->num_ip_blocks; i++) {
3209                 if (!adev->ip_blocks[i].status.valid)
3210                         continue;
3211                 if (adev->ip_blocks[i].status.hang &&
3212                     adev->ip_blocks[i].version->funcs->soft_reset) {
3213                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3214                         if (r)
3215                                 return r;
3216                 }
3217         }
3218
3219         return 0;
3220 }
3221
3222 /**
3223  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3224  *
3225  * @adev: amdgpu_device pointer
3226  *
3227  * The list of all the hardware IPs that make up the asic is walked and the
3228  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3229  * handles any IP specific hardware or software state changes that are
3230  * necessary after the IP has been soft reset.
3231  * Returns 0 on success, negative error code on failure.
3232  */
3233 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3234 {
3235         int i, r = 0;
3236
3237         for (i = 0; i < adev->num_ip_blocks; i++) {
3238                 if (!adev->ip_blocks[i].status.valid)
3239                         continue;
3240                 if (adev->ip_blocks[i].status.hang &&
3241                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3242                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3243                 if (r)
3244                         return r;
3245         }
3246
3247         return 0;
3248 }
3249
3250 /**
3251  * amdgpu_device_recover_vram - Recover some VRAM contents
3252  *
3253  * @adev: amdgpu_device pointer
3254  *
3255  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3256  * restore things like GPUVM page tables after a GPU reset where
3257  * the contents of VRAM might be lost.
3258  *
3259  * Returns:
3260  * 0 on success, negative error code on failure.
3261  */
3262 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3263 {
3264         struct dma_fence *fence = NULL, *next = NULL;
3265         struct amdgpu_bo *shadow;
3266         long r = 1, tmo;
3267
3268         if (amdgpu_sriov_runtime(adev))
3269                 tmo = msecs_to_jiffies(8000);
3270         else
3271                 tmo = msecs_to_jiffies(100);
3272
3273         DRM_INFO("recover vram bo from shadow start\n");
3274         mutex_lock(&adev->shadow_list_lock);
3275         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3276
3277                 /* No need to recover an evicted BO */
3278                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3279                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3280                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3281                         continue;
3282
3283                 r = amdgpu_bo_restore_shadow(shadow, &next);
3284                 if (r)
3285                         break;
3286
3287                 if (fence) {
3288                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3289                         dma_fence_put(fence);
3290                         fence = next;
3291                         if (tmo == 0) {
3292                                 r = -ETIMEDOUT;
3293                                 break;
3294                         } else if (tmo < 0) {
3295                                 r = tmo;
3296                                 break;
3297                         }
3298                 } else {
3299                         fence = next;
3300                 }
3301         }
3302         mutex_unlock(&adev->shadow_list_lock);
3303
3304         if (fence)
3305                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3306         dma_fence_put(fence);
3307
3308         if (r < 0 || tmo <= 0) {
3309                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3310                 return -EIO;
3311         }
3312
3313         DRM_INFO("recover vram bo from shadow done\n");
3314         return 0;
3315 }
3316
3317
3318 /**
3319  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3320  *
3321  * @adev: amdgpu device pointer
3322  * @from_hypervisor: request from hypervisor
3323  *
3324  * do VF FLR and reinitialize Asic
3325  * return 0 means succeeded otherwise failed
3326  */
3327 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3328                                      bool from_hypervisor)
3329 {
3330         int r;
3331
3332         if (from_hypervisor)
3333                 r = amdgpu_virt_request_full_gpu(adev, true);
3334         else
3335                 r = amdgpu_virt_reset_gpu(adev);
3336         if (r)
3337                 return r;
3338
3339         amdgpu_amdkfd_pre_reset(adev);
3340
3341         /* Resume IP prior to SMC */
3342         r = amdgpu_device_ip_reinit_early_sriov(adev);
3343         if (r)
3344                 goto error;
3345
3346         /* we need recover gart prior to run SMC/CP/SDMA resume */
3347         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3348
3349         r = amdgpu_device_fw_loading(adev);
3350         if (r)
3351                 return r;
3352
3353         /* now we are okay to resume SMC/CP/SDMA */
3354         r = amdgpu_device_ip_reinit_late_sriov(adev);
3355         if (r)
3356                 goto error;
3357
3358         amdgpu_irq_gpu_reset_resume_helper(adev);
3359         r = amdgpu_ib_ring_tests(adev);
3360         amdgpu_amdkfd_post_reset(adev);
3361
3362 error:
3363         amdgpu_virt_init_data_exchange(adev);
3364         amdgpu_virt_release_full_gpu(adev, true);
3365         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3366                 atomic_inc(&adev->vram_lost_counter);
3367                 r = amdgpu_device_recover_vram(adev);
3368         }
3369
3370         return r;
3371 }
3372
3373 /**
3374  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3375  *
3376  * @adev: amdgpu device pointer
3377  *
3378  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3379  * a hung GPU.
3380  */
3381 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3382 {
3383         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3384                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3385                 return false;
3386         }
3387
3388         if (amdgpu_gpu_recovery == 0)
3389                 goto disabled;
3390
3391         if (amdgpu_sriov_vf(adev))
3392                 return true;
3393
3394         if (amdgpu_gpu_recovery == -1) {
3395                 switch (adev->asic_type) {
3396                 case CHIP_BONAIRE:
3397                 case CHIP_HAWAII:
3398                 case CHIP_TOPAZ:
3399                 case CHIP_TONGA:
3400                 case CHIP_FIJI:
3401                 case CHIP_POLARIS10:
3402                 case CHIP_POLARIS11:
3403                 case CHIP_POLARIS12:
3404                 case CHIP_VEGAM:
3405                 case CHIP_VEGA20:
3406                 case CHIP_VEGA10:
3407                 case CHIP_VEGA12:
3408                         break;
3409                 default:
3410                         goto disabled;
3411                 }
3412         }
3413
3414         return true;
3415
3416 disabled:
3417                 DRM_INFO("GPU recovery disabled.\n");
3418                 return false;
3419 }
3420
3421
3422 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3423                                         struct amdgpu_job *job,
3424                                         bool *need_full_reset_arg)
3425 {
3426         int i, r = 0;
3427         bool need_full_reset  = *need_full_reset_arg;
3428
3429         /* block all schedulers and reset given job's ring */
3430         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3431                 struct amdgpu_ring *ring = adev->rings[i];
3432
3433                 if (!ring || !ring->sched.thread)
3434                         continue;
3435
3436                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3437                 amdgpu_fence_driver_force_completion(ring);
3438         }
3439
3440         if(job)
3441                 drm_sched_increase_karma(&job->base);
3442
3443         /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3444         if (!amdgpu_sriov_vf(adev)) {
3445
3446                 if (!need_full_reset)
3447                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3448
3449                 if (!need_full_reset) {
3450                         amdgpu_device_ip_pre_soft_reset(adev);
3451                         r = amdgpu_device_ip_soft_reset(adev);
3452                         amdgpu_device_ip_post_soft_reset(adev);
3453                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3454                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3455                                 need_full_reset = true;
3456                         }
3457                 }
3458
3459                 if (need_full_reset)
3460                         r = amdgpu_device_ip_suspend(adev);
3461
3462                 *need_full_reset_arg = need_full_reset;
3463         }
3464
3465         return r;
3466 }
3467
3468 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3469                                struct list_head *device_list_handle,
3470                                bool *need_full_reset_arg)
3471 {
3472         struct amdgpu_device *tmp_adev = NULL;
3473         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3474         int r = 0;
3475
3476         /*
3477          * ASIC reset has to be done on all HGMI hive nodes ASAP
3478          * to allow proper links negotiation in FW (within 1 sec)
3479          */
3480         if (need_full_reset) {
3481                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3482                         /* For XGMI run all resets in parallel to speed up the process */
3483                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3484                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3485                                         r = -EALREADY;
3486                         } else
3487                                 r = amdgpu_asic_reset(tmp_adev);
3488
3489                         if (r) {
3490                                 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3491                                          r, tmp_adev->ddev->unique);
3492                                 break;
3493                         }
3494                 }
3495
3496                 /* For XGMI wait for all PSP resets to complete before proceed */
3497                 if (!r) {
3498                         list_for_each_entry(tmp_adev, device_list_handle,
3499                                             gmc.xgmi.head) {
3500                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3501                                         flush_work(&tmp_adev->xgmi_reset_work);
3502                                         r = tmp_adev->asic_reset_res;
3503                                         if (r)
3504                                                 break;
3505                                 }
3506                         }
3507
3508                         list_for_each_entry(tmp_adev, device_list_handle,
3509                                         gmc.xgmi.head) {
3510                                 amdgpu_ras_reserve_bad_pages(tmp_adev);
3511                         }
3512                 }
3513         }
3514
3515
3516         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3517                 if (need_full_reset) {
3518                         /* post card */
3519                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3520                                 DRM_WARN("asic atom init failed!");
3521
3522                         if (!r) {
3523                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3524                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3525                                 if (r)
3526                                         goto out;
3527
3528                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3529                                 if (vram_lost) {
3530                                         DRM_INFO("VRAM is lost due to GPU reset!\n");
3531                                         atomic_inc(&tmp_adev->vram_lost_counter);
3532                                 }
3533
3534                                 r = amdgpu_gtt_mgr_recover(
3535                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3536                                 if (r)
3537                                         goto out;
3538
3539                                 r = amdgpu_device_fw_loading(tmp_adev);
3540                                 if (r)
3541                                         return r;
3542
3543                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3544                                 if (r)
3545                                         goto out;
3546
3547                                 if (vram_lost)
3548                                         amdgpu_device_fill_reset_magic(tmp_adev);
3549
3550                                 r = amdgpu_device_ip_late_init(tmp_adev);
3551                                 if (r)
3552                                         goto out;
3553
3554                                 /* must succeed. */
3555                                 amdgpu_ras_resume(tmp_adev);
3556
3557                                 /* Update PSP FW topology after reset */
3558                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3559                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3560                         }
3561                 }
3562
3563
3564 out:
3565                 if (!r) {
3566                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3567                         r = amdgpu_ib_ring_tests(tmp_adev);
3568                         if (r) {
3569                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3570                                 r = amdgpu_device_ip_suspend(tmp_adev);
3571                                 need_full_reset = true;
3572                                 r = -EAGAIN;
3573                                 goto end;
3574                         }
3575                 }
3576
3577                 if (!r)
3578                         r = amdgpu_device_recover_vram(tmp_adev);
3579                 else
3580                         tmp_adev->asic_reset_res = r;
3581         }
3582
3583 end:
3584         *need_full_reset_arg = need_full_reset;
3585         return r;
3586 }
3587
3588 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3589 {
3590         if (trylock) {
3591                 if (!mutex_trylock(&adev->lock_reset))
3592                         return false;
3593         } else
3594                 mutex_lock(&adev->lock_reset);
3595
3596         atomic_inc(&adev->gpu_reset_counter);
3597         adev->in_gpu_reset = 1;
3598         /* Block kfd: SRIOV would do it separately */
3599         if (!amdgpu_sriov_vf(adev))
3600                 amdgpu_amdkfd_pre_reset(adev);
3601
3602         return true;
3603 }
3604
3605 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3606 {
3607         /*unlock kfd: SRIOV would do it separately */
3608         if (!amdgpu_sriov_vf(adev))
3609                 amdgpu_amdkfd_post_reset(adev);
3610         amdgpu_vf_error_trans_all(adev);
3611         adev->in_gpu_reset = 0;
3612         mutex_unlock(&adev->lock_reset);
3613 }
3614
3615
3616 /**
3617  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3618  *
3619  * @adev: amdgpu device pointer
3620  * @job: which job trigger hang
3621  *
3622  * Attempt to reset the GPU if it has hung (all asics).
3623  * Attempt to do soft-reset or full-reset and reinitialize Asic
3624  * Returns 0 for success or an error on failure.
3625  */
3626
3627 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3628                               struct amdgpu_job *job)
3629 {
3630         struct list_head device_list, *device_list_handle =  NULL;
3631         bool need_full_reset, job_signaled;
3632         struct amdgpu_hive_info *hive = NULL;
3633         struct amdgpu_device *tmp_adev = NULL;
3634         int i, r = 0;
3635
3636         need_full_reset = job_signaled = false;
3637         INIT_LIST_HEAD(&device_list);
3638
3639         dev_info(adev->dev, "GPU reset begin!\n");
3640
3641         cancel_delayed_work_sync(&adev->delayed_init_work);
3642
3643         hive = amdgpu_get_xgmi_hive(adev, false);
3644
3645         /*
3646          * Here we trylock to avoid chain of resets executing from
3647          * either trigger by jobs on different adevs in XGMI hive or jobs on
3648          * different schedulers for same device while this TO handler is running.
3649          * We always reset all schedulers for device and all devices for XGMI
3650          * hive so that should take care of them too.
3651          */
3652
3653         if (hive && !mutex_trylock(&hive->reset_lock)) {
3654                 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3655                          job->base.id, hive->hive_id);
3656                 return 0;
3657         }
3658
3659         /* Start with adev pre asic reset first for soft reset check.*/
3660         if (!amdgpu_device_lock_adev(adev, !hive)) {
3661                 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3662                                          job->base.id);
3663                 return 0;
3664         }
3665
3666         /* Build list of devices to reset */
3667         if  (adev->gmc.xgmi.num_physical_nodes > 1) {
3668                 if (!hive) {
3669                         amdgpu_device_unlock_adev(adev);
3670                         return -ENODEV;
3671                 }
3672
3673                 /*
3674                  * In case we are in XGMI hive mode device reset is done for all the
3675                  * nodes in the hive to retrain all XGMI links and hence the reset
3676                  * sequence is executed in loop on all nodes.
3677                  */
3678                 device_list_handle = &hive->device_list;
3679         } else {
3680                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3681                 device_list_handle = &device_list;
3682         }
3683
3684         /* block all schedulers and reset given job's ring */
3685         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3686                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3687                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3688
3689                         if (!ring || !ring->sched.thread)
3690                                 continue;
3691
3692                         drm_sched_stop(&ring->sched, &job->base);
3693                 }
3694         }
3695
3696
3697         /*
3698          * Must check guilty signal here since after this point all old
3699          * HW fences are force signaled.
3700          *
3701          * job->base holds a reference to parent fence
3702          */
3703         if (job && job->base.s_fence->parent &&
3704             dma_fence_is_signaled(job->base.s_fence->parent))
3705                 job_signaled = true;
3706
3707         if (!amdgpu_device_ip_need_full_reset(adev))
3708                 device_list_handle = &device_list;
3709
3710         if (job_signaled) {
3711                 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3712                 goto skip_hw_reset;
3713         }
3714
3715
3716         /* Guilty job will be freed after this*/
3717         r = amdgpu_device_pre_asic_reset(adev,
3718                                          job,
3719                                          &need_full_reset);
3720         if (r) {
3721                 /*TODO Should we stop ?*/
3722                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3723                           r, adev->ddev->unique);
3724                 adev->asic_reset_res = r;
3725         }
3726
3727 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3728         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3729
3730                 if (tmp_adev == adev)
3731                         continue;
3732
3733                 amdgpu_device_lock_adev(tmp_adev, false);
3734                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3735                                                  NULL,
3736                                                  &need_full_reset);
3737                 /*TODO Should we stop ?*/
3738                 if (r) {
3739                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3740                                   r, tmp_adev->ddev->unique);
3741                         tmp_adev->asic_reset_res = r;
3742                 }
3743         }
3744
3745         /* Actual ASIC resets if needed.*/
3746         /* TODO Implement XGMI hive reset logic for SRIOV */
3747         if (amdgpu_sriov_vf(adev)) {
3748                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3749                 if (r)
3750                         adev->asic_reset_res = r;
3751         } else {
3752                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3753                 if (r && r == -EAGAIN)
3754                         goto retry;
3755         }
3756
3757 skip_hw_reset:
3758
3759         /* Post ASIC reset for all devs .*/
3760         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3761                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3762                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3763
3764                         if (!ring || !ring->sched.thread)
3765                                 continue;
3766
3767                         /* No point to resubmit jobs if we didn't HW reset*/
3768                         if (!tmp_adev->asic_reset_res && !job_signaled)
3769                                 drm_sched_resubmit_jobs(&ring->sched);
3770
3771                         drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3772                 }
3773
3774                 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3775                         drm_helper_resume_force_mode(tmp_adev->ddev);
3776                 }
3777
3778                 tmp_adev->asic_reset_res = 0;
3779
3780                 if (r) {
3781                         /* bad news, how to tell it to userspace ? */
3782                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3783                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3784                 } else {
3785                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3786                 }
3787
3788                 amdgpu_device_unlock_adev(tmp_adev);
3789         }
3790
3791         if (hive)
3792                 mutex_unlock(&hive->reset_lock);
3793
3794         if (r)
3795                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3796         return r;
3797 }
3798
3799 /**
3800  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3801  *
3802  * @adev: amdgpu_device pointer
3803  *
3804  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3805  * and lanes) of the slot the device is in. Handles APUs and
3806  * virtualized environments where PCIE config space may not be available.
3807  */
3808 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3809 {
3810         struct pci_dev *pdev;
3811         enum pci_bus_speed speed_cap, platform_speed_cap;
3812         enum pcie_link_width platform_link_width;
3813
3814         if (amdgpu_pcie_gen_cap)
3815                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3816
3817         if (amdgpu_pcie_lane_cap)
3818                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3819
3820         /* covers APUs as well */
3821         if (pci_is_root_bus(adev->pdev->bus)) {
3822                 if (adev->pm.pcie_gen_mask == 0)
3823                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3824                 if (adev->pm.pcie_mlw_mask == 0)
3825                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3826                 return;
3827         }
3828
3829         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3830                 return;
3831
3832         pcie_bandwidth_available(adev->pdev, NULL,
3833                                  &platform_speed_cap, &platform_link_width);
3834
3835         if (adev->pm.pcie_gen_mask == 0) {
3836                 /* asic caps */
3837                 pdev = adev->pdev;
3838                 speed_cap = pcie_get_speed_cap(pdev);
3839                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3840                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3841                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3842                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3843                 } else {
3844                         if (speed_cap == PCIE_SPEED_16_0GT)
3845                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3846                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3847                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3848                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3849                         else if (speed_cap == PCIE_SPEED_8_0GT)
3850                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3851                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3852                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3853                         else if (speed_cap == PCIE_SPEED_5_0GT)
3854                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3855                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3856                         else
3857                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3858                 }
3859                 /* platform caps */
3860                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3861                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3862                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3863                 } else {
3864                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
3865                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3866                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3867                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3868                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3869                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3870                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3871                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3872                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3873                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3874                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3875                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3876                         else
3877                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3878
3879                 }
3880         }
3881         if (adev->pm.pcie_mlw_mask == 0) {
3882                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3883                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3884                 } else {
3885                         switch (platform_link_width) {
3886                         case PCIE_LNK_X32:
3887                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3888                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3889                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3890                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3891                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3892                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3893                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3894                                 break;
3895                         case PCIE_LNK_X16:
3896                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3897                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3898                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3899                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3900                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3901                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3902                                 break;
3903                         case PCIE_LNK_X12:
3904                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3905                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3906                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3907                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3908                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3909                                 break;
3910                         case PCIE_LNK_X8:
3911                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3912                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3913                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3914                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3915                                 break;
3916                         case PCIE_LNK_X4:
3917                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3918                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3919                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3920                                 break;
3921                         case PCIE_LNK_X2:
3922                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3923                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3924                                 break;
3925                         case PCIE_LNK_X1:
3926                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3927                                 break;
3928                         default:
3929                                 break;
3930                         }
3931                 }
3932         }
3933 }
3934