drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mxgpu_nv.h"
  63 #include "smuio_v11_0.h"
  64 #include "smuio_v11_0_6.h"
  65
  66 static const struct amd_ip_funcs nv_common_ip_funcs;
  67
  68 /* Navi */
  69 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
  70         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
  71         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
  72 };
  73
  74 static const struct amdgpu_video_codecs nv_video_codecs_encode = {
  75         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  76         .codec_array = nv_video_codecs_encode_array,
  77 };
  78
  79 /* Navi1x */
  80 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
  81         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
  82         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
  83         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  84         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  88 };
  89
  90 static const struct amdgpu_video_codecs nv_video_codecs_decode = {
  91         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  92         .codec_array = nv_video_codecs_decode_array,
  93 };
  94
  95 /* Sienna Cichlid */
  96 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
  97         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
  98         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
  99 };
 100
 101 static const struct amdgpu_video_codecs sc_video_codecs_encode = {
 102         .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
 103         .codec_array = sc_video_codecs_encode_array,
 104 };
 105
 106 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 111         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 112         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 113         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 114         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 115 };
 116
 117 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
 118         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 119         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 120         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 121         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 122         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 124         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 125 };
 126
 127 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = {
 128         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
 129         .codec_array = sc_video_codecs_decode_array_vcn0,
 130 };
 131
 132 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
 133         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
 134         .codec_array = sc_video_codecs_decode_array_vcn1,
 135 };
 136
 137 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 138 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
 139         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 140         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
 141 };
 142
 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 148         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 149         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 150         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 151         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 152 };
 153
 154 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {
 155         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 156         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 157         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 158         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 159         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 160         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 161         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 162 };
 163
 164 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = {
 165         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 166         .codec_array = sriov_sc_video_codecs_encode_array,
 167 };
 168
 169 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = {
 170         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
 171         .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
 172 };
 173
 174 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = {
 175         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
 176         .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
 177 };
 178
 179 /* Beige Goby*/
 180 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 181         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 182         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 183         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 184 };
 185
 186 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 187         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 188         .codec_array = bg_video_codecs_decode_array,
 189 };
 190
 191 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 192         .codec_count = 0,
 193         .codec_array = NULL,
 194 };
 195
 196 /* Yellow Carp*/
 197 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 198         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 199         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 200         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 201         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 202         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 203 };
 204
 205 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 206         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 207         .codec_array = yc_video_codecs_decode_array,
 208 };
 209
 210 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 211                                  const struct amdgpu_video_codecs **codecs)
 212 {
 213         if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 214                 return -EINVAL;
 215
 216         switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
 217         case IP_VERSION(3, 0, 0):
 218         case IP_VERSION(3, 0, 64):
 219         case IP_VERSION(3, 0, 192):
 220                 if (amdgpu_sriov_vf(adev)) {
 221                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 222                                 if (encode)
 223                                         *codecs = &sriov_sc_video_codecs_encode;
 224                                 else
 225                                         *codecs = &sriov_sc_video_codecs_decode_vcn1;
 226                         } else {
 227                                 if (encode)
 228                                         *codecs = &sriov_sc_video_codecs_encode;
 229                                 else
 230                                         *codecs = &sriov_sc_video_codecs_decode_vcn0;
 231                         }
 232                 } else {
 233                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 234                                 if (encode)
 235                                         *codecs = &sc_video_codecs_encode;
 236                                 else
 237                                         *codecs = &sc_video_codecs_decode_vcn1;
 238                         } else {
 239                                 if (encode)
 240                                         *codecs = &sc_video_codecs_encode;
 241                                 else
 242                                         *codecs = &sc_video_codecs_decode_vcn0;
 243                         }
 244                 }
 245                 return 0;
 246         case IP_VERSION(3, 0, 16):
 247         case IP_VERSION(3, 0, 2):
 248                 if (encode)
 249                         *codecs = &sc_video_codecs_encode;
 250                 else
 251                         *codecs = &sc_video_codecs_decode_vcn0;
 252                 return 0;
 253         case IP_VERSION(3, 1, 1):
 254         case IP_VERSION(3, 1, 2):
 255                 if (encode)
 256                         *codecs = &sc_video_codecs_encode;
 257                 else
 258                         *codecs = &yc_video_codecs_decode;
 259                 return 0;
 260         case IP_VERSION(3, 0, 33):
 261                 if (encode)
 262                         *codecs = &bg_video_codecs_encode;
 263                 else
 264                         *codecs = &bg_video_codecs_decode;
 265                 return 0;
 266         case IP_VERSION(2, 0, 0):
 267         case IP_VERSION(2, 0, 2):
 268                 if (encode)
 269                         *codecs = &nv_video_codecs_encode;
 270                 else
 271                         *codecs = &nv_video_codecs_decode;
 272                 return 0;
 273         default:
 274                 return -EINVAL;
 275         }
 276 }
 277
 278 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 279 {
 280         unsigned long flags, address, data;
 281         u32 r;
 282
 283         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 284         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 285
 286         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 287         WREG32(address, (reg));
 288         r = RREG32(data);
 289         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 290         return r;
 291 }
 292
 293 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 294 {
 295         unsigned long flags, address, data;
 296
 297         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 298         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 299
 300         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 301         WREG32(address, (reg));
 302         WREG32(data, (v));
 303         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 304 }
 305
 306 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 307 {
 308         return adev->nbio.funcs->get_memsize(adev);
 309 }
 310
 311 static u32 nv_get_xclk(struct amdgpu_device *adev)
 312 {
 313         return adev->clock.spll.reference_freq;
 314 }
 315
 316
 317 void nv_grbm_select(struct amdgpu_device *adev,
 318                      u32 me, u32 pipe, u32 queue, u32 vmid)
 319 {
 320         u32 grbm_gfx_cntl = 0;
 321         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 322         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 323         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 324         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 325
 326         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 327 }
 328
 329 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 330 {
 331         /* todo */
 332         return false;
 333 }
 334
 335 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 336         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 337         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 338         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 339         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 340         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 341         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 342         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 343         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 344         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 345         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 346         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 347         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 348         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 349         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 350         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 351         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 352         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 353         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 354         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 355 };
 356
 357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 358                                          u32 sh_num, u32 reg_offset)
 359 {
 360         uint32_t val;
 361
 362         mutex_lock(&adev->grbm_idx_mutex);
 363         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 364                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
 365
 366         val = RREG32(reg_offset);
 367
 368         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 369                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 370         mutex_unlock(&adev->grbm_idx_mutex);
 371         return val;
 372 }
 373
 374 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 375                                       bool indexed, u32 se_num,
 376                                       u32 sh_num, u32 reg_offset)
 377 {
 378         if (indexed) {
 379                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 380         } else {
 381                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 382                         return adev->gfx.config.gb_addr_config;
 383                 return RREG32(reg_offset);
 384         }
 385 }
 386
 387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 388                             u32 sh_num, u32 reg_offset, u32 *value)
 389 {
 390         uint32_t i;
 391         struct soc15_allowed_register_entry  *en;
 392
 393         *value = 0;
 394         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 395                 en = &nv_allowed_read_registers[i];
 396                 if (!adev->reg_offset[en->hwip][en->inst])
 397                         continue;
 398                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 399                                         + en->reg_offset))
 400                         continue;
 401
 402                 *value = nv_get_register_value(adev,
 403                                                nv_allowed_read_registers[i].grbm_indexed,
 404                                                se_num, sh_num, reg_offset);
 405                 return 0;
 406         }
 407         return -EINVAL;
 408 }
 409
 410 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 411 {
 412         u32 i;
 413         int ret = 0;
 414
 415         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 416
 417         /* disable BM */
 418         pci_clear_master(adev->pdev);
 419
 420         amdgpu_device_cache_pci_state(adev->pdev);
 421
 422         ret = amdgpu_dpm_mode2_reset(adev);
 423         if (ret)
 424                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 425
 426         amdgpu_device_load_pci_state(adev->pdev);
 427
 428         /* wait for asic to come out of reset */
 429         for (i = 0; i < adev->usec_timeout; i++) {
 430                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 431
 432                 if (memsize != 0xffffffff)
 433                         break;
 434                 udelay(1);
 435         }
 436
 437         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 438
 439         return ret;
 440 }
 441
 442 static enum amd_reset_method
 443 nv_asic_reset_method(struct amdgpu_device *adev)
 444 {
 445         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 446             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 447             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 448             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 449                 return amdgpu_reset_method;
 450
 451         if (amdgpu_reset_method != -1)
 452                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 453                                   amdgpu_reset_method);
 454
 455         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 456         case IP_VERSION(11, 5, 0):
 457         case IP_VERSION(13, 0, 1):
 458         case IP_VERSION(13, 0, 3):
 459         case IP_VERSION(13, 0, 5):
 460         case IP_VERSION(13, 0, 8):
 461                 return AMD_RESET_METHOD_MODE2;
 462         case IP_VERSION(11, 0, 7):
 463         case IP_VERSION(11, 0, 11):
 464         case IP_VERSION(11, 0, 12):
 465         case IP_VERSION(11, 0, 13):
 466                 return AMD_RESET_METHOD_MODE1;
 467         default:
 468                 if (amdgpu_dpm_is_baco_supported(adev))
 469                         return AMD_RESET_METHOD_BACO;
 470                 else
 471                         return AMD_RESET_METHOD_MODE1;
 472         }
 473 }
 474
 475 static int nv_asic_reset(struct amdgpu_device *adev)
 476 {
 477         int ret = 0;
 478
 479         switch (nv_asic_reset_method(adev)) {
 480         case AMD_RESET_METHOD_PCI:
 481                 dev_info(adev->dev, "PCI reset\n");
 482                 ret = amdgpu_device_pci_reset(adev);
 483                 break;
 484         case AMD_RESET_METHOD_BACO:
 485                 dev_info(adev->dev, "BACO reset\n");
 486                 ret = amdgpu_dpm_baco_reset(adev);
 487                 break;
 488         case AMD_RESET_METHOD_MODE2:
 489                 dev_info(adev->dev, "MODE2 reset\n");
 490                 ret = nv_asic_mode2_reset(adev);
 491                 break;
 492         default:
 493                 dev_info(adev->dev, "MODE1 reset\n");
 494                 ret = amdgpu_device_mode1_reset(adev);
 495                 break;
 496         }
 497
 498         return ret;
 499 }
 500
 501 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 502 {
 503         /* todo */
 504         return 0;
 505 }
 506
 507 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 508 {
 509         /* todo */
 510         return 0;
 511 }
 512
 513 static void nv_program_aspm(struct amdgpu_device *adev)
 514 {
 515         if (!amdgpu_device_should_use_aspm(adev))
 516                 return;
 517
 518         if (adev->nbio.funcs->program_aspm)
 519                 adev->nbio.funcs->program_aspm(adev);
 520
 521 }
 522
 523 const struct amdgpu_ip_block_version nv_common_ip_block = {
 524         .type = AMD_IP_BLOCK_TYPE_COMMON,
 525         .major = 1,
 526         .minor = 0,
 527         .rev = 0,
 528         .funcs = &nv_common_ip_funcs,
 529 };
 530
 531 void nv_set_virt_ops(struct amdgpu_device *adev)
 532 {
 533         adev->virt.ops = &xgpu_nv_virt_ops;
 534 }
 535
 536 static bool nv_need_full_reset(struct amdgpu_device *adev)
 537 {
 538         return true;
 539 }
 540
 541 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 542 {
 543         u32 sol_reg;
 544
 545         if (adev->flags & AMD_IS_APU)
 546                 return false;
 547
 548         /* Check sOS sign of life register to confirm sys driver and sOS
 549          * are already been loaded.
 550          */
 551         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 552         if (sol_reg)
 553                 return true;
 554
 555         return false;
 556 }
 557
 558 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 559 {
 560         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 561         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 562         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 563         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 564         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 565         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 566         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 567         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 568         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 569         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 570         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 571         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 572         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 573         adev->doorbell_index.gfx_userqueue_start =
 574                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 575         adev->doorbell_index.gfx_userqueue_end =
 576                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
 577         adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
 578         adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
 579         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 580         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 581         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 582         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 583         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 584         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 585         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 586         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 587         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 588         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 589         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 590
 591         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 592         adev->doorbell_index.sdma_doorbell_range = 20;
 593 }
 594
 595 static void nv_pre_asic_init(struct amdgpu_device *adev)
 596 {
 597 }
 598
 599 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 600                                        bool enter)
 601 {
 602         if (enter)
 603                 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 604         else
 605                 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 606
 607         if (adev->gfx.funcs->update_perfmon_mgcg)
 608                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 609
 610         if (adev->nbio.funcs->enable_aspm &&
 611             amdgpu_device_should_use_aspm(adev))
 612                 adev->nbio.funcs->enable_aspm(adev, !enter);
 613
 614         return 0;
 615 }
 616
 617 static const struct amdgpu_asic_funcs nv_asic_funcs = {
 618         .read_disabled_bios = &nv_read_disabled_bios,
 619         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 620         .read_register = &nv_read_register,
 621         .reset = &nv_asic_reset,
 622         .reset_method = &nv_asic_reset_method,
 623         .get_xclk = &nv_get_xclk,
 624         .set_uvd_clocks = &nv_set_uvd_clocks,
 625         .set_vce_clocks = &nv_set_vce_clocks,
 626         .get_config_memsize = &nv_get_config_memsize,
 627         .init_doorbell_index = &nv_init_doorbell_index,
 628         .need_full_reset = &nv_need_full_reset,
 629         .need_reset_on_init = &nv_need_reset_on_init,
 630         .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
 631         .supports_baco = &amdgpu_dpm_is_baco_supported,
 632         .pre_asic_init = &nv_pre_asic_init,
 633         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 634         .query_video_codecs = &nv_query_video_codecs,
 635 };
 636
 637 static int nv_common_early_init(struct amdgpu_ip_block *ip_block)
 638 {
 639         struct amdgpu_device *adev = ip_block->adev;
 640
 641         adev->nbio.funcs->set_reg_remap(adev);
 642         adev->smc_rreg = NULL;
 643         adev->smc_wreg = NULL;
 644         adev->pcie_rreg = &amdgpu_device_indirect_rreg;
 645         adev->pcie_wreg = &amdgpu_device_indirect_wreg;
 646         adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
 647         adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
 648         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 649         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 650
 651         /* TODO: will add them during VCN v2 implementation */
 652         adev->uvd_ctx_rreg = NULL;
 653         adev->uvd_ctx_wreg = NULL;
 654
 655         adev->didt_rreg = &nv_didt_rreg;
 656         adev->didt_wreg = &nv_didt_wreg;
 657
 658         adev->asic_funcs = &nv_asic_funcs;
 659
 660         adev->rev_id = amdgpu_device_get_rev_id(adev);
 661         adev->external_rev_id = 0xff;
 662         /* TODO: split the GC and PG flags based on the relevant IP version for which
 663          * they are relevant.
 664          */
 665         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 666         case IP_VERSION(10, 1, 10):
 667                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 668                         AMD_CG_SUPPORT_GFX_CGCG |
 669                         AMD_CG_SUPPORT_IH_CG |
 670                         AMD_CG_SUPPORT_HDP_MGCG |
 671                         AMD_CG_SUPPORT_HDP_LS |
 672                         AMD_CG_SUPPORT_SDMA_MGCG |
 673                         AMD_CG_SUPPORT_SDMA_LS |
 674                         AMD_CG_SUPPORT_MC_MGCG |
 675                         AMD_CG_SUPPORT_MC_LS |
 676                         AMD_CG_SUPPORT_ATHUB_MGCG |
 677                         AMD_CG_SUPPORT_ATHUB_LS |
 678                         AMD_CG_SUPPORT_VCN_MGCG |
 679                         AMD_CG_SUPPORT_JPEG_MGCG |
 680                         AMD_CG_SUPPORT_BIF_MGCG |
 681                         AMD_CG_SUPPORT_BIF_LS;
 682                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 683                         AMD_PG_SUPPORT_VCN_DPG |
 684                         AMD_PG_SUPPORT_JPEG |
 685                         AMD_PG_SUPPORT_ATHUB;
 686                 adev->external_rev_id = adev->rev_id + 0x1;
 687                 break;
 688         case IP_VERSION(10, 1, 1):
 689                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 690                         AMD_CG_SUPPORT_GFX_CGCG |
 691                         AMD_CG_SUPPORT_IH_CG |
 692                         AMD_CG_SUPPORT_HDP_MGCG |
 693                         AMD_CG_SUPPORT_HDP_LS |
 694                         AMD_CG_SUPPORT_SDMA_MGCG |
 695                         AMD_CG_SUPPORT_SDMA_LS |
 696                         AMD_CG_SUPPORT_MC_MGCG |
 697                         AMD_CG_SUPPORT_MC_LS |
 698                         AMD_CG_SUPPORT_ATHUB_MGCG |
 699                         AMD_CG_SUPPORT_ATHUB_LS |
 700                         AMD_CG_SUPPORT_VCN_MGCG |
 701                         AMD_CG_SUPPORT_JPEG_MGCG |
 702                         AMD_CG_SUPPORT_BIF_MGCG |
 703                         AMD_CG_SUPPORT_BIF_LS;
 704                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 705                         AMD_PG_SUPPORT_JPEG |
 706                         AMD_PG_SUPPORT_VCN_DPG;
 707                 adev->external_rev_id = adev->rev_id + 20;
 708                 break;
 709         case IP_VERSION(10, 1, 2):
 710                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 711                         AMD_CG_SUPPORT_GFX_MGLS |
 712                         AMD_CG_SUPPORT_GFX_CGCG |
 713                         AMD_CG_SUPPORT_GFX_CP_LS |
 714                         AMD_CG_SUPPORT_GFX_RLC_LS |
 715                         AMD_CG_SUPPORT_IH_CG |
 716                         AMD_CG_SUPPORT_HDP_MGCG |
 717                         AMD_CG_SUPPORT_HDP_LS |
 718                         AMD_CG_SUPPORT_SDMA_MGCG |
 719                         AMD_CG_SUPPORT_SDMA_LS |
 720                         AMD_CG_SUPPORT_MC_MGCG |
 721                         AMD_CG_SUPPORT_MC_LS |
 722                         AMD_CG_SUPPORT_ATHUB_MGCG |
 723                         AMD_CG_SUPPORT_ATHUB_LS |
 724                         AMD_CG_SUPPORT_VCN_MGCG |
 725                         AMD_CG_SUPPORT_JPEG_MGCG;
 726                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 727                         AMD_PG_SUPPORT_VCN_DPG |
 728                         AMD_PG_SUPPORT_JPEG |
 729                         AMD_PG_SUPPORT_ATHUB;
 730                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 731                  * as a consequence, the rev_id and external_rev_id are wrong.
 732                  * workaround it by hardcoding rev_id to 0 (default value).
 733                  */
 734                 if (amdgpu_sriov_vf(adev))
 735                         adev->rev_id = 0;
 736                 adev->external_rev_id = adev->rev_id + 0xa;
 737                 break;
 738         case IP_VERSION(10, 3, 0):
 739                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 740                         AMD_CG_SUPPORT_GFX_CGCG |
 741                         AMD_CG_SUPPORT_GFX_CGLS |
 742                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 743                         AMD_CG_SUPPORT_MC_MGCG |
 744                         AMD_CG_SUPPORT_VCN_MGCG |
 745                         AMD_CG_SUPPORT_JPEG_MGCG |
 746                         AMD_CG_SUPPORT_HDP_MGCG |
 747                         AMD_CG_SUPPORT_HDP_LS |
 748                         AMD_CG_SUPPORT_IH_CG |
 749                         AMD_CG_SUPPORT_MC_LS;
 750                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 751                         AMD_PG_SUPPORT_VCN_DPG |
 752                         AMD_PG_SUPPORT_JPEG |
 753                         AMD_PG_SUPPORT_ATHUB |
 754                         AMD_PG_SUPPORT_MMHUB;
 755                 if (amdgpu_sriov_vf(adev)) {
 756                         /* hypervisor control CG and PG enablement */
 757                         adev->cg_flags = 0;
 758                         adev->pg_flags = 0;
 759                 }
 760                 adev->external_rev_id = adev->rev_id + 0x28;
 761                 break;
 762         case IP_VERSION(10, 3, 2):
 763                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 764                         AMD_CG_SUPPORT_GFX_CGCG |
 765                         AMD_CG_SUPPORT_GFX_CGLS |
 766                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 767                         AMD_CG_SUPPORT_VCN_MGCG |
 768                         AMD_CG_SUPPORT_JPEG_MGCG |
 769                         AMD_CG_SUPPORT_MC_MGCG |
 770                         AMD_CG_SUPPORT_MC_LS |
 771                         AMD_CG_SUPPORT_HDP_MGCG |
 772                         AMD_CG_SUPPORT_HDP_LS |
 773                         AMD_CG_SUPPORT_IH_CG;
 774                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 775                         AMD_PG_SUPPORT_VCN_DPG |
 776                         AMD_PG_SUPPORT_JPEG |
 777                         AMD_PG_SUPPORT_ATHUB |
 778                         AMD_PG_SUPPORT_MMHUB;
 779                 adev->external_rev_id = adev->rev_id + 0x32;
 780                 break;
 781         case IP_VERSION(10, 3, 1):
 782                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 783                         AMD_CG_SUPPORT_GFX_MGLS |
 784                         AMD_CG_SUPPORT_GFX_CP_LS |
 785                         AMD_CG_SUPPORT_GFX_RLC_LS |
 786                         AMD_CG_SUPPORT_GFX_CGCG |
 787                         AMD_CG_SUPPORT_GFX_CGLS |
 788                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 789                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 790                         AMD_CG_SUPPORT_MC_MGCG |
 791                         AMD_CG_SUPPORT_MC_LS |
 792                         AMD_CG_SUPPORT_GFX_FGCG |
 793                         AMD_CG_SUPPORT_VCN_MGCG |
 794                         AMD_CG_SUPPORT_SDMA_MGCG |
 795                         AMD_CG_SUPPORT_SDMA_LS |
 796                         AMD_CG_SUPPORT_JPEG_MGCG;
 797                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 798                         AMD_PG_SUPPORT_VCN |
 799                         AMD_PG_SUPPORT_VCN_DPG |
 800                         AMD_PG_SUPPORT_JPEG;
 801                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 802                         adev->external_rev_id = adev->rev_id + 0x01;
 803                 break;
 804         case IP_VERSION(10, 3, 4):
 805                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 806                         AMD_CG_SUPPORT_GFX_CGCG |
 807                         AMD_CG_SUPPORT_GFX_CGLS |
 808                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 809                         AMD_CG_SUPPORT_VCN_MGCG |
 810                         AMD_CG_SUPPORT_JPEG_MGCG |
 811                         AMD_CG_SUPPORT_MC_MGCG |
 812                         AMD_CG_SUPPORT_MC_LS |
 813                         AMD_CG_SUPPORT_HDP_MGCG |
 814                         AMD_CG_SUPPORT_HDP_LS |
 815                         AMD_CG_SUPPORT_IH_CG;
 816                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 817                         AMD_PG_SUPPORT_VCN_DPG |
 818                         AMD_PG_SUPPORT_JPEG |
 819                         AMD_PG_SUPPORT_ATHUB |
 820                         AMD_PG_SUPPORT_MMHUB;
 821                 adev->external_rev_id = adev->rev_id + 0x3c;
 822                 break;
 823         case IP_VERSION(10, 3, 5):
 824                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 825                         AMD_CG_SUPPORT_GFX_CGCG |
 826                         AMD_CG_SUPPORT_GFX_CGLS |
 827                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 828                         AMD_CG_SUPPORT_MC_MGCG |
 829                         AMD_CG_SUPPORT_MC_LS |
 830                         AMD_CG_SUPPORT_HDP_MGCG |
 831                         AMD_CG_SUPPORT_HDP_LS |
 832                         AMD_CG_SUPPORT_IH_CG |
 833                         AMD_CG_SUPPORT_VCN_MGCG;
 834                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 835                         AMD_PG_SUPPORT_VCN_DPG |
 836                         AMD_PG_SUPPORT_ATHUB |
 837                         AMD_PG_SUPPORT_MMHUB;
 838                 adev->external_rev_id = adev->rev_id + 0x46;
 839                 break;
 840         case IP_VERSION(10, 3, 3):
 841                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 842                         AMD_CG_SUPPORT_GFX_MGLS |
 843                         AMD_CG_SUPPORT_GFX_CGCG |
 844                         AMD_CG_SUPPORT_GFX_CGLS |
 845                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 846                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 847                         AMD_CG_SUPPORT_GFX_RLC_LS |
 848                         AMD_CG_SUPPORT_GFX_CP_LS |
 849                         AMD_CG_SUPPORT_GFX_FGCG |
 850                         AMD_CG_SUPPORT_MC_MGCG |
 851                         AMD_CG_SUPPORT_MC_LS |
 852                         AMD_CG_SUPPORT_SDMA_LS |
 853                         AMD_CG_SUPPORT_HDP_MGCG |
 854                         AMD_CG_SUPPORT_HDP_LS |
 855                         AMD_CG_SUPPORT_ATHUB_MGCG |
 856                         AMD_CG_SUPPORT_ATHUB_LS |
 857                         AMD_CG_SUPPORT_IH_CG |
 858                         AMD_CG_SUPPORT_VCN_MGCG |
 859                         AMD_CG_SUPPORT_JPEG_MGCG |
 860                         AMD_CG_SUPPORT_SDMA_MGCG;
 861                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 862                         AMD_PG_SUPPORT_VCN |
 863                         AMD_PG_SUPPORT_VCN_DPG |
 864                         AMD_PG_SUPPORT_JPEG;
 865                 if (adev->pdev->device == 0x1681)
 866                         adev->external_rev_id = 0x20;
 867                 else
 868                         adev->external_rev_id = adev->rev_id + 0x01;
 869                 break;
 870         case IP_VERSION(10, 1, 3):
 871         case IP_VERSION(10, 1, 4):
 872                 adev->cg_flags = 0;
 873                 adev->pg_flags = 0;
 874                 adev->external_rev_id = adev->rev_id + 0x82;
 875                 break;
 876         case IP_VERSION(10, 3, 6):
 877                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 878                         AMD_CG_SUPPORT_GFX_MGLS |
 879                         AMD_CG_SUPPORT_GFX_CGCG |
 880                         AMD_CG_SUPPORT_GFX_CGLS |
 881                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 882                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 883                         AMD_CG_SUPPORT_GFX_RLC_LS |
 884                         AMD_CG_SUPPORT_GFX_CP_LS |
 885                         AMD_CG_SUPPORT_GFX_FGCG |
 886                         AMD_CG_SUPPORT_MC_MGCG |
 887                         AMD_CG_SUPPORT_MC_LS |
 888                         AMD_CG_SUPPORT_SDMA_LS |
 889                         AMD_CG_SUPPORT_HDP_MGCG |
 890                         AMD_CG_SUPPORT_HDP_LS |
 891                         AMD_CG_SUPPORT_ATHUB_MGCG |
 892                         AMD_CG_SUPPORT_ATHUB_LS |
 893                         AMD_CG_SUPPORT_IH_CG |
 894                         AMD_CG_SUPPORT_VCN_MGCG |
 895                         AMD_CG_SUPPORT_JPEG_MGCG;
 896                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 897                         AMD_PG_SUPPORT_VCN |
 898                         AMD_PG_SUPPORT_VCN_DPG |
 899                         AMD_PG_SUPPORT_JPEG;
 900                 adev->external_rev_id = adev->rev_id + 0x01;
 901                 break;
 902         case IP_VERSION(10, 3, 7):
 903                 adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
 904                         AMD_CG_SUPPORT_GFX_MGLS |
 905                         AMD_CG_SUPPORT_GFX_CGCG |
 906                         AMD_CG_SUPPORT_GFX_CGLS |
 907                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 908                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 909                         AMD_CG_SUPPORT_GFX_RLC_LS |
 910                         AMD_CG_SUPPORT_GFX_CP_LS |
 911                         AMD_CG_SUPPORT_GFX_FGCG |
 912                         AMD_CG_SUPPORT_MC_MGCG |
 913                         AMD_CG_SUPPORT_MC_LS |
 914                         AMD_CG_SUPPORT_SDMA_LS |
 915                         AMD_CG_SUPPORT_HDP_MGCG |
 916                         AMD_CG_SUPPORT_HDP_LS |
 917                         AMD_CG_SUPPORT_ATHUB_MGCG |
 918                         AMD_CG_SUPPORT_ATHUB_LS |
 919                         AMD_CG_SUPPORT_IH_CG |
 920                         AMD_CG_SUPPORT_VCN_MGCG |
 921                         AMD_CG_SUPPORT_JPEG_MGCG |
 922                         AMD_CG_SUPPORT_SDMA_MGCG;
 923                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 924                         AMD_PG_SUPPORT_VCN_DPG |
 925                         AMD_PG_SUPPORT_JPEG |
 926                         AMD_PG_SUPPORT_GFX_PG;
 927                 adev->external_rev_id = adev->rev_id + 0x01;
 928                 break;
 929         default:
 930                 /* FIXME: not supported yet */
 931                 return -EINVAL;
 932         }
 933
 934         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
 935                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
 936                                     AMD_PG_SUPPORT_VCN_DPG |
 937                                     AMD_PG_SUPPORT_JPEG);
 938
 939         if (amdgpu_sriov_vf(adev)) {
 940                 amdgpu_virt_init_setting(adev);
 941                 xgpu_nv_mailbox_set_irq_funcs(adev);
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int nv_common_late_init(struct amdgpu_ip_block *ip_block)
 948 {
 949         struct amdgpu_device *adev = ip_block->adev;
 950
 951         if (amdgpu_sriov_vf(adev)) {
 952                 xgpu_nv_mailbox_get_irq(adev);
 953                 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 954                         amdgpu_virt_update_sriov_video_codec(adev,
 955                                                              sriov_sc_video_codecs_encode_array,
 956                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 957                                                              sriov_sc_video_codecs_decode_array_vcn1,
 958                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
 959                 } else {
 960                         amdgpu_virt_update_sriov_video_codec(adev,
 961                                                              sriov_sc_video_codecs_encode_array,
 962                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 963                                                              sriov_sc_video_codecs_decode_array_vcn0,
 964                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));
 965                 }
 966         }
 967
 968         /* Enable selfring doorbell aperture late because doorbell BAR
 969          * aperture will change if resize BAR successfully in gmc sw_init.
 970          */
 971         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
 972
 973         return 0;
 974 }
 975
 976 static int nv_common_sw_init(struct amdgpu_ip_block *ip_block)
 977 {
 978         struct amdgpu_device *adev = ip_block->adev;
 979
 980         if (amdgpu_sriov_vf(adev))
 981                 xgpu_nv_mailbox_add_irq_id(adev);
 982
 983         return 0;
 984 }
 985
 986 static int nv_common_hw_init(struct amdgpu_ip_block *ip_block)
 987 {
 988         struct amdgpu_device *adev = ip_block->adev;
 989
 990         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
 991                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
 992
 993         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
 994                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
 995
 996         /* enable aspm */
 997         nv_program_aspm(adev);
 998         /* setup nbio registers */
 999         adev->nbio.funcs->init_registers(adev);
1000         /* remap HDP registers to a hole in mmio space,
1001          * for the purpose of expose those registers
1002          * to process space
1003          */
1004         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1005                 adev->nbio.funcs->remap_hdp_registers(adev);
1006         /* enable the doorbell aperture */
1007         adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1008
1009         return 0;
1010 }
1011
1012 static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block)
1013 {
1014         struct amdgpu_device *adev = ip_block->adev;
1015
1016         /* Disable the doorbell aperture and selfring doorbell aperture
1017          * separately in hw_fini because nv_enable_doorbell_aperture
1018          * has been removed and there is no need to delay disabling
1019          * selfring doorbell.
1020          */
1021         adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1022         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1023
1024         return 0;
1025 }
1026
1027 static int nv_common_suspend(struct amdgpu_ip_block *ip_block)
1028 {
1029         return nv_common_hw_fini(ip_block);
1030 }
1031
1032 static int nv_common_resume(struct amdgpu_ip_block *ip_block)
1033 {
1034         return nv_common_hw_init(ip_block);
1035 }
1036
1037 static bool nv_common_is_idle(void *handle)
1038 {
1039         return true;
1040 }
1041
1042 static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1043                                            enum amd_clockgating_state state)
1044 {
1045         struct amdgpu_device *adev = ip_block->adev;
1046
1047         if (amdgpu_sriov_vf(adev))
1048                 return 0;
1049
1050         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1051         case IP_VERSION(2, 3, 0):
1052         case IP_VERSION(2, 3, 1):
1053         case IP_VERSION(2, 3, 2):
1054         case IP_VERSION(3, 3, 0):
1055         case IP_VERSION(3, 3, 1):
1056         case IP_VERSION(3, 3, 2):
1057         case IP_VERSION(3, 3, 3):
1058                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1059                                 state == AMD_CG_STATE_GATE);
1060                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1061                                 state == AMD_CG_STATE_GATE);
1062                 adev->hdp.funcs->update_clock_gating(adev,
1063                                 state == AMD_CG_STATE_GATE);
1064                 adev->smuio.funcs->update_rom_clock_gating(adev,
1065                                 state == AMD_CG_STATE_GATE);
1066                 break;
1067         default:
1068                 break;
1069         }
1070         return 0;
1071 }
1072
1073 static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1074                                            enum amd_powergating_state state)
1075 {
1076         /* TODO */
1077         return 0;
1078 }
1079
1080 static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1081 {
1082         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083
1084         if (amdgpu_sriov_vf(adev))
1085                 *flags = 0;
1086
1087         adev->nbio.funcs->get_clockgating_state(adev, flags);
1088
1089         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1090
1091         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1092 }
1093
1094 static const struct amd_ip_funcs nv_common_ip_funcs = {
1095         .name = "nv_common",
1096         .early_init = nv_common_early_init,
1097         .late_init = nv_common_late_init,
1098         .sw_init = nv_common_sw_init,
1099         .hw_init = nv_common_hw_init,
1100         .hw_fini = nv_common_hw_fini,
1101         .suspend = nv_common_suspend,
1102         .resume = nv_common_resume,
1103         .is_idle = nv_common_is_idle,
1104         .set_clockgating_state = nv_common_set_clockgating_state,
1105         .set_powergating_state = nv_common_set_powergating_state,
1106         .get_clockgating_state = nv_common_get_clockgating_state,
1107 };