drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <[email protected]>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "amdgpu/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "amdgpu/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "amdgpu/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "amdgpu/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "amdgpu/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_vce.bin"
  55 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_vce.bin"
  56 #define FIRMWARE_VEGAM          "amdgpu/vegam_vce.bin"
  57
  58 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
  59 #define FIRMWARE_VEGA12         "amdgpu/vega12_vce.bin"
  60 #define FIRMWARE_VEGA20         "amdgpu/vega20_vce.bin"
  61
  62 #ifdef CONFIG_DRM_AMDGPU_CIK
  63 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  64 MODULE_FIRMWARE(FIRMWARE_KABINI);
  65 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  66 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  67 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  68 #endif
  69 MODULE_FIRMWARE(FIRMWARE_TONGA);
  70 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  71 MODULE_FIRMWARE(FIRMWARE_FIJI);
  72 MODULE_FIRMWARE(FIRMWARE_STONEY);
  73 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  74 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  75 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
  76 MODULE_FIRMWARE(FIRMWARE_VEGAM);
  77
  78 MODULE_FIRMWARE(FIRMWARE_VEGA10);
  79 MODULE_FIRMWARE(FIRMWARE_VEGA12);
  80 MODULE_FIRMWARE(FIRMWARE_VEGA20);
  81
  82 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  83
  84 /**
  85  * amdgpu_vce_init - allocate memory, load vce firmware
  86  *
  87  * @adev: amdgpu_device pointer
  88  *
  89  * First step to get VCE online, allocate memory and load the firmware
  90  */
  91 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  92 {
  93         const char *fw_name;
  94         const struct common_firmware_header *hdr;
  95         unsigned ucode_version, version_major, version_minor, binary_id;
  96         int i, r;
  97
  98         switch (adev->asic_type) {
  99 #ifdef CONFIG_DRM_AMDGPU_CIK
 100         case CHIP_BONAIRE:
 101                 fw_name = FIRMWARE_BONAIRE;
 102                 break;
 103         case CHIP_KAVERI:
 104                 fw_name = FIRMWARE_KAVERI;
 105                 break;
 106         case CHIP_KABINI:
 107                 fw_name = FIRMWARE_KABINI;
 108                 break;
 109         case CHIP_HAWAII:
 110                 fw_name = FIRMWARE_HAWAII;
 111                 break;
 112         case CHIP_MULLINS:
 113                 fw_name = FIRMWARE_MULLINS;
 114                 break;
 115 #endif
 116         case CHIP_TONGA:
 117                 fw_name = FIRMWARE_TONGA;
 118                 break;
 119         case CHIP_CARRIZO:
 120                 fw_name = FIRMWARE_CARRIZO;
 121                 break;
 122         case CHIP_FIJI:
 123                 fw_name = FIRMWARE_FIJI;
 124                 break;
 125         case CHIP_STONEY:
 126                 fw_name = FIRMWARE_STONEY;
 127                 break;
 128         case CHIP_POLARIS10:
 129                 fw_name = FIRMWARE_POLARIS10;
 130                 break;
 131         case CHIP_POLARIS11:
 132                 fw_name = FIRMWARE_POLARIS11;
 133                 break;
 134         case CHIP_POLARIS12:
 135                 fw_name = FIRMWARE_POLARIS12;
 136                 break;
 137         case CHIP_VEGAM:
 138                 fw_name = FIRMWARE_VEGAM;
 139                 break;
 140         case CHIP_VEGA10:
 141                 fw_name = FIRMWARE_VEGA10;
 142                 break;
 143         case CHIP_VEGA12:
 144                 fw_name = FIRMWARE_VEGA12;
 145                 break;
 146         case CHIP_VEGA20:
 147                 fw_name = FIRMWARE_VEGA20;
 148                 break;
 149
 150         default:
 151                 return -EINVAL;
 152         }
 153
 154         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 155         if (r) {
 156                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 157                         fw_name);
 158                 return r;
 159         }
 160
 161         r = amdgpu_ucode_validate(adev->vce.fw);
 162         if (r) {
 163                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 164                         fw_name);
 165                 release_firmware(adev->vce.fw);
 166                 adev->vce.fw = NULL;
 167                 return r;
 168         }
 169
 170         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 171
 172         ucode_version = le32_to_cpu(hdr->ucode_version);
 173         version_major = (ucode_version >> 20) & 0xfff;
 174         version_minor = (ucode_version >> 8) & 0xfff;
 175         binary_id = ucode_version & 0xff;
 176         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 177                 version_major, version_minor, binary_id);
 178         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 179                                 (binary_id << 8));
 180
 181         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 182                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 183                                     &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 184         if (r) {
 185                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 186                 return r;
 187         }
 188
 189         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 190                 atomic_set(&adev->vce.handles[i], 0);
 191                 adev->vce.filp[i] = NULL;
 192         }
 193
 194         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 195         mutex_init(&adev->vce.idle_mutex);
 196
 197         return 0;
 198 }
 199
 200 /**
 201  * amdgpu_vce_fini - free memory
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Last step on VCE teardown, free firmware memory
 206  */
 207 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 208 {
 209         unsigned i;
 210
 211         if (adev->vce.vcpu_bo == NULL)
 212                 return 0;
 213
 214         drm_sched_entity_destroy(&adev->vce.entity);
 215
 216         amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
 217                 (void **)&adev->vce.cpu_addr);
 218
 219         for (i = 0; i < adev->vce.num_rings; i++)
 220                 amdgpu_ring_fini(&adev->vce.ring[i]);
 221
 222         release_firmware(adev->vce.fw);
 223         mutex_destroy(&adev->vce.idle_mutex);
 224
 225         return 0;
 226 }
 227
 228 /**
 229  * amdgpu_vce_entity_init - init entity
 230  *
 231  * @adev: amdgpu_device pointer
 232  *
 233  */
 234 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 235 {
 236         struct amdgpu_ring *ring;
 237         struct drm_sched_rq *rq;
 238         int r;
 239
 240         ring = &adev->vce.ring[0];
 241         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 242         r = drm_sched_entity_init(&adev->vce.entity, &rq, 1, NULL);
 243         if (r != 0) {
 244                 DRM_ERROR("Failed setting up VCE run queue.\n");
 245                 return r;
 246         }
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * amdgpu_vce_suspend - unpin VCE fw memory
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  */
 257 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 258 {
 259         int i;
 260
 261         if (adev->vce.vcpu_bo == NULL)
 262                 return 0;
 263
 264         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 265                 if (atomic_read(&adev->vce.handles[i]))
 266                         break;
 267
 268         if (i == AMDGPU_MAX_VCE_HANDLES)
 269                 return 0;
 270
 271         cancel_delayed_work_sync(&adev->vce.idle_work);
 272         /* TODO: suspending running encoding sessions isn't supported */
 273         return -EINVAL;
 274 }
 275
 276 /**
 277  * amdgpu_vce_resume - pin VCE fw memory
 278  *
 279  * @adev: amdgpu_device pointer
 280  *
 281  */
 282 int amdgpu_vce_resume(struct amdgpu_device *adev)
 283 {
 284         void *cpu_addr;
 285         const struct common_firmware_header *hdr;
 286         unsigned offset;
 287         int r;
 288
 289         if (adev->vce.vcpu_bo == NULL)
 290                 return -EINVAL;
 291
 292         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 293         if (r) {
 294                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 295                 return r;
 296         }
 297
 298         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 299         if (r) {
 300                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 301                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 302                 return r;
 303         }
 304
 305         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 306         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 307         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 308                     adev->vce.fw->size - offset);
 309
 310         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 311
 312         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 313
 314         return 0;
 315 }
 316
 317 /**
 318  * amdgpu_vce_idle_work_handler - power off VCE
 319  *
 320  * @work: pointer to work structure
 321  *
 322  * power of VCE when it's not used any more
 323  */
 324 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 325 {
 326         struct amdgpu_device *adev =
 327                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 328         unsigned i, count = 0;
 329
 330         for (i = 0; i < adev->vce.num_rings; i++)
 331                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 332
 333         if (count == 0) {
 334                 if (adev->pm.dpm_enabled) {
 335                         amdgpu_dpm_enable_vce(adev, false);
 336                 } else {
 337                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 338                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 339                                                                AMD_PG_STATE_GATE);
 340                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 341                                                                AMD_CG_STATE_GATE);
 342                 }
 343         } else {
 344                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 345         }
 346 }
 347
 348 /**
 349  * amdgpu_vce_ring_begin_use - power up VCE
 350  *
 351  * @ring: amdgpu ring
 352  *
 353  * Make sure VCE is powerd up when we want to use it
 354  */
 355 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 356 {
 357         struct amdgpu_device *adev = ring->adev;
 358         bool set_clocks;
 359
 360         if (amdgpu_sriov_vf(adev))
 361                 return;
 362
 363         mutex_lock(&adev->vce.idle_mutex);
 364         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 365         if (set_clocks) {
 366                 if (adev->pm.dpm_enabled) {
 367                         amdgpu_dpm_enable_vce(adev, true);
 368                 } else {
 369                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 370                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 371                                                                AMD_CG_STATE_UNGATE);
 372                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 373                                                                AMD_PG_STATE_UNGATE);
 374
 375                 }
 376         }
 377         mutex_unlock(&adev->vce.idle_mutex);
 378 }
 379
 380 /**
 381  * amdgpu_vce_ring_end_use - power VCE down
 382  *
 383  * @ring: amdgpu ring
 384  *
 385  * Schedule work to power VCE down again
 386  */
 387 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 388 {
 389         if (!amdgpu_sriov_vf(ring->adev))
 390                 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 391 }
 392
 393 /**
 394  * amdgpu_vce_free_handles - free still open VCE handles
 395  *
 396  * @adev: amdgpu_device pointer
 397  * @filp: drm file pointer
 398  *
 399  * Close all VCE handles still open by this file pointer
 400  */
 401 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 402 {
 403         struct amdgpu_ring *ring = &adev->vce.ring[0];
 404         int i, r;
 405         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 406                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 407
 408                 if (!handle || adev->vce.filp[i] != filp)
 409                         continue;
 410
 411                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 412                 if (r)
 413                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 414
 415                 adev->vce.filp[i] = NULL;
 416                 atomic_set(&adev->vce.handles[i], 0);
 417         }
 418 }
 419
 420 /**
 421  * amdgpu_vce_get_create_msg - generate a VCE create msg
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @ring: ring we should submit the msg to
 425  * @handle: VCE session handle to use
 426  * @fence: optional fence to return
 427  *
 428  * Open up a stream for HW test
 429  */
 430 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 431                               struct dma_fence **fence)
 432 {
 433         const unsigned ib_size_dw = 1024;
 434         struct amdgpu_job *job;
 435         struct amdgpu_ib *ib;
 436         struct dma_fence *f = NULL;
 437         uint64_t dummy;
 438         int i, r;
 439
 440         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 441         if (r)
 442                 return r;
 443
 444         ib = &job->ibs[0];
 445
 446         dummy = ib->gpu_addr + 1024;
 447
 448         /* stitch together an VCE create msg */
 449         ib->length_dw = 0;
 450         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 451         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 452         ib->ptr[ib->length_dw++] = handle;
 453
 454         if ((ring->adev->vce.fw_version >> 24) >= 52)
 455                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 456         else
 457                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 458         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 459         ib->ptr[ib->length_dw++] = 0x00000000;
 460         ib->ptr[ib->length_dw++] = 0x00000042;
 461         ib->ptr[ib->length_dw++] = 0x0000000a;
 462         ib->ptr[ib->length_dw++] = 0x00000001;
 463         ib->ptr[ib->length_dw++] = 0x00000080;
 464         ib->ptr[ib->length_dw++] = 0x00000060;
 465         ib->ptr[ib->length_dw++] = 0x00000100;
 466         ib->ptr[ib->length_dw++] = 0x00000100;
 467         ib->ptr[ib->length_dw++] = 0x0000000c;
 468         ib->ptr[ib->length_dw++] = 0x00000000;
 469         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 470                 ib->ptr[ib->length_dw++] = 0x00000000;
 471                 ib->ptr[ib->length_dw++] = 0x00000000;
 472                 ib->ptr[ib->length_dw++] = 0x00000000;
 473                 ib->ptr[ib->length_dw++] = 0x00000000;
 474         }
 475
 476         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 477         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 478         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 479         ib->ptr[ib->length_dw++] = dummy;
 480         ib->ptr[ib->length_dw++] = 0x00000001;
 481
 482         for (i = ib->length_dw; i < ib_size_dw; ++i)
 483                 ib->ptr[i] = 0x0;
 484
 485         r = amdgpu_job_submit_direct(job, ring, &f);
 486         if (r)
 487                 goto err;
 488
 489         if (fence)
 490                 *fence = dma_fence_get(f);
 491         dma_fence_put(f);
 492         return 0;
 493
 494 err:
 495         amdgpu_job_free(job);
 496         return r;
 497 }
 498
 499 /**
 500  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 501  *
 502  * @adev: amdgpu_device pointer
 503  * @ring: ring we should submit the msg to
 504  * @handle: VCE session handle to use
 505  * @fence: optional fence to return
 506  *
 507  * Close up a stream for HW test or if userspace failed to do so
 508  */
 509 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 510                                bool direct, struct dma_fence **fence)
 511 {
 512         const unsigned ib_size_dw = 1024;
 513         struct amdgpu_job *job;
 514         struct amdgpu_ib *ib;
 515         struct dma_fence *f = NULL;
 516         int i, r;
 517
 518         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 519         if (r)
 520                 return r;
 521
 522         ib = &job->ibs[0];
 523
 524         /* stitch together an VCE destroy msg */
 525         ib->length_dw = 0;
 526         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 527         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 528         ib->ptr[ib->length_dw++] = handle;
 529
 530         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 531         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 532         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 533         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 534         ib->ptr[ib->length_dw++] = 0x00000000;
 535         ib->ptr[ib->length_dw++] = 0x00000000;
 536         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 537         ib->ptr[ib->length_dw++] = 0x00000000;
 538
 539         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 540         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 541
 542         for (i = ib->length_dw; i < ib_size_dw; ++i)
 543                 ib->ptr[i] = 0x0;
 544
 545         if (direct)
 546                 r = amdgpu_job_submit_direct(job, ring, &f);
 547         else
 548                 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
 549                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 550         if (r)
 551                 goto err;
 552
 553         if (fence)
 554                 *fence = dma_fence_get(f);
 555         dma_fence_put(f);
 556         return 0;
 557
 558 err:
 559         amdgpu_job_free(job);
 560         return r;
 561 }
 562
 563 /**
 564  * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
 565  *
 566  * @p: parser context
 567  * @lo: address of lower dword
 568  * @hi: address of higher dword
 569  * @size: minimum size
 570  * @index: bs/fb index
 571  *
 572  * Make sure that no BO cross a 4GB boundary.
 573  */
 574 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 575                                   int lo, int hi, unsigned size, int32_t index)
 576 {
 577         int64_t offset = ((uint64_t)size) * ((int64_t)index);
 578         struct ttm_operation_ctx ctx = { false, false };
 579         struct amdgpu_bo_va_mapping *mapping;
 580         unsigned i, fpfn, lpfn;
 581         struct amdgpu_bo *bo;
 582         uint64_t addr;
 583         int r;
 584
 585         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 586                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 587         if (index >= 0) {
 588                 addr += offset;
 589                 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
 590                 lpfn = 0x100000000ULL >> PAGE_SHIFT;
 591         } else {
 592                 fpfn = 0;
 593                 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
 594         }
 595
 596         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 597         if (r) {
 598                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 599                           addr, lo, hi, size, index);
 600                 return r;
 601         }
 602
 603         for (i = 0; i < bo->placement.num_placement; ++i) {
 604                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
 605                 bo->placements[i].lpfn = bo->placements[i].lpfn ?
 606                         min(bo->placements[i].lpfn, lpfn) : lpfn;
 607         }
 608         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 609 }
 610
 611
 612 /**
 613  * amdgpu_vce_cs_reloc - command submission relocation
 614  *
 615  * @p: parser context
 616  * @lo: address of lower dword
 617  * @hi: address of higher dword
 618  * @size: minimum size
 619  *
 620  * Patch relocation inside command stream with real buffer address
 621  */
 622 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 623                                int lo, int hi, unsigned size, uint32_t index)
 624 {
 625         struct amdgpu_bo_va_mapping *mapping;
 626         struct amdgpu_bo *bo;
 627         uint64_t addr;
 628         int r;
 629
 630         if (index == 0xffffffff)
 631                 index = 0;
 632
 633         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 634                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 635         addr += ((uint64_t)size) * ((uint64_t)index);
 636
 637         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 638         if (r) {
 639                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 640                           addr, lo, hi, size, index);
 641                 return r;
 642         }
 643
 644         if ((addr + (uint64_t)size) >
 645             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 646                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 647                           addr, lo, hi);
 648                 return -EINVAL;
 649         }
 650
 651         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 652         addr += amdgpu_bo_gpu_offset(bo);
 653         addr -= ((uint64_t)size) * ((uint64_t)index);
 654
 655         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 656         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 657
 658         return 0;
 659 }
 660
 661 /**
 662  * amdgpu_vce_validate_handle - validate stream handle
 663  *
 664  * @p: parser context
 665  * @handle: handle to validate
 666  * @allocated: allocated a new handle?
 667  *
 668  * Validates the handle and return the found session index or -EINVAL
 669  * we we don't have another free session index.
 670  */
 671 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 672                                       uint32_t handle, uint32_t *allocated)
 673 {
 674         unsigned i;
 675
 676         /* validate the handle */
 677         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 678                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 679                         if (p->adev->vce.filp[i] != p->filp) {
 680                                 DRM_ERROR("VCE handle collision detected!\n");
 681                                 return -EINVAL;
 682                         }
 683                         return i;
 684                 }
 685         }
 686
 687         /* handle not found try to alloc a new one */
 688         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 689                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 690                         p->adev->vce.filp[i] = p->filp;
 691                         p->adev->vce.img_size[i] = 0;
 692                         *allocated |= 1 << i;
 693                         return i;
 694                 }
 695         }
 696
 697         DRM_ERROR("No more free VCE handles!\n");
 698         return -EINVAL;
 699 }
 700
 701 /**
 702  * amdgpu_vce_cs_parse - parse and validate the command stream
 703  *
 704  * @p: parser context
 705  *
 706  */
 707 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 708 {
 709         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 710         unsigned fb_idx = 0, bs_idx = 0;
 711         int session_idx = -1;
 712         uint32_t destroyed = 0;
 713         uint32_t created = 0;
 714         uint32_t allocated = 0;
 715         uint32_t tmp, handle = 0;
 716         uint32_t *size = &tmp;
 717         unsigned idx;
 718         int i, r = 0;
 719
 720         p->job->vm = NULL;
 721         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 722
 723         for (idx = 0; idx < ib->length_dw;) {
 724                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 725                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 726
 727                 if ((len < 8) || (len & 3)) {
 728                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 729                         r = -EINVAL;
 730                         goto out;
 731                 }
 732
 733                 switch (cmd) {
 734                 case 0x00000002: /* task info */
 735                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 736                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 737                         break;
 738
 739                 case 0x03000001: /* encode */
 740                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
 741                                                    idx + 9, 0, 0);
 742                         if (r)
 743                                 goto out;
 744
 745                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
 746                                                    idx + 11, 0, 0);
 747                         if (r)
 748                                 goto out;
 749                         break;
 750
 751                 case 0x05000001: /* context buffer */
 752                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 753                                                    idx + 2, 0, 0);
 754                         if (r)
 755                                 goto out;
 756                         break;
 757
 758                 case 0x05000004: /* video bitstream buffer */
 759                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 760                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 761                                                    tmp, bs_idx);
 762                         if (r)
 763                                 goto out;
 764                         break;
 765
 766                 case 0x05000005: /* feedback buffer */
 767                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 768                                                    4096, fb_idx);
 769                         if (r)
 770                                 goto out;
 771                         break;
 772
 773                 case 0x0500000d: /* MV buffer */
 774                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 775                                                         idx + 2, 0, 0);
 776                         if (r)
 777                                 goto out;
 778
 779                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
 780                                                         idx + 7, 0, 0);
 781                         if (r)
 782                                 goto out;
 783                         break;
 784                 }
 785
 786                 idx += len / 4;
 787         }
 788
 789         for (idx = 0; idx < ib->length_dw;) {
 790                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 791                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 792
 793                 switch (cmd) {
 794                 case 0x00000001: /* session */
 795                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 796                         session_idx = amdgpu_vce_validate_handle(p, handle,
 797                                                                  &allocated);
 798                         if (session_idx < 0) {
 799                                 r = session_idx;
 800                                 goto out;
 801                         }
 802                         size = &p->adev->vce.img_size[session_idx];
 803                         break;
 804
 805                 case 0x00000002: /* task info */
 806                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 807                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 808                         break;
 809
 810                 case 0x01000001: /* create */
 811                         created |= 1 << session_idx;
 812                         if (destroyed & (1 << session_idx)) {
 813                                 destroyed &= ~(1 << session_idx);
 814                                 allocated |= 1 << session_idx;
 815
 816                         } else if (!(allocated & (1 << session_idx))) {
 817                                 DRM_ERROR("Handle already in use!\n");
 818                                 r = -EINVAL;
 819                                 goto out;
 820                         }
 821
 822                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 823                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 824                                 8 * 3 / 2;
 825                         break;
 826
 827                 case 0x04000001: /* config extension */
 828                 case 0x04000002: /* pic control */
 829                 case 0x04000005: /* rate control */
 830                 case 0x04000007: /* motion estimation */
 831                 case 0x04000008: /* rdo */
 832                 case 0x04000009: /* vui */
 833                 case 0x05000002: /* auxiliary buffer */
 834                 case 0x05000009: /* clock table */
 835                         break;
 836
 837                 case 0x0500000c: /* hw config */
 838                         switch (p->adev->asic_type) {
 839 #ifdef CONFIG_DRM_AMDGPU_CIK
 840                         case CHIP_KAVERI:
 841                         case CHIP_MULLINS:
 842 #endif
 843                         case CHIP_CARRIZO:
 844                                 break;
 845                         default:
 846                                 r = -EINVAL;
 847                                 goto out;
 848                         }
 849                         break;
 850
 851                 case 0x03000001: /* encode */
 852                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 853                                                 *size, 0);
 854                         if (r)
 855                                 goto out;
 856
 857                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 858                                                 *size / 3, 0);
 859                         if (r)
 860                                 goto out;
 861                         break;
 862
 863                 case 0x02000001: /* destroy */
 864                         destroyed |= 1 << session_idx;
 865                         break;
 866
 867                 case 0x05000001: /* context buffer */
 868                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 869                                                 *size * 2, 0);
 870                         if (r)
 871                                 goto out;
 872                         break;
 873
 874                 case 0x05000004: /* video bitstream buffer */
 875                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 876                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 877                                                 tmp, bs_idx);
 878                         if (r)
 879                                 goto out;
 880                         break;
 881
 882                 case 0x05000005: /* feedback buffer */
 883                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 884                                                 4096, fb_idx);
 885                         if (r)
 886                                 goto out;
 887                         break;
 888
 889                 case 0x0500000d: /* MV buffer */
 890                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
 891                                                         idx + 2, *size, 0);
 892                         if (r)
 893                                 goto out;
 894
 895                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
 896                                                         idx + 7, *size / 12, 0);
 897                         if (r)
 898                                 goto out;
 899                         break;
 900
 901                 default:
 902                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 903                         r = -EINVAL;
 904                         goto out;
 905                 }
 906
 907                 if (session_idx == -1) {
 908                         DRM_ERROR("no session command at start of IB\n");
 909                         r = -EINVAL;
 910                         goto out;
 911                 }
 912
 913                 idx += len / 4;
 914         }
 915
 916         if (allocated & ~created) {
 917                 DRM_ERROR("New session without create command!\n");
 918                 r = -ENOENT;
 919         }
 920
 921 out:
 922         if (!r) {
 923                 /* No error, free all destroyed handle slots */
 924                 tmp = destroyed;
 925         } else {
 926                 /* Error during parsing, free all allocated handle slots */
 927                 tmp = allocated;
 928         }
 929
 930         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 931                 if (tmp & (1 << i))
 932                         atomic_set(&p->adev->vce.handles[i], 0);
 933
 934         return r;
 935 }
 936
 937 /**
 938  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 939  *
 940  * @p: parser context
 941  *
 942  */
 943 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 944 {
 945         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 946         int session_idx = -1;
 947         uint32_t destroyed = 0;
 948         uint32_t created = 0;
 949         uint32_t allocated = 0;
 950         uint32_t tmp, handle = 0;
 951         int i, r = 0, idx = 0;
 952
 953         while (idx < ib->length_dw) {
 954                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 955                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 956
 957                 if ((len < 8) || (len & 3)) {
 958                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 959                         r = -EINVAL;
 960                         goto out;
 961                 }
 962
 963                 switch (cmd) {
 964                 case 0x00000001: /* session */
 965                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 966                         session_idx = amdgpu_vce_validate_handle(p, handle,
 967                                                                  &allocated);
 968                         if (session_idx < 0) {
 969                                 r = session_idx;
 970                                 goto out;
 971                         }
 972                         break;
 973
 974                 case 0x01000001: /* create */
 975                         created |= 1 << session_idx;
 976                         if (destroyed & (1 << session_idx)) {
 977                                 destroyed &= ~(1 << session_idx);
 978                                 allocated |= 1 << session_idx;
 979
 980                         } else if (!(allocated & (1 << session_idx))) {
 981                                 DRM_ERROR("Handle already in use!\n");
 982                                 r = -EINVAL;
 983                                 goto out;
 984                         }
 985
 986                         break;
 987
 988                 case 0x02000001: /* destroy */
 989                         destroyed |= 1 << session_idx;
 990                         break;
 991
 992                 default:
 993                         break;
 994                 }
 995
 996                 if (session_idx == -1) {
 997                         DRM_ERROR("no session command at start of IB\n");
 998                         r = -EINVAL;
 999                         goto out;
1000                 }
1001
1002                 idx += len / 4;
1003         }
1004
1005         if (allocated & ~created) {
1006                 DRM_ERROR("New session without create command!\n");
1007                 r = -ENOENT;
1008         }
1009
1010 out:
1011         if (!r) {
1012                 /* No error, free all destroyed handle slots */
1013                 tmp = destroyed;
1014                 amdgpu_ib_free(p->adev, ib, NULL);
1015         } else {
1016                 /* Error during parsing, free all allocated handle slots */
1017                 tmp = allocated;
1018         }
1019
1020         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1021                 if (tmp & (1 << i))
1022                         atomic_set(&p->adev->vce.handles[i], 0);
1023
1024         return r;
1025 }
1026
1027 /**
1028  * amdgpu_vce_ring_emit_ib - execute indirect buffer
1029  *
1030  * @ring: engine to use
1031  * @ib: the IB to execute
1032  *
1033  */
1034 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
1035                              unsigned vmid, bool ctx_switch)
1036 {
1037         amdgpu_ring_write(ring, VCE_CMD_IB);
1038         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1039         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1040         amdgpu_ring_write(ring, ib->length_dw);
1041 }
1042
1043 /**
1044  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1045  *
1046  * @ring: engine to use
1047  * @fence: the fence
1048  *
1049  */
1050 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1051                                 unsigned flags)
1052 {
1053         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1054
1055         amdgpu_ring_write(ring, VCE_CMD_FENCE);
1056         amdgpu_ring_write(ring, addr);
1057         amdgpu_ring_write(ring, upper_32_bits(addr));
1058         amdgpu_ring_write(ring, seq);
1059         amdgpu_ring_write(ring, VCE_CMD_TRAP);
1060         amdgpu_ring_write(ring, VCE_CMD_END);
1061 }
1062
1063 /**
1064  * amdgpu_vce_ring_test_ring - test if VCE ring is working
1065  *
1066  * @ring: the engine to test on
1067  *
1068  */
1069 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1070 {
1071         struct amdgpu_device *adev = ring->adev;
1072         uint32_t rptr = amdgpu_ring_get_rptr(ring);
1073         unsigned i;
1074         int r, timeout = adev->usec_timeout;
1075
1076         /* skip ring test for sriov*/
1077         if (amdgpu_sriov_vf(adev))
1078                 return 0;
1079
1080         r = amdgpu_ring_alloc(ring, 16);
1081         if (r) {
1082                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
1083                           ring->idx, r);
1084                 return r;
1085         }
1086         amdgpu_ring_write(ring, VCE_CMD_END);
1087         amdgpu_ring_commit(ring);
1088
1089         for (i = 0; i < timeout; i++) {
1090                 if (amdgpu_ring_get_rptr(ring) != rptr)
1091                         break;
1092                 DRM_UDELAY(1);
1093         }
1094
1095         if (i < timeout) {
1096                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1097                          ring->idx, i);
1098         } else {
1099                 DRM_ERROR("amdgpu: ring %d test failed\n",
1100                           ring->idx);
1101                 r = -ETIMEDOUT;
1102         }
1103
1104         return r;
1105 }
1106
1107 /**
1108  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1109  *
1110  * @ring: the engine to test on
1111  *
1112  */
1113 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1114 {
1115         struct dma_fence *fence = NULL;
1116         long r;
1117
1118         /* skip vce ring1/2 ib test for now, since it's not reliable */
1119         if (ring != &ring->adev->vce.ring[0])
1120                 return 0;
1121
1122         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1123         if (r) {
1124                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1125                 goto error;
1126         }
1127
1128         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1129         if (r) {
1130                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1131                 goto error;
1132         }
1133
1134         r = dma_fence_wait_timeout(fence, false, timeout);
1135         if (r == 0) {
1136                 DRM_ERROR("amdgpu: IB test timed out.\n");
1137                 r = -ETIMEDOUT;
1138         } else if (r < 0) {
1139                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1140         } else {
1141                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1142                 r = 0;
1143         }
1144 error:
1145         dma_fence_put(fence);
1146         return r;
1147 }