drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34
  35 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  36 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  37 static int uvd_v6_0_start(struct amdgpu_device *adev);
  38 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  39
  40 /**
  41  * uvd_v6_0_ring_get_rptr - get read pointer
  42  *
  43  * @ring: amdgpu_ring pointer
  44  *
  45  * Returns the current hardware read pointer
  46  */
  47 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  48 {
  49         struct amdgpu_device *adev = ring->adev;
  50
  51         return RREG32(mmUVD_RBC_RB_RPTR);
  52 }
  53
  54 /**
  55  * uvd_v6_0_ring_get_wptr - get write pointer
  56  *
  57  * @ring: amdgpu_ring pointer
  58  *
  59  * Returns the current hardware write pointer
  60  */
  61 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  62 {
  63         struct amdgpu_device *adev = ring->adev;
  64
  65         return RREG32(mmUVD_RBC_RB_WPTR);
  66 }
  67
  68 /**
  69  * uvd_v6_0_ring_set_wptr - set write pointer
  70  *
  71  * @ring: amdgpu_ring pointer
  72  *
  73  * Commits the write pointer to the hardware
  74  */
  75 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  76 {
  77         struct amdgpu_device *adev = ring->adev;
  78
  79         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  80 }
  81
  82 static int uvd_v6_0_early_init(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         uvd_v6_0_set_ring_funcs(adev);
  87         uvd_v6_0_set_irq_funcs(adev);
  88
  89         return 0;
  90 }
  91
  92 static int uvd_v6_0_sw_init(void *handle)
  93 {
  94         struct amdgpu_ring *ring;
  95         int r;
  96         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  97
  98         /* UVD TRAP */
  99         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 100         if (r)
 101                 return r;
 102
 103         r = amdgpu_uvd_sw_init(adev);
 104         if (r)
 105                 return r;
 106
 107         r = amdgpu_uvd_resume(adev);
 108         if (r)
 109                 return r;
 110
 111         ring = &adev->uvd.ring;
 112         sprintf(ring->name, "uvd");
 113         r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
 114                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 115
 116         return r;
 117 }
 118
 119 static int uvd_v6_0_sw_fini(void *handle)
 120 {
 121         int r;
 122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 123
 124         r = amdgpu_uvd_suspend(adev);
 125         if (r)
 126                 return r;
 127
 128         r = amdgpu_uvd_sw_fini(adev);
 129         if (r)
 130                 return r;
 131
 132         return r;
 133 }
 134
 135 /**
 136  * uvd_v6_0_hw_init - start and test UVD block
 137  *
 138  * @adev: amdgpu_device pointer
 139  *
 140  * Initialize the hardware, boot up the VCPU and do some testing
 141  */
 142 static int uvd_v6_0_hw_init(void *handle)
 143 {
 144         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 145         struct amdgpu_ring *ring = &adev->uvd.ring;
 146         uint32_t tmp;
 147         int r;
 148
 149         r = uvd_v6_0_start(adev);
 150         if (r)
 151                 goto done;
 152
 153         ring->ready = true;
 154         r = amdgpu_ring_test_ring(ring);
 155         if (r) {
 156                 ring->ready = false;
 157                 goto done;
 158         }
 159
 160         r = amdgpu_ring_alloc(ring, 10);
 161         if (r) {
 162                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 163                 goto done;
 164         }
 165
 166         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 167         amdgpu_ring_write(ring, tmp);
 168         amdgpu_ring_write(ring, 0xFFFFF);
 169
 170         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 171         amdgpu_ring_write(ring, tmp);
 172         amdgpu_ring_write(ring, 0xFFFFF);
 173
 174         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 175         amdgpu_ring_write(ring, tmp);
 176         amdgpu_ring_write(ring, 0xFFFFF);
 177
 178         /* Clear timeout status bits */
 179         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 180         amdgpu_ring_write(ring, 0x8);
 181
 182         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 183         amdgpu_ring_write(ring, 3);
 184
 185         amdgpu_ring_commit(ring);
 186
 187 done:
 188         if (!r)
 189                 DRM_INFO("UVD initialized successfully.\n");
 190
 191         return r;
 192 }
 193
 194 /**
 195  * uvd_v6_0_hw_fini - stop the hardware block
 196  *
 197  * @adev: amdgpu_device pointer
 198  *
 199  * Stop the UVD block, mark ring as not ready any more
 200  */
 201 static int uvd_v6_0_hw_fini(void *handle)
 202 {
 203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 204         struct amdgpu_ring *ring = &adev->uvd.ring;
 205
 206         uvd_v6_0_stop(adev);
 207         ring->ready = false;
 208
 209         return 0;
 210 }
 211
 212 static int uvd_v6_0_suspend(void *handle)
 213 {
 214         int r;
 215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 216
 217         r = uvd_v6_0_hw_fini(adev);
 218         if (r)
 219                 return r;
 220
 221         /* Skip this for APU for now */
 222         if (!(adev->flags & AMD_IS_APU)) {
 223                 r = amdgpu_uvd_suspend(adev);
 224                 if (r)
 225                         return r;
 226         }
 227
 228         return r;
 229 }
 230
 231 static int uvd_v6_0_resume(void *handle)
 232 {
 233         int r;
 234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 235
 236         /* Skip this for APU for now */
 237         if (!(adev->flags & AMD_IS_APU)) {
 238                 r = amdgpu_uvd_resume(adev);
 239                 if (r)
 240                         return r;
 241         }
 242         r = uvd_v6_0_hw_init(adev);
 243         if (r)
 244                 return r;
 245
 246         return r;
 247 }
 248
 249 /**
 250  * uvd_v6_0_mc_resume - memory controller programming
 251  *
 252  * @adev: amdgpu_device pointer
 253  *
 254  * Let the UVD memory controller know it's offsets
 255  */
 256 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 257 {
 258         uint64_t offset;
 259         uint32_t size;
 260
 261         /* programm memory controller bits 0-27 */
 262         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 263                         lower_32_bits(adev->uvd.gpu_addr));
 264         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 265                         upper_32_bits(adev->uvd.gpu_addr));
 266
 267         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 268         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 269         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 270         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 271
 272         offset += size;
 273         size = AMDGPU_UVD_STACK_SIZE;
 274         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 275         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 276
 277         offset += size;
 278         size = AMDGPU_UVD_HEAP_SIZE;
 279         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 280         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 281
 282         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 283         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 284         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 285 }
 286
 287 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 288                 bool enable)
 289 {
 290         u32 data, data1;
 291
 292         data = RREG32(mmUVD_CGC_GATE);
 293         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 294         if (enable) {
 295                 data |= UVD_CGC_GATE__SYS_MASK |
 296                                 UVD_CGC_GATE__UDEC_MASK |
 297                                 UVD_CGC_GATE__MPEG2_MASK |
 298                                 UVD_CGC_GATE__RBC_MASK |
 299                                 UVD_CGC_GATE__LMI_MC_MASK |
 300                                 UVD_CGC_GATE__IDCT_MASK |
 301                                 UVD_CGC_GATE__MPRD_MASK |
 302                                 UVD_CGC_GATE__MPC_MASK |
 303                                 UVD_CGC_GATE__LBSI_MASK |
 304                                 UVD_CGC_GATE__LRBBM_MASK |
 305                                 UVD_CGC_GATE__UDEC_RE_MASK |
 306                                 UVD_CGC_GATE__UDEC_CM_MASK |
 307                                 UVD_CGC_GATE__UDEC_IT_MASK |
 308                                 UVD_CGC_GATE__UDEC_DB_MASK |
 309                                 UVD_CGC_GATE__UDEC_MP_MASK |
 310                                 UVD_CGC_GATE__WCB_MASK |
 311                                 UVD_CGC_GATE__VCPU_MASK |
 312                                 UVD_CGC_GATE__SCPU_MASK;
 313                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 314                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 315                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 316                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 317                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 318                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 319                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 320                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 321                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 322                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 323                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 324                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 325                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 326         } else {
 327                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 328                                 UVD_CGC_GATE__UDEC_MASK |
 329                                 UVD_CGC_GATE__MPEG2_MASK |
 330                                 UVD_CGC_GATE__RBC_MASK |
 331                                 UVD_CGC_GATE__LMI_MC_MASK |
 332                                 UVD_CGC_GATE__LMI_UMC_MASK |
 333                                 UVD_CGC_GATE__IDCT_MASK |
 334                                 UVD_CGC_GATE__MPRD_MASK |
 335                                 UVD_CGC_GATE__MPC_MASK |
 336                                 UVD_CGC_GATE__LBSI_MASK |
 337                                 UVD_CGC_GATE__LRBBM_MASK |
 338                                 UVD_CGC_GATE__UDEC_RE_MASK |
 339                                 UVD_CGC_GATE__UDEC_CM_MASK |
 340                                 UVD_CGC_GATE__UDEC_IT_MASK |
 341                                 UVD_CGC_GATE__UDEC_DB_MASK |
 342                                 UVD_CGC_GATE__UDEC_MP_MASK |
 343                                 UVD_CGC_GATE__WCB_MASK |
 344                                 UVD_CGC_GATE__VCPU_MASK |
 345                                 UVD_CGC_GATE__SCPU_MASK);
 346                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 347                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 348                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 349                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 350                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 351                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 352                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 353                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 354                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 355                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 356                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 357                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 358                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 359         }
 360         WREG32(mmUVD_CGC_GATE, data);
 361         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 362 }
 363
 364 static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 365                 bool enable)
 366 {
 367         u32 data, data1;
 368
 369         data = RREG32(mmUVD_CGC_GATE);
 370         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 371         if (enable) {
 372                 data |= UVD_CGC_GATE__SYS_MASK |
 373                                 UVD_CGC_GATE__UDEC_MASK |
 374                                 UVD_CGC_GATE__MPEG2_MASK |
 375                                 UVD_CGC_GATE__RBC_MASK |
 376                                 UVD_CGC_GATE__LMI_MC_MASK |
 377                                 UVD_CGC_GATE__IDCT_MASK |
 378                                 UVD_CGC_GATE__MPRD_MASK |
 379                                 UVD_CGC_GATE__MPC_MASK |
 380                                 UVD_CGC_GATE__LBSI_MASK |
 381                                 UVD_CGC_GATE__LRBBM_MASK |
 382                                 UVD_CGC_GATE__UDEC_RE_MASK |
 383                                 UVD_CGC_GATE__UDEC_CM_MASK |
 384                                 UVD_CGC_GATE__UDEC_IT_MASK |
 385                                 UVD_CGC_GATE__UDEC_DB_MASK |
 386                                 UVD_CGC_GATE__UDEC_MP_MASK |
 387                                 UVD_CGC_GATE__WCB_MASK |
 388                                 UVD_CGC_GATE__VCPU_MASK |
 389                                 UVD_CGC_GATE__SCPU_MASK;
 390                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 391                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 392                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 393                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 394                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 395         } else {
 396                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 397                                 UVD_CGC_GATE__UDEC_MASK |
 398                                 UVD_CGC_GATE__MPEG2_MASK |
 399                                 UVD_CGC_GATE__RBC_MASK |
 400                                 UVD_CGC_GATE__LMI_MC_MASK |
 401                                 UVD_CGC_GATE__LMI_UMC_MASK |
 402                                 UVD_CGC_GATE__IDCT_MASK |
 403                                 UVD_CGC_GATE__MPRD_MASK |
 404                                 UVD_CGC_GATE__MPC_MASK |
 405                                 UVD_CGC_GATE__LBSI_MASK |
 406                                 UVD_CGC_GATE__LRBBM_MASK |
 407                                 UVD_CGC_GATE__UDEC_RE_MASK |
 408                                 UVD_CGC_GATE__UDEC_CM_MASK |
 409                                 UVD_CGC_GATE__UDEC_IT_MASK |
 410                                 UVD_CGC_GATE__UDEC_DB_MASK |
 411                                 UVD_CGC_GATE__UDEC_MP_MASK |
 412                                 UVD_CGC_GATE__WCB_MASK |
 413                                 UVD_CGC_GATE__VCPU_MASK |
 414                                 UVD_CGC_GATE__SCPU_MASK);
 415                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 416                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 417                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 418                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 419                                 UVD_SUVD_CGC_GATE__SDB_MASK);
 420         }
 421         WREG32(mmUVD_CGC_GATE, data);
 422         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 423 }
 424
 425 static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev,
 426                 bool swmode)
 427 {
 428         u32 data, data1 = 0, data2;
 429
 430         /* Always un-gate UVD REGS bit */
 431         data = RREG32(mmUVD_CGC_GATE);
 432         data &= ~(UVD_CGC_GATE__REGS_MASK);
 433         WREG32(mmUVD_CGC_GATE, data);
 434
 435         data = RREG32(mmUVD_CGC_CTRL);
 436         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 437                         UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 438         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 439                         1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) |
 440                         4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY);
 441
 442         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 443         if (swmode) {
 444                 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 445                                 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 446                                 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 447                                 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 448                                 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 449                                 UVD_CGC_CTRL__SYS_MODE_MASK |
 450                                 UVD_CGC_CTRL__UDEC_MODE_MASK |
 451                                 UVD_CGC_CTRL__MPEG2_MODE_MASK |
 452                                 UVD_CGC_CTRL__REGS_MODE_MASK |
 453                                 UVD_CGC_CTRL__RBC_MODE_MASK |
 454                                 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 455                                 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 456                                 UVD_CGC_CTRL__IDCT_MODE_MASK |
 457                                 UVD_CGC_CTRL__MPRD_MODE_MASK |
 458                                 UVD_CGC_CTRL__MPC_MODE_MASK |
 459                                 UVD_CGC_CTRL__LBSI_MODE_MASK |
 460                                 UVD_CGC_CTRL__LRBBM_MODE_MASK |
 461                                 UVD_CGC_CTRL__WCB_MODE_MASK |
 462                                 UVD_CGC_CTRL__VCPU_MODE_MASK |
 463                                 UVD_CGC_CTRL__JPEG_MODE_MASK |
 464                                 UVD_CGC_CTRL__SCPU_MODE_MASK);
 465                 data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
 466                                 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK;
 467                 data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK;
 468                 data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID);
 469                 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 470                                 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 471                                 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 472                                 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 473                                 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 474         } else {
 475                 data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 476                                 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 477                                 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 478                                 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 479                                 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 480                                 UVD_CGC_CTRL__SYS_MODE_MASK |
 481                                 UVD_CGC_CTRL__UDEC_MODE_MASK |
 482                                 UVD_CGC_CTRL__MPEG2_MODE_MASK |
 483                                 UVD_CGC_CTRL__REGS_MODE_MASK |
 484                                 UVD_CGC_CTRL__RBC_MODE_MASK |
 485                                 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 486                                 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 487                                 UVD_CGC_CTRL__IDCT_MODE_MASK |
 488                                 UVD_CGC_CTRL__MPRD_MODE_MASK |
 489                                 UVD_CGC_CTRL__MPC_MODE_MASK |
 490                                 UVD_CGC_CTRL__LBSI_MODE_MASK |
 491                                 UVD_CGC_CTRL__LRBBM_MODE_MASK |
 492                                 UVD_CGC_CTRL__WCB_MODE_MASK |
 493                                 UVD_CGC_CTRL__VCPU_MODE_MASK |
 494                                 UVD_CGC_CTRL__SCPU_MODE_MASK;
 495                 data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 496                                 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 497                                 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 498                                 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 499                                 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK;
 500         }
 501         WREG32(mmUVD_CGC_CTRL, data);
 502         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 503
 504         data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2);
 505         data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
 506                         REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
 507                         REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
 508         data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
 509                         REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
 510                         REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
 511         data |= data1;
 512         WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data);
 513 }
 514
 515 /**
 516  * uvd_v6_0_start - start UVD block
 517  *
 518  * @adev: amdgpu_device pointer
 519  *
 520  * Setup and start the UVD block
 521  */
 522 static int uvd_v6_0_start(struct amdgpu_device *adev)
 523 {
 524         struct amdgpu_ring *ring = &adev->uvd.ring;
 525         uint32_t rb_bufsz, tmp;
 526         uint32_t lmi_swap_cntl;
 527         uint32_t mp_swap_cntl;
 528         int i, j, r;
 529
 530         /*disable DPG */
 531         WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
 532
 533         /* disable byte swapping */
 534         lmi_swap_cntl = 0;
 535         mp_swap_cntl = 0;
 536
 537         uvd_v6_0_mc_resume(adev);
 538
 539         /* Set dynamic clock gating in S/W control mode */
 540         if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
 541                 if (adev->flags & AMD_IS_APU)
 542                         cz_set_uvd_clock_gating_branches(adev, false);
 543                 else
 544                         tonga_set_uvd_clock_gating_branches(adev, false);
 545                 uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
 546         } else {
 547                 /* disable clock gating */
 548                 uint32_t data = RREG32(mmUVD_CGC_CTRL);
 549                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 550                 WREG32(mmUVD_CGC_CTRL, data);
 551         }
 552
 553         /* disable interupt */
 554         WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
 555
 556         /* stall UMC and register bus before resetting VCPU */
 557         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 558         mdelay(1);
 559
 560         /* put LMI, VCPU, RBC etc... into reset */
 561         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 562                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 563                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 564                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 565                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 566         mdelay(5);
 567
 568         /* take UVD block out of reset */
 569         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 570         mdelay(5);
 571
 572         /* initialize UVD memory controller */
 573         WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
 574                              (1 << 21) | (1 << 9) | (1 << 20));
 575
 576 #ifdef __BIG_ENDIAN
 577         /* swap (8 in 32) RB and IB */
 578         lmi_swap_cntl = 0xa;
 579         mp_swap_cntl = 0;
 580 #endif
 581         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 582         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 583
 584         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 585         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 586         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 587         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 588         WREG32(mmUVD_MPC_SET_ALU, 0);
 589         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 590
 591         /* take all subblocks out of reset, except VCPU */
 592         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 593         mdelay(5);
 594
 595         /* enable VCPU clock */
 596         WREG32(mmUVD_VCPU_CNTL,  1 << 9);
 597
 598         /* enable UMC */
 599         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 600
 601         /* boot up the VCPU */
 602         WREG32(mmUVD_SOFT_RESET, 0);
 603         mdelay(10);
 604
 605         for (i = 0; i < 10; ++i) {
 606                 uint32_t status;
 607
 608                 for (j = 0; j < 100; ++j) {
 609                         status = RREG32(mmUVD_STATUS);
 610                         if (status & 2)
 611                                 break;
 612                         mdelay(10);
 613                 }
 614                 r = 0;
 615                 if (status & 2)
 616                         break;
 617
 618                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 619                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 620                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 621                 mdelay(10);
 622                 WREG32_P(mmUVD_SOFT_RESET, 0,
 623                          ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 624                 mdelay(10);
 625                 r = -1;
 626         }
 627
 628         if (r) {
 629                 DRM_ERROR("UVD not responding, giving up!!!\n");
 630                 return r;
 631         }
 632         /* enable master interrupt */
 633         WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
 634
 635         /* clear the bit 4 of UVD_STATUS */
 636         WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
 637
 638         rb_bufsz = order_base_2(ring->ring_size);
 639         tmp = 0;
 640         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 641         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 642         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 643         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 644         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 645         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 646         /* force RBC into idle state */
 647         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 648
 649         /* set the write pointer delay */
 650         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 651
 652         /* set the wb address */
 653         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 654
 655         /* programm the RB_BASE for ring buffer */
 656         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 657                         lower_32_bits(ring->gpu_addr));
 658         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 659                         upper_32_bits(ring->gpu_addr));
 660
 661         /* Initialize the ring buffer's read and write pointers */
 662         WREG32(mmUVD_RBC_RB_RPTR, 0);
 663
 664         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 665         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 666
 667         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * uvd_v6_0_stop - stop UVD block
 674  *
 675  * @adev: amdgpu_device pointer
 676  *
 677  * stop the UVD block
 678  */
 679 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 680 {
 681         /* force RBC into idle state */
 682         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 683
 684         /* Stall UMC and register bus before resetting VCPU */
 685         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 686         mdelay(1);
 687
 688         /* put VCPU into reset */
 689         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 690         mdelay(5);
 691
 692         /* disable VCPU clock */
 693         WREG32(mmUVD_VCPU_CNTL, 0x0);
 694
 695         /* Unstall UMC and register bus */
 696         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 697 }
 698
 699 /**
 700  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 701  *
 702  * @ring: amdgpu_ring pointer
 703  * @fence: fence to emit
 704  *
 705  * Write a fence and a trap command to the ring.
 706  */
 707 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 708                                      unsigned flags)
 709 {
 710         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 711
 712         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 713         amdgpu_ring_write(ring, seq);
 714         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 715         amdgpu_ring_write(ring, addr & 0xffffffff);
 716         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 717         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 718         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 719         amdgpu_ring_write(ring, 0);
 720
 721         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 722         amdgpu_ring_write(ring, 0);
 723         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 724         amdgpu_ring_write(ring, 0);
 725         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 726         amdgpu_ring_write(ring, 2);
 727 }
 728
 729 /**
 730  * uvd_v6_0_ring_test_ring - register write test
 731  *
 732  * @ring: amdgpu_ring pointer
 733  *
 734  * Test if we can successfully write to the context register
 735  */
 736 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 737 {
 738         struct amdgpu_device *adev = ring->adev;
 739         uint32_t tmp = 0;
 740         unsigned i;
 741         int r;
 742
 743         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 744         r = amdgpu_ring_alloc(ring, 3);
 745         if (r) {
 746                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 747                           ring->idx, r);
 748                 return r;
 749         }
 750         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 751         amdgpu_ring_write(ring, 0xDEADBEEF);
 752         amdgpu_ring_commit(ring);
 753         for (i = 0; i < adev->usec_timeout; i++) {
 754                 tmp = RREG32(mmUVD_CONTEXT_ID);
 755                 if (tmp == 0xDEADBEEF)
 756                         break;
 757                 DRM_UDELAY(1);
 758         }
 759
 760         if (i < adev->usec_timeout) {
 761                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 762                          ring->idx, i);
 763         } else {
 764                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 765                           ring->idx, tmp);
 766                 r = -EINVAL;
 767         }
 768         return r;
 769 }
 770
 771 /**
 772  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 773  *
 774  * @ring: amdgpu_ring pointer
 775  * @ib: indirect buffer to execute
 776  *
 777  * Write ring commands to execute the indirect buffer
 778  */
 779 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 780                                   struct amdgpu_ib *ib)
 781 {
 782         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 783         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 784         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 785         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 786         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 787         amdgpu_ring_write(ring, ib->length_dw);
 788 }
 789
 790 /**
 791  * uvd_v6_0_ring_test_ib - test ib execution
 792  *
 793  * @ring: amdgpu_ring pointer
 794  *
 795  * Test if we can successfully execute an IB
 796  */
 797 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring)
 798 {
 799         struct fence *fence = NULL;
 800         int r;
 801
 802         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
 803         if (r) {
 804                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 805                 goto error;
 806         }
 807
 808         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
 809         if (r) {
 810                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 811                 goto error;
 812         }
 813
 814         r = fence_wait(fence, false);
 815         if (r) {
 816                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 817                 goto error;
 818         }
 819         DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
 820 error:
 821         fence_put(fence);
 822         return r;
 823 }
 824
 825 static bool uvd_v6_0_is_idle(void *handle)
 826 {
 827         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 828
 829         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 830 }
 831
 832 static int uvd_v6_0_wait_for_idle(void *handle)
 833 {
 834         unsigned i;
 835         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 836
 837         for (i = 0; i < adev->usec_timeout; i++) {
 838                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 839                         return 0;
 840         }
 841         return -ETIMEDOUT;
 842 }
 843
 844 static int uvd_v6_0_soft_reset(void *handle)
 845 {
 846         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 847
 848         uvd_v6_0_stop(adev);
 849
 850         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 851                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 852         mdelay(5);
 853
 854         return uvd_v6_0_start(adev);
 855 }
 856
 857 static void uvd_v6_0_print_status(void *handle)
 858 {
 859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 860         dev_info(adev->dev, "UVD 6.0 registers\n");
 861         dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
 862                  RREG32(mmUVD_SEMA_ADDR_LOW));
 863         dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
 864                  RREG32(mmUVD_SEMA_ADDR_HIGH));
 865         dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
 866                  RREG32(mmUVD_SEMA_CMD));
 867         dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
 868                  RREG32(mmUVD_GPCOM_VCPU_CMD));
 869         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
 870                  RREG32(mmUVD_GPCOM_VCPU_DATA0));
 871         dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
 872                  RREG32(mmUVD_GPCOM_VCPU_DATA1));
 873         dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
 874                  RREG32(mmUVD_ENGINE_CNTL));
 875         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
 876                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
 877         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
 878                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
 879         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
 880                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
 881         dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
 882                  RREG32(mmUVD_SEMA_CNTL));
 883         dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
 884                  RREG32(mmUVD_LMI_EXT40_ADDR));
 885         dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
 886                  RREG32(mmUVD_CTX_INDEX));
 887         dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
 888                  RREG32(mmUVD_CTX_DATA));
 889         dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
 890                  RREG32(mmUVD_CGC_GATE));
 891         dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
 892                  RREG32(mmUVD_CGC_CTRL));
 893         dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
 894                  RREG32(mmUVD_LMI_CTRL2));
 895         dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
 896                  RREG32(mmUVD_MASTINT_EN));
 897         dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
 898                  RREG32(mmUVD_LMI_ADDR_EXT));
 899         dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
 900                  RREG32(mmUVD_LMI_CTRL));
 901         dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
 902                  RREG32(mmUVD_LMI_SWAP_CNTL));
 903         dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
 904                  RREG32(mmUVD_MP_SWAP_CNTL));
 905         dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
 906                  RREG32(mmUVD_MPC_SET_MUXA0));
 907         dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
 908                  RREG32(mmUVD_MPC_SET_MUXA1));
 909         dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
 910                  RREG32(mmUVD_MPC_SET_MUXB0));
 911         dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
 912                  RREG32(mmUVD_MPC_SET_MUXB1));
 913         dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
 914                  RREG32(mmUVD_MPC_SET_MUX));
 915         dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
 916                  RREG32(mmUVD_MPC_SET_ALU));
 917         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
 918                  RREG32(mmUVD_VCPU_CACHE_OFFSET0));
 919         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
 920                  RREG32(mmUVD_VCPU_CACHE_SIZE0));
 921         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
 922                  RREG32(mmUVD_VCPU_CACHE_OFFSET1));
 923         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
 924                  RREG32(mmUVD_VCPU_CACHE_SIZE1));
 925         dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
 926                  RREG32(mmUVD_VCPU_CACHE_OFFSET2));
 927         dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
 928                  RREG32(mmUVD_VCPU_CACHE_SIZE2));
 929         dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
 930                  RREG32(mmUVD_VCPU_CNTL));
 931         dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
 932                  RREG32(mmUVD_SOFT_RESET));
 933         dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
 934                  RREG32(mmUVD_RBC_IB_SIZE));
 935         dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
 936                  RREG32(mmUVD_RBC_RB_RPTR));
 937         dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
 938                  RREG32(mmUVD_RBC_RB_WPTR));
 939         dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
 940                  RREG32(mmUVD_RBC_RB_WPTR_CNTL));
 941         dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
 942                  RREG32(mmUVD_RBC_RB_CNTL));
 943         dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
 944                  RREG32(mmUVD_STATUS));
 945         dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
 946                  RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
 947         dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 948                  RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
 949         dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
 950                  RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
 951         dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
 952                  RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
 953         dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
 954                  RREG32(mmUVD_CONTEXT_ID));
 955         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
 956                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
 957         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
 958                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
 959         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
 960                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
 961 }
 962
 963 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 964                                         struct amdgpu_irq_src *source,
 965                                         unsigned type,
 966                                         enum amdgpu_interrupt_state state)
 967 {
 968         // TODO
 969         return 0;
 970 }
 971
 972 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 973                                       struct amdgpu_irq_src *source,
 974                                       struct amdgpu_iv_entry *entry)
 975 {
 976         DRM_DEBUG("IH: UVD TRAP\n");
 977         amdgpu_fence_process(&adev->uvd.ring);
 978         return 0;
 979 }
 980
 981 static int uvd_v6_0_set_clockgating_state(void *handle,
 982                                           enum amd_clockgating_state state)
 983 {
 984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 985         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 986
 987         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 988                 return 0;
 989
 990         if (enable) {
 991                 if (adev->flags & AMD_IS_APU)
 992                         cz_set_uvd_clock_gating_branches(adev, enable);
 993                 else
 994                         tonga_set_uvd_clock_gating_branches(adev, enable);
 995                 uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
 996         } else {
 997                 uint32_t data = RREG32(mmUVD_CGC_CTRL);
 998                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 999                 WREG32(mmUVD_CGC_CTRL, data);
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int uvd_v6_0_set_powergating_state(void *handle,
1006                                           enum amd_powergating_state state)
1007 {
1008         /* This doesn't actually powergate the UVD block.
1009          * That's done in the dpm code via the SMC.  This
1010          * just re-inits the block as necessary.  The actual
1011          * gating still happens in the dpm code.  We should
1012          * revisit this when there is a cleaner line between
1013          * the smc and the hw blocks
1014          */
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1018                 return 0;
1019
1020         if (state == AMD_PG_STATE_GATE) {
1021                 uvd_v6_0_stop(adev);
1022                 return 0;
1023         } else {
1024                 return uvd_v6_0_start(adev);
1025         }
1026 }
1027
1028 const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1029         .early_init = uvd_v6_0_early_init,
1030         .late_init = NULL,
1031         .sw_init = uvd_v6_0_sw_init,
1032         .sw_fini = uvd_v6_0_sw_fini,
1033         .hw_init = uvd_v6_0_hw_init,
1034         .hw_fini = uvd_v6_0_hw_fini,
1035         .suspend = uvd_v6_0_suspend,
1036         .resume = uvd_v6_0_resume,
1037         .is_idle = uvd_v6_0_is_idle,
1038         .wait_for_idle = uvd_v6_0_wait_for_idle,
1039         .soft_reset = uvd_v6_0_soft_reset,
1040         .print_status = uvd_v6_0_print_status,
1041         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1042         .set_powergating_state = uvd_v6_0_set_powergating_state,
1043 };
1044
1045 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
1046         .get_rptr = uvd_v6_0_ring_get_rptr,
1047         .get_wptr = uvd_v6_0_ring_get_wptr,
1048         .set_wptr = uvd_v6_0_ring_set_wptr,
1049         .parse_cs = amdgpu_uvd_ring_parse_cs,
1050         .emit_ib = uvd_v6_0_ring_emit_ib,
1051         .emit_fence = uvd_v6_0_ring_emit_fence,
1052         .test_ring = uvd_v6_0_ring_test_ring,
1053         .test_ib = uvd_v6_0_ring_test_ib,
1054         .insert_nop = amdgpu_ring_insert_nop,
1055         .pad_ib = amdgpu_ring_generic_pad_ib,
1056 };
1057
1058 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1059 {
1060         adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs;
1061 }
1062
1063 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1064         .set = uvd_v6_0_set_interrupt_state,
1065         .process = uvd_v6_0_process_interrupt,
1066 };
1067
1068 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1069 {
1070         adev->uvd.irq.num_types = 1;
1071         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1072 }