arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <[email protected]>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <[email protected]>
  15  *         Juha Yrjölä <[email protected]>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/sched_clock.h>
  45
  46 #include <asm/mach/time.h>
  47
  48 #include "omap_hwmod.h"
  49 #include "omap_device.h"
  50 #include <plat/counter-32k.h>
  51 #include <clocksource/timer-ti-dm.h>
  52
  53 #include "soc.h"
  54 #include "common.h"
  55 #include "control.h"
  56 #include "powerdomain.h"
  57 #include "omap-secure.h"
  58
  59 #define REALTIME_COUNTER_BASE                           0x48243200
  60 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  61 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  62 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  63
  64 /* Clockevent code */
  65
  66 static struct omap_dm_timer clkev;
  67 static struct clock_event_device clockevent_gpt;
  68
  69 /* Clockevent hwmod for am335x and am437x suspend */
  70 static struct omap_hwmod *clockevent_gpt_hwmod;
  71
  72 /* Clockesource hwmod for am437x suspend */
  73 static struct omap_hwmod *clocksource_gpt_hwmod;
  74
  75 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
  76 static unsigned long arch_timer_freq;
  77
  78 void set_cntfreq(void)
  79 {
  80         omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
  81 }
  82 #endif
  83
  84 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  85 {
  86         struct clock_event_device *evt = &clockevent_gpt;
  87
  88         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  89
  90         evt->event_handler(evt);
  91         return IRQ_HANDLED;
  92 }
  93
  94 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  95                                          struct clock_event_device *evt)
  96 {
  97         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
  98                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
  99
 100         return 0;
 101 }
 102
 103 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
 104 {
 105         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 106         return 0;
 107 }
 108
 109 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
 110 {
 111         u32 period;
 112
 113         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 114
 115         period = clkev.rate / HZ;
 116         period -= 1;
 117         /* Looks like we need to first set the load value separately */
 118         __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
 119                               OMAP_TIMER_POSTED);
 120         __omap_dm_timer_load_start(&clkev,
 121                                    OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 122                                    0xffffffff - period, OMAP_TIMER_POSTED);
 123         return 0;
 124 }
 125
 126 static void omap_clkevt_idle(struct clock_event_device *unused)
 127 {
 128         if (!clockevent_gpt_hwmod)
 129                 return;
 130
 131         omap_hwmod_idle(clockevent_gpt_hwmod);
 132 }
 133
 134 static void omap_clkevt_unidle(struct clock_event_device *unused)
 135 {
 136         if (!clockevent_gpt_hwmod)
 137                 return;
 138
 139         omap_hwmod_enable(clockevent_gpt_hwmod);
 140         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 141 }
 142
 143 static struct clock_event_device clockevent_gpt = {
 144         .features               = CLOCK_EVT_FEAT_PERIODIC |
 145                                   CLOCK_EVT_FEAT_ONESHOT,
 146         .rating                 = 300,
 147         .set_next_event         = omap2_gp_timer_set_next_event,
 148         .set_state_shutdown     = omap2_gp_timer_shutdown,
 149         .set_state_periodic     = omap2_gp_timer_set_periodic,
 150         .set_state_oneshot      = omap2_gp_timer_shutdown,
 151         .tick_resume            = omap2_gp_timer_shutdown,
 152 };
 153
 154 static const struct of_device_id omap_timer_match[] __initconst = {
 155         { .compatible = "ti,omap2420-timer", },
 156         { .compatible = "ti,omap3430-timer", },
 157         { .compatible = "ti,omap4430-timer", },
 158         { .compatible = "ti,omap5430-timer", },
 159         { .compatible = "ti,dm814-timer", },
 160         { .compatible = "ti,dm816-timer", },
 161         { .compatible = "ti,am335x-timer", },
 162         { .compatible = "ti,am335x-timer-1ms", },
 163         { }
 164 };
 165
 166 static int omap_timer_add_disabled_property(struct device_node *np)
 167 {
 168         struct property *prop;
 169
 170         prop = kzalloc(sizeof(*prop), GFP_KERNEL);
 171         if (!prop)
 172                 return -ENOMEM;
 173
 174         prop->name = "status";
 175         prop->value = "disabled";
 176         prop->length = strlen(prop->value);
 177
 178         return of_add_property(np, prop);
 179 }
 180
 181 static int omap_timer_update_dt(struct device_node *np)
 182 {
 183         int error = 0;
 184
 185         if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
 186                 error = omap_timer_add_disabled_property(np);
 187                 if (error)
 188                         return error;
 189         }
 190
 191         /* No parent interconnect target module configured? */
 192         if (of_get_property(np, "ti,hwmods", NULL))
 193                 return error;
 194
 195         /* Tag parent interconnect target module disabled */
 196         error = omap_timer_add_disabled_property(np->parent);
 197         if (error)
 198                 return error;
 199
 200         return 0;
 201 }
 202
 203 /**
 204  * omap_get_timer_dt - get a timer using device-tree
 205  * @match       - device-tree match structure for matching a device type
 206  * @property    - optional timer property to match
 207  *
 208  * Helper function to get a timer during early boot using device-tree for use
 209  * as kernel system timer. Optionally, the property argument can be used to
 210  * select a timer with a specific property. Once a timer is found then mark
 211  * the timer node in device-tree as disabled, to prevent the kernel from
 212  * registering this timer as a platform device and so no one else can use it.
 213  */
 214 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 215                                                      const char *property)
 216 {
 217         struct device_node *np;
 218         int error;
 219
 220         for_each_matching_node(np, match) {
 221                 if (!of_device_is_available(np))
 222                         continue;
 223
 224                 if (property && !of_get_property(np, property, NULL))
 225                         continue;
 226
 227                 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 228                                   of_get_property(np, "ti,timer-dsp", NULL) ||
 229                                   of_get_property(np, "ti,timer-pwm", NULL) ||
 230                                   of_get_property(np, "ti,timer-secure", NULL)))
 231                         continue;
 232
 233                 error = omap_timer_update_dt(np);
 234                 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
 235
 236                 return np;
 237         }
 238
 239         return NULL;
 240 }
 241
 242 /**
 243  * omap_dmtimer_init - initialisation function when device tree is used
 244  *
 245  * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
 246  * cannot be used by the kernel as they are reserved. Therefore, to prevent the
 247  * kernel registering these devices remove them dynamically from the device
 248  * tree on boot.
 249  */
 250 static void __init omap_dmtimer_init(void)
 251 {
 252         struct device_node *np;
 253
 254         if (!cpu_is_omap34xx() && !soc_is_dra7xx())
 255                 return;
 256
 257         /* If we are a secure device, remove any secure timer nodes */
 258         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 259                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 260                 of_node_put(np);
 261         }
 262 }
 263
 264 /**
 265  * omap_dm_timer_get_errata - get errata flags for a timer
 266  *
 267  * Get the timer errata flags that are specific to the OMAP device being used.
 268  */
 269 static u32 __init omap_dm_timer_get_errata(void)
 270 {
 271         if (cpu_is_omap24xx())
 272                 return 0;
 273
 274         return OMAP_TIMER_ERRATA_I103_I767;
 275 }
 276
 277 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 278                                          const char *fck_source,
 279                                          const char *property,
 280                                          const char **timer_name,
 281                                          int posted)
 282 {
 283         const char *oh_name = NULL;
 284         struct device_node *np;
 285         struct omap_hwmod *oh;
 286         struct clk *src;
 287         int r = 0;
 288
 289         np = omap_get_timer_dt(omap_timer_match, property);
 290         if (!np)
 291                 return -ENODEV;
 292
 293         of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 294         if (!oh_name) {
 295                 of_property_read_string_index(np->parent, "ti,hwmods", 0,
 296                                               &oh_name);
 297                 if (!oh_name)
 298                         return -ENODEV;
 299         }
 300
 301         timer->irq = irq_of_parse_and_map(np, 0);
 302         if (!timer->irq)
 303                 return -ENXIO;
 304
 305         timer->io_base = of_iomap(np, 0);
 306
 307         timer->fclk = of_clk_get_by_name(np, "fck");
 308
 309         of_node_put(np);
 310
 311         oh = omap_hwmod_lookup(oh_name);
 312         if (!oh)
 313                 return -ENODEV;
 314
 315         *timer_name = oh->name;
 316
 317         if (!timer->io_base)
 318                 return -ENXIO;
 319
 320         omap_hwmod_setup_one(oh_name);
 321
 322         /* After the dmtimer is using hwmod these clocks won't be needed */
 323         if (IS_ERR_OR_NULL(timer->fclk))
 324                 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 325         if (IS_ERR(timer->fclk))
 326                 return PTR_ERR(timer->fclk);
 327
 328         src = clk_get(NULL, fck_source);
 329         if (IS_ERR(src))
 330                 return PTR_ERR(src);
 331
 332         WARN(clk_set_parent(timer->fclk, src) < 0,
 333              "Cannot set timer parent clock, no PLL clock driver?");
 334
 335         clk_put(src);
 336
 337         omap_hwmod_enable(oh);
 338         __omap_dm_timer_init_regs(timer);
 339
 340         if (posted)
 341                 __omap_dm_timer_enable_posted(timer);
 342
 343         /* Check that the intended posted configuration matches the actual */
 344         if (posted != timer->posted)
 345                 return -EINVAL;
 346
 347         timer->rate = clk_get_rate(timer->fclk);
 348         timer->reserved = 1;
 349
 350         return r;
 351 }
 352
 353 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
 354 void tick_broadcast(const struct cpumask *mask)
 355 {
 356 }
 357 #endif
 358
 359 static void __init omap2_gp_clockevent_init(int gptimer_id,
 360                                                 const char *fck_source,
 361                                                 const char *property)
 362 {
 363         int res;
 364
 365         clkev.id = gptimer_id;
 366         clkev.errata = omap_dm_timer_get_errata();
 367
 368         /*
 369          * For clock-event timers we never read the timer counter and
 370          * so we are not impacted by errata i103 and i767. Therefore,
 371          * we can safely ignore this errata for clock-event timers.
 372          */
 373         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 374
 375         res = omap_dm_timer_init_one(&clkev, fck_source, property,
 376                                      &clockevent_gpt.name, OMAP_TIMER_POSTED);
 377         BUG_ON(res);
 378
 379         if (request_irq(clkev.irq, omap2_gp_timer_interrupt,
 380                         IRQF_TIMER | IRQF_IRQPOLL, "gp_timer", &clkev))
 381                 pr_err("Failed to request irq %d (gp_timer)\n", clkev.irq);
 382
 383         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 384
 385         clockevent_gpt.cpumask = cpu_possible_mask;
 386         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 387         clockevents_config_and_register(&clockevent_gpt, clkev.rate,
 388                                         3, /* Timer internal resynch latency */
 389                                         0xffffffff);
 390
 391         if (soc_is_am33xx() || soc_is_am43xx()) {
 392                 clockevent_gpt.suspend = omap_clkevt_idle;
 393                 clockevent_gpt.resume = omap_clkevt_unidle;
 394
 395                 clockevent_gpt_hwmod =
 396                         omap_hwmod_lookup(clockevent_gpt.name);
 397         }
 398
 399         pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
 400                 clkev.rate);
 401 }
 402
 403 /* Clocksource code */
 404 static struct omap_dm_timer clksrc;
 405 static bool use_gptimer_clksrc __initdata;
 406
 407 /*
 408  * clocksource
 409  */
 410 static u64 clocksource_read_cycles(struct clocksource *cs)
 411 {
 412         return (u64)__omap_dm_timer_read_counter(&clksrc,
 413                                                      OMAP_TIMER_NONPOSTED);
 414 }
 415
 416 static struct clocksource clocksource_gpt = {
 417         .rating         = 300,
 418         .read           = clocksource_read_cycles,
 419         .mask           = CLOCKSOURCE_MASK(32),
 420         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 421 };
 422
 423 static u64 notrace dmtimer_read_sched_clock(void)
 424 {
 425         if (clksrc.reserved)
 426                 return __omap_dm_timer_read_counter(&clksrc,
 427                                                     OMAP_TIMER_NONPOSTED);
 428
 429         return 0;
 430 }
 431
 432 static const struct of_device_id omap_counter_match[] __initconst = {
 433         { .compatible = "ti,omap-counter32k", },
 434         { }
 435 };
 436
 437 /* Setup free-running counter for clocksource */
 438 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 439 {
 440         int ret;
 441         struct device_node *np = NULL;
 442         struct omap_hwmod *oh;
 443         const char *oh_name = "counter_32k";
 444
 445         /*
 446          * See if the 32kHz counter is supported.
 447          */
 448         np = omap_get_timer_dt(omap_counter_match, NULL);
 449         if (!np)
 450                 return -ENODEV;
 451
 452         of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
 453         if (!oh_name) {
 454                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 455                 if (!oh_name)
 456                         return -ENODEV;
 457         }
 458
 459         /*
 460          * First check hwmod data is available for sync32k counter
 461          */
 462         oh = omap_hwmod_lookup(oh_name);
 463         if (!oh || oh->slaves_cnt == 0)
 464                 return -ENODEV;
 465
 466         omap_hwmod_setup_one(oh_name);
 467
 468         ret = omap_hwmod_enable(oh);
 469         if (ret) {
 470                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 471                                                         __func__, ret);
 472                 return ret;
 473         }
 474
 475         return ret;
 476 }
 477
 478 static unsigned int omap2_gptimer_clksrc_load;
 479
 480 static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
 481 {
 482         omap2_gptimer_clksrc_load =
 483                 __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
 484
 485         omap_hwmod_idle(clocksource_gpt_hwmod);
 486 }
 487
 488 static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
 489 {
 490         omap_hwmod_enable(clocksource_gpt_hwmod);
 491
 492         __omap_dm_timer_load_start(&clksrc,
 493                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
 494                                    omap2_gptimer_clksrc_load,
 495                                    OMAP_TIMER_NONPOSTED);
 496 }
 497
 498 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 499                                                   const char *fck_source,
 500                                                   const char *property)
 501 {
 502         int res;
 503
 504         clksrc.id = gptimer_id;
 505         clksrc.errata = omap_dm_timer_get_errata();
 506
 507         res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 508                                      &clocksource_gpt.name,
 509                                      OMAP_TIMER_NONPOSTED);
 510
 511         if (soc_is_am43xx()) {
 512                 clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
 513                 clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
 514
 515                 clocksource_gpt_hwmod =
 516                         omap_hwmod_lookup(clocksource_gpt.name);
 517         }
 518
 519         BUG_ON(res);
 520
 521         __omap_dm_timer_load_start(&clksrc,
 522                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 523                                    OMAP_TIMER_NONPOSTED);
 524         sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 525
 526         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 527                 pr_err("Could not register clocksource %s\n",
 528                         clocksource_gpt.name);
 529         else
 530                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 531                         clocksource_gpt.name, clksrc.rate);
 532 }
 533
 534 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 535                 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 536                 const char *clksrc_prop, bool gptimer)
 537 {
 538         omap_clk_init();
 539         omap_dmtimer_init();
 540         omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
 541
 542         /* Enable the use of clocksource="gp_timer" kernel parameter */
 543         if (clksrc_nr && (use_gptimer_clksrc || gptimer))
 544                 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 545                                                 clksrc_prop);
 546         else
 547                 omap2_sync32k_clocksource_init();
 548 }
 549
 550 void __init omap_init_time(void)
 551 {
 552         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 553                         2, "timer_sys_ck", NULL, false);
 554
 555         timer_probe();
 556 }
 557
 558 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 559 void __init omap3_secure_sync32k_timer_init(void)
 560 {
 561         __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 562                         2, "timer_sys_ck", NULL, false);
 563
 564         timer_probe();
 565 }
 566 #endif /* CONFIG_ARCH_OMAP3 */
 567
 568 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 569         defined(CONFIG_SOC_AM43XX)
 570 void __init omap3_gptimer_timer_init(void)
 571 {
 572         __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 573                         1, "timer_sys_ck", "ti,timer-alwon", true);
 574         if (of_have_populated_dt())
 575                 timer_probe();
 576 }
 577 #endif
 578
 579 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||          \
 580         defined(CONFIG_SOC_DRA7XX)
 581 static void __init omap4_sync32k_timer_init(void)
 582 {
 583         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 584                                   0, NULL, NULL, false);
 585 }
 586
 587 void __init omap4_local_timer_init(void)
 588 {
 589         omap4_sync32k_timer_init();
 590         timer_probe();
 591 }
 592 #endif
 593
 594 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 595
 596 /*
 597  * The realtime counter also called master counter, is a free-running
 598  * counter, which is related to real time. It produces the count used
 599  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 600  * at a rate of 6.144 MHz. Because the device operates on different clocks
 601  * in different power modes, the master counter shifts operation between
 602  * clocks, adjusting the increment per clock in hardware accordingly to
 603  * maintain a constant count rate.
 604  */
 605 static void __init realtime_counter_init(void)
 606 {
 607 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 608         void __iomem *base;
 609         static struct clk *sys_clk;
 610         unsigned long rate;
 611         unsigned int reg;
 612         unsigned long long num, den;
 613
 614         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 615         if (!base) {
 616                 pr_err("%s: ioremap failed\n", __func__);
 617                 return;
 618         }
 619         sys_clk = clk_get(NULL, "sys_clkin");
 620         if (IS_ERR(sys_clk)) {
 621                 pr_err("%s: failed to get system clock handle\n", __func__);
 622                 iounmap(base);
 623                 return;
 624         }
 625
 626         rate = clk_get_rate(sys_clk);
 627
 628         if (soc_is_dra7xx()) {
 629                 /*
 630                  * Errata i856 says the 32.768KHz crystal does not start at
 631                  * power on, so the CPU falls back to an emulated 32KHz clock
 632                  * based on sysclk / 610 instead. This causes the master counter
 633                  * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
 634                  * (OR sysclk * 75 / 244)
 635                  *
 636                  * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
 637                  * Of course any board built without a populated 32.768KHz
 638                  * crystal would also need this fix even if the CPU is fixed
 639                  * later.
 640                  *
 641                  * Either case can be detected by using the two speedselect bits
 642                  * If they are not 0, then the 32.768KHz clock driving the
 643                  * coarse counter that corrects the fine counter every time it
 644                  * ticks is actually rate/610 rather than 32.768KHz and we
 645                  * should compensate to avoid the 570ppm (at 20MHz, much worse
 646                  * at other rates) too fast system time.
 647                  */
 648                 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
 649                 if (reg & DRA7_SPEEDSELECT_MASK) {
 650                         num = 75;
 651                         den = 244;
 652                         goto sysclk1_based;
 653                 }
 654         }
 655
 656         /* Numerator/denumerator values refer TRM Realtime Counter section */
 657         switch (rate) {
 658         case 12000000:
 659                 num = 64;
 660                 den = 125;
 661                 break;
 662         case 13000000:
 663                 num = 768;
 664                 den = 1625;
 665                 break;
 666         case 19200000:
 667                 num = 8;
 668                 den = 25;
 669                 break;
 670         case 20000000:
 671                 num = 192;
 672                 den = 625;
 673                 break;
 674         case 26000000:
 675                 num = 384;
 676                 den = 1625;
 677                 break;
 678         case 27000000:
 679                 num = 256;
 680                 den = 1125;
 681                 break;
 682         case 38400000:
 683         default:
 684                 /* Program it for 38.4 MHz */
 685                 num = 4;
 686                 den = 25;
 687                 break;
 688         }
 689
 690 sysclk1_based:
 691         /* Program numerator and denumerator registers */
 692         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 693                         NUMERATOR_DENUMERATOR_MASK;
 694         reg |= num;
 695         writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 696
 697         reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 698                         NUMERATOR_DENUMERATOR_MASK;
 699         reg |= den;
 700         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 701
 702         arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 703         set_cntfreq();
 704
 705         iounmap(base);
 706 #endif
 707 }
 708
 709 void __init omap5_realtime_timer_init(void)
 710 {
 711         omap4_sync32k_timer_init();
 712         realtime_counter_init();
 713
 714         timer_probe();
 715 }
 716 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 717
 718 /**
 719  * omap2_override_clocksource - clocksource override with user configuration
 720  *
 721  * Allows user to override default clocksource, using kernel parameter
 722  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 723  *
 724  * Note that, here we are using same standard kernel parameter "clocksource=",
 725  * and not introducing any OMAP specific interface.
 726  */
 727 static int __init omap2_override_clocksource(char *str)
 728 {
 729         if (!str)
 730                 return 0;
 731         /*
 732          * For OMAP architecture, we only have two options
 733          *    - sync_32k (default)
 734          *    - gp_timer (sys_clk based)
 735          */
 736         if (!strcmp(str, "gp_timer"))
 737                 use_gptimer_clksrc = true;
 738
 739         return 0;
 740 }
 741 early_param("clocksource", omap2_override_clocksource);