drivers/net/dsa/qca/qca8k-8xxx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <[email protected]>
   4  * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <[email protected]>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/bitfield.h>
  13 #include <linux/regmap.h>
  14 #include <net/dsa.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/mdio.h>
  19 #include <linux/phylink.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/dsa/tag_qca.h>
  23
  24 #include "qca8k.h"
  25
  26 static void
  27 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  28 {
  29         regaddr >>= 1;
  30         *r1 = regaddr & 0x1e;
  31
  32         regaddr >>= 5;
  33         *r2 = regaddr & 0x7;
  34
  35         regaddr >>= 3;
  36         *page = regaddr & 0x3ff;
  37 }
  38
  39 static int
  40 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  41 {
  42         int ret;
  43         u16 lo;
  44
  45         lo = val & 0xffff;
  46         ret = bus->write(bus, phy_id, regnum, lo);
  47         if (ret < 0)
  48                 dev_err_ratelimited(&bus->dev,
  49                                     "failed to write qca8k 32bit lo register\n");
  50
  51         return ret;
  52 }
  53
  54 static int
  55 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  56 {
  57         int ret;
  58         u16 hi;
  59
  60         hi = (u16)(val >> 16);
  61         ret = bus->write(bus, phy_id, regnum, hi);
  62         if (ret < 0)
  63                 dev_err_ratelimited(&bus->dev,
  64                                     "failed to write qca8k 32bit hi register\n");
  65
  66         return ret;
  67 }
  68
  69 static int
  70 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  71 {
  72         int ret;
  73
  74         ret = bus->read(bus, phy_id, regnum);
  75         if (ret < 0)
  76                 goto err;
  77
  78         *val = ret & 0xffff;
  79         return 0;
  80
  81 err:
  82         dev_err_ratelimited(&bus->dev,
  83                             "failed to read qca8k 32bit lo register\n");
  84         *val = 0;
  85
  86         return ret;
  87 }
  88
  89 static int
  90 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  91 {
  92         int ret;
  93
  94         ret = bus->read(bus, phy_id, regnum);
  95         if (ret < 0)
  96                 goto err;
  97
  98         *val = ret << 16;
  99         return 0;
 100
 101 err:
 102         dev_err_ratelimited(&bus->dev,
 103                             "failed to read qca8k 32bit hi register\n");
 104         *val = 0;
 105
 106         return ret;
 107 }
 108
 109 static int
 110 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 111 {
 112         u32 hi, lo;
 113         int ret;
 114
 115         *val = 0;
 116
 117         ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
 118         if (ret < 0)
 119                 goto err;
 120
 121         ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
 122         if (ret < 0)
 123                 goto err;
 124
 125         *val = lo | hi;
 126
 127 err:
 128         return ret;
 129 }
 130
 131 static void
 132 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 133 {
 134         if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
 135                 return;
 136
 137         qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
 138 }
 139
 140 static int
 141 qca8k_set_page(struct qca8k_priv *priv, u16 page)
 142 {
 143         u16 *cached_page = &priv->mdio_cache.page;
 144         struct mii_bus *bus = priv->bus;
 145         int ret;
 146
 147         if (page == *cached_page)
 148                 return 0;
 149
 150         ret = bus->write(bus, 0x18, 0, page);
 151         if (ret < 0) {
 152                 dev_err_ratelimited(&bus->dev,
 153                                     "failed to set qca8k page\n");
 154                 return ret;
 155         }
 156
 157         *cached_page = page;
 158         usleep_range(1000, 2000);
 159         return 0;
 160 }
 161
 162 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 163 {
 164         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 165         struct qca8k_priv *priv = ds->priv;
 166         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 167         u32 command;
 168         u8 len, cmd;
 169         int i;
 170
 171         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
 172         mgmt_eth_data = &priv->mgmt_eth_data;
 173
 174         command = get_unaligned_le32(&mgmt_ethhdr->command);
 175         cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
 176
 177         len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
 178         /* Special case for len of 15 as this is the max value for len and needs to
 179          * be increased before converting it from word to dword.
 180          */
 181         if (len == 15)
 182                 len++;
 183
 184         /* We can ignore odd value, we always round up them in the alloc function. */
 185         len *= sizeof(u16);
 186
 187         /* Make sure the seq match the requested packet */
 188         if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
 189                 mgmt_eth_data->ack = true;
 190
 191         if (cmd == MDIO_READ) {
 192                 u32 *val = mgmt_eth_data->data;
 193
 194                 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data);
 195
 196                 /* Get the rest of the 12 byte of data.
 197                  * The read/write function will extract the requested data.
 198                  */
 199                 if (len > QCA_HDR_MGMT_DATA1_LEN) {
 200                         __le32 *data2 = (__le32 *)skb->data;
 201                         int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 202                                              len - QCA_HDR_MGMT_DATA1_LEN);
 203
 204                         val++;
 205
 206                         for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 207                                 *val = get_unaligned_le32(data2);
 208                                 val++;
 209                                 data2++;
 210                         }
 211                 }
 212         }
 213
 214         complete(&mgmt_eth_data->rw_done);
 215 }
 216
 217 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
 218                                                int priority, unsigned int len)
 219 {
 220         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 221         unsigned int real_len;
 222         struct sk_buff *skb;
 223         __le32 *data2;
 224         u32 command;
 225         u16 hdr;
 226         int i;
 227
 228         skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
 229         if (!skb)
 230                 return NULL;
 231
 232         /* Hdr mgmt length value is in step of word size.
 233          * As an example to process 4 byte of data the correct length to set is 2.
 234          * To process 8 byte 4, 12 byte 6, 16 byte 8...
 235          *
 236          * Odd values will always return the next size on the ack packet.
 237          * (length of 3 (6 byte) will always return 8 bytes of data)
 238          *
 239          * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
 240          * of data.
 241          *
 242          * To correctly calculate the length we devide the requested len by word and
 243          * round up.
 244          * On the ack function we can skip the odd check as we already handle the
 245          * case here.
 246          */
 247         real_len = DIV_ROUND_UP(len, sizeof(u16));
 248
 249         /* We check if the result len is odd and we round up another time to
 250          * the next size. (length of 3 will be increased to 4 as switch will always
 251          * return 8 bytes)
 252          */
 253         if (real_len % sizeof(u16) != 0)
 254                 real_len++;
 255
 256         /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
 257         if (real_len == 16)
 258                 real_len--;
 259
 260         skb_reset_mac_header(skb);
 261         skb_set_network_header(skb, skb->len);
 262
 263         mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
 264
 265         hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
 266         hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
 267         hdr |= QCA_HDR_XMIT_FROM_CPU;
 268         hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
 269         hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
 270
 271         command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
 272         command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
 273         command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
 274         command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
 275                                            QCA_HDR_MGMT_CHECK_CODE_VAL);
 276
 277         put_unaligned_le32(command, &mgmt_ethhdr->command);
 278
 279         if (cmd == MDIO_WRITE)
 280                 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data);
 281
 282         mgmt_ethhdr->hdr = htons(hdr);
 283
 284         data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
 285         if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) {
 286                 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN,
 287                                      len - QCA_HDR_MGMT_DATA1_LEN);
 288
 289                 val++;
 290
 291                 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) {
 292                         put_unaligned_le32(*val, data2);
 293                         data2++;
 294                         val++;
 295                 }
 296         }
 297
 298         return skb;
 299 }
 300
 301 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
 302 {
 303         struct qca_mgmt_ethhdr *mgmt_ethhdr;
 304         u32 seq;
 305
 306         seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
 307         mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
 308         put_unaligned_le32(seq, &mgmt_ethhdr->seq);
 309 }
 310
 311 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 312 {
 313         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 314         struct sk_buff *skb;
 315         bool ack;
 316         int ret;
 317
 318         skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
 319                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 320         if (!skb)
 321                 return -ENOMEM;
 322
 323         mutex_lock(&mgmt_eth_data->mutex);
 324
 325         /* Check mgmt_master if is operational */
 326         if (!priv->mgmt_master) {
 327                 kfree_skb(skb);
 328                 mutex_unlock(&mgmt_eth_data->mutex);
 329                 return -EINVAL;
 330         }
 331
 332         skb->dev = priv->mgmt_master;
 333
 334         reinit_completion(&mgmt_eth_data->rw_done);
 335
 336         /* Increment seq_num and set it in the mdio pkt */
 337         mgmt_eth_data->seq++;
 338         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 339         mgmt_eth_data->ack = false;
 340
 341         dev_queue_xmit(skb);
 342
 343         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 344                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 345
 346         *val = mgmt_eth_data->data[0];
 347         if (len > QCA_HDR_MGMT_DATA1_LEN)
 348                 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
 349
 350         ack = mgmt_eth_data->ack;
 351
 352         mutex_unlock(&mgmt_eth_data->mutex);
 353
 354         if (ret <= 0)
 355                 return -ETIMEDOUT;
 356
 357         if (!ack)
 358                 return -EINVAL;
 359
 360         return 0;
 361 }
 362
 363 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
 364 {
 365         struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
 366         struct sk_buff *skb;
 367         bool ack;
 368         int ret;
 369
 370         skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
 371                                       QCA8K_ETHERNET_MDIO_PRIORITY, len);
 372         if (!skb)
 373                 return -ENOMEM;
 374
 375         mutex_lock(&mgmt_eth_data->mutex);
 376
 377         /* Check mgmt_master if is operational */
 378         if (!priv->mgmt_master) {
 379                 kfree_skb(skb);
 380                 mutex_unlock(&mgmt_eth_data->mutex);
 381                 return -EINVAL;
 382         }
 383
 384         skb->dev = priv->mgmt_master;
 385
 386         reinit_completion(&mgmt_eth_data->rw_done);
 387
 388         /* Increment seq_num and set it in the mdio pkt */
 389         mgmt_eth_data->seq++;
 390         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 391         mgmt_eth_data->ack = false;
 392
 393         dev_queue_xmit(skb);
 394
 395         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 396                                           msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
 397
 398         ack = mgmt_eth_data->ack;
 399
 400         mutex_unlock(&mgmt_eth_data->mutex);
 401
 402         if (ret <= 0)
 403                 return -ETIMEDOUT;
 404
 405         if (!ack)
 406                 return -EINVAL;
 407
 408         return 0;
 409 }
 410
 411 static int
 412 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 413 {
 414         u32 val = 0;
 415         int ret;
 416
 417         ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
 418         if (ret)
 419                 return ret;
 420
 421         val &= ~mask;
 422         val |= write_val;
 423
 424         return qca8k_write_eth(priv, reg, &val, sizeof(val));
 425 }
 426
 427 static int
 428 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val)
 429 {
 430         struct mii_bus *bus = priv->bus;
 431         u16 r1, r2, page;
 432         int ret;
 433
 434         qca8k_split_addr(reg, &r1, &r2, &page);
 435
 436         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 437
 438         ret = qca8k_set_page(priv, page);
 439         if (ret < 0)
 440                 goto exit;
 441
 442         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 443
 444 exit:
 445         mutex_unlock(&bus->mdio_lock);
 446         return ret;
 447 }
 448
 449 static int
 450 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val)
 451 {
 452         struct mii_bus *bus = priv->bus;
 453         u16 r1, r2, page;
 454         int ret;
 455
 456         qca8k_split_addr(reg, &r1, &r2, &page);
 457
 458         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 459
 460         ret = qca8k_set_page(priv, page);
 461         if (ret < 0)
 462                 goto exit;
 463
 464         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 465
 466 exit:
 467         mutex_unlock(&bus->mdio_lock);
 468         return ret;
 469 }
 470
 471 static int
 472 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg,
 473                              uint32_t mask, uint32_t write_val)
 474 {
 475         struct mii_bus *bus = priv->bus;
 476         u16 r1, r2, page;
 477         u32 val;
 478         int ret;
 479
 480         qca8k_split_addr(reg, &r1, &r2, &page);
 481
 482         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 483
 484         ret = qca8k_set_page(priv, page);
 485         if (ret < 0)
 486                 goto exit;
 487
 488         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 489         if (ret < 0)
 490                 goto exit;
 491
 492         val &= ~mask;
 493         val |= write_val;
 494         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 495
 496 exit:
 497         mutex_unlock(&bus->mdio_lock);
 498
 499         return ret;
 500 }
 501
 502 static int
 503 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len,
 504                 void *val_buf, size_t val_len)
 505 {
 506         int i, count = val_len / sizeof(u32), ret;
 507         u32 reg = *(u32 *)reg_buf & U16_MAX;
 508         struct qca8k_priv *priv = ctx;
 509
 510         if (priv->mgmt_master &&
 511             !qca8k_read_eth(priv, reg, val_buf, val_len))
 512                 return 0;
 513
 514         /* loop count times and increment reg of 4 */
 515         for (i = 0; i < count; i++, reg += sizeof(u32)) {
 516                 ret = qca8k_read_mii(priv, reg, val_buf + i);
 517                 if (ret < 0)
 518                         return ret;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int
 525 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len,
 526                         const void *val_buf, size_t val_len)
 527 {
 528         int i, count = val_len / sizeof(u32), ret;
 529         u32 reg = *(u32 *)reg_buf & U16_MAX;
 530         struct qca8k_priv *priv = ctx;
 531         u32 *val = (u32 *)val_buf;
 532
 533         if (priv->mgmt_master &&
 534             !qca8k_write_eth(priv, reg, val, val_len))
 535                 return 0;
 536
 537         /* loop count times, increment reg of 4 and increment val ptr to
 538          * the next value
 539          */
 540         for (i = 0; i < count; i++, reg += sizeof(u32), val++) {
 541                 ret = qca8k_write_mii(priv, reg, *val);
 542                 if (ret < 0)
 543                         return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int
 550 qca8k_bulk_write(void *ctx, const void *data, size_t bytes)
 551 {
 552         return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16),
 553                                        bytes - sizeof(u16));
 554 }
 555
 556 static int
 557 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
 558 {
 559         struct qca8k_priv *priv = ctx;
 560
 561         if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
 562                 return 0;
 563
 564         return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val);
 565 }
 566
 567 static struct regmap_config qca8k_regmap_config = {
 568         .reg_bits = 16,
 569         .val_bits = 32,
 570         .reg_stride = 4,
 571         .max_register = 0x16ac, /* end MIB - Port6 range */
 572         .read = qca8k_bulk_read,
 573         .write = qca8k_bulk_write,
 574         .reg_update_bits = qca8k_regmap_update_bits,
 575         .rd_table = &qca8k_readable_table,
 576         .disable_locking = true, /* Locking is handled by qca8k read/write */
 577         .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
 578         .max_raw_read = 32, /* mgmt eth can read/write up to 8 registers at time */
 579         .max_raw_write = 32,
 580 };
 581
 582 static int
 583 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
 584                         struct sk_buff *read_skb, u32 *val)
 585 {
 586         struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
 587         bool ack;
 588         int ret;
 589
 590         reinit_completion(&mgmt_eth_data->rw_done);
 591
 592         /* Increment seq_num and set it in the copy pkt */
 593         mgmt_eth_data->seq++;
 594         qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
 595         mgmt_eth_data->ack = false;
 596
 597         dev_queue_xmit(skb);
 598
 599         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 600                                           QCA8K_ETHERNET_TIMEOUT);
 601
 602         ack = mgmt_eth_data->ack;
 603
 604         if (ret <= 0)
 605                 return -ETIMEDOUT;
 606
 607         if (!ack)
 608                 return -EINVAL;
 609
 610         *val = mgmt_eth_data->data[0];
 611
 612         return 0;
 613 }
 614
 615 static int
 616 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
 617                       int regnum, u16 data)
 618 {
 619         struct sk_buff *write_skb, *clear_skb, *read_skb;
 620         struct qca8k_mgmt_eth_data *mgmt_eth_data;
 621         u32 write_val, clear_val = 0, val;
 622         struct net_device *mgmt_master;
 623         int ret, ret1;
 624         bool ack;
 625
 626         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 627                 return -EINVAL;
 628
 629         mgmt_eth_data = &priv->mgmt_eth_data;
 630
 631         write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 632                     QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 633                     QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 634
 635         if (read) {
 636                 write_val |= QCA8K_MDIO_MASTER_READ;
 637         } else {
 638                 write_val |= QCA8K_MDIO_MASTER_WRITE;
 639                 write_val |= QCA8K_MDIO_MASTER_DATA(data);
 640         }
 641
 642         /* Prealloc all the needed skb before the lock */
 643         write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
 644                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
 645         if (!write_skb)
 646                 return -ENOMEM;
 647
 648         clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 649                                             QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 650         if (!clear_skb) {
 651                 ret = -ENOMEM;
 652                 goto err_clear_skb;
 653         }
 654
 655         read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
 656                                            QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
 657         if (!read_skb) {
 658                 ret = -ENOMEM;
 659                 goto err_read_skb;
 660         }
 661
 662         /* Actually start the request:
 663          * 1. Send mdio master packet
 664          * 2. Busy Wait for mdio master command
 665          * 3. Get the data if we are reading
 666          * 4. Reset the mdio master (even with error)
 667          */
 668         mutex_lock(&mgmt_eth_data->mutex);
 669
 670         /* Check if mgmt_master is operational */
 671         mgmt_master = priv->mgmt_master;
 672         if (!mgmt_master) {
 673                 mutex_unlock(&mgmt_eth_data->mutex);
 674                 ret = -EINVAL;
 675                 goto err_mgmt_master;
 676         }
 677
 678         read_skb->dev = mgmt_master;
 679         clear_skb->dev = mgmt_master;
 680         write_skb->dev = mgmt_master;
 681
 682         reinit_completion(&mgmt_eth_data->rw_done);
 683
 684         /* Increment seq_num and set it in the write pkt */
 685         mgmt_eth_data->seq++;
 686         qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
 687         mgmt_eth_data->ack = false;
 688
 689         dev_queue_xmit(write_skb);
 690
 691         ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 692                                           QCA8K_ETHERNET_TIMEOUT);
 693
 694         ack = mgmt_eth_data->ack;
 695
 696         if (ret <= 0) {
 697                 ret = -ETIMEDOUT;
 698                 kfree_skb(read_skb);
 699                 goto exit;
 700         }
 701
 702         if (!ack) {
 703                 ret = -EINVAL;
 704                 kfree_skb(read_skb);
 705                 goto exit;
 706         }
 707
 708         ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
 709                                 !(val & QCA8K_MDIO_MASTER_BUSY), 0,
 710                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 711                                 mgmt_eth_data, read_skb, &val);
 712
 713         if (ret < 0 && ret1 < 0) {
 714                 ret = ret1;
 715                 goto exit;
 716         }
 717
 718         if (read) {
 719                 reinit_completion(&mgmt_eth_data->rw_done);
 720
 721                 /* Increment seq_num and set it in the read pkt */
 722                 mgmt_eth_data->seq++;
 723                 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
 724                 mgmt_eth_data->ack = false;
 725
 726                 dev_queue_xmit(read_skb);
 727
 728                 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 729                                                   QCA8K_ETHERNET_TIMEOUT);
 730
 731                 ack = mgmt_eth_data->ack;
 732
 733                 if (ret <= 0) {
 734                         ret = -ETIMEDOUT;
 735                         goto exit;
 736                 }
 737
 738                 if (!ack) {
 739                         ret = -EINVAL;
 740                         goto exit;
 741                 }
 742
 743                 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
 744         } else {
 745                 kfree_skb(read_skb);
 746         }
 747 exit:
 748         reinit_completion(&mgmt_eth_data->rw_done);
 749
 750         /* Increment seq_num and set it in the clear pkt */
 751         mgmt_eth_data->seq++;
 752         qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
 753         mgmt_eth_data->ack = false;
 754
 755         dev_queue_xmit(clear_skb);
 756
 757         wait_for_completion_timeout(&mgmt_eth_data->rw_done,
 758                                     QCA8K_ETHERNET_TIMEOUT);
 759
 760         mutex_unlock(&mgmt_eth_data->mutex);
 761
 762         return ret;
 763
 764         /* Error handling before lock */
 765 err_mgmt_master:
 766         kfree_skb(read_skb);
 767 err_read_skb:
 768         kfree_skb(clear_skb);
 769 err_clear_skb:
 770         kfree_skb(write_skb);
 771
 772         return ret;
 773 }
 774
 775 static u32
 776 qca8k_port_to_phy(int port)
 777 {
 778         /* From Andrew Lunn:
 779          * Port 0 has no internal phy.
 780          * Port 1 has an internal PHY at MDIO address 0.
 781          * Port 2 has an internal PHY at MDIO address 1.
 782          * ...
 783          * Port 5 has an internal PHY at MDIO address 4.
 784          * Port 6 has no internal PHY.
 785          */
 786
 787         return port - 1;
 788 }
 789
 790 static int
 791 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 792 {
 793         u16 r1, r2, page;
 794         u32 val;
 795         int ret, ret1;
 796
 797         qca8k_split_addr(reg, &r1, &r2, &page);
 798
 799         ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
 800                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 801                                 bus, 0x10 | r2, r1 + 1, &val);
 802
 803         /* Check if qca8k_read has failed for a different reason
 804          * before returnting -ETIMEDOUT
 805          */
 806         if (ret < 0 && ret1 < 0)
 807                 return ret1;
 808
 809         return ret;
 810 }
 811
 812 static int
 813 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
 814 {
 815         struct mii_bus *bus = priv->bus;
 816         u16 r1, r2, page;
 817         u32 val;
 818         int ret;
 819
 820         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 821                 return -EINVAL;
 822
 823         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 824               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 825               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 826               QCA8K_MDIO_MASTER_DATA(data);
 827
 828         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 829
 830         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 831
 832         ret = qca8k_set_page(priv, page);
 833         if (ret)
 834                 goto exit;
 835
 836         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 837
 838         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 839                                    QCA8K_MDIO_MASTER_BUSY);
 840
 841 exit:
 842         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 843         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 844
 845         mutex_unlock(&bus->mdio_lock);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 852 {
 853         struct mii_bus *bus = priv->bus;
 854         u16 r1, r2, page;
 855         u32 val;
 856         int ret;
 857
 858         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 859                 return -EINVAL;
 860
 861         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 862               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 863               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 864
 865         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 866
 867         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 868
 869         ret = qca8k_set_page(priv, page);
 870         if (ret)
 871                 goto exit;
 872
 873         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
 874
 875         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 876                                    QCA8K_MDIO_MASTER_BUSY);
 877         if (ret)
 878                 goto exit;
 879
 880         ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
 881
 882 exit:
 883         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 884         qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 885
 886         mutex_unlock(&bus->mdio_lock);
 887
 888         if (ret >= 0)
 889                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 890
 891         return ret;
 892 }
 893
 894 static int
 895 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
 896 {
 897         struct qca8k_priv *priv = slave_bus->priv;
 898         int ret;
 899
 900         /* Use mdio Ethernet when available, fallback to legacy one on error */
 901         ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
 902         if (!ret)
 903                 return 0;
 904
 905         return qca8k_mdio_write(priv, phy, regnum, data);
 906 }
 907
 908 static int
 909 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
 910 {
 911         struct qca8k_priv *priv = slave_bus->priv;
 912         int ret;
 913
 914         /* Use mdio Ethernet when available, fallback to legacy one on error */
 915         ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
 916         if (ret >= 0)
 917                 return ret;
 918
 919         ret = qca8k_mdio_read(priv, phy, regnum);
 920
 921         if (ret < 0)
 922                 return 0xffff;
 923
 924         return ret;
 925 }
 926
 927 static int
 928 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
 929 {
 930         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 931
 932         return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
 933 }
 934
 935 static int
 936 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
 937 {
 938         port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 939
 940         return qca8k_internal_mdio_read(slave_bus, port, regnum);
 941 }
 942
 943 static int
 944 qca8k_mdio_register(struct qca8k_priv *priv)
 945 {
 946         struct dsa_switch *ds = priv->ds;
 947         struct device_node *mdio;
 948         struct mii_bus *bus;
 949
 950         bus = devm_mdiobus_alloc(ds->dev);
 951         if (!bus)
 952                 return -ENOMEM;
 953
 954         bus->priv = (void *)priv;
 955         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
 956                  ds->dst->index, ds->index);
 957         bus->parent = ds->dev;
 958         bus->phy_mask = ~ds->phys_mii_mask;
 959         ds->slave_mii_bus = bus;
 960
 961         /* Check if the devicetree declare the port:phy mapping */
 962         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 963         if (of_device_is_available(mdio)) {
 964                 bus->name = "qca8k slave mii";
 965                 bus->read = qca8k_internal_mdio_read;
 966                 bus->write = qca8k_internal_mdio_write;
 967                 return devm_of_mdiobus_register(priv->dev, bus, mdio);
 968         }
 969
 970         /* If a mapping can't be found the legacy mapping is used,
 971          * using the qca8k_port_to_phy function
 972          */
 973         bus->name = "qca8k-legacy slave mii";
 974         bus->read = qca8k_legacy_mdio_read;
 975         bus->write = qca8k_legacy_mdio_write;
 976         return devm_mdiobus_register(priv->dev, bus);
 977 }
 978
 979 static int
 980 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 981 {
 982         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 983         struct device_node *ports, *port;
 984         phy_interface_t mode;
 985         int err;
 986
 987         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 988         if (!ports)
 989                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 990
 991         if (!ports)
 992                 return -EINVAL;
 993
 994         for_each_available_child_of_node(ports, port) {
 995                 err = of_property_read_u32(port, "reg", &reg);
 996                 if (err) {
 997                         of_node_put(port);
 998                         of_node_put(ports);
 999                         return err;
1000                 }
1001
1002                 if (!dsa_is_user_port(priv->ds, reg))
1003                         continue;
1004
1005                 of_get_phy_mode(port, &mode);
1006
1007                 if (of_property_read_bool(port, "phy-handle") &&
1008                     mode != PHY_INTERFACE_MODE_INTERNAL)
1009                         external_mdio_mask |= BIT(reg);
1010                 else
1011                         internal_mdio_mask |= BIT(reg);
1012         }
1013
1014         of_node_put(ports);
1015         if (!external_mdio_mask && !internal_mdio_mask) {
1016                 dev_err(priv->dev, "no PHYs are defined.\n");
1017                 return -EINVAL;
1018         }
1019
1020         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
1021          * the MDIO_MASTER register also _disconnects_ the external MDC
1022          * passthrough to the internal PHYs. It's not possible to use both
1023          * configurations at the same time!
1024          *
1025          * Because this came up during the review process:
1026          * If the external mdio-bus driver is capable magically disabling
1027          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
1028          * accessors for the time being, it would be possible to pull this
1029          * off.
1030          */
1031         if (!!external_mdio_mask && !!internal_mdio_mask) {
1032                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
1033                 return -EINVAL;
1034         }
1035
1036         if (external_mdio_mask) {
1037                 /* Make sure to disable the internal mdio bus in cases
1038                  * a dt-overlay and driver reload changed the configuration
1039                  */
1040
1041                 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
1042                                          QCA8K_MDIO_MASTER_EN);
1043         }
1044
1045         return qca8k_mdio_register(priv);
1046 }
1047
1048 static int
1049 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
1050 {
1051         u32 mask = 0;
1052         int ret = 0;
1053
1054         /* SoC specific settings for ipq8064.
1055          * If more device require this consider adding
1056          * a dedicated binding.
1057          */
1058         if (of_machine_is_compatible("qcom,ipq8064"))
1059                 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
1060
1061         /* SoC specific settings for ipq8065 */
1062         if (of_machine_is_compatible("qcom,ipq8065"))
1063                 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
1064
1065         if (mask) {
1066                 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
1067                                 QCA8K_MAC_PWR_RGMII0_1_8V |
1068                                 QCA8K_MAC_PWR_RGMII1_1_8V,
1069                                 mask);
1070         }
1071
1072         return ret;
1073 }
1074
1075 static int qca8k_find_cpu_port(struct dsa_switch *ds)
1076 {
1077         struct qca8k_priv *priv = ds->priv;
1078
1079         /* Find the connected cpu port. Valid port are 0 or 6 */
1080         if (dsa_is_cpu_port(ds, 0))
1081                 return 0;
1082
1083         dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
1084
1085         if (dsa_is_cpu_port(ds, 6))
1086                 return 6;
1087
1088         return -EINVAL;
1089 }
1090
1091 static int
1092 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
1093 {
1094         const struct qca8k_match_data *data = priv->info;
1095         struct device_node *node = priv->dev->of_node;
1096         u32 val = 0;
1097         int ret;
1098
1099         /* QCA8327 require to set to the correct mode.
1100          * His bigger brother QCA8328 have the 172 pin layout.
1101          * Should be applied by default but we set this just to make sure.
1102          */
1103         if (priv->switch_id == QCA8K_ID_QCA8327) {
1104                 /* Set the correct package of 148 pin for QCA8327 */
1105                 if (data->reduced_package)
1106                         val |= QCA8327_PWS_PACKAGE148_EN;
1107
1108                 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1109                                 val);
1110                 if (ret)
1111                         return ret;
1112         }
1113
1114         if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1115                 val |= QCA8K_PWS_POWER_ON_SEL;
1116
1117         if (of_property_read_bool(node, "qca,led-open-drain")) {
1118                 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1119                         dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1120                         return -EINVAL;
1121                 }
1122
1123                 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1124         }
1125
1126         return qca8k_rmw(priv, QCA8K_REG_PWS,
1127                         QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1128                         val);
1129 }
1130
1131 static int
1132 qca8k_parse_port_config(struct qca8k_priv *priv)
1133 {
1134         int port, cpu_port_index = -1, ret;
1135         struct device_node *port_dn;
1136         phy_interface_t mode;
1137         struct dsa_port *dp;
1138         u32 delay;
1139
1140         /* We have 2 CPU port. Check them */
1141         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1142                 /* Skip every other port */
1143                 if (port != 0 && port != 6)
1144                         continue;
1145
1146                 dp = dsa_to_port(priv->ds, port);
1147                 port_dn = dp->dn;
1148                 cpu_port_index++;
1149
1150                 if (!of_device_is_available(port_dn))
1151                         continue;
1152
1153                 ret = of_get_phy_mode(port_dn, &mode);
1154                 if (ret)
1155                         continue;
1156
1157                 switch (mode) {
1158                 case PHY_INTERFACE_MODE_RGMII:
1159                 case PHY_INTERFACE_MODE_RGMII_ID:
1160                 case PHY_INTERFACE_MODE_RGMII_TXID:
1161                 case PHY_INTERFACE_MODE_RGMII_RXID:
1162                 case PHY_INTERFACE_MODE_SGMII:
1163                         delay = 0;
1164
1165                         if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1166                                 /* Switch regs accept value in ns, convert ps to ns */
1167                                 delay = delay / 1000;
1168                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1169                                  mode == PHY_INTERFACE_MODE_RGMII_TXID)
1170                                 delay = 1;
1171
1172                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1173                                 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1174                                 delay = 3;
1175                         }
1176
1177                         priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1178
1179                         delay = 0;
1180
1181                         if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1182                                 /* Switch regs accept value in ns, convert ps to ns */
1183                                 delay = delay / 1000;
1184                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1185                                  mode == PHY_INTERFACE_MODE_RGMII_RXID)
1186                                 delay = 2;
1187
1188                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1189                                 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1190                                 delay = 3;
1191                         }
1192
1193                         priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1194
1195                         /* Skip sgmii parsing for rgmii* mode */
1196                         if (mode == PHY_INTERFACE_MODE_RGMII ||
1197                             mode == PHY_INTERFACE_MODE_RGMII_ID ||
1198                             mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1199                             mode == PHY_INTERFACE_MODE_RGMII_RXID)
1200                                 break;
1201
1202                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1203                                 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1204
1205                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1206                                 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1207
1208                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1209                                 priv->ports_config.sgmii_enable_pll = true;
1210
1211                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
1212                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1213                                         priv->ports_config.sgmii_enable_pll = false;
1214                                 }
1215
1216                                 if (priv->switch_revision < 2)
1217                                         dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1218                         }
1219
1220                         break;
1221                 default:
1222                         continue;
1223                 }
1224         }
1225
1226         return 0;
1227 }
1228
1229 static void
1230 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1231                                       u32 reg)
1232 {
1233         u32 delay, val = 0;
1234         int ret;
1235
1236         /* Delay can be declared in 3 different way.
1237          * Mode to rgmii and internal-delay standard binding defined
1238          * rgmii-id or rgmii-tx/rx phy mode set.
1239          * The parse logic set a delay different than 0 only when one
1240          * of the 3 different way is used. In all other case delay is
1241          * not enabled. With ID or TX/RXID delay is enabled and set
1242          * to the default and recommended value.
1243          */
1244         if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1245                 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1246
1247                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1248                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1249         }
1250
1251         if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1252                 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1253
1254                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1255                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1256         }
1257
1258         /* Set RGMII delay based on the selected values */
1259         ret = qca8k_rmw(priv, reg,
1260                         QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1261                         QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1262                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1263                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1264                         val);
1265         if (ret)
1266                 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1267                         cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1268 }
1269
1270 static struct phylink_pcs *
1271 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
1272                              phy_interface_t interface)
1273 {
1274         struct qca8k_priv *priv = ds->priv;
1275         struct phylink_pcs *pcs = NULL;
1276
1277         switch (interface) {
1278         case PHY_INTERFACE_MODE_SGMII:
1279         case PHY_INTERFACE_MODE_1000BASEX:
1280                 switch (port) {
1281                 case 0:
1282                         pcs = &priv->pcs_port_0.pcs;
1283                         break;
1284
1285                 case 6:
1286                         pcs = &priv->pcs_port_6.pcs;
1287                         break;
1288                 }
1289                 break;
1290
1291         default:
1292                 break;
1293         }
1294
1295         return pcs;
1296 }
1297
1298 static void
1299 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1300                          const struct phylink_link_state *state)
1301 {
1302         struct qca8k_priv *priv = ds->priv;
1303         int cpu_port_index;
1304         u32 reg;
1305
1306         switch (port) {
1307         case 0: /* 1st CPU port */
1308                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1309                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1310                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1311                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1312                     state->interface != PHY_INTERFACE_MODE_SGMII)
1313                         return;
1314
1315                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1316                 cpu_port_index = QCA8K_CPU_PORT0;
1317                 break;
1318         case 1:
1319         case 2:
1320         case 3:
1321         case 4:
1322         case 5:
1323                 /* Internal PHY, nothing to do */
1324                 return;
1325         case 6: /* 2nd CPU port / external PHY */
1326                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1327                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1328                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1329                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1330                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1331                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1332                         return;
1333
1334                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1335                 cpu_port_index = QCA8K_CPU_PORT6;
1336                 break;
1337         default:
1338                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1339                 return;
1340         }
1341
1342         if (port != 6 && phylink_autoneg_inband(mode)) {
1343                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1344                         __func__);
1345                 return;
1346         }
1347
1348         switch (state->interface) {
1349         case PHY_INTERFACE_MODE_RGMII:
1350         case PHY_INTERFACE_MODE_RGMII_ID:
1351         case PHY_INTERFACE_MODE_RGMII_TXID:
1352         case PHY_INTERFACE_MODE_RGMII_RXID:
1353                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1354
1355                 /* Configure rgmii delay */
1356                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1357
1358                 /* QCA8337 requires to set rgmii rx delay for all ports.
1359                  * This is enabled through PORT5_PAD_CTRL for all ports,
1360                  * rather than individual port registers.
1361                  */
1362                 if (priv->switch_id == QCA8K_ID_QCA8337)
1363                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1364                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1365                 break;
1366         case PHY_INTERFACE_MODE_SGMII:
1367         case PHY_INTERFACE_MODE_1000BASEX:
1368                 /* Enable SGMII on the port */
1369                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1370                 break;
1371         default:
1372                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1373                         phy_modes(state->interface), port);
1374                 return;
1375         }
1376 }
1377
1378 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port,
1379                                    struct phylink_config *config)
1380 {
1381         switch (port) {
1382         case 0: /* 1st CPU port */
1383                 phy_interface_set_rgmii(config->supported_interfaces);
1384                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1385                           config->supported_interfaces);
1386                 break;
1387
1388         case 1:
1389         case 2:
1390         case 3:
1391         case 4:
1392         case 5:
1393                 /* Internal PHY */
1394                 __set_bit(PHY_INTERFACE_MODE_GMII,
1395                           config->supported_interfaces);
1396                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1397                           config->supported_interfaces);
1398                 break;
1399
1400         case 6: /* 2nd CPU port / external PHY */
1401                 phy_interface_set_rgmii(config->supported_interfaces);
1402                 __set_bit(PHY_INTERFACE_MODE_SGMII,
1403                           config->supported_interfaces);
1404                 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1405                           config->supported_interfaces);
1406                 break;
1407         }
1408
1409         config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1410                 MAC_10 | MAC_100 | MAC_1000FD;
1411
1412         config->legacy_pre_march2020 = false;
1413 }
1414
1415 static void
1416 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1417                             phy_interface_t interface)
1418 {
1419         struct qca8k_priv *priv = ds->priv;
1420
1421         qca8k_port_set_status(priv, port, 0);
1422 }
1423
1424 static void
1425 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1426                           phy_interface_t interface, struct phy_device *phydev,
1427                           int speed, int duplex, bool tx_pause, bool rx_pause)
1428 {
1429         struct qca8k_priv *priv = ds->priv;
1430         u32 reg;
1431
1432         if (phylink_autoneg_inband(mode)) {
1433                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1434         } else {
1435                 switch (speed) {
1436                 case SPEED_10:
1437                         reg = QCA8K_PORT_STATUS_SPEED_10;
1438                         break;
1439                 case SPEED_100:
1440                         reg = QCA8K_PORT_STATUS_SPEED_100;
1441                         break;
1442                 case SPEED_1000:
1443                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1444                         break;
1445                 default:
1446                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1447                         break;
1448                 }
1449
1450                 if (duplex == DUPLEX_FULL)
1451                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1452
1453                 if (rx_pause || dsa_is_cpu_port(ds, port))
1454                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1455
1456                 if (tx_pause || dsa_is_cpu_port(ds, port))
1457                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1458         }
1459
1460         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1461
1462         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1463 }
1464
1465 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
1466 {
1467         return container_of(pcs, struct qca8k_pcs, pcs);
1468 }
1469
1470 static void qca8k_pcs_get_state(struct phylink_pcs *pcs,
1471                                 struct phylink_link_state *state)
1472 {
1473         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1474         int port = pcs_to_qca8k_pcs(pcs)->port;
1475         u32 reg;
1476         int ret;
1477
1478         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1479         if (ret < 0) {
1480                 state->link = false;
1481                 return;
1482         }
1483
1484         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1485         state->an_complete = state->link;
1486         state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1487         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1488                                                            DUPLEX_HALF;
1489
1490         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1491         case QCA8K_PORT_STATUS_SPEED_10:
1492                 state->speed = SPEED_10;
1493                 break;
1494         case QCA8K_PORT_STATUS_SPEED_100:
1495                 state->speed = SPEED_100;
1496                 break;
1497         case QCA8K_PORT_STATUS_SPEED_1000:
1498                 state->speed = SPEED_1000;
1499                 break;
1500         default:
1501                 state->speed = SPEED_UNKNOWN;
1502                 break;
1503         }
1504
1505         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1506                 state->pause |= MLO_PAUSE_RX;
1507         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1508                 state->pause |= MLO_PAUSE_TX;
1509 }
1510
1511 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
1512                             phy_interface_t interface,
1513                             const unsigned long *advertising,
1514                             bool permit_pause_to_mac)
1515 {
1516         struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
1517         int cpu_port_index, ret, port;
1518         u32 reg, val;
1519
1520         port = pcs_to_qca8k_pcs(pcs)->port;
1521         switch (port) {
1522         case 0:
1523                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1524                 cpu_port_index = QCA8K_CPU_PORT0;
1525                 break;
1526
1527         case 6:
1528                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1529                 cpu_port_index = QCA8K_CPU_PORT6;
1530                 break;
1531
1532         default:
1533                 WARN_ON(1);
1534                 return -EINVAL;
1535         }
1536
1537         /* Enable/disable SerDes auto-negotiation as necessary */
1538         ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1539         if (ret)
1540                 return ret;
1541         if (phylink_autoneg_inband(mode))
1542                 val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1543         else
1544                 val |= QCA8K_PWS_SERDES_AEN_DIS;
1545         qca8k_write(priv, QCA8K_REG_PWS, val);
1546
1547         /* Configure the SGMII parameters */
1548         ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1549         if (ret)
1550                 return ret;
1551
1552         val |= QCA8K_SGMII_EN_SD;
1553
1554         if (priv->ports_config.sgmii_enable_pll)
1555                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1556                        QCA8K_SGMII_EN_TX;
1557
1558         if (dsa_is_cpu_port(priv->ds, port)) {
1559                 /* CPU port, we're talking to the CPU MAC, be a PHY */
1560                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1561                 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1562         } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1563                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1564                 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1565         } else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
1566                 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1567                 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1568         }
1569
1570         qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1571
1572         /* From original code is reported port instability as SGMII also
1573          * require delay set. Apply advised values here or take them from DT.
1574          */
1575         if (interface == PHY_INTERFACE_MODE_SGMII)
1576                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1577         /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1578          * falling edge is set writing in the PORT0 PAD reg
1579          */
1580         if (priv->switch_id == QCA8K_ID_QCA8327 ||
1581             priv->switch_id == QCA8K_ID_QCA8337)
1582                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1583
1584         val = 0;
1585
1586         /* SGMII Clock phase configuration */
1587         if (priv->ports_config.sgmii_rx_clk_falling_edge)
1588                 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1589
1590         if (priv->ports_config.sgmii_tx_clk_falling_edge)
1591                 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1592
1593         if (val)
1594                 ret = qca8k_rmw(priv, reg,
1595                                 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1596                                 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1597                                 val);
1598
1599         return 0;
1600 }
1601
1602 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs)
1603 {
1604 }
1605
1606 static const struct phylink_pcs_ops qca8k_pcs_ops = {
1607         .pcs_get_state = qca8k_pcs_get_state,
1608         .pcs_config = qca8k_pcs_config,
1609         .pcs_an_restart = qca8k_pcs_an_restart,
1610 };
1611
1612 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs,
1613                             int port)
1614 {
1615         qpcs->pcs.ops = &qca8k_pcs_ops;
1616
1617         /* We don't have interrupts for link changes, so we need to poll */
1618         qpcs->pcs.poll = true;
1619         qpcs->priv = priv;
1620         qpcs->port = port;
1621 }
1622
1623 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
1624 {
1625         struct qca8k_mib_eth_data *mib_eth_data;
1626         struct qca8k_priv *priv = ds->priv;
1627         const struct qca8k_mib_desc *mib;
1628         struct mib_ethhdr *mib_ethhdr;
1629         __le32 *data2;
1630         u8 port;
1631         int i;
1632
1633         mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
1634         mib_eth_data = &priv->mib_eth_data;
1635
1636         /* The switch autocast every port. Ignore other packet and
1637          * parse only the requested one.
1638          */
1639         port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
1640         if (port != mib_eth_data->req_port)
1641                 goto exit;
1642
1643         data2 = (__le32 *)skb->data;
1644
1645         for (i = 0; i < priv->info->mib_count; i++) {
1646                 mib = &ar8327_mib[i];
1647
1648                 /* First 3 mib are present in the skb head */
1649                 if (i < 3) {
1650                         mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i);
1651                         continue;
1652                 }
1653
1654                 /* Some mib are 64 bit wide */
1655                 if (mib->size == 2)
1656                         mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2);
1657                 else
1658                         mib_eth_data->data[i] = get_unaligned_le32(data2);
1659
1660                 data2 += mib->size;
1661         }
1662
1663 exit:
1664         /* Complete on receiving all the mib packet */
1665         if (refcount_dec_and_test(&mib_eth_data->port_parsed))
1666                 complete(&mib_eth_data->rw_done);
1667 }
1668
1669 static int
1670 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
1671 {
1672         struct dsa_port *dp = dsa_to_port(ds, port);
1673         struct qca8k_mib_eth_data *mib_eth_data;
1674         struct qca8k_priv *priv = ds->priv;
1675         int ret;
1676
1677         mib_eth_data = &priv->mib_eth_data;
1678
1679         mutex_lock(&mib_eth_data->mutex);
1680
1681         reinit_completion(&mib_eth_data->rw_done);
1682
1683         mib_eth_data->req_port = dp->index;
1684         mib_eth_data->data = data;
1685         refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
1686
1687         mutex_lock(&priv->reg_mutex);
1688
1689         /* Send mib autocast request */
1690         ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
1691                                  QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
1692                                  FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
1693                                  QCA8K_MIB_BUSY);
1694
1695         mutex_unlock(&priv->reg_mutex);
1696
1697         if (ret)
1698                 goto exit;
1699
1700         ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
1701
1702 exit:
1703         mutex_unlock(&mib_eth_data->mutex);
1704
1705         return ret;
1706 }
1707
1708 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1709 {
1710         struct qca8k_priv *priv = ds->priv;
1711
1712         /* Communicate to the phy internal driver the switch revision.
1713          * Based on the switch revision different values needs to be
1714          * set to the dbg and mmd reg on the phy.
1715          * The first 2 bit are used to communicate the switch revision
1716          * to the phy driver.
1717          */
1718         if (port > 0 && port < 6)
1719                 return priv->switch_revision;
1720
1721         return 0;
1722 }
1723
1724 static enum dsa_tag_protocol
1725 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1726                        enum dsa_tag_protocol mp)
1727 {
1728         return DSA_TAG_PROTO_QCA;
1729 }
1730
1731 static void
1732 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
1733                     bool operational)
1734 {
1735         struct dsa_port *dp = master->dsa_ptr;
1736         struct qca8k_priv *priv = ds->priv;
1737
1738         /* Ethernet MIB/MDIO is only supported for CPU port 0 */
1739         if (dp->index != 0)
1740                 return;
1741
1742         mutex_lock(&priv->mgmt_eth_data.mutex);
1743         mutex_lock(&priv->mib_eth_data.mutex);
1744
1745         priv->mgmt_master = operational ? (struct net_device *)master : NULL;
1746
1747         mutex_unlock(&priv->mib_eth_data.mutex);
1748         mutex_unlock(&priv->mgmt_eth_data.mutex);
1749 }
1750
1751 static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
1752                                       enum dsa_tag_protocol proto)
1753 {
1754         struct qca_tagger_data *tagger_data;
1755
1756         switch (proto) {
1757         case DSA_TAG_PROTO_QCA:
1758                 tagger_data = ds->tagger_data;
1759
1760                 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
1761                 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
1762
1763                 break;
1764         default:
1765                 return -EOPNOTSUPP;
1766         }
1767
1768         return 0;
1769 }
1770
1771 static int
1772 qca8k_setup(struct dsa_switch *ds)
1773 {
1774         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1775         int cpu_port, ret, i;
1776         u32 mask;
1777
1778         cpu_port = qca8k_find_cpu_port(ds);
1779         if (cpu_port < 0) {
1780                 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1781                 return cpu_port;
1782         }
1783
1784         /* Parse CPU port config to be later used in phy_link mac_config */
1785         ret = qca8k_parse_port_config(priv);
1786         if (ret)
1787                 return ret;
1788
1789         ret = qca8k_setup_mdio_bus(priv);
1790         if (ret)
1791                 return ret;
1792
1793         ret = qca8k_setup_of_pws_reg(priv);
1794         if (ret)
1795                 return ret;
1796
1797         ret = qca8k_setup_mac_pwr_sel(priv);
1798         if (ret)
1799                 return ret;
1800
1801         qca8k_setup_pcs(priv, &priv->pcs_port_0, 0);
1802         qca8k_setup_pcs(priv, &priv->pcs_port_6, 6);
1803
1804         /* Make sure MAC06 is disabled */
1805         ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1806                                 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1807         if (ret) {
1808                 dev_err(priv->dev, "failed disabling MAC06 exchange");
1809                 return ret;
1810         }
1811
1812         /* Enable CPU Port */
1813         ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1814                               QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1815         if (ret) {
1816                 dev_err(priv->dev, "failed enabling CPU port");
1817                 return ret;
1818         }
1819
1820         /* Enable MIB counters */
1821         ret = qca8k_mib_init(priv);
1822         if (ret)
1823                 dev_warn(priv->dev, "mib init failed");
1824
1825         /* Initial setup of all ports */
1826         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1827                 /* Disable forwarding by default on all ports */
1828                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1829                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
1830                 if (ret)
1831                         return ret;
1832
1833                 /* Enable QCA header mode on all cpu ports */
1834                 if (dsa_is_cpu_port(ds, i)) {
1835                         ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1836                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1837                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1838                         if (ret) {
1839                                 dev_err(priv->dev, "failed enabling QCA header mode");
1840                                 return ret;
1841                         }
1842                 }
1843
1844                 /* Disable MAC by default on all user ports */
1845                 if (dsa_is_user_port(ds, i))
1846                         qca8k_port_set_status(priv, i, 0);
1847         }
1848
1849         /* Forward all unknown frames to CPU port for Linux processing
1850          * Notice that in multi-cpu config only one port should be set
1851          * for igmp, unknown, multicast and broadcast packet
1852          */
1853         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1854                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1855                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1856                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1857                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1858         if (ret)
1859                 return ret;
1860
1861         /* Setup connection between CPU port & user ports
1862          * Configure specific switch configuration for ports
1863          */
1864         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1865                 /* CPU port gets connected to all user ports of the switch */
1866                 if (dsa_is_cpu_port(ds, i)) {
1867                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1868                                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1869                         if (ret)
1870                                 return ret;
1871                 }
1872
1873                 /* Individual user ports get connected to CPU port only */
1874                 if (dsa_is_user_port(ds, i)) {
1875                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1876                                         QCA8K_PORT_LOOKUP_MEMBER,
1877                                         BIT(cpu_port));
1878                         if (ret)
1879                                 return ret;
1880
1881                         /* Enable ARP Auto-learning by default */
1882                         ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
1883                                               QCA8K_PORT_LOOKUP_LEARN);
1884                         if (ret)
1885                                 return ret;
1886
1887                         /* For port based vlans to work we need to set the
1888                          * default egress vid
1889                          */
1890                         ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1891                                         QCA8K_EGREES_VLAN_PORT_MASK(i),
1892                                         QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
1893                         if (ret)
1894                                 return ret;
1895
1896                         ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1897                                           QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1898                                           QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1899                         if (ret)
1900                                 return ret;
1901                 }
1902
1903                 /* The port 5 of the qca8337 have some problem in flood condition. The
1904                  * original legacy driver had some specific buffer and priority settings
1905                  * for the different port suggested by the QCA switch team. Add this
1906                  * missing settings to improve switch stability under load condition.
1907                  * This problem is limited to qca8337 and other qca8k switch are not affected.
1908                  */
1909                 if (priv->switch_id == QCA8K_ID_QCA8337) {
1910                         switch (i) {
1911                         /* The 2 CPU port and port 5 requires some different
1912                          * priority than any other ports.
1913                          */
1914                         case 0:
1915                         case 5:
1916                         case 6:
1917                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1918                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1919                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1920                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1921                                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1922                                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1923                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1924                                 break;
1925                         default:
1926                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1927                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1928                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1929                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1930                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1931                         }
1932                         qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1933
1934                         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1935                         QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1936                         QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1937                         QCA8K_PORT_HOL_CTRL1_WRED_EN;
1938                         qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1939                                   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1940                                   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1941                                   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1942                                   QCA8K_PORT_HOL_CTRL1_WRED_EN,
1943                                   mask);
1944                 }
1945         }
1946
1947         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1948         if (priv->switch_id == QCA8K_ID_QCA8327) {
1949                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1950                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1951                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1952                           QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1953                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1954                           mask);
1955         }
1956
1957         /* Setup our port MTUs to match power on defaults */
1958         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1959         if (ret)
1960                 dev_warn(priv->dev, "failed setting MTU settings");
1961
1962         /* Flush the FDB table */
1963         qca8k_fdb_flush(priv);
1964
1965         /* Set min a max ageing value supported */
1966         ds->ageing_time_min = 7000;
1967         ds->ageing_time_max = 458745000;
1968
1969         /* Set max number of LAGs supported */
1970         ds->num_lag_ids = QCA8K_NUM_LAGS;
1971
1972         return 0;
1973 }
1974
1975 static const struct dsa_switch_ops qca8k_switch_ops = {
1976         .get_tag_protocol       = qca8k_get_tag_protocol,
1977         .setup                  = qca8k_setup,
1978         .get_strings            = qca8k_get_strings,
1979         .get_ethtool_stats      = qca8k_get_ethtool_stats,
1980         .get_sset_count         = qca8k_get_sset_count,
1981         .set_ageing_time        = qca8k_set_ageing_time,
1982         .get_mac_eee            = qca8k_get_mac_eee,
1983         .set_mac_eee            = qca8k_set_mac_eee,
1984         .port_enable            = qca8k_port_enable,
1985         .port_disable           = qca8k_port_disable,
1986         .port_change_mtu        = qca8k_port_change_mtu,
1987         .port_max_mtu           = qca8k_port_max_mtu,
1988         .port_stp_state_set     = qca8k_port_stp_state_set,
1989         .port_bridge_join       = qca8k_port_bridge_join,
1990         .port_bridge_leave      = qca8k_port_bridge_leave,
1991         .port_fast_age          = qca8k_port_fast_age,
1992         .port_fdb_add           = qca8k_port_fdb_add,
1993         .port_fdb_del           = qca8k_port_fdb_del,
1994         .port_fdb_dump          = qca8k_port_fdb_dump,
1995         .port_mdb_add           = qca8k_port_mdb_add,
1996         .port_mdb_del           = qca8k_port_mdb_del,
1997         .port_mirror_add        = qca8k_port_mirror_add,
1998         .port_mirror_del        = qca8k_port_mirror_del,
1999         .port_vlan_filtering    = qca8k_port_vlan_filtering,
2000         .port_vlan_add          = qca8k_port_vlan_add,
2001         .port_vlan_del          = qca8k_port_vlan_del,
2002         .phylink_get_caps       = qca8k_phylink_get_caps,
2003         .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs,
2004         .phylink_mac_config     = qca8k_phylink_mac_config,
2005         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
2006         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
2007         .get_phy_flags          = qca8k_get_phy_flags,
2008         .port_lag_join          = qca8k_port_lag_join,
2009         .port_lag_leave         = qca8k_port_lag_leave,
2010         .master_state_change    = qca8k_master_change,
2011         .connect_tag_protocol   = qca8k_connect_tag_protocol,
2012 };
2013
2014 static int
2015 qca8k_sw_probe(struct mdio_device *mdiodev)
2016 {
2017         struct qca8k_priv *priv;
2018         int ret;
2019
2020         /* allocate the private data struct so that we can probe the switches
2021          * ID register
2022          */
2023         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2024         if (!priv)
2025                 return -ENOMEM;
2026
2027         priv->bus = mdiodev->bus;
2028         priv->dev = &mdiodev->dev;
2029         priv->info = of_device_get_match_data(priv->dev);
2030
2031         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2032                                                    GPIOD_ASIS);
2033         if (IS_ERR(priv->reset_gpio))
2034                 return PTR_ERR(priv->reset_gpio);
2035
2036         if (priv->reset_gpio) {
2037                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2038                 /* The active low duration must be greater than 10 ms
2039                  * and checkpatch.pl wants 20 ms.
2040                  */
2041                 msleep(20);
2042                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2043         }
2044
2045         /* Start by setting up the register mapping */
2046         priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
2047                                         &qca8k_regmap_config);
2048         if (IS_ERR(priv->regmap)) {
2049                 dev_err(priv->dev, "regmap initialization failed");
2050                 return PTR_ERR(priv->regmap);
2051         }
2052
2053         priv->mdio_cache.page = 0xffff;
2054
2055         /* Check the detected switch id */
2056         ret = qca8k_read_switch_id(priv);
2057         if (ret)
2058                 return ret;
2059
2060         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2061         if (!priv->ds)
2062                 return -ENOMEM;
2063
2064         mutex_init(&priv->mgmt_eth_data.mutex);
2065         init_completion(&priv->mgmt_eth_data.rw_done);
2066
2067         mutex_init(&priv->mib_eth_data.mutex);
2068         init_completion(&priv->mib_eth_data.rw_done);
2069
2070         priv->ds->dev = &mdiodev->dev;
2071         priv->ds->num_ports = QCA8K_NUM_PORTS;
2072         priv->ds->priv = priv;
2073         priv->ds->ops = &qca8k_switch_ops;
2074         mutex_init(&priv->reg_mutex);
2075         dev_set_drvdata(&mdiodev->dev, priv);
2076
2077         return dsa_register_switch(priv->ds);
2078 }
2079
2080 static void
2081 qca8k_sw_remove(struct mdio_device *mdiodev)
2082 {
2083         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2084         int i;
2085
2086         if (!priv)
2087                 return;
2088
2089         for (i = 0; i < QCA8K_NUM_PORTS; i++)
2090                 qca8k_port_set_status(priv, i, 0);
2091
2092         dsa_unregister_switch(priv->ds);
2093 }
2094
2095 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2096 {
2097         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2098
2099         if (!priv)
2100                 return;
2101
2102         dsa_switch_shutdown(priv->ds);
2103
2104         dev_set_drvdata(&mdiodev->dev, NULL);
2105 }
2106
2107 #ifdef CONFIG_PM_SLEEP
2108 static void
2109 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2110 {
2111         int port;
2112
2113         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
2114                 /* Do not enable on resume if the port was
2115                  * disabled before.
2116                  */
2117                 if (!(priv->port_enabled_map & BIT(port)))
2118                         continue;
2119
2120                 qca8k_port_set_status(priv, port, enable);
2121         }
2122 }
2123
2124 static int qca8k_suspend(struct device *dev)
2125 {
2126         struct qca8k_priv *priv = dev_get_drvdata(dev);
2127
2128         qca8k_set_pm(priv, 0);
2129
2130         return dsa_switch_suspend(priv->ds);
2131 }
2132
2133 static int qca8k_resume(struct device *dev)
2134 {
2135         struct qca8k_priv *priv = dev_get_drvdata(dev);
2136
2137         qca8k_set_pm(priv, 1);
2138
2139         return dsa_switch_resume(priv->ds);
2140 }
2141 #endif /* CONFIG_PM_SLEEP */
2142
2143 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2144                          qca8k_suspend, qca8k_resume);
2145
2146 static const struct qca8k_info_ops qca8xxx_ops = {
2147         .autocast_mib = qca8k_get_ethtool_stats_eth,
2148 };
2149
2150 static const struct qca8k_match_data qca8327 = {
2151         .id = QCA8K_ID_QCA8327,
2152         .reduced_package = true,
2153         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2154         .ops = &qca8xxx_ops,
2155 };
2156
2157 static const struct qca8k_match_data qca8328 = {
2158         .id = QCA8K_ID_QCA8327,
2159         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2160         .ops = &qca8xxx_ops,
2161 };
2162
2163 static const struct qca8k_match_data qca833x = {
2164         .id = QCA8K_ID_QCA8337,
2165         .mib_count = QCA8K_QCA833X_MIB_COUNT,
2166         .ops = &qca8xxx_ops,
2167 };
2168
2169 static const struct of_device_id qca8k_of_match[] = {
2170         { .compatible = "qca,qca8327", .data = &qca8327 },
2171         { .compatible = "qca,qca8328", .data = &qca8328 },
2172         { .compatible = "qca,qca8334", .data = &qca833x },
2173         { .compatible = "qca,qca8337", .data = &qca833x },
2174         { /* sentinel */ },
2175 };
2176
2177 static struct mdio_driver qca8kmdio_driver = {
2178         .probe  = qca8k_sw_probe,
2179         .remove = qca8k_sw_remove,
2180         .shutdown = qca8k_sw_shutdown,
2181         .mdiodrv.driver = {
2182                 .name = "qca8k",
2183                 .of_match_table = qca8k_of_match,
2184                 .pm = &qca8k_pm_ops,
2185         },
2186 };
2187
2188 mdio_module_driver(qca8kmdio_driver);
2189
2190 MODULE_AUTHOR("Mathieu Olivari, John Crispin <[email protected]>");
2191 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2192 MODULE_LICENSE("GPL v2");
2193 MODULE_ALIAS("platform:qca8k");