drivers/clk/mmp/clk-mmp2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * mmp2 clock framework source file
   4  *
   5  * Copyright (C) 2012 Marvell
   6  * Chao Xie <[email protected]>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/spinlock.h>
  13 #include <linux/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk/mmp.h>
  17
  18 #include "clk.h"
  19
  20 #define APBC_RTC        0x0
  21 #define APBC_TWSI0      0x4
  22 #define APBC_TWSI1      0x8
  23 #define APBC_TWSI2      0xc
  24 #define APBC_TWSI3      0x10
  25 #define APBC_TWSI4      0x7c
  26 #define APBC_TWSI5      0x80
  27 #define APBC_KPC        0x18
  28 #define APBC_UART0      0x2c
  29 #define APBC_UART1      0x30
  30 #define APBC_UART2      0x34
  31 #define APBC_UART3      0x88
  32 #define APBC_GPIO       0x38
  33 #define APBC_PWM0       0x3c
  34 #define APBC_PWM1       0x40
  35 #define APBC_PWM2       0x44
  36 #define APBC_PWM3       0x48
  37 #define APBC_SSP0       0x50
  38 #define APBC_SSP1       0x54
  39 #define APBC_SSP2       0x58
  40 #define APBC_SSP3       0x5c
  41 #define APMU_SDH0       0x54
  42 #define APMU_SDH1       0x58
  43 #define APMU_SDH2       0xe8
  44 #define APMU_SDH3       0xec
  45 #define APMU_USB        0x5c
  46 #define APMU_DISP0      0x4c
  47 #define APMU_DISP1      0x110
  48 #define APMU_CCIC0      0x50
  49 #define APMU_CCIC1      0xf4
  50 #define MPMU_UART_PLL   0x14
  51
  52 static DEFINE_SPINLOCK(clk_lock);
  53
  54 static struct mmp_clk_factor_masks uart_factor_masks = {
  55         .factor = 2,
  56         .num_mask = 0x1fff,
  57         .den_mask = 0x1fff,
  58         .num_shift = 16,
  59         .den_shift = 0,
  60 };
  61
  62 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  63         {.num = 8125, .den = 1536},     /*14.745MHZ */
  64         {.num = 3521, .den = 689},      /*19.23MHZ */
  65 };
  66
  67 static const char *uart_parent[] = {"uart_pll", "vctcxo"};
  68 static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  69 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  70 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  71 static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
  72
  73 void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  74                           phys_addr_t apbc_phys)
  75 {
  76         struct clk *clk;
  77         struct clk *vctcxo;
  78         void __iomem *mpmu_base;
  79         void __iomem *apmu_base;
  80         void __iomem *apbc_base;
  81
  82         mpmu_base = ioremap(mpmu_phys, SZ_4K);
  83         if (!mpmu_base) {
  84                 pr_err("error to ioremap MPMU base\n");
  85                 return;
  86         }
  87
  88         apmu_base = ioremap(apmu_phys, SZ_4K);
  89         if (!apmu_base) {
  90                 pr_err("error to ioremap APMU base\n");
  91                 return;
  92         }
  93
  94         apbc_base = ioremap(apbc_phys, SZ_4K);
  95         if (!apbc_base) {
  96                 pr_err("error to ioremap APBC base\n");
  97                 return;
  98         }
  99
 100         clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
 101         clk_register_clkdev(clk, "clk32", NULL);
 102
 103         vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
 104         clk_register_clkdev(vctcxo, "vctcxo", NULL);
 105
 106         clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
 107         clk_register_clkdev(clk, "pll1", NULL);
 108
 109         clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
 110         clk_register_clkdev(clk, "usb_pll", NULL);
 111
 112         clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
 113         clk_register_clkdev(clk, "pll2", NULL);
 114
 115         clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
 116                                 CLK_SET_RATE_PARENT, 1, 2);
 117         clk_register_clkdev(clk, "pll1_2", NULL);
 118
 119         clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
 120                                 CLK_SET_RATE_PARENT, 1, 2);
 121         clk_register_clkdev(clk, "pll1_4", NULL);
 122
 123         clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
 124                                 CLK_SET_RATE_PARENT, 1, 2);
 125         clk_register_clkdev(clk, "pll1_8", NULL);
 126
 127         clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
 128                                 CLK_SET_RATE_PARENT, 1, 2);
 129         clk_register_clkdev(clk, "pll1_16", NULL);
 130
 131         clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
 132                                 CLK_SET_RATE_PARENT, 1, 5);
 133         clk_register_clkdev(clk, "pll1_20", NULL);
 134
 135         clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
 136                                 CLK_SET_RATE_PARENT, 1, 3);
 137         clk_register_clkdev(clk, "pll1_3", NULL);
 138
 139         clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
 140                                 CLK_SET_RATE_PARENT, 1, 2);
 141         clk_register_clkdev(clk, "pll1_6", NULL);
 142
 143         clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
 144                                 CLK_SET_RATE_PARENT, 1, 2);
 145         clk_register_clkdev(clk, "pll1_12", NULL);
 146
 147         clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
 148                                 CLK_SET_RATE_PARENT, 1, 2);
 149         clk_register_clkdev(clk, "pll2_2", NULL);
 150
 151         clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
 152                                 CLK_SET_RATE_PARENT, 1, 2);
 153         clk_register_clkdev(clk, "pll2_4", NULL);
 154
 155         clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
 156                                 CLK_SET_RATE_PARENT, 1, 2);
 157         clk_register_clkdev(clk, "pll2_8", NULL);
 158
 159         clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
 160                                 CLK_SET_RATE_PARENT, 1, 2);
 161         clk_register_clkdev(clk, "pll2_16", NULL);
 162
 163         clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
 164                                 CLK_SET_RATE_PARENT, 1, 3);
 165         clk_register_clkdev(clk, "pll2_3", NULL);
 166
 167         clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
 168                                 CLK_SET_RATE_PARENT, 1, 2);
 169         clk_register_clkdev(clk, "pll2_6", NULL);
 170
 171         clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
 172                                 CLK_SET_RATE_PARENT, 1, 2);
 173         clk_register_clkdev(clk, "pll2_12", NULL);
 174
 175         clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
 176                                 CLK_SET_RATE_PARENT, 1, 2);
 177         clk_register_clkdev(clk, "vctcxo_2", NULL);
 178
 179         clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
 180                                 CLK_SET_RATE_PARENT, 1, 2);
 181         clk_register_clkdev(clk, "vctcxo_4", NULL);
 182
 183         clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
 184                                 mpmu_base + MPMU_UART_PLL,
 185                                 &uart_factor_masks, uart_factor_tbl,
 186                                 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
 187         clk_set_rate(clk, 14745600);
 188         clk_register_clkdev(clk, "uart_pll", NULL);
 189
 190         clk = mmp_clk_register_apbc("twsi0", "vctcxo",
 191                                 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
 192         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
 193
 194         clk = mmp_clk_register_apbc("twsi1", "vctcxo",
 195                                 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
 196         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
 197
 198         clk = mmp_clk_register_apbc("twsi2", "vctcxo",
 199                                 apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
 200         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
 201
 202         clk = mmp_clk_register_apbc("twsi3", "vctcxo",
 203                                 apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
 204         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
 205
 206         clk = mmp_clk_register_apbc("twsi4", "vctcxo",
 207                                 apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
 208         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
 209
 210         clk = mmp_clk_register_apbc("twsi5", "vctcxo",
 211                                 apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
 212         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
 213
 214         clk = mmp_clk_register_apbc("gpio", "vctcxo",
 215                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
 216         clk_register_clkdev(clk, NULL, "mmp2-gpio");
 217
 218         clk = mmp_clk_register_apbc("kpc", "clk32",
 219                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
 220         clk_register_clkdev(clk, NULL, "pxa27x-keypad");
 221
 222         clk = mmp_clk_register_apbc("rtc", "clk32",
 223                                 apbc_base + APBC_RTC, 10, 0, &clk_lock);
 224         clk_register_clkdev(clk, NULL, "mmp-rtc");
 225
 226         clk = mmp_clk_register_apbc("pwm0", "vctcxo",
 227                                 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
 228         clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
 229
 230         clk = mmp_clk_register_apbc("pwm1", "vctcxo",
 231                                 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
 232         clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
 233
 234         clk = mmp_clk_register_apbc("pwm2", "vctcxo",
 235                                 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
 236         clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
 237
 238         clk = mmp_clk_register_apbc("pwm3", "vctcxo",
 239                                 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
 240         clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
 241
 242         clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
 243                                 ARRAY_SIZE(uart_parent),
 244                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 245                                 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 246         clk_set_parent(clk, vctcxo);
 247         clk_register_clkdev(clk, "uart_mux.0", NULL);
 248
 249         clk = mmp_clk_register_apbc("uart0", "uart0_mux",
 250                                 apbc_base + APBC_UART0, 10, 0, &clk_lock);
 251         clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 252
 253         clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
 254                                 ARRAY_SIZE(uart_parent),
 255                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 256                                 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 257         clk_set_parent(clk, vctcxo);
 258         clk_register_clkdev(clk, "uart_mux.1", NULL);
 259
 260         clk = mmp_clk_register_apbc("uart1", "uart1_mux",
 261                                 apbc_base + APBC_UART1, 10, 0, &clk_lock);
 262         clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 263
 264         clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
 265                                 ARRAY_SIZE(uart_parent),
 266                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 267                                 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 268         clk_set_parent(clk, vctcxo);
 269         clk_register_clkdev(clk, "uart_mux.2", NULL);
 270
 271         clk = mmp_clk_register_apbc("uart2", "uart2_mux",
 272                                 apbc_base + APBC_UART2, 10, 0, &clk_lock);
 273         clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 274
 275         clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
 276                                 ARRAY_SIZE(uart_parent),
 277                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 278                                 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
 279         clk_set_parent(clk, vctcxo);
 280         clk_register_clkdev(clk, "uart_mux.3", NULL);
 281
 282         clk = mmp_clk_register_apbc("uart3", "uart3_mux",
 283                                 apbc_base + APBC_UART3, 10, 0, &clk_lock);
 284         clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
 285
 286         clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
 287                                 ARRAY_SIZE(ssp_parent),
 288                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 289                                 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 290         clk_register_clkdev(clk, "uart_mux.0", NULL);
 291
 292         clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
 293                                 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
 294         clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 295
 296         clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
 297                                 ARRAY_SIZE(ssp_parent),
 298                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 299                                 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 300         clk_register_clkdev(clk, "ssp_mux.1", NULL);
 301
 302         clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
 303                                 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
 304         clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 305
 306         clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
 307                                 ARRAY_SIZE(ssp_parent),
 308                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 309                                 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 310         clk_register_clkdev(clk, "ssp_mux.2", NULL);
 311
 312         clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
 313                                 apbc_base + APBC_SSP2, 10, 0, &clk_lock);
 314         clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 315
 316         clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
 317                                 ARRAY_SIZE(ssp_parent),
 318                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 319                                 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 320         clk_register_clkdev(clk, "ssp_mux.3", NULL);
 321
 322         clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
 323                                 apbc_base + APBC_SSP3, 10, 0, &clk_lock);
 324         clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 325
 326         clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
 327                                 ARRAY_SIZE(sdh_parent),
 328                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 329                                 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
 330         clk_register_clkdev(clk, "sdh_mux", NULL);
 331
 332         clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
 333                                 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
 334                                 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 335         clk_register_clkdev(clk, "sdh_div", NULL);
 336
 337         clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
 338                                 0x1b, &clk_lock);
 339         clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
 340
 341         clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
 342                                 0x1b, &clk_lock);
 343         clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
 344
 345         clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
 346                                 0x1b, &clk_lock);
 347         clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
 348
 349         clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
 350                                 0x1b, &clk_lock);
 351         clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
 352
 353         clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
 354                                 0x9, &clk_lock);
 355         clk_register_clkdev(clk, "usb_clk", NULL);
 356
 357         clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
 358                                 ARRAY_SIZE(disp_parent),
 359                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 360                                 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
 361         clk_register_clkdev(clk, "disp_mux.0", NULL);
 362
 363         clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
 364                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
 365                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 366         clk_register_clkdev(clk, "disp_div.0", NULL);
 367
 368         clk = mmp_clk_register_apmu("disp0", "disp0_div",
 369                                 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
 370         clk_register_clkdev(clk, NULL, "mmp-disp.0");
 371
 372         clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
 373                                 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
 374         clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
 375
 376         clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
 377                                 apmu_base + APMU_DISP0, 0x1024, &clk_lock);
 378         clk_register_clkdev(clk, "disp_sphy.0", NULL);
 379
 380         clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
 381                                 ARRAY_SIZE(disp_parent),
 382                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 383                                 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
 384         clk_register_clkdev(clk, "disp_mux.1", NULL);
 385
 386         clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
 387                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
 388                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 389         clk_register_clkdev(clk, "disp_div.1", NULL);
 390
 391         clk = mmp_clk_register_apmu("disp1", "disp1_div",
 392                                 apmu_base + APMU_DISP1, 0x1b, &clk_lock);
 393         clk_register_clkdev(clk, NULL, "mmp-disp.1");
 394
 395         clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
 396                                 apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
 397         clk_register_clkdev(clk, "ccic_arbiter", NULL);
 398
 399         clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
 400                                 ARRAY_SIZE(ccic_parent),
 401                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 402                                 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
 403         clk_register_clkdev(clk, "ccic_mux.0", NULL);
 404
 405         clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
 406                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 407                                 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 408         clk_register_clkdev(clk, "ccic_div.0", NULL);
 409
 410         clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
 411                                 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
 412         clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
 413
 414         clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
 415                                 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
 416         clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
 417
 418         clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
 419                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 420                                 10, 5, 0, &clk_lock);
 421         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
 422
 423         clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
 424                                 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
 425         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
 426
 427         clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
 428                                 ARRAY_SIZE(ccic_parent),
 429                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 430                                 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
 431         clk_register_clkdev(clk, "ccic_mux.1", NULL);
 432
 433         clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
 434                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 435                                 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 436         clk_register_clkdev(clk, "ccic_div.1", NULL);
 437
 438         clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
 439                                 apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
 440         clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
 441
 442         clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
 443                                 apmu_base + APMU_CCIC1, 0x24, &clk_lock);
 444         clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
 445
 446         clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
 447                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 448                                 10, 5, 0, &clk_lock);
 449         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
 450
 451         clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
 452                                 apmu_base + APMU_CCIC1, 0x300, &clk_lock);
 453         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
 454 }