drivers/clk/mediatek/clk-mt2701-g3d.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Sean Wang <[email protected]>
   5  *
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "clk-mtk.h"
  15 #include "clk-gate.h"
  16
  17 #include <dt-bindings/clock/mt2701-clk.h>
  18
  19 #define GATE_G3D(_id, _name, _parent, _shift) { \
  20                 .id = _id,                              \
  21                 .name = _name,                          \
  22                 .parent_name = _parent,                 \
  23                 .regs = &g3d_cg_regs,                   \
  24                 .shift = _shift,                        \
  25                 .ops = &mtk_clk_gate_ops_setclr,        \
  26         }
  27
  28 static const struct mtk_gate_regs g3d_cg_regs = {
  29         .sta_ofs = 0x0,
  30         .set_ofs = 0x4,
  31         .clr_ofs = 0x8,
  32 };
  33
  34 static const struct mtk_gate g3d_clks[] = {
  35         GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
  36 };
  37
  38 static u16 rst_ofs[] = { 0xc, };
  39
  40 static const struct mtk_clk_rst_desc clk_rst_desc = {
  41         .version = MTK_RST_SIMPLE,
  42         .rst_bank_ofs = rst_ofs,
  43         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
  44 };
  45
  46 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
  47 {
  48         struct clk_hw_onecell_data *clk_data;
  49         struct device_node *node = pdev->dev.of_node;
  50         int r;
  51
  52         clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
  53
  54         mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
  55                                clk_data);
  56
  57         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  58         if (r)
  59                 dev_err(&pdev->dev,
  60                         "could not register clock provider: %s: %d\n",
  61                         pdev->name, r);
  62
  63         mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
  64
  65         return r;
  66 }
  67
  68 static const struct of_device_id of_match_clk_mt2701_g3d[] = {
  69         {
  70                 .compatible = "mediatek,mt2701-g3dsys",
  71                 .data = clk_mt2701_g3dsys_init,
  72         }, {
  73                 /* sentinel */
  74         }
  75 };
  76
  77 static int clk_mt2701_g3d_probe(struct platform_device *pdev)
  78 {
  79         int (*clk_init)(struct platform_device *);
  80         int r;
  81
  82         clk_init = of_device_get_match_data(&pdev->dev);
  83         if (!clk_init)
  84                 return -EINVAL;
  85
  86         r = clk_init(pdev);
  87         if (r)
  88                 dev_err(&pdev->dev,
  89                         "could not register clock provider: %s: %d\n",
  90                         pdev->name, r);
  91
  92         return r;
  93 }
  94
  95 static struct platform_driver clk_mt2701_g3d_drv = {
  96         .probe = clk_mt2701_g3d_probe,
  97         .driver = {
  98                 .name = "clk-mt2701-g3d",
  99                 .of_match_table = of_match_clk_mt2701_g3d,
 100         },
 101 };
 102
 103 builtin_platform_driver(clk_mt2701_g3d_drv);