drivers/pwm/pwm-samsung.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2007 Ben Dooks
   4  * Copyright (c) 2008 Simtec Electronics
   5  *     Ben Dooks <[email protected]>, <[email protected]>
   6  * Copyright (c) 2013 Tomasz Figa <[email protected]>
   7  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
   8  *
   9  * PWM driver for Samsung SoCs
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/export.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pwm.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/time.h>
  25
  26 /* For struct samsung_timer_variant and samsung_pwm_lock. */
  27 #include <clocksource/samsung_pwm.h>
  28
  29 #define REG_TCFG0                       0x00
  30 #define REG_TCFG1                       0x04
  31 #define REG_TCON                        0x08
  32
  33 #define REG_TCNTB(chan)                 (0x0c + ((chan) * 0xc))
  34 #define REG_TCMPB(chan)                 (0x10 + ((chan) * 0xc))
  35
  36 #define TCFG0_PRESCALER_MASK            0xff
  37 #define TCFG0_PRESCALER1_SHIFT          8
  38
  39 #define TCFG1_MUX_MASK                  0xf
  40 #define TCFG1_SHIFT(chan)               (4 * (chan))
  41
  42 /*
  43  * Each channel occupies 4 bits in TCON register, but there is a gap of 4
  44  * bits (one channel) after channel 0, so channels have different numbering
  45  * when accessing TCON register. See to_tcon_channel() function.
  46  *
  47  * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
  48  * in its set of bits is 2 as opposed to 3 for other channels.
  49  */
  50 #define TCON_START(chan)                BIT(4 * (chan) + 0)
  51 #define TCON_MANUALUPDATE(chan)         BIT(4 * (chan) + 1)
  52 #define TCON_INVERT(chan)               BIT(4 * (chan) + 2)
  53 #define _TCON_AUTORELOAD(chan)          BIT(4 * (chan) + 3)
  54 #define _TCON_AUTORELOAD4(chan)         BIT(4 * (chan) + 2)
  55 #define TCON_AUTORELOAD(chan)           \
  56         ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
  57
  58 /**
  59  * struct samsung_pwm_channel - private data of PWM channel
  60  * @period_ns:  current period in nanoseconds programmed to the hardware
  61  * @duty_ns:    current duty time in nanoseconds programmed to the hardware
  62  * @tin_ns:     time of one timer tick in nanoseconds with current timer rate
  63  */
  64 struct samsung_pwm_channel {
  65         u32 period_ns;
  66         u32 duty_ns;
  67         u32 tin_ns;
  68 };
  69
  70 /**
  71  * struct samsung_pwm_chip - private data of PWM chip
  72  * @chip:               generic PWM chip
  73  * @variant:            local copy of hardware variant data
  74  * @inverter_mask:      inverter status for all channels - one bit per channel
  75  * @disabled_mask:      disabled status for all channels - one bit per channel
  76  * @base:               base address of mapped PWM registers
  77  * @base_clk:           base clock used to drive the timers
  78  * @tclk0:              external clock 0 (can be ERR_PTR if not present)
  79  * @tclk1:              external clock 1 (can be ERR_PTR if not present)
  80  * @channel:            per channel driver data
  81  */
  82 struct samsung_pwm_chip {
  83         struct pwm_chip chip;
  84         struct samsung_pwm_variant variant;
  85         u8 inverter_mask;
  86         u8 disabled_mask;
  87
  88         void __iomem *base;
  89         struct clk *base_clk;
  90         struct clk *tclk0;
  91         struct clk *tclk1;
  92         struct samsung_pwm_channel channel[SAMSUNG_PWM_NUM];
  93 };
  94
  95 #ifndef CONFIG_CLKSRC_SAMSUNG_PWM
  96 /*
  97  * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
  98  * and some registers need access synchronization. If both drivers are
  99  * compiled in, the spinlock is defined in the clocksource driver,
 100  * otherwise following definition is used.
 101  *
 102  * Currently we do not need any more complex synchronization method
 103  * because all the supported SoCs contain only one instance of the PWM
 104  * IP. Should this change, both drivers will need to be modified to
 105  * properly synchronize accesses to particular instances.
 106  */
 107 static DEFINE_SPINLOCK(samsung_pwm_lock);
 108 #endif
 109
 110 static inline
 111 struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
 112 {
 113         return container_of(chip, struct samsung_pwm_chip, chip);
 114 }
 115
 116 static inline unsigned int to_tcon_channel(unsigned int channel)
 117 {
 118         /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
 119         return (channel == 0) ? 0 : (channel + 1);
 120 }
 121
 122 static void __pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
 123                                       struct pwm_device *pwm)
 124 {
 125         unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
 126         u32 tcon;
 127
 128         tcon = readl(our_chip->base + REG_TCON);
 129         tcon |= TCON_MANUALUPDATE(tcon_chan);
 130         writel(tcon, our_chip->base + REG_TCON);
 131
 132         tcon &= ~TCON_MANUALUPDATE(tcon_chan);
 133         writel(tcon, our_chip->base + REG_TCON);
 134 }
 135
 136 static void pwm_samsung_set_divisor(struct samsung_pwm_chip *our_chip,
 137                                     unsigned int channel, u8 divisor)
 138 {
 139         u8 shift = TCFG1_SHIFT(channel);
 140         unsigned long flags;
 141         u32 reg;
 142         u8 bits;
 143
 144         bits = (fls(divisor) - 1) - our_chip->variant.div_base;
 145
 146         spin_lock_irqsave(&samsung_pwm_lock, flags);
 147
 148         reg = readl(our_chip->base + REG_TCFG1);
 149         reg &= ~(TCFG1_MUX_MASK << shift);
 150         reg |= bits << shift;
 151         writel(reg, our_chip->base + REG_TCFG1);
 152
 153         spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 154 }
 155
 156 static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan)
 157 {
 158         struct samsung_pwm_variant *variant = &our_chip->variant;
 159         u32 reg;
 160
 161         reg = readl(our_chip->base + REG_TCFG1);
 162         reg >>= TCFG1_SHIFT(chan);
 163         reg &= TCFG1_MUX_MASK;
 164
 165         return (BIT(reg) & variant->tclk_mask) == 0;
 166 }
 167
 168 static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *our_chip,
 169                                               unsigned int chan)
 170 {
 171         unsigned long rate;
 172         u32 reg;
 173
 174         rate = clk_get_rate(our_chip->base_clk);
 175
 176         reg = readl(our_chip->base + REG_TCFG0);
 177         if (chan >= 2)
 178                 reg >>= TCFG0_PRESCALER1_SHIFT;
 179         reg &= TCFG0_PRESCALER_MASK;
 180
 181         return rate / (reg + 1);
 182 }
 183
 184 static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *our_chip,
 185                                           unsigned int chan, unsigned long freq)
 186 {
 187         struct samsung_pwm_variant *variant = &our_chip->variant;
 188         unsigned long rate;
 189         struct clk *clk;
 190         u8 div;
 191
 192         if (!pwm_samsung_is_tdiv(our_chip, chan)) {
 193                 clk = (chan < 2) ? our_chip->tclk0 : our_chip->tclk1;
 194                 if (!IS_ERR(clk)) {
 195                         rate = clk_get_rate(clk);
 196                         if (rate)
 197                                 return rate;
 198                 }
 199
 200                 dev_warn(our_chip->chip.dev,
 201                         "tclk of PWM %d is inoperational, using tdiv\n", chan);
 202         }
 203
 204         rate = pwm_samsung_get_tin_rate(our_chip, chan);
 205         dev_dbg(our_chip->chip.dev, "tin parent at %lu\n", rate);
 206
 207         /*
 208          * Compare minimum PWM frequency that can be achieved with possible
 209          * divider settings and choose the lowest divisor that can generate
 210          * frequencies lower than requested.
 211          */
 212         if (variant->bits < 32) {
 213                 /* Only for s3c24xx */
 214                 for (div = variant->div_base; div < 4; ++div)
 215                         if ((rate >> (variant->bits + div)) < freq)
 216                                 break;
 217         } else {
 218                 /*
 219                  * Other variants have enough counter bits to generate any
 220                  * requested rate, so no need to check higher divisors.
 221                  */
 222                 div = variant->div_base;
 223         }
 224
 225         pwm_samsung_set_divisor(our_chip, chan, BIT(div));
 226
 227         return rate >> div;
 228 }
 229
 230 static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
 231 {
 232         struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
 233
 234         if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
 235                 dev_warn(chip->dev,
 236                         "tried to request PWM channel %d without output\n",
 237                         pwm->hwpwm);
 238                 return -EINVAL;
 239         }
 240
 241         memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm]));
 242
 243         return 0;
 244 }
 245
 246 static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 247 {
 248         struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
 249         unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
 250         unsigned long flags;
 251         u32 tcon;
 252
 253         spin_lock_irqsave(&samsung_pwm_lock, flags);
 254
 255         tcon = readl(our_chip->base + REG_TCON);
 256
 257         tcon &= ~TCON_START(tcon_chan);
 258         tcon |= TCON_MANUALUPDATE(tcon_chan);
 259         writel(tcon, our_chip->base + REG_TCON);
 260
 261         tcon &= ~TCON_MANUALUPDATE(tcon_chan);
 262         tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
 263         writel(tcon, our_chip->base + REG_TCON);
 264
 265         our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
 266
 267         spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 268
 269         return 0;
 270 }
 271
 272 static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 273 {
 274         struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
 275         unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
 276         unsigned long flags;
 277         u32 tcon;
 278
 279         spin_lock_irqsave(&samsung_pwm_lock, flags);
 280
 281         tcon = readl(our_chip->base + REG_TCON);
 282         tcon &= ~TCON_AUTORELOAD(tcon_chan);
 283         writel(tcon, our_chip->base + REG_TCON);
 284
 285         /*
 286          * In case the PWM is at 100% duty cycle, force a manual
 287          * update to prevent the signal from staying high.
 288          */
 289         if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U)
 290                 __pwm_samsung_manual_update(our_chip, pwm);
 291
 292         our_chip->disabled_mask |= BIT(pwm->hwpwm);
 293
 294         spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 295 }
 296
 297 static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
 298                                       struct pwm_device *pwm)
 299 {
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&samsung_pwm_lock, flags);
 303
 304         __pwm_samsung_manual_update(our_chip, pwm);
 305
 306         spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 307 }
 308
 309 static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
 310                                 int duty_ns, int period_ns, bool force_period)
 311 {
 312         struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
 313         struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm];
 314         u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
 315
 316         tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
 317         oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
 318
 319         /* We need tick count for calculation, not last tick. */
 320         ++tcnt;
 321
 322         /* Check to see if we are changing the clock rate of the PWM. */
 323         if (chan->period_ns != period_ns || force_period) {
 324                 unsigned long tin_rate;
 325                 u32 period;
 326
 327                 period = NSEC_PER_SEC / period_ns;
 328
 329                 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
 330                                                 duty_ns, period_ns, period);
 331
 332                 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
 333
 334                 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
 335
 336                 tin_ns = NSEC_PER_SEC / tin_rate;
 337                 tcnt = period_ns / tin_ns;
 338         }
 339
 340         /* Period is too short. */
 341         if (tcnt <= 1)
 342                 return -ERANGE;
 343
 344         /* Note that counters count down. */
 345         tcmp = duty_ns / tin_ns;
 346
 347         /* 0% duty is not available */
 348         if (!tcmp)
 349                 ++tcmp;
 350
 351         tcmp = tcnt - tcmp;
 352
 353         /* Decrement to get tick numbers, instead of tick counts. */
 354         --tcnt;
 355         /* -1UL will give 100% duty. */
 356         --tcmp;
 357
 358         dev_dbg(our_chip->chip.dev,
 359                                 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
 360
 361         /* Update PWM registers. */
 362         writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
 363         writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
 364
 365         /*
 366          * In case the PWM is currently at 100% duty cycle, force a manual
 367          * update to prevent the signal staying high if the PWM is disabled
 368          * shortly afer this update (before it autoreloaded the new values).
 369          */
 370         if (oldtcmp == (u32) -1) {
 371                 dev_dbg(our_chip->chip.dev, "Forcing manual update");
 372                 pwm_samsung_manual_update(our_chip, pwm);
 373         }
 374
 375         chan->period_ns = period_ns;
 376         chan->tin_ns = tin_ns;
 377         chan->duty_ns = duty_ns;
 378
 379         return 0;
 380 }
 381
 382 static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
 383                               int duty_ns, int period_ns)
 384 {
 385         return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
 386 }
 387
 388 static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip,
 389                                    unsigned int channel, bool invert)
 390 {
 391         unsigned int tcon_chan = to_tcon_channel(channel);
 392         unsigned long flags;
 393         u32 tcon;
 394
 395         spin_lock_irqsave(&samsung_pwm_lock, flags);
 396
 397         tcon = readl(our_chip->base + REG_TCON);
 398
 399         if (invert) {
 400                 our_chip->inverter_mask |= BIT(channel);
 401                 tcon |= TCON_INVERT(tcon_chan);
 402         } else {
 403                 our_chip->inverter_mask &= ~BIT(channel);
 404                 tcon &= ~TCON_INVERT(tcon_chan);
 405         }
 406
 407         writel(tcon, our_chip->base + REG_TCON);
 408
 409         spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 410 }
 411
 412 static int pwm_samsung_set_polarity(struct pwm_chip *chip,
 413                                     struct pwm_device *pwm,
 414                                     enum pwm_polarity polarity)
 415 {
 416         struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
 417         bool invert = (polarity == PWM_POLARITY_NORMAL);
 418
 419         /* Inverted means normal in the hardware. */
 420         pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
 421
 422         return 0;
 423 }
 424
 425 static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 426                              const struct pwm_state *state)
 427 {
 428         int err, enabled = pwm->state.enabled;
 429
 430         if (state->polarity != pwm->state.polarity) {
 431                 if (enabled) {
 432                         pwm_samsung_disable(chip, pwm);
 433                         enabled = false;
 434                 }
 435
 436                 err = pwm_samsung_set_polarity(chip, pwm, state->polarity);
 437                 if (err)
 438                         return err;
 439         }
 440
 441         if (!state->enabled) {
 442                 if (enabled)
 443                         pwm_samsung_disable(chip, pwm);
 444
 445                 return 0;
 446         }
 447
 448         /*
 449          * We currently avoid using 64bit arithmetic by using the
 450          * fact that anything faster than 1Hz is easily representable
 451          * by 32bits.
 452          */
 453         if (state->period > NSEC_PER_SEC)
 454                 return -ERANGE;
 455
 456         err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period);
 457         if (err)
 458                 return err;
 459
 460         if (!pwm->state.enabled)
 461                 err = pwm_samsung_enable(chip, pwm);
 462
 463         return err;
 464 }
 465
 466 static const struct pwm_ops pwm_samsung_ops = {
 467         .request        = pwm_samsung_request,
 468         .apply          = pwm_samsung_apply,
 469 };
 470
 471 #ifdef CONFIG_OF
 472 static const struct samsung_pwm_variant s3c24xx_variant = {
 473         .bits           = 16,
 474         .div_base       = 1,
 475         .has_tint_cstat = false,
 476         .tclk_mask      = BIT(4),
 477 };
 478
 479 static const struct samsung_pwm_variant s3c64xx_variant = {
 480         .bits           = 32,
 481         .div_base       = 0,
 482         .has_tint_cstat = true,
 483         .tclk_mask      = BIT(7) | BIT(6) | BIT(5),
 484 };
 485
 486 static const struct samsung_pwm_variant s5p64x0_variant = {
 487         .bits           = 32,
 488         .div_base       = 0,
 489         .has_tint_cstat = true,
 490         .tclk_mask      = 0,
 491 };
 492
 493 static const struct samsung_pwm_variant s5pc100_variant = {
 494         .bits           = 32,
 495         .div_base       = 0,
 496         .has_tint_cstat = true,
 497         .tclk_mask      = BIT(5),
 498 };
 499
 500 static const struct of_device_id samsung_pwm_matches[] = {
 501         { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
 502         { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
 503         { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
 504         { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
 505         { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
 506         {},
 507 };
 508 MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
 509
 510 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *our_chip)
 511 {
 512         struct device_node *np = our_chip->chip.dev->of_node;
 513         const struct of_device_id *match;
 514         struct property *prop;
 515         const __be32 *cur;
 516         u32 val;
 517
 518         match = of_match_node(samsung_pwm_matches, np);
 519         if (!match)
 520                 return -ENODEV;
 521
 522         memcpy(&our_chip->variant, match->data, sizeof(our_chip->variant));
 523
 524         of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
 525                 if (val >= SAMSUNG_PWM_NUM) {
 526                         dev_err(our_chip->chip.dev,
 527                                 "%s: invalid channel index in samsung,pwm-outputs property\n",
 528                                                                 __func__);
 529                         continue;
 530                 }
 531                 our_chip->variant.output_mask |= BIT(val);
 532         }
 533
 534         return 0;
 535 }
 536 #else
 537 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *our_chip)
 538 {
 539         return -ENODEV;
 540 }
 541 #endif
 542
 543 static int pwm_samsung_probe(struct platform_device *pdev)
 544 {
 545         struct device *dev = &pdev->dev;
 546         struct samsung_pwm_chip *our_chip;
 547         unsigned int chan;
 548         int ret;
 549
 550         our_chip = devm_kzalloc(&pdev->dev, sizeof(*our_chip), GFP_KERNEL);
 551         if (our_chip == NULL)
 552                 return -ENOMEM;
 553
 554         our_chip->chip.dev = &pdev->dev;
 555         our_chip->chip.ops = &pwm_samsung_ops;
 556         our_chip->chip.npwm = SAMSUNG_PWM_NUM;
 557         our_chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 558
 559         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 560                 ret = pwm_samsung_parse_dt(our_chip);
 561                 if (ret)
 562                         return ret;
 563         } else {
 564                 if (!pdev->dev.platform_data) {
 565                         dev_err(&pdev->dev, "no platform data specified\n");
 566                         return -EINVAL;
 567                 }
 568
 569                 memcpy(&our_chip->variant, pdev->dev.platform_data,
 570                                                         sizeof(our_chip->variant));
 571         }
 572
 573         our_chip->base = devm_platform_ioremap_resource(pdev, 0);
 574         if (IS_ERR(our_chip->base))
 575                 return PTR_ERR(our_chip->base);
 576
 577         our_chip->base_clk = devm_clk_get(&pdev->dev, "timers");
 578         if (IS_ERR(our_chip->base_clk)) {
 579                 dev_err(dev, "failed to get timer base clk\n");
 580                 return PTR_ERR(our_chip->base_clk);
 581         }
 582
 583         ret = clk_prepare_enable(our_chip->base_clk);
 584         if (ret < 0) {
 585                 dev_err(dev, "failed to enable base clock\n");
 586                 return ret;
 587         }
 588
 589         for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
 590                 if (our_chip->variant.output_mask & BIT(chan))
 591                         pwm_samsung_set_invert(our_chip, chan, true);
 592
 593         /* Following clocks are optional. */
 594         our_chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
 595         our_chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
 596
 597         platform_set_drvdata(pdev, our_chip);
 598
 599         ret = pwmchip_add(&our_chip->chip);
 600         if (ret < 0) {
 601                 dev_err(dev, "failed to register PWM chip\n");
 602                 clk_disable_unprepare(our_chip->base_clk);
 603                 return ret;
 604         }
 605
 606         dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
 607                 clk_get_rate(our_chip->base_clk),
 608                 !IS_ERR(our_chip->tclk0) ? clk_get_rate(our_chip->tclk0) : 0,
 609                 !IS_ERR(our_chip->tclk1) ? clk_get_rate(our_chip->tclk1) : 0);
 610
 611         return 0;
 612 }
 613
 614 static void pwm_samsung_remove(struct platform_device *pdev)
 615 {
 616         struct samsung_pwm_chip *our_chip = platform_get_drvdata(pdev);
 617
 618         pwmchip_remove(&our_chip->chip);
 619
 620         clk_disable_unprepare(our_chip->base_clk);
 621 }
 622
 623 #ifdef CONFIG_PM_SLEEP
 624 static int pwm_samsung_resume(struct device *dev)
 625 {
 626         struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
 627         struct pwm_chip *chip = &our_chip->chip;
 628         unsigned int i;
 629
 630         for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
 631                 struct pwm_device *pwm = &chip->pwms[i];
 632                 struct samsung_pwm_channel *chan = &our_chip->channel[i];
 633
 634                 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
 635                         continue;
 636
 637                 if (our_chip->variant.output_mask & BIT(i))
 638                         pwm_samsung_set_invert(our_chip, i,
 639                                         our_chip->inverter_mask & BIT(i));
 640
 641                 if (chan->period_ns) {
 642                         __pwm_samsung_config(chip, pwm, chan->duty_ns,
 643                                              chan->period_ns, true);
 644                         /* needed to make PWM disable work on Odroid-XU3 */
 645                         pwm_samsung_manual_update(our_chip, pwm);
 646                 }
 647
 648                 if (our_chip->disabled_mask & BIT(i))
 649                         pwm_samsung_disable(chip, pwm);
 650                 else
 651                         pwm_samsung_enable(chip, pwm);
 652         }
 653
 654         return 0;
 655 }
 656 #endif
 657
 658 static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
 659
 660 static struct platform_driver pwm_samsung_driver = {
 661         .driver         = {
 662                 .name   = "samsung-pwm",
 663                 .pm     = &pwm_samsung_pm_ops,
 664                 .of_match_table = of_match_ptr(samsung_pwm_matches),
 665         },
 666         .probe          = pwm_samsung_probe,
 667         .remove_new     = pwm_samsung_remove,
 668 };
 669 module_platform_driver(pwm_samsung_driver);
 670
 671 MODULE_LICENSE("GPL");
 672 MODULE_AUTHOR("Tomasz Figa <[email protected]>");
 673 MODULE_ALIAS("platform:samsung-pwm");