drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <[email protected]>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT_MS     1000
  44
  45 /* Firmware Names */
  46 #ifdef CONFIG_DRM_AMDGPU_CIK
  47 #define FIRMWARE_BONAIRE        "radeon/bonaire_uvd.bin"
  48 #define FIRMWARE_KABINI         "radeon/kabini_uvd.bin"
  49 #define FIRMWARE_KAVERI         "radeon/kaveri_uvd.bin"
  50 #define FIRMWARE_HAWAII         "radeon/hawaii_uvd.bin"
  51 #define FIRMWARE_MULLINS        "radeon/mullins_uvd.bin"
  52 #endif
  53 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  54 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  55 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  56 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
  57 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
  58 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
  59
  60 /**
  61  * amdgpu_uvd_cs_ctx - Command submission parser context
  62  *
  63  * Used for emulating virtual memory support on UVD 4.2.
  64  */
  65 struct amdgpu_uvd_cs_ctx {
  66         struct amdgpu_cs_parser *parser;
  67         unsigned reg, count;
  68         unsigned data0, data1;
  69         unsigned idx;
  70         unsigned ib_idx;
  71
  72         /* does the IB has a msg command */
  73         bool has_msg_cmd;
  74
  75         /* minimum buffer sizes */
  76         unsigned *buf_sizes;
  77 };
  78
  79 #ifdef CONFIG_DRM_AMDGPU_CIK
  80 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  81 MODULE_FIRMWARE(FIRMWARE_KABINI);
  82 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  83 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  84 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  85 #endif
  86 MODULE_FIRMWARE(FIRMWARE_TONGA);
  87 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  88 MODULE_FIRMWARE(FIRMWARE_FIJI);
  89 MODULE_FIRMWARE(FIRMWARE_STONEY);
  90 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  91 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  92
  93 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
  94 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
  95
  96 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
  97 {
  98         struct amdgpu_ring *ring;
  99         struct amd_sched_rq *rq;
 100         unsigned long bo_size;
 101         const char *fw_name;
 102         const struct common_firmware_header *hdr;
 103         unsigned version_major, version_minor, family_id;
 104         int i, r;
 105
 106         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 107
 108         switch (adev->asic_type) {
 109 #ifdef CONFIG_DRM_AMDGPU_CIK
 110         case CHIP_BONAIRE:
 111                 fw_name = FIRMWARE_BONAIRE;
 112                 break;
 113         case CHIP_KABINI:
 114                 fw_name = FIRMWARE_KABINI;
 115                 break;
 116         case CHIP_KAVERI:
 117                 fw_name = FIRMWARE_KAVERI;
 118                 break;
 119         case CHIP_HAWAII:
 120                 fw_name = FIRMWARE_HAWAII;
 121                 break;
 122         case CHIP_MULLINS:
 123                 fw_name = FIRMWARE_MULLINS;
 124                 break;
 125 #endif
 126         case CHIP_TONGA:
 127                 fw_name = FIRMWARE_TONGA;
 128                 break;
 129         case CHIP_FIJI:
 130                 fw_name = FIRMWARE_FIJI;
 131                 break;
 132         case CHIP_CARRIZO:
 133                 fw_name = FIRMWARE_CARRIZO;
 134                 break;
 135         case CHIP_STONEY:
 136                 fw_name = FIRMWARE_STONEY;
 137                 break;
 138         case CHIP_POLARIS10:
 139                 fw_name = FIRMWARE_POLARIS10;
 140                 break;
 141         case CHIP_POLARIS11:
 142                 fw_name = FIRMWARE_POLARIS11;
 143                 break;
 144         default:
 145                 return -EINVAL;
 146         }
 147
 148         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 149         if (r) {
 150                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 151                         fw_name);
 152                 return r;
 153         }
 154
 155         r = amdgpu_ucode_validate(adev->uvd.fw);
 156         if (r) {
 157                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 158                         fw_name);
 159                 release_firmware(adev->uvd.fw);
 160                 adev->uvd.fw = NULL;
 161                 return r;
 162         }
 163
 164         /* Set the default UVD handles that the firmware can handle */
 165         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 166
 167         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 168         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 169         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 170         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 171         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 172                 version_major, version_minor, family_id);
 173
 174         /*
 175          * Limit the number of UVD handles depending on microcode major
 176          * and minor versions. The firmware version which has 40 UVD
 177          * instances support is 1.80. So all subsequent versions should
 178          * also have the same support.
 179          */
 180         if ((version_major > 0x01) ||
 181             ((version_major == 0x01) && (version_minor >= 0x50)))
 182                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 183
 184         adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 185                                 (family_id << 8));
 186
 187         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 188                   +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 189                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 190         r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
 191                              AMDGPU_GEM_DOMAIN_VRAM,
 192                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 193                              NULL, NULL, &adev->uvd.vcpu_bo);
 194         if (r) {
 195                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 196                 return r;
 197         }
 198
 199         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 200         if (r) {
 201                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 202                 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
 203                 return r;
 204         }
 205
 206         r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 207                           &adev->uvd.gpu_addr);
 208         if (r) {
 209                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 210                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 211                 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
 212                 return r;
 213         }
 214
 215         r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
 216         if (r) {
 217                 dev_err(adev->dev, "(%d) UVD map failed\n", r);
 218                 return r;
 219         }
 220
 221         amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 222
 223         ring = &adev->uvd.ring;
 224         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 225         r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
 226                                   rq, amdgpu_sched_jobs);
 227         if (r != 0) {
 228                 DRM_ERROR("Failed setting up UVD run queue.\n");
 229                 return r;
 230         }
 231
 232         for (i = 0; i < adev->uvd.max_handles; ++i) {
 233                 atomic_set(&adev->uvd.handles[i], 0);
 234                 adev->uvd.filp[i] = NULL;
 235         }
 236
 237         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 238         if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 239                 adev->uvd.address_64_bit = true;
 240
 241         return 0;
 242 }
 243
 244 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 245 {
 246         int r;
 247
 248         if (adev->uvd.vcpu_bo == NULL)
 249                 return 0;
 250
 251         amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
 252
 253         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 254         if (!r) {
 255                 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
 256                 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
 257                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 258         }
 259
 260         amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 261
 262         amdgpu_ring_fini(&adev->uvd.ring);
 263
 264         release_firmware(adev->uvd.fw);
 265
 266         return 0;
 267 }
 268
 269 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 270 {
 271         unsigned size;
 272         void *ptr;
 273         int i;
 274
 275         if (adev->uvd.vcpu_bo == NULL)
 276                 return 0;
 277
 278         for (i = 0; i < adev->uvd.max_handles; ++i)
 279                 if (atomic_read(&adev->uvd.handles[i]))
 280                         break;
 281
 282         if (i == AMDGPU_MAX_UVD_HANDLES)
 283                 return 0;
 284
 285         cancel_delayed_work_sync(&adev->uvd.idle_work);
 286
 287         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 288         ptr = adev->uvd.cpu_addr;
 289
 290         adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 291         if (!adev->uvd.saved_bo)
 292                 return -ENOMEM;
 293
 294         memcpy(adev->uvd.saved_bo, ptr, size);
 295
 296         return 0;
 297 }
 298
 299 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 300 {
 301         unsigned size;
 302         void *ptr;
 303
 304         if (adev->uvd.vcpu_bo == NULL)
 305                 return -EINVAL;
 306
 307         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 308         ptr = adev->uvd.cpu_addr;
 309
 310         if (adev->uvd.saved_bo != NULL) {
 311                 memcpy(ptr, adev->uvd.saved_bo, size);
 312                 kfree(adev->uvd.saved_bo);
 313                 adev->uvd.saved_bo = NULL;
 314         } else {
 315                 const struct common_firmware_header *hdr;
 316                 unsigned offset;
 317
 318                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 319                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 320                 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
 321                         (adev->uvd.fw->size) - offset);
 322                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 323                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 324                 memset(ptr, 0, size);
 325         }
 326
 327         return 0;
 328 }
 329
 330 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 331 {
 332         struct amdgpu_ring *ring = &adev->uvd.ring;
 333         int i, r;
 334
 335         for (i = 0; i < adev->uvd.max_handles; ++i) {
 336                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 337                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 338                         struct fence *fence;
 339
 340                         amdgpu_uvd_note_usage(adev);
 341
 342                         r = amdgpu_uvd_get_destroy_msg(ring, handle,
 343                                                        false, &fence);
 344                         if (r) {
 345                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 346                                 continue;
 347                         }
 348
 349                         fence_wait(fence, false);
 350                         fence_put(fence);
 351
 352                         adev->uvd.filp[i] = NULL;
 353                         atomic_set(&adev->uvd.handles[i], 0);
 354                 }
 355         }
 356 }
 357
 358 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
 359 {
 360         int i;
 361         for (i = 0; i < rbo->placement.num_placement; ++i) {
 362                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 363                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 364         }
 365 }
 366
 367 /**
 368  * amdgpu_uvd_cs_pass1 - first parsing round
 369  *
 370  * @ctx: UVD parser context
 371  *
 372  * Make sure UVD message and feedback buffers are in VRAM and
 373  * nobody is violating an 256MB boundary.
 374  */
 375 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 376 {
 377         struct amdgpu_bo_va_mapping *mapping;
 378         struct amdgpu_bo *bo;
 379         uint32_t cmd, lo, hi;
 380         uint64_t addr;
 381         int r = 0;
 382
 383         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 384         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 385         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 386
 387         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 388         if (mapping == NULL) {
 389                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 390                 return -EINVAL;
 391         }
 392
 393         if (!ctx->parser->adev->uvd.address_64_bit) {
 394                 /* check if it's a message or feedback command */
 395                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 396                 if (cmd == 0x0 || cmd == 0x3) {
 397                         /* yes, force it into VRAM */
 398                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 399                         amdgpu_ttm_placement_from_domain(bo, domain);
 400                 }
 401                 amdgpu_uvd_force_into_uvd_segment(bo);
 402
 403                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 404         }
 405
 406         return r;
 407 }
 408
 409 /**
 410  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 411  *
 412  * @msg: pointer to message structure
 413  * @buf_sizes: returned buffer sizes
 414  *
 415  * Peek into the decode message and calculate the necessary buffer sizes.
 416  */
 417 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 418 {
 419         unsigned stream_type = msg[4];
 420         unsigned width = msg[6];
 421         unsigned height = msg[7];
 422         unsigned dpb_size = msg[9];
 423         unsigned pitch = msg[28];
 424         unsigned level = msg[57];
 425
 426         unsigned width_in_mb = width / 16;
 427         unsigned height_in_mb = ALIGN(height / 16, 2);
 428         unsigned fs_in_mb = width_in_mb * height_in_mb;
 429
 430         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 431         unsigned min_ctx_size = 0;
 432
 433         image_size = width * height;
 434         image_size += image_size / 2;
 435         image_size = ALIGN(image_size, 1024);
 436
 437         switch (stream_type) {
 438         case 0: /* H264 */
 439         case 7: /* H264 Perf */
 440                 switch(level) {
 441                 case 30:
 442                         num_dpb_buffer = 8100 / fs_in_mb;
 443                         break;
 444                 case 31:
 445                         num_dpb_buffer = 18000 / fs_in_mb;
 446                         break;
 447                 case 32:
 448                         num_dpb_buffer = 20480 / fs_in_mb;
 449                         break;
 450                 case 41:
 451                         num_dpb_buffer = 32768 / fs_in_mb;
 452                         break;
 453                 case 42:
 454                         num_dpb_buffer = 34816 / fs_in_mb;
 455                         break;
 456                 case 50:
 457                         num_dpb_buffer = 110400 / fs_in_mb;
 458                         break;
 459                 case 51:
 460                         num_dpb_buffer = 184320 / fs_in_mb;
 461                         break;
 462                 default:
 463                         num_dpb_buffer = 184320 / fs_in_mb;
 464                         break;
 465                 }
 466                 num_dpb_buffer++;
 467                 if (num_dpb_buffer > 17)
 468                         num_dpb_buffer = 17;
 469
 470                 /* reference picture buffer */
 471                 min_dpb_size = image_size * num_dpb_buffer;
 472
 473                 /* macroblock context buffer */
 474                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 475
 476                 /* IT surface buffer */
 477                 min_dpb_size += width_in_mb * height_in_mb * 32;
 478                 break;
 479
 480         case 1: /* VC1 */
 481
 482                 /* reference picture buffer */
 483                 min_dpb_size = image_size * 3;
 484
 485                 /* CONTEXT_BUFFER */
 486                 min_dpb_size += width_in_mb * height_in_mb * 128;
 487
 488                 /* IT surface buffer */
 489                 min_dpb_size += width_in_mb * 64;
 490
 491                 /* DB surface buffer */
 492                 min_dpb_size += width_in_mb * 128;
 493
 494                 /* BP */
 495                 tmp = max(width_in_mb, height_in_mb);
 496                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 497                 break;
 498
 499         case 3: /* MPEG2 */
 500
 501                 /* reference picture buffer */
 502                 min_dpb_size = image_size * 3;
 503                 break;
 504
 505         case 4: /* MPEG4 */
 506
 507                 /* reference picture buffer */
 508                 min_dpb_size = image_size * 3;
 509
 510                 /* CM */
 511                 min_dpb_size += width_in_mb * height_in_mb * 64;
 512
 513                 /* IT surface buffer */
 514                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 515                 break;
 516
 517         case 16: /* H265 */
 518                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 519                 image_size = ALIGN(image_size, 256);
 520
 521                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 522                 min_dpb_size = image_size * num_dpb_buffer;
 523                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 524                                            * 16 * num_dpb_buffer + 52 * 1024;
 525                 break;
 526
 527         default:
 528                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 529                 return -EINVAL;
 530         }
 531
 532         if (width > pitch) {
 533                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 534                 return -EINVAL;
 535         }
 536
 537         if (dpb_size < min_dpb_size) {
 538                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 539                           dpb_size, min_dpb_size);
 540                 return -EINVAL;
 541         }
 542
 543         buf_sizes[0x1] = dpb_size;
 544         buf_sizes[0x2] = image_size;
 545         buf_sizes[0x4] = min_ctx_size;
 546         return 0;
 547 }
 548
 549 /**
 550  * amdgpu_uvd_cs_msg - handle UVD message
 551  *
 552  * @ctx: UVD parser context
 553  * @bo: buffer object containing the message
 554  * @offset: offset into the buffer object
 555  *
 556  * Peek into the UVD message and extract the session id.
 557  * Make sure that we don't open up to many sessions.
 558  */
 559 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 560                              struct amdgpu_bo *bo, unsigned offset)
 561 {
 562         struct amdgpu_device *adev = ctx->parser->adev;
 563         int32_t *msg, msg_type, handle;
 564         void *ptr;
 565         long r;
 566         int i;
 567
 568         if (offset & 0x3F) {
 569                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 570                 return -EINVAL;
 571         }
 572
 573         r = amdgpu_bo_kmap(bo, &ptr);
 574         if (r) {
 575                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
 576                 return r;
 577         }
 578
 579         msg = ptr + offset;
 580
 581         msg_type = msg[1];
 582         handle = msg[2];
 583
 584         if (handle == 0) {
 585                 DRM_ERROR("Invalid UVD handle!\n");
 586                 return -EINVAL;
 587         }
 588
 589         switch (msg_type) {
 590         case 0:
 591                 /* it's a create msg, calc image size (width * height) */
 592                 amdgpu_bo_kunmap(bo);
 593
 594                 /* try to alloc a new handle */
 595                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 596                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 597                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
 598                                 return -EINVAL;
 599                         }
 600
 601                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 602                                 adev->uvd.filp[i] = ctx->parser->filp;
 603                                 return 0;
 604                         }
 605                 }
 606
 607                 DRM_ERROR("No more free UVD handles!\n");
 608                 return -EINVAL;
 609
 610         case 1:
 611                 /* it's a decode msg, calc buffer sizes */
 612                 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
 613                 amdgpu_bo_kunmap(bo);
 614                 if (r)
 615                         return r;
 616
 617                 /* validate the handle */
 618                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 619                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 620                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 621                                         DRM_ERROR("UVD handle collision detected!\n");
 622                                         return -EINVAL;
 623                                 }
 624                                 return 0;
 625                         }
 626                 }
 627
 628                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 629                 return -ENOENT;
 630
 631         case 2:
 632                 /* it's a destroy msg, free the handle */
 633                 for (i = 0; i < adev->uvd.max_handles; ++i)
 634                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 635                 amdgpu_bo_kunmap(bo);
 636                 return 0;
 637
 638         default:
 639                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 640                 return -EINVAL;
 641         }
 642         BUG();
 643         return -EINVAL;
 644 }
 645
 646 /**
 647  * amdgpu_uvd_cs_pass2 - second parsing round
 648  *
 649  * @ctx: UVD parser context
 650  *
 651  * Patch buffer addresses, make sure buffer sizes are correct.
 652  */
 653 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 654 {
 655         struct amdgpu_bo_va_mapping *mapping;
 656         struct amdgpu_bo *bo;
 657         uint32_t cmd, lo, hi;
 658         uint64_t start, end;
 659         uint64_t addr;
 660         int r;
 661
 662         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 663         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 664         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 665
 666         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 667         if (mapping == NULL)
 668                 return -EINVAL;
 669
 670         start = amdgpu_bo_gpu_offset(bo);
 671
 672         end = (mapping->it.last + 1 - mapping->it.start);
 673         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 674
 675         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 676         start += addr;
 677
 678         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 679                             lower_32_bits(start));
 680         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 681                             upper_32_bits(start));
 682
 683         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 684         if (cmd < 0x4) {
 685                 if ((end - start) < ctx->buf_sizes[cmd]) {
 686                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 687                                   (unsigned)(end - start),
 688                                   ctx->buf_sizes[cmd]);
 689                         return -EINVAL;
 690                 }
 691
 692         } else if (cmd == 0x206) {
 693                 if ((end - start) < ctx->buf_sizes[4]) {
 694                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 695                                           (unsigned)(end - start),
 696                                           ctx->buf_sizes[4]);
 697                         return -EINVAL;
 698                 }
 699         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 700                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 701                 return -EINVAL;
 702         }
 703
 704         if (!ctx->parser->adev->uvd.address_64_bit) {
 705                 if ((start >> 28) != ((end - 1) >> 28)) {
 706                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 707                                   start, end);
 708                         return -EINVAL;
 709                 }
 710
 711                 if ((cmd == 0 || cmd == 0x3) &&
 712                     (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
 713                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 714                                   start, end);
 715                         return -EINVAL;
 716                 }
 717         }
 718
 719         if (cmd == 0) {
 720                 ctx->has_msg_cmd = true;
 721                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 722                 if (r)
 723                         return r;
 724         } else if (!ctx->has_msg_cmd) {
 725                 DRM_ERROR("Message needed before other commands are send!\n");
 726                 return -EINVAL;
 727         }
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * amdgpu_uvd_cs_reg - parse register writes
 734  *
 735  * @ctx: UVD parser context
 736  * @cb: callback function
 737  *
 738  * Parse the register writes, call cb on each complete command.
 739  */
 740 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 741                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 742 {
 743         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 744         int i, r;
 745
 746         ctx->idx++;
 747         for (i = 0; i <= ctx->count; ++i) {
 748                 unsigned reg = ctx->reg + i;
 749
 750                 if (ctx->idx >= ib->length_dw) {
 751                         DRM_ERROR("Register command after end of CS!\n");
 752                         return -EINVAL;
 753                 }
 754
 755                 switch (reg) {
 756                 case mmUVD_GPCOM_VCPU_DATA0:
 757                         ctx->data0 = ctx->idx;
 758                         break;
 759                 case mmUVD_GPCOM_VCPU_DATA1:
 760                         ctx->data1 = ctx->idx;
 761                         break;
 762                 case mmUVD_GPCOM_VCPU_CMD:
 763                         r = cb(ctx);
 764                         if (r)
 765                                 return r;
 766                         break;
 767                 case mmUVD_ENGINE_CNTL:
 768                         break;
 769                 default:
 770                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 771                         return -EINVAL;
 772                 }
 773                 ctx->idx++;
 774         }
 775         return 0;
 776 }
 777
 778 /**
 779  * amdgpu_uvd_cs_packets - parse UVD packets
 780  *
 781  * @ctx: UVD parser context
 782  * @cb: callback function
 783  *
 784  * Parse the command stream packets.
 785  */
 786 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 787                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 788 {
 789         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 790         int r;
 791
 792         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 793                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 794                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 795                 switch (type) {
 796                 case PACKET_TYPE0:
 797                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 798                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 799                         r = amdgpu_uvd_cs_reg(ctx, cb);
 800                         if (r)
 801                                 return r;
 802                         break;
 803                 case PACKET_TYPE2:
 804                         ++ctx->idx;
 805                         break;
 806                 default:
 807                         DRM_ERROR("Unknown packet type %d !\n", type);
 808                         return -EINVAL;
 809                 }
 810         }
 811         return 0;
 812 }
 813
 814 /**
 815  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 816  *
 817  * @parser: Command submission parser context
 818  *
 819  * Parse the command stream, patch in addresses as necessary.
 820  */
 821 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 822 {
 823         struct amdgpu_uvd_cs_ctx ctx = {};
 824         unsigned buf_sizes[] = {
 825                 [0x00000000]    =       2048,
 826                 [0x00000001]    =       0xFFFFFFFF,
 827                 [0x00000002]    =       0xFFFFFFFF,
 828                 [0x00000003]    =       2048,
 829                 [0x00000004]    =       0xFFFFFFFF,
 830         };
 831         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 832         int r;
 833
 834         if (ib->length_dw % 16) {
 835                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 836                           ib->length_dw);
 837                 return -EINVAL;
 838         }
 839
 840         ctx.parser = parser;
 841         ctx.buf_sizes = buf_sizes;
 842         ctx.ib_idx = ib_idx;
 843
 844         /* first round, make sure the buffers are actually in the UVD segment */
 845         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 846         if (r)
 847                 return r;
 848
 849         /* second round, patch buffer addresses into the command stream */
 850         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 851         if (r)
 852                 return r;
 853
 854         if (!ctx.has_msg_cmd) {
 855                 DRM_ERROR("UVD-IBs need a msg command!\n");
 856                 return -EINVAL;
 857         }
 858
 859         amdgpu_uvd_note_usage(ctx.parser->adev);
 860
 861         return 0;
 862 }
 863
 864 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
 865                                bool direct, struct fence **fence)
 866 {
 867         struct ttm_validate_buffer tv;
 868         struct ww_acquire_ctx ticket;
 869         struct list_head head;
 870         struct amdgpu_job *job;
 871         struct amdgpu_ib *ib;
 872         struct fence *f = NULL;
 873         struct amdgpu_device *adev = ring->adev;
 874         uint64_t addr;
 875         int i, r;
 876
 877         memset(&tv, 0, sizeof(tv));
 878         tv.bo = &bo->tbo;
 879
 880         INIT_LIST_HEAD(&head);
 881         list_add(&tv.head, &head);
 882
 883         r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
 884         if (r)
 885                 return r;
 886
 887         if (!bo->adev->uvd.address_64_bit) {
 888                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 889                 amdgpu_uvd_force_into_uvd_segment(bo);
 890         }
 891
 892         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 893         if (r)
 894                 goto err;
 895
 896         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 897         if (r)
 898                 goto err;
 899
 900         ib = &job->ibs[0];
 901         addr = amdgpu_bo_gpu_offset(bo);
 902         ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
 903         ib->ptr[1] = addr;
 904         ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
 905         ib->ptr[3] = addr >> 32;
 906         ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
 907         ib->ptr[5] = 0;
 908         for (i = 6; i < 16; ++i)
 909                 ib->ptr[i] = PACKET2(0);
 910         ib->length_dw = 16;
 911
 912         if (direct) {
 913                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 914                 job->fence = f;
 915                 if (r)
 916                         goto err_free;
 917
 918                 amdgpu_job_free(job);
 919         } else {
 920                 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
 921                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 922                 if (r)
 923                         goto err_free;
 924         }
 925
 926         ttm_eu_fence_buffer_objects(&ticket, &head, f);
 927
 928         if (fence)
 929                 *fence = fence_get(f);
 930         amdgpu_bo_unref(&bo);
 931         fence_put(f);
 932
 933         return 0;
 934
 935 err_free:
 936         amdgpu_job_free(job);
 937
 938 err:
 939         ttm_eu_backoff_reservation(&ticket, &head);
 940         return r;
 941 }
 942
 943 /* multiple fence commands without any stream commands in between can
 944    crash the vcpu so just try to emmit a dummy create/destroy msg to
 945    avoid this */
 946 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 947                               struct fence **fence)
 948 {
 949         struct amdgpu_device *adev = ring->adev;
 950         struct amdgpu_bo *bo;
 951         uint32_t *msg;
 952         int r, i;
 953
 954         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 955                              AMDGPU_GEM_DOMAIN_VRAM,
 956                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 957                              NULL, NULL, &bo);
 958         if (r)
 959                 return r;
 960
 961         r = amdgpu_bo_reserve(bo, false);
 962         if (r) {
 963                 amdgpu_bo_unref(&bo);
 964                 return r;
 965         }
 966
 967         r = amdgpu_bo_kmap(bo, (void **)&msg);
 968         if (r) {
 969                 amdgpu_bo_unreserve(bo);
 970                 amdgpu_bo_unref(&bo);
 971                 return r;
 972         }
 973
 974         /* stitch together an UVD create msg */
 975         msg[0] = cpu_to_le32(0x00000de4);
 976         msg[1] = cpu_to_le32(0x00000000);
 977         msg[2] = cpu_to_le32(handle);
 978         msg[3] = cpu_to_le32(0x00000000);
 979         msg[4] = cpu_to_le32(0x00000000);
 980         msg[5] = cpu_to_le32(0x00000000);
 981         msg[6] = cpu_to_le32(0x00000000);
 982         msg[7] = cpu_to_le32(0x00000780);
 983         msg[8] = cpu_to_le32(0x00000440);
 984         msg[9] = cpu_to_le32(0x00000000);
 985         msg[10] = cpu_to_le32(0x01b37000);
 986         for (i = 11; i < 1024; ++i)
 987                 msg[i] = cpu_to_le32(0x0);
 988
 989         amdgpu_bo_kunmap(bo);
 990         amdgpu_bo_unreserve(bo);
 991
 992         return amdgpu_uvd_send_msg(ring, bo, true, fence);
 993 }
 994
 995 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 996                                bool direct, struct fence **fence)
 997 {
 998         struct amdgpu_device *adev = ring->adev;
 999         struct amdgpu_bo *bo;
1000         uint32_t *msg;
1001         int r, i;
1002
1003         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1004                              AMDGPU_GEM_DOMAIN_VRAM,
1005                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1006                              NULL, NULL, &bo);
1007         if (r)
1008                 return r;
1009
1010         r = amdgpu_bo_reserve(bo, false);
1011         if (r) {
1012                 amdgpu_bo_unref(&bo);
1013                 return r;
1014         }
1015
1016         r = amdgpu_bo_kmap(bo, (void **)&msg);
1017         if (r) {
1018                 amdgpu_bo_unreserve(bo);
1019                 amdgpu_bo_unref(&bo);
1020                 return r;
1021         }
1022
1023         /* stitch together an UVD destroy msg */
1024         msg[0] = cpu_to_le32(0x00000de4);
1025         msg[1] = cpu_to_le32(0x00000002);
1026         msg[2] = cpu_to_le32(handle);
1027         msg[3] = cpu_to_le32(0x00000000);
1028         for (i = 4; i < 1024; ++i)
1029                 msg[i] = cpu_to_le32(0x0);
1030
1031         amdgpu_bo_kunmap(bo);
1032         amdgpu_bo_unreserve(bo);
1033
1034         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1035 }
1036
1037 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1038 {
1039         struct amdgpu_device *adev =
1040                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1041         unsigned i, fences, handles = 0;
1042
1043         fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1044
1045         for (i = 0; i < adev->uvd.max_handles; ++i)
1046                 if (atomic_read(&adev->uvd.handles[i]))
1047                         ++handles;
1048
1049         if (fences == 0 && handles == 0) {
1050                 if (adev->pm.dpm_enabled) {
1051                         amdgpu_dpm_enable_uvd(adev, false);
1052                 } else {
1053                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1054                 }
1055         } else {
1056                 schedule_delayed_work(&adev->uvd.idle_work,
1057                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1058         }
1059 }
1060
1061 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1062 {
1063         bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1064         set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1065                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1066
1067         if (set_clocks) {
1068                 if (adev->pm.dpm_enabled) {
1069                         amdgpu_dpm_enable_uvd(adev, true);
1070                 } else {
1071                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1072                 }
1073         }
1074 }