drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39 #include "ivsrcid/ivsrcid_vislands30.h"
  40
  41 /* Polaris10/11/12 firmware version */
  42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
  43
  44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  46
  47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  48 static int uvd_v6_0_start(struct amdgpu_device *adev);
  49 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  51 static int uvd_v6_0_set_clockgating_state(void *handle,
  52                                           enum amd_clockgating_state state);
  53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  54                                  bool enable);
  55
  56 /**
  57 * uvd_v6_0_enc_support - get encode support status
  58 *
  59 * @adev: amdgpu_device pointer
  60 *
  61 * Returns the current hardware encode support status
  62 */
  63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  64 {
  65         return ((adev->asic_type >= CHIP_POLARIS10) &&
  66                         (adev->asic_type <= CHIP_VEGAM) &&
  67                         (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
  68 }
  69
  70 /**
  71  * uvd_v6_0_ring_get_rptr - get read pointer
  72  *
  73  * @ring: amdgpu_ring pointer
  74  *
  75  * Returns the current hardware read pointer
  76  */
  77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  78 {
  79         struct amdgpu_device *adev = ring->adev;
  80
  81         return RREG32(mmUVD_RBC_RB_RPTR);
  82 }
  83
  84 /**
  85  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  86  *
  87  * @ring: amdgpu_ring pointer
  88  *
  89  * Returns the current hardware enc read pointer
  90  */
  91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  92 {
  93         struct amdgpu_device *adev = ring->adev;
  94
  95         if (ring == &adev->uvd.inst->ring_enc[0])
  96                 return RREG32(mmUVD_RB_RPTR);
  97         else
  98                 return RREG32(mmUVD_RB_RPTR2);
  99 }
 100 /**
 101  * uvd_v6_0_ring_get_wptr - get write pointer
 102  *
 103  * @ring: amdgpu_ring pointer
 104  *
 105  * Returns the current hardware write pointer
 106  */
 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 108 {
 109         struct amdgpu_device *adev = ring->adev;
 110
 111         return RREG32(mmUVD_RBC_RB_WPTR);
 112 }
 113
 114 /**
 115  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 116  *
 117  * @ring: amdgpu_ring pointer
 118  *
 119  * Returns the current hardware enc write pointer
 120  */
 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 122 {
 123         struct amdgpu_device *adev = ring->adev;
 124
 125         if (ring == &adev->uvd.inst->ring_enc[0])
 126                 return RREG32(mmUVD_RB_WPTR);
 127         else
 128                 return RREG32(mmUVD_RB_WPTR2);
 129 }
 130
 131 /**
 132  * uvd_v6_0_ring_set_wptr - set write pointer
 133  *
 134  * @ring: amdgpu_ring pointer
 135  *
 136  * Commits the write pointer to the hardware
 137  */
 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 139 {
 140         struct amdgpu_device *adev = ring->adev;
 141
 142         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 143 }
 144
 145 /**
 146  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 147  *
 148  * @ring: amdgpu_ring pointer
 149  *
 150  * Commits the enc write pointer to the hardware
 151  */
 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 153 {
 154         struct amdgpu_device *adev = ring->adev;
 155
 156         if (ring == &adev->uvd.inst->ring_enc[0])
 157                 WREG32(mmUVD_RB_WPTR,
 158                         lower_32_bits(ring->wptr));
 159         else
 160                 WREG32(mmUVD_RB_WPTR2,
 161                         lower_32_bits(ring->wptr));
 162 }
 163
 164 /**
 165  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 166  *
 167  * @ring: the engine to test on
 168  *
 169  */
 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 171 {
 172         struct amdgpu_device *adev = ring->adev;
 173         uint32_t rptr;
 174         unsigned i;
 175         int r;
 176
 177         r = amdgpu_ring_alloc(ring, 16);
 178         if (r)
 179                 return r;
 180
 181         rptr = amdgpu_ring_get_rptr(ring);
 182
 183         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 184         amdgpu_ring_commit(ring);
 185
 186         for (i = 0; i < adev->usec_timeout; i++) {
 187                 if (amdgpu_ring_get_rptr(ring) != rptr)
 188                         break;
 189                 udelay(1);
 190         }
 191
 192         if (i >= adev->usec_timeout)
 193                 r = -ETIMEDOUT;
 194
 195         return r;
 196 }
 197
 198 /**
 199  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 200  *
 201  * @ring: ring we should submit the msg to
 202  * @handle: session handle to use
 203  * @bo: amdgpu object for which we query the offset
 204  * @fence: optional fence to return
 205  *
 206  * Open up a stream for HW test
 207  */
 208 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 209                                        struct amdgpu_bo *bo,
 210                                        struct dma_fence **fence)
 211 {
 212         const unsigned ib_size_dw = 16;
 213         struct amdgpu_job *job;
 214         struct amdgpu_ib *ib;
 215         struct dma_fence *f = NULL;
 216         uint64_t addr;
 217         int i, r;
 218
 219         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 220                                         AMDGPU_IB_POOL_DIRECT, &job);
 221         if (r)
 222                 return r;
 223
 224         ib = &job->ibs[0];
 225         addr = amdgpu_bo_gpu_offset(bo);
 226
 227         ib->length_dw = 0;
 228         ib->ptr[ib->length_dw++] = 0x00000018;
 229         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 230         ib->ptr[ib->length_dw++] = handle;
 231         ib->ptr[ib->length_dw++] = 0x00010000;
 232         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 233         ib->ptr[ib->length_dw++] = addr;
 234
 235         ib->ptr[ib->length_dw++] = 0x00000014;
 236         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 237         ib->ptr[ib->length_dw++] = 0x0000001c;
 238         ib->ptr[ib->length_dw++] = 0x00000001;
 239         ib->ptr[ib->length_dw++] = 0x00000000;
 240
 241         ib->ptr[ib->length_dw++] = 0x00000008;
 242         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 243
 244         for (i = ib->length_dw; i < ib_size_dw; ++i)
 245                 ib->ptr[i] = 0x0;
 246
 247         r = amdgpu_job_submit_direct(job, ring, &f);
 248         if (r)
 249                 goto err;
 250
 251         if (fence)
 252                 *fence = dma_fence_get(f);
 253         dma_fence_put(f);
 254         return 0;
 255
 256 err:
 257         amdgpu_job_free(job);
 258         return r;
 259 }
 260
 261 /**
 262  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 263  *
 264  * @ring: ring we should submit the msg to
 265  * @handle: session handle to use
 266  * @bo: amdgpu object for which we query the offset
 267  * @fence: optional fence to return
 268  *
 269  * Close up a stream for HW test or if userspace failed to do so
 270  */
 271 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 272                                         uint32_t handle,
 273                                         struct amdgpu_bo *bo,
 274                                         struct dma_fence **fence)
 275 {
 276         const unsigned ib_size_dw = 16;
 277         struct amdgpu_job *job;
 278         struct amdgpu_ib *ib;
 279         struct dma_fence *f = NULL;
 280         uint64_t addr;
 281         int i, r;
 282
 283         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 284                                         AMDGPU_IB_POOL_DIRECT, &job);
 285         if (r)
 286                 return r;
 287
 288         ib = &job->ibs[0];
 289         addr = amdgpu_bo_gpu_offset(bo);
 290
 291         ib->length_dw = 0;
 292         ib->ptr[ib->length_dw++] = 0x00000018;
 293         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 294         ib->ptr[ib->length_dw++] = handle;
 295         ib->ptr[ib->length_dw++] = 0x00010000;
 296         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 297         ib->ptr[ib->length_dw++] = addr;
 298
 299         ib->ptr[ib->length_dw++] = 0x00000014;
 300         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 301         ib->ptr[ib->length_dw++] = 0x0000001c;
 302         ib->ptr[ib->length_dw++] = 0x00000001;
 303         ib->ptr[ib->length_dw++] = 0x00000000;
 304
 305         ib->ptr[ib->length_dw++] = 0x00000008;
 306         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 307
 308         for (i = ib->length_dw; i < ib_size_dw; ++i)
 309                 ib->ptr[i] = 0x0;
 310
 311         r = amdgpu_job_submit_direct(job, ring, &f);
 312         if (r)
 313                 goto err;
 314
 315         if (fence)
 316                 *fence = dma_fence_get(f);
 317         dma_fence_put(f);
 318         return 0;
 319
 320 err:
 321         amdgpu_job_free(job);
 322         return r;
 323 }
 324
 325 /**
 326  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 327  *
 328  * @ring: the engine to test on
 329  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 330  *
 331  */
 332 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 333 {
 334         struct dma_fence *fence = NULL;
 335         struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
 336         long r;
 337
 338         r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL);
 339         if (r)
 340                 goto error;
 341
 342         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence);
 343         if (r)
 344                 goto error;
 345
 346         r = dma_fence_wait_timeout(fence, false, timeout);
 347         if (r == 0)
 348                 r = -ETIMEDOUT;
 349         else if (r > 0)
 350                 r = 0;
 351
 352 error:
 353         dma_fence_put(fence);
 354         return r;
 355 }
 356
 357 static int uvd_v6_0_early_init(void *handle)
 358 {
 359         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 360         adev->uvd.num_uvd_inst = 1;
 361
 362         if (!(adev->flags & AMD_IS_APU) &&
 363             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 364                 return -ENOENT;
 365
 366         uvd_v6_0_set_ring_funcs(adev);
 367
 368         if (uvd_v6_0_enc_support(adev)) {
 369                 adev->uvd.num_enc_rings = 2;
 370                 uvd_v6_0_set_enc_ring_funcs(adev);
 371         }
 372
 373         uvd_v6_0_set_irq_funcs(adev);
 374
 375         return 0;
 376 }
 377
 378 static int uvd_v6_0_sw_init(void *handle)
 379 {
 380         struct amdgpu_ring *ring;
 381         int i, r;
 382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 383
 384         /* UVD TRAP */
 385         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 386         if (r)
 387                 return r;
 388
 389         /* UVD ENC TRAP */
 390         if (uvd_v6_0_enc_support(adev)) {
 391                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 392                         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
 393                         if (r)
 394                                 return r;
 395                 }
 396         }
 397
 398         r = amdgpu_uvd_sw_init(adev);
 399         if (r)
 400                 return r;
 401
 402         if (!uvd_v6_0_enc_support(adev)) {
 403                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 404                         adev->uvd.inst->ring_enc[i].funcs = NULL;
 405
 406                 adev->uvd.inst->irq.num_types = 1;
 407                 adev->uvd.num_enc_rings = 0;
 408
 409                 DRM_INFO("UVD ENC is disabled\n");
 410         }
 411
 412         ring = &adev->uvd.inst->ring;
 413         sprintf(ring->name, "uvd");
 414         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
 415                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 416         if (r)
 417                 return r;
 418
 419         r = amdgpu_uvd_resume(adev);
 420         if (r)
 421                 return r;
 422
 423         if (uvd_v6_0_enc_support(adev)) {
 424                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 425                         ring = &adev->uvd.inst->ring_enc[i];
 426                         sprintf(ring->name, "uvd_enc%d", i);
 427                         r = amdgpu_ring_init(adev, ring, 512,
 428                                              &adev->uvd.inst->irq, 0,
 429                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 430                         if (r)
 431                                 return r;
 432                 }
 433         }
 434
 435         r = amdgpu_uvd_entity_init(adev);
 436
 437         return r;
 438 }
 439
 440 static int uvd_v6_0_sw_fini(void *handle)
 441 {
 442         int i, r;
 443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 444
 445         r = amdgpu_uvd_suspend(adev);
 446         if (r)
 447                 return r;
 448
 449         if (uvd_v6_0_enc_support(adev)) {
 450                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 451                         amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
 452         }
 453
 454         return amdgpu_uvd_sw_fini(adev);
 455 }
 456
 457 /**
 458  * uvd_v6_0_hw_init - start and test UVD block
 459  *
 460  * @handle: handle used to pass amdgpu_device pointer
 461  *
 462  * Initialize the hardware, boot up the VCPU and do some testing
 463  */
 464 static int uvd_v6_0_hw_init(void *handle)
 465 {
 466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 467         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 468         uint32_t tmp;
 469         int i, r;
 470
 471         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 472         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 473         uvd_v6_0_enable_mgcg(adev, true);
 474
 475         r = amdgpu_ring_test_helper(ring);
 476         if (r)
 477                 goto done;
 478
 479         r = amdgpu_ring_alloc(ring, 10);
 480         if (r) {
 481                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 482                 goto done;
 483         }
 484
 485         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 486         amdgpu_ring_write(ring, tmp);
 487         amdgpu_ring_write(ring, 0xFFFFF);
 488
 489         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 490         amdgpu_ring_write(ring, tmp);
 491         amdgpu_ring_write(ring, 0xFFFFF);
 492
 493         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 494         amdgpu_ring_write(ring, tmp);
 495         amdgpu_ring_write(ring, 0xFFFFF);
 496
 497         /* Clear timeout status bits */
 498         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 499         amdgpu_ring_write(ring, 0x8);
 500
 501         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 502         amdgpu_ring_write(ring, 3);
 503
 504         amdgpu_ring_commit(ring);
 505
 506         if (uvd_v6_0_enc_support(adev)) {
 507                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 508                         ring = &adev->uvd.inst->ring_enc[i];
 509                         r = amdgpu_ring_test_helper(ring);
 510                         if (r)
 511                                 goto done;
 512                 }
 513         }
 514
 515 done:
 516         if (!r) {
 517                 if (uvd_v6_0_enc_support(adev))
 518                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 519                 else
 520                         DRM_INFO("UVD initialized successfully.\n");
 521         }
 522
 523         return r;
 524 }
 525
 526 /**
 527  * uvd_v6_0_hw_fini - stop the hardware block
 528  *
 529  * @handle: handle used to pass amdgpu_device pointer
 530  *
 531  * Stop the UVD block, mark ring as not ready any more
 532  */
 533 static int uvd_v6_0_hw_fini(void *handle)
 534 {
 535         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 536
 537         /*
 538          * Proper cleanups before halting the HW engine:
 539          *   - cancel the delayed idle work
 540          *   - enable powergating
 541          *   - enable clockgating
 542          *   - disable dpm
 543          *
 544          * TODO: to align with the VCN implementation, move the
 545          * jobs for clockgating/powergating/dpm setting to
 546          * ->set_powergating_state().
 547          */
 548         cancel_delayed_work_sync(&adev->uvd.idle_work);
 549
 550         if (adev->pm.dpm_enabled) {
 551                 amdgpu_dpm_enable_uvd(adev, false);
 552         } else {
 553                 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 554                 /* shutdown the UVD block */
 555                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 556                                                        AMD_PG_STATE_GATE);
 557                 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 558                                                        AMD_CG_STATE_GATE);
 559         }
 560
 561         if (RREG32(mmUVD_STATUS) != 0)
 562                 uvd_v6_0_stop(adev);
 563
 564         return 0;
 565 }
 566
 567 static int uvd_v6_0_suspend(void *handle)
 568 {
 569         int r;
 570         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 571
 572         r = uvd_v6_0_hw_fini(adev);
 573         if (r)
 574                 return r;
 575
 576         return amdgpu_uvd_suspend(adev);
 577 }
 578
 579 static int uvd_v6_0_resume(void *handle)
 580 {
 581         int r;
 582         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 583
 584         r = amdgpu_uvd_resume(adev);
 585         if (r)
 586                 return r;
 587
 588         return uvd_v6_0_hw_init(adev);
 589 }
 590
 591 /**
 592  * uvd_v6_0_mc_resume - memory controller programming
 593  *
 594  * @adev: amdgpu_device pointer
 595  *
 596  * Let the UVD memory controller know it's offsets
 597  */
 598 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 599 {
 600         uint64_t offset;
 601         uint32_t size;
 602
 603         /* program memory controller bits 0-27 */
 604         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 605                         lower_32_bits(adev->uvd.inst->gpu_addr));
 606         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 607                         upper_32_bits(adev->uvd.inst->gpu_addr));
 608
 609         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 610         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 611         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 612         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 613
 614         offset += size;
 615         size = AMDGPU_UVD_HEAP_SIZE;
 616         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 617         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 618
 619         offset += size;
 620         size = AMDGPU_UVD_STACK_SIZE +
 621                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 622         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 623         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 624
 625         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 626         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 627         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 628
 629         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 630 }
 631
 632 #if 0
 633 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 634                 bool enable)
 635 {
 636         u32 data, data1;
 637
 638         data = RREG32(mmUVD_CGC_GATE);
 639         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 640         if (enable) {
 641                 data |= UVD_CGC_GATE__SYS_MASK |
 642                                 UVD_CGC_GATE__UDEC_MASK |
 643                                 UVD_CGC_GATE__MPEG2_MASK |
 644                                 UVD_CGC_GATE__RBC_MASK |
 645                                 UVD_CGC_GATE__LMI_MC_MASK |
 646                                 UVD_CGC_GATE__IDCT_MASK |
 647                                 UVD_CGC_GATE__MPRD_MASK |
 648                                 UVD_CGC_GATE__MPC_MASK |
 649                                 UVD_CGC_GATE__LBSI_MASK |
 650                                 UVD_CGC_GATE__LRBBM_MASK |
 651                                 UVD_CGC_GATE__UDEC_RE_MASK |
 652                                 UVD_CGC_GATE__UDEC_CM_MASK |
 653                                 UVD_CGC_GATE__UDEC_IT_MASK |
 654                                 UVD_CGC_GATE__UDEC_DB_MASK |
 655                                 UVD_CGC_GATE__UDEC_MP_MASK |
 656                                 UVD_CGC_GATE__WCB_MASK |
 657                                 UVD_CGC_GATE__VCPU_MASK |
 658                                 UVD_CGC_GATE__SCPU_MASK;
 659                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 660                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 661                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 662                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 663                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 664                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 665                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 666                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 667                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 668                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 669                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 670                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 671                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 672         } else {
 673                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 674                                 UVD_CGC_GATE__UDEC_MASK |
 675                                 UVD_CGC_GATE__MPEG2_MASK |
 676                                 UVD_CGC_GATE__RBC_MASK |
 677                                 UVD_CGC_GATE__LMI_MC_MASK |
 678                                 UVD_CGC_GATE__LMI_UMC_MASK |
 679                                 UVD_CGC_GATE__IDCT_MASK |
 680                                 UVD_CGC_GATE__MPRD_MASK |
 681                                 UVD_CGC_GATE__MPC_MASK |
 682                                 UVD_CGC_GATE__LBSI_MASK |
 683                                 UVD_CGC_GATE__LRBBM_MASK |
 684                                 UVD_CGC_GATE__UDEC_RE_MASK |
 685                                 UVD_CGC_GATE__UDEC_CM_MASK |
 686                                 UVD_CGC_GATE__UDEC_IT_MASK |
 687                                 UVD_CGC_GATE__UDEC_DB_MASK |
 688                                 UVD_CGC_GATE__UDEC_MP_MASK |
 689                                 UVD_CGC_GATE__WCB_MASK |
 690                                 UVD_CGC_GATE__VCPU_MASK |
 691                                 UVD_CGC_GATE__SCPU_MASK);
 692                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 693                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 694                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 695                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 696                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 697                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 698                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 699                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 700                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 701                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 702                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 703                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 704                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 705         }
 706         WREG32(mmUVD_CGC_GATE, data);
 707         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 708 }
 709 #endif
 710
 711 /**
 712  * uvd_v6_0_start - start UVD block
 713  *
 714  * @adev: amdgpu_device pointer
 715  *
 716  * Setup and start the UVD block
 717  */
 718 static int uvd_v6_0_start(struct amdgpu_device *adev)
 719 {
 720         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 721         uint32_t rb_bufsz, tmp;
 722         uint32_t lmi_swap_cntl;
 723         uint32_t mp_swap_cntl;
 724         int i, j, r;
 725
 726         /* disable DPG */
 727         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 728
 729         /* disable byte swapping */
 730         lmi_swap_cntl = 0;
 731         mp_swap_cntl = 0;
 732
 733         uvd_v6_0_mc_resume(adev);
 734
 735         /* disable interupt */
 736         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 737
 738         /* stall UMC and register bus before resetting VCPU */
 739         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 740         mdelay(1);
 741
 742         /* put LMI, VCPU, RBC etc... into reset */
 743         WREG32(mmUVD_SOFT_RESET,
 744                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 745                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 746                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 747                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 748                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 749                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 750                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 751                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 752         mdelay(5);
 753
 754         /* take UVD block out of reset */
 755         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 756         mdelay(5);
 757
 758         /* initialize UVD memory controller */
 759         WREG32(mmUVD_LMI_CTRL,
 760                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 761                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 762                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 763                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 764                 UVD_LMI_CTRL__REQ_MODE_MASK |
 765                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 766
 767 #ifdef __BIG_ENDIAN
 768         /* swap (8 in 32) RB and IB */
 769         lmi_swap_cntl = 0xa;
 770         mp_swap_cntl = 0;
 771 #endif
 772         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 773         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 774
 775         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 776         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 777         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 778         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 779         WREG32(mmUVD_MPC_SET_ALU, 0);
 780         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 781
 782         /* take all subblocks out of reset, except VCPU */
 783         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 784         mdelay(5);
 785
 786         /* enable VCPU clock */
 787         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 788
 789         /* enable UMC */
 790         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 791
 792         /* boot up the VCPU */
 793         WREG32(mmUVD_SOFT_RESET, 0);
 794         mdelay(10);
 795
 796         for (i = 0; i < 10; ++i) {
 797                 uint32_t status;
 798
 799                 for (j = 0; j < 100; ++j) {
 800                         status = RREG32(mmUVD_STATUS);
 801                         if (status & 2)
 802                                 break;
 803                         mdelay(10);
 804                 }
 805                 r = 0;
 806                 if (status & 2)
 807                         break;
 808
 809                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 810                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 811                 mdelay(10);
 812                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 813                 mdelay(10);
 814                 r = -1;
 815         }
 816
 817         if (r) {
 818                 DRM_ERROR("UVD not responding, giving up!!!\n");
 819                 return r;
 820         }
 821         /* enable master interrupt */
 822         WREG32_P(mmUVD_MASTINT_EN,
 823                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 824                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 825
 826         /* clear the bit 4 of UVD_STATUS */
 827         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 828
 829         /* force RBC into idle state */
 830         rb_bufsz = order_base_2(ring->ring_size);
 831         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 832         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 833         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 834         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 835         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 836         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 837         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 838
 839         /* set the write pointer delay */
 840         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 841
 842         /* set the wb address */
 843         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 844
 845         /* program the RB_BASE for ring buffer */
 846         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 847                         lower_32_bits(ring->gpu_addr));
 848         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 849                         upper_32_bits(ring->gpu_addr));
 850
 851         /* Initialize the ring buffer's read and write pointers */
 852         WREG32(mmUVD_RBC_RB_RPTR, 0);
 853
 854         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 855         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 856
 857         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 858
 859         if (uvd_v6_0_enc_support(adev)) {
 860                 ring = &adev->uvd.inst->ring_enc[0];
 861                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 862                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 863                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 864                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 865                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 866
 867                 ring = &adev->uvd.inst->ring_enc[1];
 868                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 869                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 870                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 871                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 872                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 873         }
 874
 875         return 0;
 876 }
 877
 878 /**
 879  * uvd_v6_0_stop - stop UVD block
 880  *
 881  * @adev: amdgpu_device pointer
 882  *
 883  * stop the UVD block
 884  */
 885 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 886 {
 887         /* force RBC into idle state */
 888         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 889
 890         /* Stall UMC and register bus before resetting VCPU */
 891         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 892         mdelay(1);
 893
 894         /* put VCPU into reset */
 895         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 896         mdelay(5);
 897
 898         /* disable VCPU clock */
 899         WREG32(mmUVD_VCPU_CNTL, 0x0);
 900
 901         /* Unstall UMC and register bus */
 902         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 903
 904         WREG32(mmUVD_STATUS, 0);
 905 }
 906
 907 /**
 908  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 909  *
 910  * @ring: amdgpu_ring pointer
 911  * @addr: address
 912  * @seq: sequence number
 913  * @flags: fence related flags
 914  *
 915  * Write a fence and a trap command to the ring.
 916  */
 917 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 918                                      unsigned flags)
 919 {
 920         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 921
 922         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 923         amdgpu_ring_write(ring, seq);
 924         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 925         amdgpu_ring_write(ring, addr & 0xffffffff);
 926         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 927         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 928         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 929         amdgpu_ring_write(ring, 0);
 930
 931         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 932         amdgpu_ring_write(ring, 0);
 933         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 934         amdgpu_ring_write(ring, 0);
 935         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 936         amdgpu_ring_write(ring, 2);
 937 }
 938
 939 /**
 940  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 941  *
 942  * @ring: amdgpu_ring pointer
 943  * @addr: address
 944  * @seq: sequence number
 945  * @flags: fence related flags
 946  *
 947  * Write enc a fence and a trap command to the ring.
 948  */
 949 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 950                         u64 seq, unsigned flags)
 951 {
 952         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 953
 954         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 955         amdgpu_ring_write(ring, addr);
 956         amdgpu_ring_write(ring, upper_32_bits(addr));
 957         amdgpu_ring_write(ring, seq);
 958         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 959 }
 960
 961 /**
 962  * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
 963  *
 964  * @ring: amdgpu_ring pointer
 965  */
 966 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 967 {
 968         /* The firmware doesn't seem to like touching registers at this point. */
 969 }
 970
 971 /**
 972  * uvd_v6_0_ring_test_ring - register write test
 973  *
 974  * @ring: amdgpu_ring pointer
 975  *
 976  * Test if we can successfully write to the context register
 977  */
 978 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 979 {
 980         struct amdgpu_device *adev = ring->adev;
 981         uint32_t tmp = 0;
 982         unsigned i;
 983         int r;
 984
 985         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 986         r = amdgpu_ring_alloc(ring, 3);
 987         if (r)
 988                 return r;
 989
 990         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 991         amdgpu_ring_write(ring, 0xDEADBEEF);
 992         amdgpu_ring_commit(ring);
 993         for (i = 0; i < adev->usec_timeout; i++) {
 994                 tmp = RREG32(mmUVD_CONTEXT_ID);
 995                 if (tmp == 0xDEADBEEF)
 996                         break;
 997                 udelay(1);
 998         }
 999
1000         if (i >= adev->usec_timeout)
1001                 r = -ETIMEDOUT;
1002
1003         return r;
1004 }
1005
1006 /**
1007  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1008  *
1009  * @ring: amdgpu_ring pointer
1010  * @job: job to retrieve vmid from
1011  * @ib: indirect buffer to execute
1012  * @flags: unused
1013  *
1014  * Write ring commands to execute the indirect buffer
1015  */
1016 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1017                                   struct amdgpu_job *job,
1018                                   struct amdgpu_ib *ib,
1019                                   uint32_t flags)
1020 {
1021         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1022
1023         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1024         amdgpu_ring_write(ring, vmid);
1025
1026         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1027         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1028         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1029         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1030         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1031         amdgpu_ring_write(ring, ib->length_dw);
1032 }
1033
1034 /**
1035  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1036  *
1037  * @ring: amdgpu_ring pointer
1038  * @job: job to retrive vmid from
1039  * @ib: indirect buffer to execute
1040  * @flags: unused
1041  *
1042  * Write enc ring commands to execute the indirect buffer
1043  */
1044 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1045                                         struct amdgpu_job *job,
1046                                         struct amdgpu_ib *ib,
1047                                         uint32_t flags)
1048 {
1049         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1050
1051         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1052         amdgpu_ring_write(ring, vmid);
1053         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1054         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1055         amdgpu_ring_write(ring, ib->length_dw);
1056 }
1057
1058 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1059                                     uint32_t reg, uint32_t val)
1060 {
1061         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1062         amdgpu_ring_write(ring, reg << 2);
1063         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1064         amdgpu_ring_write(ring, val);
1065         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1066         amdgpu_ring_write(ring, 0x8);
1067 }
1068
1069 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1070                                         unsigned vmid, uint64_t pd_addr)
1071 {
1072         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1073
1074         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1075         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1076         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1077         amdgpu_ring_write(ring, 0);
1078         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1079         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1080         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1081         amdgpu_ring_write(ring, 0xC);
1082 }
1083
1084 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1085 {
1086         uint32_t seq = ring->fence_drv.sync_seq;
1087         uint64_t addr = ring->fence_drv.gpu_addr;
1088
1089         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1090         amdgpu_ring_write(ring, lower_32_bits(addr));
1091         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1092         amdgpu_ring_write(ring, upper_32_bits(addr));
1093         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1094         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1095         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1096         amdgpu_ring_write(ring, seq);
1097         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1098         amdgpu_ring_write(ring, 0xE);
1099 }
1100
1101 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1102 {
1103         int i;
1104
1105         WARN_ON(ring->wptr % 2 || count % 2);
1106
1107         for (i = 0; i < count / 2; i++) {
1108                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
1109                 amdgpu_ring_write(ring, 0);
1110         }
1111 }
1112
1113 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1114 {
1115         uint32_t seq = ring->fence_drv.sync_seq;
1116         uint64_t addr = ring->fence_drv.gpu_addr;
1117
1118         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1119         amdgpu_ring_write(ring, lower_32_bits(addr));
1120         amdgpu_ring_write(ring, upper_32_bits(addr));
1121         amdgpu_ring_write(ring, seq);
1122 }
1123
1124 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1125 {
1126         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1127 }
1128
1129 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1130                                             unsigned int vmid, uint64_t pd_addr)
1131 {
1132         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1133         amdgpu_ring_write(ring, vmid);
1134         amdgpu_ring_write(ring, pd_addr >> 12);
1135
1136         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1137         amdgpu_ring_write(ring, vmid);
1138 }
1139
1140 static bool uvd_v6_0_is_idle(void *handle)
1141 {
1142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143
1144         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1145 }
1146
1147 static int uvd_v6_0_wait_for_idle(void *handle)
1148 {
1149         unsigned i;
1150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151
1152         for (i = 0; i < adev->usec_timeout; i++) {
1153                 if (uvd_v6_0_is_idle(handle))
1154                         return 0;
1155         }
1156         return -ETIMEDOUT;
1157 }
1158
1159 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1160 static bool uvd_v6_0_check_soft_reset(void *handle)
1161 {
1162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163         u32 srbm_soft_reset = 0;
1164         u32 tmp = RREG32(mmSRBM_STATUS);
1165
1166         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1167             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1168             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1169                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1170
1171         if (srbm_soft_reset) {
1172                 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1173                 return true;
1174         } else {
1175                 adev->uvd.inst->srbm_soft_reset = 0;
1176                 return false;
1177         }
1178 }
1179
1180 static int uvd_v6_0_pre_soft_reset(void *handle)
1181 {
1182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183
1184         if (!adev->uvd.inst->srbm_soft_reset)
1185                 return 0;
1186
1187         uvd_v6_0_stop(adev);
1188         return 0;
1189 }
1190
1191 static int uvd_v6_0_soft_reset(void *handle)
1192 {
1193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194         u32 srbm_soft_reset;
1195
1196         if (!adev->uvd.inst->srbm_soft_reset)
1197                 return 0;
1198         srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1199
1200         if (srbm_soft_reset) {
1201                 u32 tmp;
1202
1203                 tmp = RREG32(mmSRBM_SOFT_RESET);
1204                 tmp |= srbm_soft_reset;
1205                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1206                 WREG32(mmSRBM_SOFT_RESET, tmp);
1207                 tmp = RREG32(mmSRBM_SOFT_RESET);
1208
1209                 udelay(50);
1210
1211                 tmp &= ~srbm_soft_reset;
1212                 WREG32(mmSRBM_SOFT_RESET, tmp);
1213                 tmp = RREG32(mmSRBM_SOFT_RESET);
1214
1215                 /* Wait a little for things to settle down */
1216                 udelay(50);
1217         }
1218
1219         return 0;
1220 }
1221
1222 static int uvd_v6_0_post_soft_reset(void *handle)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225
1226         if (!adev->uvd.inst->srbm_soft_reset)
1227                 return 0;
1228
1229         mdelay(5);
1230
1231         return uvd_v6_0_start(adev);
1232 }
1233
1234 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1235                                         struct amdgpu_irq_src *source,
1236                                         unsigned type,
1237                                         enum amdgpu_interrupt_state state)
1238 {
1239         // TODO
1240         return 0;
1241 }
1242
1243 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1244                                       struct amdgpu_irq_src *source,
1245                                       struct amdgpu_iv_entry *entry)
1246 {
1247         bool int_handled = true;
1248         DRM_DEBUG("IH: UVD TRAP\n");
1249
1250         switch (entry->src_id) {
1251         case 124:
1252                 amdgpu_fence_process(&adev->uvd.inst->ring);
1253                 break;
1254         case 119:
1255                 if (likely(uvd_v6_0_enc_support(adev)))
1256                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1257                 else
1258                         int_handled = false;
1259                 break;
1260         case 120:
1261                 if (likely(uvd_v6_0_enc_support(adev)))
1262                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1263                 else
1264                         int_handled = false;
1265                 break;
1266         }
1267
1268         if (!int_handled)
1269                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1270                           entry->src_id, entry->src_data[0]);
1271
1272         return 0;
1273 }
1274
1275 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1276 {
1277         uint32_t data1, data3;
1278
1279         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1280         data3 = RREG32(mmUVD_CGC_GATE);
1281
1282         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1283                      UVD_SUVD_CGC_GATE__SIT_MASK |
1284                      UVD_SUVD_CGC_GATE__SMP_MASK |
1285                      UVD_SUVD_CGC_GATE__SCM_MASK |
1286                      UVD_SUVD_CGC_GATE__SDB_MASK |
1287                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1288                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1289                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1290                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1291                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1292                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1293                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1294                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1295
1296         if (enable) {
1297                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1298                         UVD_CGC_GATE__UDEC_MASK      |
1299                         UVD_CGC_GATE__MPEG2_MASK     |
1300                         UVD_CGC_GATE__RBC_MASK       |
1301                         UVD_CGC_GATE__LMI_MC_MASK    |
1302                         UVD_CGC_GATE__LMI_UMC_MASK   |
1303                         UVD_CGC_GATE__IDCT_MASK      |
1304                         UVD_CGC_GATE__MPRD_MASK      |
1305                         UVD_CGC_GATE__MPC_MASK       |
1306                         UVD_CGC_GATE__LBSI_MASK      |
1307                         UVD_CGC_GATE__LRBBM_MASK     |
1308                         UVD_CGC_GATE__UDEC_RE_MASK   |
1309                         UVD_CGC_GATE__UDEC_CM_MASK   |
1310                         UVD_CGC_GATE__UDEC_IT_MASK   |
1311                         UVD_CGC_GATE__UDEC_DB_MASK   |
1312                         UVD_CGC_GATE__UDEC_MP_MASK   |
1313                         UVD_CGC_GATE__WCB_MASK       |
1314                         UVD_CGC_GATE__JPEG_MASK      |
1315                         UVD_CGC_GATE__SCPU_MASK      |
1316                         UVD_CGC_GATE__JPEG2_MASK);
1317                 /* only in pg enabled, we can gate clock to vcpu*/
1318                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1319                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1320
1321                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1322         } else {
1323                 data3 = 0;
1324         }
1325
1326         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1327         WREG32(mmUVD_CGC_GATE, data3);
1328 }
1329
1330 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1331 {
1332         uint32_t data, data2;
1333
1334         data = RREG32(mmUVD_CGC_CTRL);
1335         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1336
1337
1338         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1339                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1340
1341
1342         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1343                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1344                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1345
1346         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1347                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1348                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1349                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1350                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1351                         UVD_CGC_CTRL__SYS_MODE_MASK |
1352                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1353                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1354                         UVD_CGC_CTRL__REGS_MODE_MASK |
1355                         UVD_CGC_CTRL__RBC_MODE_MASK |
1356                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1357                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1358                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1359                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1360                         UVD_CGC_CTRL__MPC_MODE_MASK |
1361                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1362                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1363                         UVD_CGC_CTRL__WCB_MODE_MASK |
1364                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1365                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1366                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1367                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1368         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1369                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1370                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1371                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1372                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1373
1374         WREG32(mmUVD_CGC_CTRL, data);
1375         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1376 }
1377
1378 #if 0
1379 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1380 {
1381         uint32_t data, data1, cgc_flags, suvd_flags;
1382
1383         data = RREG32(mmUVD_CGC_GATE);
1384         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1385
1386         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1387                 UVD_CGC_GATE__UDEC_MASK |
1388                 UVD_CGC_GATE__MPEG2_MASK |
1389                 UVD_CGC_GATE__RBC_MASK |
1390                 UVD_CGC_GATE__LMI_MC_MASK |
1391                 UVD_CGC_GATE__IDCT_MASK |
1392                 UVD_CGC_GATE__MPRD_MASK |
1393                 UVD_CGC_GATE__MPC_MASK |
1394                 UVD_CGC_GATE__LBSI_MASK |
1395                 UVD_CGC_GATE__LRBBM_MASK |
1396                 UVD_CGC_GATE__UDEC_RE_MASK |
1397                 UVD_CGC_GATE__UDEC_CM_MASK |
1398                 UVD_CGC_GATE__UDEC_IT_MASK |
1399                 UVD_CGC_GATE__UDEC_DB_MASK |
1400                 UVD_CGC_GATE__UDEC_MP_MASK |
1401                 UVD_CGC_GATE__WCB_MASK |
1402                 UVD_CGC_GATE__VCPU_MASK |
1403                 UVD_CGC_GATE__SCPU_MASK |
1404                 UVD_CGC_GATE__JPEG_MASK |
1405                 UVD_CGC_GATE__JPEG2_MASK;
1406
1407         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1408                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1409                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1410                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1411                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1412
1413         data |= cgc_flags;
1414         data1 |= suvd_flags;
1415
1416         WREG32(mmUVD_CGC_GATE, data);
1417         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1418 }
1419 #endif
1420
1421 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1422                                  bool enable)
1423 {
1424         u32 orig, data;
1425
1426         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1427                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1428                 data |= 0xfff;
1429                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1430
1431                 orig = data = RREG32(mmUVD_CGC_CTRL);
1432                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1433                 if (orig != data)
1434                         WREG32(mmUVD_CGC_CTRL, data);
1435         } else {
1436                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1437                 data &= ~0xfff;
1438                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1439
1440                 orig = data = RREG32(mmUVD_CGC_CTRL);
1441                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1442                 if (orig != data)
1443                         WREG32(mmUVD_CGC_CTRL, data);
1444         }
1445 }
1446
1447 static int uvd_v6_0_set_clockgating_state(void *handle,
1448                                           enum amd_clockgating_state state)
1449 {
1450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451         bool enable = (state == AMD_CG_STATE_GATE);
1452
1453         if (enable) {
1454                 /* wait for STATUS to clear */
1455                 if (uvd_v6_0_wait_for_idle(handle))
1456                         return -EBUSY;
1457                 uvd_v6_0_enable_clock_gating(adev, true);
1458                 /* enable HW gates because UVD is idle */
1459 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1460         } else {
1461                 /* disable HW gating and enable Sw gating */
1462                 uvd_v6_0_enable_clock_gating(adev, false);
1463         }
1464         uvd_v6_0_set_sw_clock_gating(adev);
1465         return 0;
1466 }
1467
1468 static int uvd_v6_0_set_powergating_state(void *handle,
1469                                           enum amd_powergating_state state)
1470 {
1471         /* This doesn't actually powergate the UVD block.
1472          * That's done in the dpm code via the SMC.  This
1473          * just re-inits the block as necessary.  The actual
1474          * gating still happens in the dpm code.  We should
1475          * revisit this when there is a cleaner line between
1476          * the smc and the hw blocks
1477          */
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479         int ret = 0;
1480
1481         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1482
1483         if (state == AMD_PG_STATE_GATE) {
1484                 uvd_v6_0_stop(adev);
1485         } else {
1486                 ret = uvd_v6_0_start(adev);
1487                 if (ret)
1488                         goto out;
1489         }
1490
1491 out:
1492         return ret;
1493 }
1494
1495 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1496 {
1497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1498         int data;
1499
1500         mutex_lock(&adev->pm.mutex);
1501
1502         if (adev->flags & AMD_IS_APU)
1503                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1504         else
1505                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1506
1507         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1508                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1509                 goto out;
1510         }
1511
1512         /* AMD_CG_SUPPORT_UVD_MGCG */
1513         data = RREG32(mmUVD_CGC_CTRL);
1514         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1515                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1516
1517 out:
1518         mutex_unlock(&adev->pm.mutex);
1519 }
1520
1521 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1522         .name = "uvd_v6_0",
1523         .early_init = uvd_v6_0_early_init,
1524         .late_init = NULL,
1525         .sw_init = uvd_v6_0_sw_init,
1526         .sw_fini = uvd_v6_0_sw_fini,
1527         .hw_init = uvd_v6_0_hw_init,
1528         .hw_fini = uvd_v6_0_hw_fini,
1529         .suspend = uvd_v6_0_suspend,
1530         .resume = uvd_v6_0_resume,
1531         .is_idle = uvd_v6_0_is_idle,
1532         .wait_for_idle = uvd_v6_0_wait_for_idle,
1533         .check_soft_reset = uvd_v6_0_check_soft_reset,
1534         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1535         .soft_reset = uvd_v6_0_soft_reset,
1536         .post_soft_reset = uvd_v6_0_post_soft_reset,
1537         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1538         .set_powergating_state = uvd_v6_0_set_powergating_state,
1539         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1540 };
1541
1542 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1543         .type = AMDGPU_RING_TYPE_UVD,
1544         .align_mask = 0xf,
1545         .support_64bit_ptrs = false,
1546         .no_user_fence = true,
1547         .get_rptr = uvd_v6_0_ring_get_rptr,
1548         .get_wptr = uvd_v6_0_ring_get_wptr,
1549         .set_wptr = uvd_v6_0_ring_set_wptr,
1550         .parse_cs = amdgpu_uvd_ring_parse_cs,
1551         .emit_frame_size =
1552                 6 + /* hdp invalidate */
1553                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1554                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1555         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1556         .emit_ib = uvd_v6_0_ring_emit_ib,
1557         .emit_fence = uvd_v6_0_ring_emit_fence,
1558         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1559         .test_ring = uvd_v6_0_ring_test_ring,
1560         .test_ib = amdgpu_uvd_ring_test_ib,
1561         .insert_nop = uvd_v6_0_ring_insert_nop,
1562         .pad_ib = amdgpu_ring_generic_pad_ib,
1563         .begin_use = amdgpu_uvd_ring_begin_use,
1564         .end_use = amdgpu_uvd_ring_end_use,
1565         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1566 };
1567
1568 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1569         .type = AMDGPU_RING_TYPE_UVD,
1570         .align_mask = 0xf,
1571         .support_64bit_ptrs = false,
1572         .no_user_fence = true,
1573         .get_rptr = uvd_v6_0_ring_get_rptr,
1574         .get_wptr = uvd_v6_0_ring_get_wptr,
1575         .set_wptr = uvd_v6_0_ring_set_wptr,
1576         .emit_frame_size =
1577                 6 + /* hdp invalidate */
1578                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1579                 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
1580                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1581         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1582         .emit_ib = uvd_v6_0_ring_emit_ib,
1583         .emit_fence = uvd_v6_0_ring_emit_fence,
1584         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1585         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1586         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1587         .test_ring = uvd_v6_0_ring_test_ring,
1588         .test_ib = amdgpu_uvd_ring_test_ib,
1589         .insert_nop = uvd_v6_0_ring_insert_nop,
1590         .pad_ib = amdgpu_ring_generic_pad_ib,
1591         .begin_use = amdgpu_uvd_ring_begin_use,
1592         .end_use = amdgpu_uvd_ring_end_use,
1593         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1594 };
1595
1596 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1597         .type = AMDGPU_RING_TYPE_UVD_ENC,
1598         .align_mask = 0x3f,
1599         .nop = HEVC_ENC_CMD_NO_OP,
1600         .support_64bit_ptrs = false,
1601         .no_user_fence = true,
1602         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1603         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1604         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1605         .emit_frame_size =
1606                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1607                 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1608                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1609                 1, /* uvd_v6_0_enc_ring_insert_end */
1610         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1611         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1612         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1613         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1614         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1615         .test_ring = uvd_v6_0_enc_ring_test_ring,
1616         .test_ib = uvd_v6_0_enc_ring_test_ib,
1617         .insert_nop = amdgpu_ring_insert_nop,
1618         .insert_end = uvd_v6_0_enc_ring_insert_end,
1619         .pad_ib = amdgpu_ring_generic_pad_ib,
1620         .begin_use = amdgpu_uvd_ring_begin_use,
1621         .end_use = amdgpu_uvd_ring_end_use,
1622 };
1623
1624 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1625 {
1626         if (adev->asic_type >= CHIP_POLARIS10) {
1627                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1628                 DRM_INFO("UVD is enabled in VM mode\n");
1629         } else {
1630                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1631                 DRM_INFO("UVD is enabled in physical mode\n");
1632         }
1633 }
1634
1635 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1636 {
1637         int i;
1638
1639         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1640                 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1641
1642         DRM_INFO("UVD ENC is enabled in VM mode\n");
1643 }
1644
1645 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1646         .set = uvd_v6_0_set_interrupt_state,
1647         .process = uvd_v6_0_process_interrupt,
1648 };
1649
1650 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1651 {
1652         if (uvd_v6_0_enc_support(adev))
1653                 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1654         else
1655                 adev->uvd.inst->irq.num_types = 1;
1656
1657         adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
1658 }
1659
1660 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1661 {
1662                 .type = AMD_IP_BLOCK_TYPE_UVD,
1663                 .major = 6,
1664                 .minor = 0,
1665                 .rev = 0,
1666                 .funcs = &uvd_v6_0_ip_funcs,
1667 };
1668
1669 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1670 {
1671                 .type = AMD_IP_BLOCK_TYPE_UVD,
1672                 .major = 6,
1673                 .minor = 2,
1674                 .rev = 0,
1675                 .funcs = &uvd_v6_0_ip_funcs,
1676 };
1677
1678 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1679 {
1680                 .type = AMD_IP_BLOCK_TYPE_UVD,
1681                 .major = 6,
1682                 .minor = 3,
1683                 .rev = 0,
1684                 .funcs = &uvd_v6_0_ip_funcs,
1685 };