drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <[email protected]>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
  55 #define FIRMWARE_POLARIS12         "amdgpu/polaris12_vce.bin"
  56
  57 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
  58
  59 #ifdef CONFIG_DRM_AMDGPU_CIK
  60 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  61 MODULE_FIRMWARE(FIRMWARE_KABINI);
  62 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  63 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  64 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  65 #endif
  66 MODULE_FIRMWARE(FIRMWARE_TONGA);
  67 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  68 MODULE_FIRMWARE(FIRMWARE_FIJI);
  69 MODULE_FIRMWARE(FIRMWARE_STONEY);
  70 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  71 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  72 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
  73
  74 MODULE_FIRMWARE(FIRMWARE_VEGA10);
  75
  76 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  77
  78 /**
  79  * amdgpu_vce_init - allocate memory, load vce firmware
  80  *
  81  * @adev: amdgpu_device pointer
  82  *
  83  * First step to get VCE online, allocate memory and load the firmware
  84  */
  85 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  86 {
  87         struct amdgpu_ring *ring;
  88         struct drm_sched_rq *rq;
  89         const char *fw_name;
  90         const struct common_firmware_header *hdr;
  91         unsigned ucode_version, version_major, version_minor, binary_id;
  92         int i, r;
  93
  94         switch (adev->asic_type) {
  95 #ifdef CONFIG_DRM_AMDGPU_CIK
  96         case CHIP_BONAIRE:
  97                 fw_name = FIRMWARE_BONAIRE;
  98                 break;
  99         case CHIP_KAVERI:
 100                 fw_name = FIRMWARE_KAVERI;
 101                 break;
 102         case CHIP_KABINI:
 103                 fw_name = FIRMWARE_KABINI;
 104                 break;
 105         case CHIP_HAWAII:
 106                 fw_name = FIRMWARE_HAWAII;
 107                 break;
 108         case CHIP_MULLINS:
 109                 fw_name = FIRMWARE_MULLINS;
 110                 break;
 111 #endif
 112         case CHIP_TONGA:
 113                 fw_name = FIRMWARE_TONGA;
 114                 break;
 115         case CHIP_CARRIZO:
 116                 fw_name = FIRMWARE_CARRIZO;
 117                 break;
 118         case CHIP_FIJI:
 119                 fw_name = FIRMWARE_FIJI;
 120                 break;
 121         case CHIP_STONEY:
 122                 fw_name = FIRMWARE_STONEY;
 123                 break;
 124         case CHIP_POLARIS10:
 125                 fw_name = FIRMWARE_POLARIS10;
 126                 break;
 127         case CHIP_POLARIS11:
 128                 fw_name = FIRMWARE_POLARIS11;
 129                 break;
 130         case CHIP_VEGA10:
 131                 fw_name = FIRMWARE_VEGA10;
 132                 break;
 133         case CHIP_POLARIS12:
 134                 fw_name = FIRMWARE_POLARIS12;
 135                 break;
 136
 137         default:
 138                 return -EINVAL;
 139         }
 140
 141         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 142         if (r) {
 143                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 144                         fw_name);
 145                 return r;
 146         }
 147
 148         r = amdgpu_ucode_validate(adev->vce.fw);
 149         if (r) {
 150                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 151                         fw_name);
 152                 release_firmware(adev->vce.fw);
 153                 adev->vce.fw = NULL;
 154                 return r;
 155         }
 156
 157         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 158
 159         ucode_version = le32_to_cpu(hdr->ucode_version);
 160         version_major = (ucode_version >> 20) & 0xfff;
 161         version_minor = (ucode_version >> 8) & 0xfff;
 162         binary_id = ucode_version & 0xff;
 163         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 164                 version_major, version_minor, binary_id);
 165         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 166                                 (binary_id << 8));
 167
 168         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 169                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 170                                     &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 171         if (r) {
 172                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 173                 return r;
 174         }
 175
 176         ring = &adev->vce.ring[0];
 177         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 178         r = drm_sched_entity_init(&ring->sched, &adev->vce.entity,
 179                                   rq, amdgpu_sched_jobs, NULL);
 180         if (r != 0) {
 181                 DRM_ERROR("Failed setting up VCE run queue.\n");
 182                 return r;
 183         }
 184
 185         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 186                 atomic_set(&adev->vce.handles[i], 0);
 187                 adev->vce.filp[i] = NULL;
 188         }
 189
 190         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 191         mutex_init(&adev->vce.idle_mutex);
 192
 193         return 0;
 194 }
 195
 196 /**
 197  * amdgpu_vce_fini - free memory
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  * Last step on VCE teardown, free firmware memory
 202  */
 203 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 204 {
 205         unsigned i;
 206
 207         if (adev->vce.vcpu_bo == NULL)
 208                 return 0;
 209
 210         drm_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 211
 212         amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
 213                 (void **)&adev->vce.cpu_addr);
 214
 215         for (i = 0; i < adev->vce.num_rings; i++)
 216                 amdgpu_ring_fini(&adev->vce.ring[i]);
 217
 218         release_firmware(adev->vce.fw);
 219         mutex_destroy(&adev->vce.idle_mutex);
 220
 221         return 0;
 222 }
 223
 224 /**
 225  * amdgpu_vce_suspend - unpin VCE fw memory
 226  *
 227  * @adev: amdgpu_device pointer
 228  *
 229  */
 230 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 231 {
 232         int i;
 233
 234         if (adev->vce.vcpu_bo == NULL)
 235                 return 0;
 236
 237         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 238                 if (atomic_read(&adev->vce.handles[i]))
 239                         break;
 240
 241         if (i == AMDGPU_MAX_VCE_HANDLES)
 242                 return 0;
 243
 244         cancel_delayed_work_sync(&adev->vce.idle_work);
 245         /* TODO: suspending running encoding sessions isn't supported */
 246         return -EINVAL;
 247 }
 248
 249 /**
 250  * amdgpu_vce_resume - pin VCE fw memory
 251  *
 252  * @adev: amdgpu_device pointer
 253  *
 254  */
 255 int amdgpu_vce_resume(struct amdgpu_device *adev)
 256 {
 257         void *cpu_addr;
 258         const struct common_firmware_header *hdr;
 259         unsigned offset;
 260         int r;
 261
 262         if (adev->vce.vcpu_bo == NULL)
 263                 return -EINVAL;
 264
 265         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 266         if (r) {
 267                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 268                 return r;
 269         }
 270
 271         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 272         if (r) {
 273                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 274                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 275                 return r;
 276         }
 277
 278         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 279         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 280         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 281                     adev->vce.fw->size - offset);
 282
 283         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 284
 285         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 286
 287         return 0;
 288 }
 289
 290 /**
 291  * amdgpu_vce_idle_work_handler - power off VCE
 292  *
 293  * @work: pointer to work structure
 294  *
 295  * power of VCE when it's not used any more
 296  */
 297 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 298 {
 299         struct amdgpu_device *adev =
 300                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 301         unsigned i, count = 0;
 302
 303         if (amdgpu_sriov_vf(adev))
 304                 return;
 305
 306         for (i = 0; i < adev->vce.num_rings; i++)
 307                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 308
 309         if (count == 0) {
 310                 if (adev->pm.dpm_enabled) {
 311                         amdgpu_dpm_enable_vce(adev, false);
 312                 } else {
 313                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 314                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 315                                                                AMD_PG_STATE_GATE);
 316                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 317                                                                AMD_CG_STATE_GATE);
 318                 }
 319         } else {
 320                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 321         }
 322 }
 323
 324 /**
 325  * amdgpu_vce_ring_begin_use - power up VCE
 326  *
 327  * @ring: amdgpu ring
 328  *
 329  * Make sure VCE is powerd up when we want to use it
 330  */
 331 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 332 {
 333         struct amdgpu_device *adev = ring->adev;
 334         bool set_clocks;
 335
 336         if (amdgpu_sriov_vf(adev))
 337                 return;
 338
 339         mutex_lock(&adev->vce.idle_mutex);
 340         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 341         if (set_clocks) {
 342                 if (adev->pm.dpm_enabled) {
 343                         amdgpu_dpm_enable_vce(adev, true);
 344                 } else {
 345                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 346                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 347                                                                AMD_CG_STATE_UNGATE);
 348                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 349                                                                AMD_PG_STATE_UNGATE);
 350
 351                 }
 352         }
 353         mutex_unlock(&adev->vce.idle_mutex);
 354 }
 355
 356 /**
 357  * amdgpu_vce_ring_end_use - power VCE down
 358  *
 359  * @ring: amdgpu ring
 360  *
 361  * Schedule work to power VCE down again
 362  */
 363 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 364 {
 365         schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 366 }
 367
 368 /**
 369  * amdgpu_vce_free_handles - free still open VCE handles
 370  *
 371  * @adev: amdgpu_device pointer
 372  * @filp: drm file pointer
 373  *
 374  * Close all VCE handles still open by this file pointer
 375  */
 376 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 377 {
 378         struct amdgpu_ring *ring = &adev->vce.ring[0];
 379         int i, r;
 380         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 381                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 382
 383                 if (!handle || adev->vce.filp[i] != filp)
 384                         continue;
 385
 386                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 387                 if (r)
 388                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 389
 390                 adev->vce.filp[i] = NULL;
 391                 atomic_set(&adev->vce.handles[i], 0);
 392         }
 393 }
 394
 395 /**
 396  * amdgpu_vce_get_create_msg - generate a VCE create msg
 397  *
 398  * @adev: amdgpu_device pointer
 399  * @ring: ring we should submit the msg to
 400  * @handle: VCE session handle to use
 401  * @fence: optional fence to return
 402  *
 403  * Open up a stream for HW test
 404  */
 405 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 406                               struct dma_fence **fence)
 407 {
 408         const unsigned ib_size_dw = 1024;
 409         struct amdgpu_job *job;
 410         struct amdgpu_ib *ib;
 411         struct dma_fence *f = NULL;
 412         uint64_t dummy;
 413         int i, r;
 414
 415         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 416         if (r)
 417                 return r;
 418
 419         ib = &job->ibs[0];
 420
 421         dummy = ib->gpu_addr + 1024;
 422
 423         /* stitch together an VCE create msg */
 424         ib->length_dw = 0;
 425         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 426         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 427         ib->ptr[ib->length_dw++] = handle;
 428
 429         if ((ring->adev->vce.fw_version >> 24) >= 52)
 430                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 431         else
 432                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 433         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 434         ib->ptr[ib->length_dw++] = 0x00000000;
 435         ib->ptr[ib->length_dw++] = 0x00000042;
 436         ib->ptr[ib->length_dw++] = 0x0000000a;
 437         ib->ptr[ib->length_dw++] = 0x00000001;
 438         ib->ptr[ib->length_dw++] = 0x00000080;
 439         ib->ptr[ib->length_dw++] = 0x00000060;
 440         ib->ptr[ib->length_dw++] = 0x00000100;
 441         ib->ptr[ib->length_dw++] = 0x00000100;
 442         ib->ptr[ib->length_dw++] = 0x0000000c;
 443         ib->ptr[ib->length_dw++] = 0x00000000;
 444         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 445                 ib->ptr[ib->length_dw++] = 0x00000000;
 446                 ib->ptr[ib->length_dw++] = 0x00000000;
 447                 ib->ptr[ib->length_dw++] = 0x00000000;
 448                 ib->ptr[ib->length_dw++] = 0x00000000;
 449         }
 450
 451         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 452         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 453         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 454         ib->ptr[ib->length_dw++] = dummy;
 455         ib->ptr[ib->length_dw++] = 0x00000001;
 456
 457         for (i = ib->length_dw; i < ib_size_dw; ++i)
 458                 ib->ptr[i] = 0x0;
 459
 460         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 461         job->fence = dma_fence_get(f);
 462         if (r)
 463                 goto err;
 464
 465         amdgpu_job_free(job);
 466         if (fence)
 467                 *fence = dma_fence_get(f);
 468         dma_fence_put(f);
 469         return 0;
 470
 471 err:
 472         amdgpu_job_free(job);
 473         return r;
 474 }
 475
 476 /**
 477  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 478  *
 479  * @adev: amdgpu_device pointer
 480  * @ring: ring we should submit the msg to
 481  * @handle: VCE session handle to use
 482  * @fence: optional fence to return
 483  *
 484  * Close up a stream for HW test or if userspace failed to do so
 485  */
 486 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 487                                bool direct, struct dma_fence **fence)
 488 {
 489         const unsigned ib_size_dw = 1024;
 490         struct amdgpu_job *job;
 491         struct amdgpu_ib *ib;
 492         struct dma_fence *f = NULL;
 493         int i, r;
 494
 495         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 496         if (r)
 497                 return r;
 498
 499         ib = &job->ibs[0];
 500
 501         /* stitch together an VCE destroy msg */
 502         ib->length_dw = 0;
 503         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 504         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 505         ib->ptr[ib->length_dw++] = handle;
 506
 507         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 508         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 509         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 510         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 511         ib->ptr[ib->length_dw++] = 0x00000000;
 512         ib->ptr[ib->length_dw++] = 0x00000000;
 513         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 514         ib->ptr[ib->length_dw++] = 0x00000000;
 515
 516         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 517         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 518
 519         for (i = ib->length_dw; i < ib_size_dw; ++i)
 520                 ib->ptr[i] = 0x0;
 521
 522         if (direct) {
 523                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 524                 job->fence = dma_fence_get(f);
 525                 if (r)
 526                         goto err;
 527
 528                 amdgpu_job_free(job);
 529         } else {
 530                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 531                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 532                 if (r)
 533                         goto err;
 534         }
 535
 536         if (fence)
 537                 *fence = dma_fence_get(f);
 538         dma_fence_put(f);
 539         return 0;
 540
 541 err:
 542         amdgpu_job_free(job);
 543         return r;
 544 }
 545
 546 /**
 547  * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
 548  *
 549  * @p: parser context
 550  * @lo: address of lower dword
 551  * @hi: address of higher dword
 552  * @size: minimum size
 553  * @index: bs/fb index
 554  *
 555  * Make sure that no BO cross a 4GB boundary.
 556  */
 557 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 558                                   int lo, int hi, unsigned size, int32_t index)
 559 {
 560         int64_t offset = ((uint64_t)size) * ((int64_t)index);
 561         struct ttm_operation_ctx ctx = { false, false };
 562         struct amdgpu_bo_va_mapping *mapping;
 563         unsigned i, fpfn, lpfn;
 564         struct amdgpu_bo *bo;
 565         uint64_t addr;
 566         int r;
 567
 568         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 569                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 570         if (index >= 0) {
 571                 addr += offset;
 572                 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
 573                 lpfn = 0x100000000ULL >> PAGE_SHIFT;
 574         } else {
 575                 fpfn = 0;
 576                 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
 577         }
 578
 579         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 580         if (r) {
 581                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 582                           addr, lo, hi, size, index);
 583                 return r;
 584         }
 585
 586         for (i = 0; i < bo->placement.num_placement; ++i) {
 587                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
 588                 bo->placements[i].lpfn = bo->placements[i].lpfn ?
 589                         min(bo->placements[i].lpfn, lpfn) : lpfn;
 590         }
 591         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 592 }
 593
 594
 595 /**
 596  * amdgpu_vce_cs_reloc - command submission relocation
 597  *
 598  * @p: parser context
 599  * @lo: address of lower dword
 600  * @hi: address of higher dword
 601  * @size: minimum size
 602  *
 603  * Patch relocation inside command stream with real buffer address
 604  */
 605 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 606                                int lo, int hi, unsigned size, uint32_t index)
 607 {
 608         struct amdgpu_bo_va_mapping *mapping;
 609         struct amdgpu_bo *bo;
 610         uint64_t addr;
 611         int r;
 612
 613         if (index == 0xffffffff)
 614                 index = 0;
 615
 616         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 617                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 618         addr += ((uint64_t)size) * ((uint64_t)index);
 619
 620         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 621         if (r) {
 622                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 623                           addr, lo, hi, size, index);
 624                 return r;
 625         }
 626
 627         if ((addr + (uint64_t)size) >
 628             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 629                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 630                           addr, lo, hi);
 631                 return -EINVAL;
 632         }
 633
 634         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 635         addr += amdgpu_bo_gpu_offset(bo);
 636         addr -= ((uint64_t)size) * ((uint64_t)index);
 637
 638         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 639         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 640
 641         return 0;
 642 }
 643
 644 /**
 645  * amdgpu_vce_validate_handle - validate stream handle
 646  *
 647  * @p: parser context
 648  * @handle: handle to validate
 649  * @allocated: allocated a new handle?
 650  *
 651  * Validates the handle and return the found session index or -EINVAL
 652  * we we don't have another free session index.
 653  */
 654 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 655                                       uint32_t handle, uint32_t *allocated)
 656 {
 657         unsigned i;
 658
 659         /* validate the handle */
 660         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 661                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 662                         if (p->adev->vce.filp[i] != p->filp) {
 663                                 DRM_ERROR("VCE handle collision detected!\n");
 664                                 return -EINVAL;
 665                         }
 666                         return i;
 667                 }
 668         }
 669
 670         /* handle not found try to alloc a new one */
 671         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 672                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 673                         p->adev->vce.filp[i] = p->filp;
 674                         p->adev->vce.img_size[i] = 0;
 675                         *allocated |= 1 << i;
 676                         return i;
 677                 }
 678         }
 679
 680         DRM_ERROR("No more free VCE handles!\n");
 681         return -EINVAL;
 682 }
 683
 684 /**
 685  * amdgpu_vce_cs_parse - parse and validate the command stream
 686  *
 687  * @p: parser context
 688  *
 689  */
 690 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 691 {
 692         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 693         unsigned fb_idx = 0, bs_idx = 0;
 694         int session_idx = -1;
 695         uint32_t destroyed = 0;
 696         uint32_t created = 0;
 697         uint32_t allocated = 0;
 698         uint32_t tmp, handle = 0;
 699         uint32_t *size = &tmp;
 700         unsigned idx;
 701         int i, r = 0;
 702
 703         p->job->vm = NULL;
 704         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 705
 706         for (idx = 0; idx < ib->length_dw;) {
 707                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 708                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 709
 710                 if ((len < 8) || (len & 3)) {
 711                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 712                         r = -EINVAL;
 713                         goto out;
 714                 }
 715
 716                 switch (cmd) {
 717                 case 0x00000002: /* task info */
 718                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 719                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 720                         break;
 721
 722                 case 0x03000001: /* encode */
 723                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
 724                                                    idx + 9, 0, 0);
 725                         if (r)
 726                                 goto out;
 727
 728                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
 729                                                    idx + 11, 0, 0);
 730                         if (r)
 731                                 goto out;
 732                         break;
 733
 734                 case 0x05000001: /* context buffer */
 735                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 736                                                    idx + 2, 0, 0);
 737                         if (r)
 738                                 goto out;
 739                         break;
 740
 741                 case 0x05000004: /* video bitstream buffer */
 742                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 743                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 744                                                    tmp, bs_idx);
 745                         if (r)
 746                                 goto out;
 747                         break;
 748
 749                 case 0x05000005: /* feedback buffer */
 750                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 751                                                    4096, fb_idx);
 752                         if (r)
 753                                 goto out;
 754                         break;
 755                 }
 756
 757                 idx += len / 4;
 758         }
 759
 760         for (idx = 0; idx < ib->length_dw;) {
 761                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 762                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 763
 764                 switch (cmd) {
 765                 case 0x00000001: /* session */
 766                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 767                         session_idx = amdgpu_vce_validate_handle(p, handle,
 768                                                                  &allocated);
 769                         if (session_idx < 0) {
 770                                 r = session_idx;
 771                                 goto out;
 772                         }
 773                         size = &p->adev->vce.img_size[session_idx];
 774                         break;
 775
 776                 case 0x00000002: /* task info */
 777                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 778                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 779                         break;
 780
 781                 case 0x01000001: /* create */
 782                         created |= 1 << session_idx;
 783                         if (destroyed & (1 << session_idx)) {
 784                                 destroyed &= ~(1 << session_idx);
 785                                 allocated |= 1 << session_idx;
 786
 787                         } else if (!(allocated & (1 << session_idx))) {
 788                                 DRM_ERROR("Handle already in use!\n");
 789                                 r = -EINVAL;
 790                                 goto out;
 791                         }
 792
 793                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 794                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 795                                 8 * 3 / 2;
 796                         break;
 797
 798                 case 0x04000001: /* config extension */
 799                 case 0x04000002: /* pic control */
 800                 case 0x04000005: /* rate control */
 801                 case 0x04000007: /* motion estimation */
 802                 case 0x04000008: /* rdo */
 803                 case 0x04000009: /* vui */
 804                 case 0x05000002: /* auxiliary buffer */
 805                 case 0x05000009: /* clock table */
 806                         break;
 807
 808                 case 0x0500000c: /* hw config */
 809                         switch (p->adev->asic_type) {
 810 #ifdef CONFIG_DRM_AMDGPU_CIK
 811                         case CHIP_KAVERI:
 812                         case CHIP_MULLINS:
 813 #endif
 814                         case CHIP_CARRIZO:
 815                                 break;
 816                         default:
 817                                 r = -EINVAL;
 818                                 goto out;
 819                         }
 820                         break;
 821
 822                 case 0x03000001: /* encode */
 823                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 824                                                 *size, 0);
 825                         if (r)
 826                                 goto out;
 827
 828                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 829                                                 *size / 3, 0);
 830                         if (r)
 831                                 goto out;
 832                         break;
 833
 834                 case 0x02000001: /* destroy */
 835                         destroyed |= 1 << session_idx;
 836                         break;
 837
 838                 case 0x05000001: /* context buffer */
 839                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 840                                                 *size * 2, 0);
 841                         if (r)
 842                                 goto out;
 843                         break;
 844
 845                 case 0x05000004: /* video bitstream buffer */
 846                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 847                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 848                                                 tmp, bs_idx);
 849                         if (r)
 850                                 goto out;
 851                         break;
 852
 853                 case 0x05000005: /* feedback buffer */
 854                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 855                                                 4096, fb_idx);
 856                         if (r)
 857                                 goto out;
 858                         break;
 859
 860                 default:
 861                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 862                         r = -EINVAL;
 863                         goto out;
 864                 }
 865
 866                 if (session_idx == -1) {
 867                         DRM_ERROR("no session command at start of IB\n");
 868                         r = -EINVAL;
 869                         goto out;
 870                 }
 871
 872                 idx += len / 4;
 873         }
 874
 875         if (allocated & ~created) {
 876                 DRM_ERROR("New session without create command!\n");
 877                 r = -ENOENT;
 878         }
 879
 880 out:
 881         if (!r) {
 882                 /* No error, free all destroyed handle slots */
 883                 tmp = destroyed;
 884         } else {
 885                 /* Error during parsing, free all allocated handle slots */
 886                 tmp = allocated;
 887         }
 888
 889         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 890                 if (tmp & (1 << i))
 891                         atomic_set(&p->adev->vce.handles[i], 0);
 892
 893         return r;
 894 }
 895
 896 /**
 897  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 898  *
 899  * @p: parser context
 900  *
 901  */
 902 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 903 {
 904         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 905         int session_idx = -1;
 906         uint32_t destroyed = 0;
 907         uint32_t created = 0;
 908         uint32_t allocated = 0;
 909         uint32_t tmp, handle = 0;
 910         int i, r = 0, idx = 0;
 911
 912         while (idx < ib->length_dw) {
 913                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 914                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 915
 916                 if ((len < 8) || (len & 3)) {
 917                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 918                         r = -EINVAL;
 919                         goto out;
 920                 }
 921
 922                 switch (cmd) {
 923                 case 0x00000001: /* session */
 924                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 925                         session_idx = amdgpu_vce_validate_handle(p, handle,
 926                                                                  &allocated);
 927                         if (session_idx < 0) {
 928                                 r = session_idx;
 929                                 goto out;
 930                         }
 931                         break;
 932
 933                 case 0x01000001: /* create */
 934                         created |= 1 << session_idx;
 935                         if (destroyed & (1 << session_idx)) {
 936                                 destroyed &= ~(1 << session_idx);
 937                                 allocated |= 1 << session_idx;
 938
 939                         } else if (!(allocated & (1 << session_idx))) {
 940                                 DRM_ERROR("Handle already in use!\n");
 941                                 r = -EINVAL;
 942                                 goto out;
 943                         }
 944
 945                         break;
 946
 947                 case 0x02000001: /* destroy */
 948                         destroyed |= 1 << session_idx;
 949                         break;
 950
 951                 default:
 952                         break;
 953                 }
 954
 955                 if (session_idx == -1) {
 956                         DRM_ERROR("no session command at start of IB\n");
 957                         r = -EINVAL;
 958                         goto out;
 959                 }
 960
 961                 idx += len / 4;
 962         }
 963
 964         if (allocated & ~created) {
 965                 DRM_ERROR("New session without create command!\n");
 966                 r = -ENOENT;
 967         }
 968
 969 out:
 970         if (!r) {
 971                 /* No error, free all destroyed handle slots */
 972                 tmp = destroyed;
 973                 amdgpu_ib_free(p->adev, ib, NULL);
 974         } else {
 975                 /* Error during parsing, free all allocated handle slots */
 976                 tmp = allocated;
 977         }
 978
 979         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 980                 if (tmp & (1 << i))
 981                         atomic_set(&p->adev->vce.handles[i], 0);
 982
 983         return r;
 984 }
 985
 986 /**
 987  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 988  *
 989  * @ring: engine to use
 990  * @ib: the IB to execute
 991  *
 992  */
 993 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
 994                              unsigned vmid, bool ctx_switch)
 995 {
 996         amdgpu_ring_write(ring, VCE_CMD_IB);
 997         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 998         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 999         amdgpu_ring_write(ring, ib->length_dw);
1000 }
1001
1002 /**
1003  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1004  *
1005  * @ring: engine to use
1006  * @fence: the fence
1007  *
1008  */
1009 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1010                                 unsigned flags)
1011 {
1012         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1013
1014         amdgpu_ring_write(ring, VCE_CMD_FENCE);
1015         amdgpu_ring_write(ring, addr);
1016         amdgpu_ring_write(ring, upper_32_bits(addr));
1017         amdgpu_ring_write(ring, seq);
1018         amdgpu_ring_write(ring, VCE_CMD_TRAP);
1019         amdgpu_ring_write(ring, VCE_CMD_END);
1020 }
1021
1022 /**
1023  * amdgpu_vce_ring_test_ring - test if VCE ring is working
1024  *
1025  * @ring: the engine to test on
1026  *
1027  */
1028 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1029 {
1030         struct amdgpu_device *adev = ring->adev;
1031         uint32_t rptr = amdgpu_ring_get_rptr(ring);
1032         unsigned i;
1033         int r, timeout = adev->usec_timeout;
1034
1035         /* skip ring test for sriov*/
1036         if (amdgpu_sriov_vf(adev))
1037                 return 0;
1038
1039         r = amdgpu_ring_alloc(ring, 16);
1040         if (r) {
1041                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
1042                           ring->idx, r);
1043                 return r;
1044         }
1045         amdgpu_ring_write(ring, VCE_CMD_END);
1046         amdgpu_ring_commit(ring);
1047
1048         for (i = 0; i < timeout; i++) {
1049                 if (amdgpu_ring_get_rptr(ring) != rptr)
1050                         break;
1051                 DRM_UDELAY(1);
1052         }
1053
1054         if (i < timeout) {
1055                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1056                          ring->idx, i);
1057         } else {
1058                 DRM_ERROR("amdgpu: ring %d test failed\n",
1059                           ring->idx);
1060                 r = -ETIMEDOUT;
1061         }
1062
1063         return r;
1064 }
1065
1066 /**
1067  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1068  *
1069  * @ring: the engine to test on
1070  *
1071  */
1072 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1073 {
1074         struct dma_fence *fence = NULL;
1075         long r;
1076
1077         /* skip vce ring1/2 ib test for now, since it's not reliable */
1078         if (ring != &ring->adev->vce.ring[0])
1079                 return 0;
1080
1081         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1082         if (r) {
1083                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1084                 goto error;
1085         }
1086
1087         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1088         if (r) {
1089                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1090                 goto error;
1091         }
1092
1093         r = dma_fence_wait_timeout(fence, false, timeout);
1094         if (r == 0) {
1095                 DRM_ERROR("amdgpu: IB test timed out.\n");
1096                 r = -ETIMEDOUT;
1097         } else if (r < 0) {
1098                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1099         } else {
1100                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1101                 r = 0;
1102         }
1103 error:
1104         dma_fence_put(fence);
1105         return r;
1106 }