drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amd_pcie.h"
  30 #include "sid.h"
  31 #include "r600_dpm.h"
  32 #include "si_dpm.h"
  33 #include "atom.h"
  34 #include "../include/pptable.h"
  35 #include <linux/math64.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/firmware.h>
  38
  39 #define MC_CG_ARB_FREQ_F0           0x0a
  40 #define MC_CG_ARB_FREQ_F1           0x0b
  41 #define MC_CG_ARB_FREQ_F2           0x0c
  42 #define MC_CG_ARB_FREQ_F3           0x0d
  43
  44 #define SMC_RAM_END                 0x20000
  45
  46 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  47
  48
  49 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  56
  57 #define BIOS_SCRATCH_4                                    0x5cd
  58
  59 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  60 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  61 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  62 MODULE_FIRMWARE("radeon/verde_smc.bin");
  63 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  64 MODULE_FIRMWARE("radeon/oland_smc.bin");
  65 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  66 MODULE_FIRMWARE("radeon/hainan_smc.bin");
  67 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  68 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
  69
  70 union power_info {
  71         struct _ATOM_POWERPLAY_INFO info;
  72         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  73         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  74         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  75         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  76         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  77         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  78         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  79 };
  80
  81 union fan_info {
  82         struct _ATOM_PPLIB_FANTABLE fan;
  83         struct _ATOM_PPLIB_FANTABLE2 fan2;
  84         struct _ATOM_PPLIB_FANTABLE3 fan3;
  85 };
  86
  87 union pplib_clock_info {
  88         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  89         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  90         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  91         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  92         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  93 };
  94
  95 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  96 {
  97         R600_UTC_DFLT_00,
  98         R600_UTC_DFLT_01,
  99         R600_UTC_DFLT_02,
 100         R600_UTC_DFLT_03,
 101         R600_UTC_DFLT_04,
 102         R600_UTC_DFLT_05,
 103         R600_UTC_DFLT_06,
 104         R600_UTC_DFLT_07,
 105         R600_UTC_DFLT_08,
 106         R600_UTC_DFLT_09,
 107         R600_UTC_DFLT_10,
 108         R600_UTC_DFLT_11,
 109         R600_UTC_DFLT_12,
 110         R600_UTC_DFLT_13,
 111         R600_UTC_DFLT_14,
 112 };
 113
 114 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 115 {
 116         R600_DTC_DFLT_00,
 117         R600_DTC_DFLT_01,
 118         R600_DTC_DFLT_02,
 119         R600_DTC_DFLT_03,
 120         R600_DTC_DFLT_04,
 121         R600_DTC_DFLT_05,
 122         R600_DTC_DFLT_06,
 123         R600_DTC_DFLT_07,
 124         R600_DTC_DFLT_08,
 125         R600_DTC_DFLT_09,
 126         R600_DTC_DFLT_10,
 127         R600_DTC_DFLT_11,
 128         R600_DTC_DFLT_12,
 129         R600_DTC_DFLT_13,
 130         R600_DTC_DFLT_14,
 131 };
 132
 133 static const struct si_cac_config_reg cac_weights_tahiti[] =
 134 {
 135         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 136         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 137         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 138         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 139         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 140         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 143         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 144         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 145         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 146         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 147         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 148         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 149         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 150         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 152         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 153         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 154         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 155         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 156         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 157         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 165         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 166         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 170         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 173         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 174         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 175         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 193         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 194         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 195         { 0xFFFFFFFF }
 196 };
 197
 198 static const struct si_cac_config_reg lcac_tahiti[] =
 199 {
 200         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 201         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 202         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 203         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 204         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 205         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 206         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 207         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 208         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 209         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 210         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 211         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 212         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 213         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 214         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 215         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 216         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 217         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 218         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 219         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 220         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 221         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 222         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 223         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 224         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 225         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 226         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 227         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 228         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 229         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 230         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 231         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 232         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 233         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 234         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 235         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 236         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 237         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 238         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 239         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 240         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 241         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 242         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 243         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 244         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 245         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 246         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 247         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 248         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 249         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 250         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 251         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 252         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 253         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 254         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 255         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 256         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 257         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 258         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 259         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 260         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 261         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 262         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 263         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 264         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 265         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 266         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 267         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 268         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 269         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 270         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 271         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 272         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 273         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 274         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 275         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 276         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 277         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 278         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 279         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 280         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 281         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 282         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 283         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 284         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 285         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 286         { 0xFFFFFFFF }
 287
 288 };
 289
 290 static const struct si_cac_config_reg cac_override_tahiti[] =
 291 {
 292         { 0xFFFFFFFF }
 293 };
 294
 295 static const struct si_powertune_data powertune_data_tahiti =
 296 {
 297         ((1 << 16) | 27027),
 298         6,
 299         0,
 300         4,
 301         95,
 302         {
 303                 0UL,
 304                 0UL,
 305                 4521550UL,
 306                 309631529UL,
 307                 -1270850L,
 308                 4513710L,
 309                 40
 310         },
 311         595000000UL,
 312         12,
 313         {
 314                 0,
 315                 0,
 316                 0,
 317                 0,
 318                 0,
 319                 0,
 320                 0,
 321                 0
 322         },
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_tahiti =
 327 {
 328         { 1159409, 0, 0, 0, 0 },
 329         { 777, 0, 0, 0, 0 },
 330         2,
 331         54000,
 332         127000,
 333         25,
 334         2,
 335         10,
 336         13,
 337         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 338         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 339         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 340         85,
 341         false
 342 };
 343
 344 #if 0
 345 static const struct si_dte_data dte_data_tahiti_le =
 346 {
 347         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 348         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 349         0x5,
 350         0xAFC8,
 351         0x64,
 352         0x32,
 353         1,
 354         0,
 355         0x10,
 356         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 357         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 358         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 359         85,
 360         true
 361 };
 362 #endif
 363
 364 static const struct si_dte_data dte_data_tahiti_pro =
 365 {
 366         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 367         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 368         5,
 369         45000,
 370         100,
 371         0xA,
 372         1,
 373         0,
 374         0x10,
 375         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 376         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 377         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 378         90,
 379         true
 380 };
 381
 382 static const struct si_dte_data dte_data_new_zealand =
 383 {
 384         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 385         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 386         0x5,
 387         0xAFC8,
 388         0x69,
 389         0x32,
 390         1,
 391         0,
 392         0x10,
 393         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 394         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 395         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 396         85,
 397         true
 398 };
 399
 400 static const struct si_dte_data dte_data_aruba_pro =
 401 {
 402         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 403         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 404         5,
 405         45000,
 406         100,
 407         0xA,
 408         1,
 409         0,
 410         0x10,
 411         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 412         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 413         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 414         90,
 415         true
 416 };
 417
 418 static const struct si_dte_data dte_data_malta =
 419 {
 420         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 421         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 422         5,
 423         45000,
 424         100,
 425         0xA,
 426         1,
 427         0,
 428         0x10,
 429         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 430         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 431         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 432         90,
 433         true
 434 };
 435
 436 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 437 {
 438         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 439         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 440         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 441         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 442         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 443         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 444         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 445         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 446         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 447         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 448         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 449         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 450         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 451         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 452         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 455         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 456         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 457         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 458         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 459         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 460         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 461         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 463         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 464         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 465         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 468         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 469         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 471         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 472         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 473         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 474         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 475         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 491         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 492         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 493         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 494         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 495         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 496         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 497         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 498         { 0xFFFFFFFF }
 499 };
 500
 501 static const struct si_cac_config_reg lcac_pitcairn[] =
 502 {
 503         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 504         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 505         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 506         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 507         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 508         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 509         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 510         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 511         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 512         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 513         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 514         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 515         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 516         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 517         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 518         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 519         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 520         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 521         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 522         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 523         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 524         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 525         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 526         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 527         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 528         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 529         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 530         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 531         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 532         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 533         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 534         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 535         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 536         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 537         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 538         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 539         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 540         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 541         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 542         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 543         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 544         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 545         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 546         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 547         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 548         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 549         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 550         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 551         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 552         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 553         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 554         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 555         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 556         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 557         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 558         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 559         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 560         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 561         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 562         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 563         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 564         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 565         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 566         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 567         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 568         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 569         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 570         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 571         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 572         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 573         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 574         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 575         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 576         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 577         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 578         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 579         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 580         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 581         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 582         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 583         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 584         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 585         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 586         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 587         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 588         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 589         { 0xFFFFFFFF }
 590 };
 591
 592 static const struct si_cac_config_reg cac_override_pitcairn[] =
 593 {
 594     { 0xFFFFFFFF }
 595 };
 596
 597 static const struct si_powertune_data powertune_data_pitcairn =
 598 {
 599         ((1 << 16) | 27027),
 600         5,
 601         0,
 602         6,
 603         100,
 604         {
 605                 51600000UL,
 606                 1800000UL,
 607                 7194395UL,
 608                 309631529UL,
 609                 -1270850L,
 610                 4513710L,
 611                 100
 612         },
 613         117830498UL,
 614         12,
 615         {
 616                 0,
 617                 0,
 618                 0,
 619                 0,
 620                 0,
 621                 0,
 622                 0,
 623                 0
 624         },
 625         true
 626 };
 627
 628 static const struct si_dte_data dte_data_pitcairn =
 629 {
 630         { 0, 0, 0, 0, 0 },
 631         { 0, 0, 0, 0, 0 },
 632         0,
 633         0,
 634         0,
 635         0,
 636         0,
 637         0,
 638         0,
 639         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 641         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 642         0,
 643         false
 644 };
 645
 646 static const struct si_dte_data dte_data_curacao_xt =
 647 {
 648         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 649         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 650         5,
 651         45000,
 652         100,
 653         0xA,
 654         1,
 655         0,
 656         0x10,
 657         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 658         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 659         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 660         90,
 661         true
 662 };
 663
 664 static const struct si_dte_data dte_data_curacao_pro =
 665 {
 666         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 667         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 668         5,
 669         45000,
 670         100,
 671         0xA,
 672         1,
 673         0,
 674         0x10,
 675         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 676         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 677         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 678         90,
 679         true
 680 };
 681
 682 static const struct si_dte_data dte_data_neptune_xt =
 683 {
 684         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 685         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 686         5,
 687         45000,
 688         100,
 689         0xA,
 690         1,
 691         0,
 692         0x10,
 693         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 694         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 695         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 696         90,
 697         true
 698 };
 699
 700 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 701 {
 702         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 703         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 704         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 705         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 706         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 707         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 708         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 709         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 710         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 711         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 712         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 713         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 714         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 715         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 716         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 717         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 718         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 719         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 720         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 721         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 722         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 723         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 724         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 725         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 726         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 727         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 728         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 729         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 731         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 732         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 733         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 734         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 735         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 736         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 737         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 738         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 740         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 741         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 742         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 743         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 755         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 757         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 758         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 759         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 760         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 761         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 762         { 0xFFFFFFFF }
 763 };
 764
 765 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 766 {
 767         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 768         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 769         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 770         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 771         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 772         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 773         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 774         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 775         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 776         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 777         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 778         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 779         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 780         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 781         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 782         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 783         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 784         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 785         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 786         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 787         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 788         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 789         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 790         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 791         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 792         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 793         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 794         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 796         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 797         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 798         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 799         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 800         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 801         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 802         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 803         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 805         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 806         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 807         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 808         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 820         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 822         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 823         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 824         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 825         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 826         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 827         { 0xFFFFFFFF }
 828 };
 829
 830 static const struct si_cac_config_reg cac_weights_heathrow[] =
 831 {
 832         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 833         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 834         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 835         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 836         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 837         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 838         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 839         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 840         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 841         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 842         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 843         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 844         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 845         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 846         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 847         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 848         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 849         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 850         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 851         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 852         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 853         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 854         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 855         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 856         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 857         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 858         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 859         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 861         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 862         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 863         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 864         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 865         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 866         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 867         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 868         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 870         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 871         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 872         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 873         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 885         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 887         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 888         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 889         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 890         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 891         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 892         { 0xFFFFFFFF }
 893 };
 894
 895 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 896 {
 897         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 898         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 899         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 900         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 901         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 902         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 903         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 904         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 905         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 906         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 907         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 908         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 909         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 910         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 911         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 912         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 913         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 914         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 915         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 916         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 917         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 918         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 919         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 920         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 921         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 922         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 923         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 924         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 926         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 927         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 928         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 929         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 930         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 931         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 932         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 933         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 935         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 936         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 937         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 938         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 950         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 952         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 953         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 954         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 955         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 956         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 957         { 0xFFFFFFFF }
 958 };
 959
 960 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 961 {
 962         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 963         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 964         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 965         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 966         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 967         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 968         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 969         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 970         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 971         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 972         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 973         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 974         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 975         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 976         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 977         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 978         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 979         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 980         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 981         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 982         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 983         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 984         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 985         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 986         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 987         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 988         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 989         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 990         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 992         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 993         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 994         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 995         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 996         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 997         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 998         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1000         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1001         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1002         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1003         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1015         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1016         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1017         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1018         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1019         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1020         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1021         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1022         { 0xFFFFFFFF }
1023 };
1024
1025 static const struct si_cac_config_reg lcac_cape_verde[] =
1026 {
1027         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1028         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1029         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1030         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1032         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1034         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1036         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1040         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1042         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1044         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1046         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1052         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1054         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1058         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1060         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1062         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1064         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1066         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1067         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1068         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1071         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1072         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1075         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1076         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1077         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1078         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1079         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1080         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1081         { 0xFFFFFFFF }
1082 };
1083
1084 static const struct si_cac_config_reg cac_override_cape_verde[] =
1085 {
1086     { 0xFFFFFFFF }
1087 };
1088
1089 static const struct si_powertune_data powertune_data_cape_verde =
1090 {
1091         ((1 << 16) | 0x6993),
1092         5,
1093         0,
1094         7,
1095         105,
1096         {
1097                 0UL,
1098                 0UL,
1099                 7194395UL,
1100                 309631529UL,
1101                 -1270850L,
1102                 4513710L,
1103                 100
1104         },
1105         117830498UL,
1106         12,
1107         {
1108                 0,
1109                 0,
1110                 0,
1111                 0,
1112                 0,
1113                 0,
1114                 0,
1115                 0
1116         },
1117         true
1118 };
1119
1120 static const struct si_dte_data dte_data_cape_verde =
1121 {
1122         { 0, 0, 0, 0, 0 },
1123         { 0, 0, 0, 0, 0 },
1124         0,
1125         0,
1126         0,
1127         0,
1128         0,
1129         0,
1130         0,
1131         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1134         0,
1135         false
1136 };
1137
1138 static const struct si_dte_data dte_data_venus_xtx =
1139 {
1140         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1141         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1142         5,
1143         55000,
1144         0x69,
1145         0xA,
1146         1,
1147         0,
1148         0x3,
1149         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1152         90,
1153         true
1154 };
1155
1156 static const struct si_dte_data dte_data_venus_xt =
1157 {
1158         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1159         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1160         5,
1161         55000,
1162         0x69,
1163         0xA,
1164         1,
1165         0,
1166         0x3,
1167         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1170         90,
1171         true
1172 };
1173
1174 static const struct si_dte_data dte_data_venus_pro =
1175 {
1176         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1177         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1178         5,
1179         55000,
1180         0x69,
1181         0xA,
1182         1,
1183         0,
1184         0x3,
1185         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1188         90,
1189         true
1190 };
1191
1192 static const struct si_cac_config_reg cac_weights_oland[] =
1193 {
1194         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1195         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1196         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1197         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1198         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1199         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1200         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1201         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1202         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1203         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1204         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1205         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1206         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1207         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1208         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1209         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1210         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1211         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1212         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1213         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1214         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1215         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1216         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1217         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1218         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1219         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1220         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1221         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1223         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1224         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1225         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1226         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1227         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1228         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1229         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1230         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1232         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1233         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1234         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1235         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1247         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1250         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1252         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1253         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1254         { 0xFFFFFFFF }
1255 };
1256
1257 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1258 {
1259         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1260         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1261         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1262         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1263         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1264         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1265         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1266         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1267         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1268         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1269         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1271         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1272         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1273         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1274         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1275         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1276         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1277         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1278         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1279         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1280         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1281         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1282         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1283         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1284         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1285         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1286         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1287         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1288         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1289         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1290         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1291         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1292         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1293         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1294         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1295         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1296         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1297         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1298         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1299         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1300         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1312         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1315         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1317         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1318         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1319         { 0xFFFFFFFF }
1320 };
1321
1322 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1323 {
1324         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1325         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1326         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1327         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1328         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1329         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1330         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1331         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1332         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1333         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1334         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1336         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1337         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1338         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1339         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1340         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1341         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1342         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1343         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1344         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1345         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1346         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1347         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1348         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1349         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1350         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1351         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1352         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1353         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1354         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1355         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1356         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1357         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1358         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1359         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1360         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1361         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1362         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1363         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1364         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1365         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1377         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1380         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1382         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1383         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1384         { 0xFFFFFFFF }
1385 };
1386
1387 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1388 {
1389         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1390         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1391         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1392         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1393         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1394         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1395         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1396         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1397         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1398         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1399         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1401         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1402         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1403         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1404         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1405         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1406         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1407         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1408         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1409         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1410         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1411         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1412         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1413         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1414         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1415         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1416         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1417         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1418         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1419         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1420         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1421         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1422         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1423         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1424         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1425         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1426         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1427         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1428         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1429         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1430         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1442         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1445         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1447         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1448         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1449         { 0xFFFFFFFF }
1450 };
1451
1452 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1453 {
1454         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1455         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1456         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1457         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1458         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1459         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1460         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1461         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1462         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1463         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1464         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1465         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1466         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1467         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1468         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1469         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1470         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1471         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1472         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1473         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1474         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1475         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1476         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1477         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1478         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1479         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1480         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1481         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1482         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1484         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1485         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1486         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1487         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1488         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1489         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1490         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1491         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1492         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1495         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1505         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1506         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1507         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1508         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1509         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1510         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1511         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1512         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1513         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1514         { 0xFFFFFFFF }
1515 };
1516
1517 static const struct si_cac_config_reg lcac_oland[] =
1518 {
1519         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1520         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1521         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1522         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1524         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1526         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1528         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1530         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1532         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1534         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1547         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1548         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1555         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1557         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1561         { 0xFFFFFFFF }
1562 };
1563
1564 static const struct si_cac_config_reg lcac_mars_pro[] =
1565 {
1566         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1567         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1569         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1571         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1573         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1575         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1577         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1579         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1581         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1594         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1595         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1602         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1603         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1604         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1605         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1606         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1607         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1608         { 0xFFFFFFFF }
1609 };
1610
1611 static const struct si_cac_config_reg cac_override_oland[] =
1612 {
1613         { 0xFFFFFFFF }
1614 };
1615
1616 static const struct si_powertune_data powertune_data_oland =
1617 {
1618         ((1 << 16) | 0x6993),
1619         5,
1620         0,
1621         7,
1622         105,
1623         {
1624                 0UL,
1625                 0UL,
1626                 7194395UL,
1627                 309631529UL,
1628                 -1270850L,
1629                 4513710L,
1630                 100
1631         },
1632         117830498UL,
1633         12,
1634         {
1635                 0,
1636                 0,
1637                 0,
1638                 0,
1639                 0,
1640                 0,
1641                 0,
1642                 0
1643         },
1644         true
1645 };
1646
1647 static const struct si_powertune_data powertune_data_mars_pro =
1648 {
1649         ((1 << 16) | 0x6993),
1650         5,
1651         0,
1652         7,
1653         105,
1654         {
1655                 0UL,
1656                 0UL,
1657                 7194395UL,
1658                 309631529UL,
1659                 -1270850L,
1660                 4513710L,
1661                 100
1662         },
1663         117830498UL,
1664         12,
1665         {
1666                 0,
1667                 0,
1668                 0,
1669                 0,
1670                 0,
1671                 0,
1672                 0,
1673                 0
1674         },
1675         true
1676 };
1677
1678 static const struct si_dte_data dte_data_oland =
1679 {
1680         { 0, 0, 0, 0, 0 },
1681         { 0, 0, 0, 0, 0 },
1682         0,
1683         0,
1684         0,
1685         0,
1686         0,
1687         0,
1688         0,
1689         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1692         0,
1693         false
1694 };
1695
1696 static const struct si_dte_data dte_data_mars_pro =
1697 {
1698         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1699         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1700         5,
1701         55000,
1702         105,
1703         0xA,
1704         1,
1705         0,
1706         0x10,
1707         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1708         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1709         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1710         90,
1711         true
1712 };
1713
1714 static const struct si_dte_data dte_data_sun_xt =
1715 {
1716         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1717         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1718         5,
1719         55000,
1720         105,
1721         0xA,
1722         1,
1723         0,
1724         0x10,
1725         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1726         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1727         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1728         90,
1729         true
1730 };
1731
1732
1733 static const struct si_cac_config_reg cac_weights_hainan[] =
1734 {
1735         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1736         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1737         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1738         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1739         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1740         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1741         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1743         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1744         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1745         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1746         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1747         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1748         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1749         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1750         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1752         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1753         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1754         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1755         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1756         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1757         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1758         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1759         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1760         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1761         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1762         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1765         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1766         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1769         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1770         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1771         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1772         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1775         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1777         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1788         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1789         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1790         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1791         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1792         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1793         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1794         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1795         { 0xFFFFFFFF }
1796 };
1797
1798 static const struct si_powertune_data powertune_data_hainan =
1799 {
1800         ((1 << 16) | 0x6993),
1801         5,
1802         0,
1803         9,
1804         105,
1805         {
1806                 0UL,
1807                 0UL,
1808                 7194395UL,
1809                 309631529UL,
1810                 -1270850L,
1811                 4513710L,
1812                 100
1813         },
1814         117830498UL,
1815         12,
1816         {
1817                 0,
1818                 0,
1819                 0,
1820                 0,
1821                 0,
1822                 0,
1823                 0,
1824                 0
1825         },
1826         true
1827 };
1828
1829 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1830 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1831 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1832 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1833
1834 static int si_populate_voltage_value(struct amdgpu_device *adev,
1835                                      const struct atom_voltage_table *table,
1836                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1837 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1838                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1839                                     u16 *std_voltage);
1840 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1841                                       u16 reg_offset, u32 value);
1842 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1843                                          struct rv7xx_pl *pl,
1844                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1845 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1846                                     u32 engine_clock,
1847                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1848
1849 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1850 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1851 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854 {
1855         struct si_power_info *pi = adev->pm.dpm.priv;
1856         return pi;
1857 }
1858
1859 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1861 {
1862         s64 kt, kv, leakage_w, i_leakage, vddc;
1863         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864         s64 tmp;
1865
1866         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867         vddc = div64_s64(drm_int2fixp(v), 1000);
1868         temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874         t_ref = drm_int2fixp(coeff->t_ref);
1875
1876         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883         *leakage = drm_fixp2int(leakage_w * 1000);
1884 }
1885
1886 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887                                              const struct ni_leakage_coeffients *coeff,
1888                                              u16 v,
1889                                              s32 t,
1890                                              u32 i_leakage,
1891                                              u32 *leakage)
1892 {
1893         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894 }
1895
1896 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897                                                const u32 fixed_kt, u16 v,
1898                                                u32 ileakage, u32 *leakage)
1899 {
1900         s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903         vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911         *leakage = drm_fixp2int(leakage_w * 1000);
1912 }
1913
1914 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915                                        const struct ni_leakage_coeffients *coeff,
1916                                        const u32 fixed_kt,
1917                                        u16 v,
1918                                        u32 i_leakage,
1919                                        u32 *leakage)
1920 {
1921         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922 }
1923
1924
1925 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926                                    struct si_dte_data *dte_data)
1927 {
1928         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930         u32 k = dte_data->k;
1931         u32 t_max = dte_data->max_t;
1932         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933         u32 t_0 = dte_data->t0;
1934         u32 i;
1935
1936         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937                 dte_data->tdep_count = 3;
1938
1939                 for (i = 0; i < k; i++) {
1940                         dte_data->r[i] =
1941                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942                                 (p_limit2  * (u32)100);
1943                 }
1944
1945                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948                         dte_data->tdep_r[i] = dte_data->r[4];
1949                 }
1950         } else {
1951                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952         }
1953 }
1954
1955 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956 {
1957         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959         return pi;
1960 }
1961
1962 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963 {
1964         struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966         return pi;
1967 }
1968
1969 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970 {
1971         struct  si_ps *ps = aps->ps_priv;
1972
1973         return ps;
1974 }
1975
1976 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977 {
1978         struct ni_power_info *ni_pi = ni_get_pi(adev);
1979         struct si_power_info *si_pi = si_get_pi(adev);
1980         bool update_dte_from_pl2 = false;
1981
1982         if (adev->asic_type == CHIP_TAHITI) {
1983                 si_pi->cac_weights = cac_weights_tahiti;
1984                 si_pi->lcac_config = lcac_tahiti;
1985                 si_pi->cac_override = cac_override_tahiti;
1986                 si_pi->powertune_data = &powertune_data_tahiti;
1987                 si_pi->dte_data = dte_data_tahiti;
1988
1989                 switch (adev->pdev->device) {
1990                 case 0x6798:
1991                         si_pi->dte_data.enable_dte_by_default = true;
1992                         break;
1993                 case 0x6799:
1994                         si_pi->dte_data = dte_data_new_zealand;
1995                         break;
1996                 case 0x6790:
1997                 case 0x6791:
1998                 case 0x6792:
1999                 case 0x679E:
2000                         si_pi->dte_data = dte_data_aruba_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x679B:
2004                         si_pi->dte_data = dte_data_malta;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x679A:
2008                         si_pi->dte_data = dte_data_tahiti_pro;
2009                         update_dte_from_pl2 = true;
2010                         break;
2011                 default:
2012                         if (si_pi->dte_data.enable_dte_by_default == true)
2013                                 DRM_ERROR("DTE is not enabled!\n");
2014                         break;
2015                 }
2016         } else if (adev->asic_type == CHIP_PITCAIRN) {
2017                 si_pi->cac_weights = cac_weights_pitcairn;
2018                 si_pi->lcac_config = lcac_pitcairn;
2019                 si_pi->cac_override = cac_override_pitcairn;
2020                 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022                 switch (adev->pdev->device) {
2023                 case 0x6810:
2024                 case 0x6818:
2025                         si_pi->dte_data = dte_data_curacao_xt;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6819:
2029                 case 0x6811:
2030                         si_pi->dte_data = dte_data_curacao_pro;
2031                         update_dte_from_pl2 = true;
2032                         break;
2033                 case 0x6800:
2034                 case 0x6806:
2035                         si_pi->dte_data = dte_data_neptune_xt;
2036                         update_dte_from_pl2 = true;
2037                         break;
2038                 default:
2039                         si_pi->dte_data = dte_data_pitcairn;
2040                         break;
2041                 }
2042         } else if (adev->asic_type == CHIP_VERDE) {
2043                 si_pi->lcac_config = lcac_cape_verde;
2044                 si_pi->cac_override = cac_override_cape_verde;
2045                 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047                 switch (adev->pdev->device) {
2048                 case 0x683B:
2049                 case 0x683F:
2050                 case 0x6829:
2051                 case 0x6835:
2052                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2053                         si_pi->dte_data = dte_data_cape_verde;
2054                         break;
2055                 case 0x682C:
2056                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2057                         si_pi->dte_data = dte_data_sun_xt;
2058                         update_dte_from_pl2 = true;
2059                         break;
2060                 case 0x6825:
2061                 case 0x6827:
2062                         si_pi->cac_weights = cac_weights_heathrow;
2063                         si_pi->dte_data = dte_data_cape_verde;
2064                         break;
2065                 case 0x6824:
2066                 case 0x682D:
2067                         si_pi->cac_weights = cac_weights_chelsea_xt;
2068                         si_pi->dte_data = dte_data_cape_verde;
2069                         break;
2070                 case 0x682F:
2071                         si_pi->cac_weights = cac_weights_chelsea_pro;
2072                         si_pi->dte_data = dte_data_cape_verde;
2073                         break;
2074                 case 0x6820:
2075                         si_pi->cac_weights = cac_weights_heathrow;
2076                         si_pi->dte_data = dte_data_venus_xtx;
2077                         break;
2078                 case 0x6821:
2079                         si_pi->cac_weights = cac_weights_heathrow;
2080                         si_pi->dte_data = dte_data_venus_xt;
2081                         break;
2082                 case 0x6823:
2083                 case 0x682B:
2084                 case 0x6822:
2085                 case 0x682A:
2086                         si_pi->cac_weights = cac_weights_chelsea_pro;
2087                         si_pi->dte_data = dte_data_venus_pro;
2088                         break;
2089                 default:
2090                         si_pi->cac_weights = cac_weights_cape_verde;
2091                         si_pi->dte_data = dte_data_cape_verde;
2092                         break;
2093                 }
2094         } else if (adev->asic_type == CHIP_OLAND) {
2095                 si_pi->lcac_config = lcac_mars_pro;
2096                 si_pi->cac_override = cac_override_oland;
2097                 si_pi->powertune_data = &powertune_data_mars_pro;
2098                 si_pi->dte_data = dte_data_mars_pro;
2099
2100                 switch (adev->pdev->device) {
2101                 case 0x6601:
2102                 case 0x6621:
2103                 case 0x6603:
2104                 case 0x6605:
2105                         si_pi->cac_weights = cac_weights_mars_pro;
2106                         update_dte_from_pl2 = true;
2107                         break;
2108                 case 0x6600:
2109                 case 0x6606:
2110                 case 0x6620:
2111                 case 0x6604:
2112                         si_pi->cac_weights = cac_weights_mars_xt;
2113                         update_dte_from_pl2 = true;
2114                         break;
2115                 case 0x6611:
2116                 case 0x6613:
2117                 case 0x6608:
2118                         si_pi->cac_weights = cac_weights_oland_pro;
2119                         update_dte_from_pl2 = true;
2120                         break;
2121                 case 0x6610:
2122                         si_pi->cac_weights = cac_weights_oland_xt;
2123                         update_dte_from_pl2 = true;
2124                         break;
2125                 default:
2126                         si_pi->cac_weights = cac_weights_oland;
2127                         si_pi->lcac_config = lcac_oland;
2128                         si_pi->cac_override = cac_override_oland;
2129                         si_pi->powertune_data = &powertune_data_oland;
2130                         si_pi->dte_data = dte_data_oland;
2131                         break;
2132                 }
2133         } else if (adev->asic_type == CHIP_HAINAN) {
2134                 si_pi->cac_weights = cac_weights_hainan;
2135                 si_pi->lcac_config = lcac_oland;
2136                 si_pi->cac_override = cac_override_oland;
2137                 si_pi->powertune_data = &powertune_data_hainan;
2138                 si_pi->dte_data = dte_data_sun_xt;
2139                 update_dte_from_pl2 = true;
2140         } else {
2141                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2142                 return;
2143         }
2144
2145         ni_pi->enable_power_containment = false;
2146         ni_pi->enable_cac = false;
2147         ni_pi->enable_sq_ramping = false;
2148         si_pi->enable_dte = false;
2149
2150         if (si_pi->powertune_data->enable_powertune_by_default) {
2151                 ni_pi->enable_power_containment = true;
2152                 ni_pi->enable_cac = true;
2153                 if (si_pi->dte_data.enable_dte_by_default) {
2154                         si_pi->enable_dte = true;
2155                         if (update_dte_from_pl2)
2156                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2157
2158                 }
2159                 ni_pi->enable_sq_ramping = true;
2160         }
2161
2162         ni_pi->driver_calculate_cac_leakage = true;
2163         ni_pi->cac_configuration_required = true;
2164
2165         if (ni_pi->cac_configuration_required) {
2166                 ni_pi->support_cac_long_term_average = true;
2167                 si_pi->dyn_powertune_data.l2_lta_window_size =
2168                         si_pi->powertune_data->l2_lta_window_size_default;
2169                 si_pi->dyn_powertune_data.lts_truncate =
2170                         si_pi->powertune_data->lts_truncate_default;
2171         } else {
2172                 ni_pi->support_cac_long_term_average = false;
2173                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2174                 si_pi->dyn_powertune_data.lts_truncate = 0;
2175         }
2176
2177         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2178 }
2179
2180 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2181 {
2182         return 1;
2183 }
2184
2185 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2186 {
2187         u32 xclk;
2188         u32 wintime;
2189         u32 cac_window;
2190         u32 cac_window_size;
2191
2192         xclk = amdgpu_asic_get_xclk(adev);
2193
2194         if (xclk == 0)
2195                 return 0;
2196
2197         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2198         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2199
2200         wintime = (cac_window_size * 100) / xclk;
2201
2202         return wintime;
2203 }
2204
2205 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2206 {
2207         return power_in_watts;
2208 }
2209
2210 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2211                                             bool adjust_polarity,
2212                                             u32 tdp_adjustment,
2213                                             u32 *tdp_limit,
2214                                             u32 *near_tdp_limit)
2215 {
2216         u32 adjustment_delta, max_tdp_limit;
2217
2218         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2219                 return -EINVAL;
2220
2221         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2222
2223         if (adjust_polarity) {
2224                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2225                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2226         } else {
2227                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2228                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2229                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2230                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2231                 else
2232                         *near_tdp_limit = 0;
2233         }
2234
2235         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2236                 return -EINVAL;
2237         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2238                 return -EINVAL;
2239
2240         return 0;
2241 }
2242
2243 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2244                                       struct amdgpu_ps *amdgpu_state)
2245 {
2246         struct ni_power_info *ni_pi = ni_get_pi(adev);
2247         struct si_power_info *si_pi = si_get_pi(adev);
2248
2249         if (ni_pi->enable_power_containment) {
2250                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2251                 PP_SIslands_PAPMParameters *papm_parm;
2252                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2253                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2254                 u32 tdp_limit;
2255                 u32 near_tdp_limit;
2256                 int ret;
2257
2258                 if (scaling_factor == 0)
2259                         return -EINVAL;
2260
2261                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2262
2263                 ret = si_calculate_adjusted_tdp_limits(adev,
2264                                                        false, /* ??? */
2265                                                        adev->pm.dpm.tdp_adjustment,
2266                                                        &tdp_limit,
2267                                                        &near_tdp_limit);
2268                 if (ret)
2269                         return ret;
2270
2271                 smc_table->dpm2Params.TDPLimit =
2272                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2273                 smc_table->dpm2Params.NearTDPLimit =
2274                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2275                 smc_table->dpm2Params.SafePowerLimit =
2276                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2277
2278                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2279                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2280                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2281                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2282                                                   sizeof(u32) * 3,
2283                                                   si_pi->sram_end);
2284                 if (ret)
2285                         return ret;
2286
2287                 if (si_pi->enable_ppm) {
2288                         papm_parm = &si_pi->papm_parm;
2289                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2290                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2291                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2292                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2293                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2294                         papm_parm->PlatformPowerLimit = 0xffffffff;
2295                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2296
2297                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2298                                                           (u8 *)papm_parm,
2299                                                           sizeof(PP_SIslands_PAPMParameters),
2300                                                           si_pi->sram_end);
2301                         if (ret)
2302                                 return ret;
2303                 }
2304         }
2305         return 0;
2306 }
2307
2308 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2309                                         struct amdgpu_ps *amdgpu_state)
2310 {
2311         struct ni_power_info *ni_pi = ni_get_pi(adev);
2312         struct si_power_info *si_pi = si_get_pi(adev);
2313
2314         if (ni_pi->enable_power_containment) {
2315                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2316                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2317                 int ret;
2318
2319                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2320
2321                 smc_table->dpm2Params.NearTDPLimit =
2322                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2323                 smc_table->dpm2Params.SafePowerLimit =
2324                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2325
2326                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2327                                                   (si_pi->state_table_start +
2328                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2329                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2330                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2331                                                   sizeof(u32) * 2,
2332                                                   si_pi->sram_end);
2333                 if (ret)
2334                         return ret;
2335         }
2336
2337         return 0;
2338 }
2339
2340 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2341                                                const u16 prev_std_vddc,
2342                                                const u16 curr_std_vddc)
2343 {
2344         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2345         u64 prev_vddc = (u64)prev_std_vddc;
2346         u64 curr_vddc = (u64)curr_std_vddc;
2347         u64 pwr_efficiency_ratio, n, d;
2348
2349         if ((prev_vddc == 0) || (curr_vddc == 0))
2350                 return 0;
2351
2352         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2353         d = prev_vddc * prev_vddc;
2354         pwr_efficiency_ratio = div64_u64(n, d);
2355
2356         if (pwr_efficiency_ratio > (u64)0xFFFF)
2357                 return 0;
2358
2359         return (u16)pwr_efficiency_ratio;
2360 }
2361
2362 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2363                                             struct amdgpu_ps *amdgpu_state)
2364 {
2365         struct si_power_info *si_pi = si_get_pi(adev);
2366
2367         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2368             amdgpu_state->vclk && amdgpu_state->dclk)
2369                 return true;
2370
2371         return false;
2372 }
2373
2374 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2375 {
2376         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2377
2378         return pi;
2379 }
2380
2381 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2382                                                 struct amdgpu_ps *amdgpu_state,
2383                                                 SISLANDS_SMC_SWSTATE *smc_state)
2384 {
2385         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2386         struct ni_power_info *ni_pi = ni_get_pi(adev);
2387         struct  si_ps *state = si_get_ps(amdgpu_state);
2388         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2389         u32 prev_sclk;
2390         u32 max_sclk;
2391         u32 min_sclk;
2392         u16 prev_std_vddc;
2393         u16 curr_std_vddc;
2394         int i;
2395         u16 pwr_efficiency_ratio;
2396         u8 max_ps_percent;
2397         bool disable_uvd_power_tune;
2398         int ret;
2399
2400         if (ni_pi->enable_power_containment == false)
2401                 return 0;
2402
2403         if (state->performance_level_count == 0)
2404                 return -EINVAL;
2405
2406         if (smc_state->levelCount != state->performance_level_count)
2407                 return -EINVAL;
2408
2409         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2410
2411         smc_state->levels[0].dpm2.MaxPS = 0;
2412         smc_state->levels[0].dpm2.NearTDPDec = 0;
2413         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2414         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2415         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2416
2417         for (i = 1; i < state->performance_level_count; i++) {
2418                 prev_sclk = state->performance_levels[i-1].sclk;
2419                 max_sclk  = state->performance_levels[i].sclk;
2420                 if (i == 1)
2421                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2422                 else
2423                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2424
2425                 if (prev_sclk > max_sclk)
2426                         return -EINVAL;
2427
2428                 if ((max_ps_percent == 0) ||
2429                     (prev_sclk == max_sclk) ||
2430                     disable_uvd_power_tune)
2431                         min_sclk = max_sclk;
2432                 else if (i == 1)
2433                         min_sclk = prev_sclk;
2434                 else
2435                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2436
2437                 if (min_sclk < state->performance_levels[0].sclk)
2438                         min_sclk = state->performance_levels[0].sclk;
2439
2440                 if (min_sclk == 0)
2441                         return -EINVAL;
2442
2443                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2444                                                 state->performance_levels[i-1].vddc, &vddc);
2445                 if (ret)
2446                         return ret;
2447
2448                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2449                 if (ret)
2450                         return ret;
2451
2452                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2453                                                 state->performance_levels[i].vddc, &vddc);
2454                 if (ret)
2455                         return ret;
2456
2457                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2458                 if (ret)
2459                         return ret;
2460
2461                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2462                                                                            prev_std_vddc, curr_std_vddc);
2463
2464                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2465                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2466                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2467                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2468                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2475                                          struct amdgpu_ps *amdgpu_state,
2476                                          SISLANDS_SMC_SWSTATE *smc_state)
2477 {
2478         struct ni_power_info *ni_pi = ni_get_pi(adev);
2479         struct  si_ps *state = si_get_ps(amdgpu_state);
2480         u32 sq_power_throttle, sq_power_throttle2;
2481         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2482         int i;
2483
2484         if (state->performance_level_count == 0)
2485                 return -EINVAL;
2486
2487         if (smc_state->levelCount != state->performance_level_count)
2488                 return -EINVAL;
2489
2490         if (adev->pm.dpm.sq_ramping_threshold == 0)
2491                 return -EINVAL;
2492
2493         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2494                 enable_sq_ramping = false;
2495
2496         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2497                 enable_sq_ramping = false;
2498
2499         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2500                 enable_sq_ramping = false;
2501
2502         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2503                 enable_sq_ramping = false;
2504
2505         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2506                 enable_sq_ramping = false;
2507
2508         for (i = 0; i < state->performance_level_count; i++) {
2509                 sq_power_throttle = 0;
2510                 sq_power_throttle2 = 0;
2511
2512                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2513                     enable_sq_ramping) {
2514                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2515                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2516                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2517                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2518                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2519                 } else {
2520                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2521                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2522                 }
2523
2524                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2525                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int si_enable_power_containment(struct amdgpu_device *adev,
2532                                        struct amdgpu_ps *amdgpu_new_state,
2533                                        bool enable)
2534 {
2535         struct ni_power_info *ni_pi = ni_get_pi(adev);
2536         PPSMC_Result smc_result;
2537         int ret = 0;
2538
2539         if (ni_pi->enable_power_containment) {
2540                 if (enable) {
2541                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2542                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2543                                 if (smc_result != PPSMC_Result_OK) {
2544                                         ret = -EINVAL;
2545                                         ni_pi->pc_enabled = false;
2546                                 } else {
2547                                         ni_pi->pc_enabled = true;
2548                                 }
2549                         }
2550                 } else {
2551                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2552                         if (smc_result != PPSMC_Result_OK)
2553                                 ret = -EINVAL;
2554                         ni_pi->pc_enabled = false;
2555                 }
2556         }
2557
2558         return ret;
2559 }
2560
2561 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2562 {
2563         struct si_power_info *si_pi = si_get_pi(adev);
2564         int ret = 0;
2565         struct si_dte_data *dte_data = &si_pi->dte_data;
2566         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2567         u32 table_size;
2568         u8 tdep_count;
2569         u32 i;
2570
2571         if (dte_data == NULL)
2572                 si_pi->enable_dte = false;
2573
2574         if (si_pi->enable_dte == false)
2575                 return 0;
2576
2577         if (dte_data->k <= 0)
2578                 return -EINVAL;
2579
2580         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2581         if (dte_tables == NULL) {
2582                 si_pi->enable_dte = false;
2583                 return -ENOMEM;
2584         }
2585
2586         table_size = dte_data->k;
2587
2588         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2589                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2590
2591         tdep_count = dte_data->tdep_count;
2592         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2593                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2594
2595         dte_tables->K = cpu_to_be32(table_size);
2596         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2597         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2598         dte_tables->WindowSize = dte_data->window_size;
2599         dte_tables->temp_select = dte_data->temp_select;
2600         dte_tables->DTE_mode = dte_data->dte_mode;
2601         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2602
2603         if (tdep_count > 0)
2604                 table_size--;
2605
2606         for (i = 0; i < table_size; i++) {
2607                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2608                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2609         }
2610
2611         dte_tables->Tdep_count = tdep_count;
2612
2613         for (i = 0; i < (u32)tdep_count; i++) {
2614                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2615                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2616                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2617         }
2618
2619         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2620                                           (u8 *)dte_tables,
2621                                           sizeof(Smc_SIslands_DTE_Configuration),
2622                                           si_pi->sram_end);
2623         kfree(dte_tables);
2624
2625         return ret;
2626 }
2627
2628 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2629                                           u16 *max, u16 *min)
2630 {
2631         struct si_power_info *si_pi = si_get_pi(adev);
2632         struct amdgpu_cac_leakage_table *table =
2633                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2634         u32 i;
2635         u32 v0_loadline;
2636
2637         if (table == NULL)
2638                 return -EINVAL;
2639
2640         *max = 0;
2641         *min = 0xFFFF;
2642
2643         for (i = 0; i < table->count; i++) {
2644                 if (table->entries[i].vddc > *max)
2645                         *max = table->entries[i].vddc;
2646                 if (table->entries[i].vddc < *min)
2647                         *min = table->entries[i].vddc;
2648         }
2649
2650         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2651                 return -EINVAL;
2652
2653         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2654
2655         if (v0_loadline > 0xFFFFUL)
2656                 return -EINVAL;
2657
2658         *min = (u16)v0_loadline;
2659
2660         if ((*min > *max) || (*max == 0) || (*min == 0))
2661                 return -EINVAL;
2662
2663         return 0;
2664 }
2665
2666 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2667 {
2668         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2669                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2670 }
2671
2672 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2673                                      PP_SIslands_CacConfig *cac_tables,
2674                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2675                                      u16 t0, u16 t_step)
2676 {
2677         struct si_power_info *si_pi = si_get_pi(adev);
2678         u32 leakage;
2679         unsigned int i, j;
2680         s32 t;
2681         u32 smc_leakage;
2682         u32 scaling_factor;
2683         u16 voltage;
2684
2685         scaling_factor = si_get_smc_power_scaling_factor(adev);
2686
2687         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2688                 t = (1000 * (i * t_step + t0));
2689
2690                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2691                         voltage = vddc_max - (vddc_step * j);
2692
2693                         si_calculate_leakage_for_v_and_t(adev,
2694                                                          &si_pi->powertune_data->leakage_coefficients,
2695                                                          voltage,
2696                                                          t,
2697                                                          si_pi->dyn_powertune_data.cac_leakage,
2698                                                          &leakage);
2699
2700                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2701
2702                         if (smc_leakage > 0xFFFF)
2703                                 smc_leakage = 0xFFFF;
2704
2705                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2706                                 cpu_to_be16((u16)smc_leakage);
2707                 }
2708         }
2709         return 0;
2710 }
2711
2712 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2713                                             PP_SIslands_CacConfig *cac_tables,
2714                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2715 {
2716         struct si_power_info *si_pi = si_get_pi(adev);
2717         u32 leakage;
2718         unsigned int i, j;
2719         u32 smc_leakage;
2720         u32 scaling_factor;
2721         u16 voltage;
2722
2723         scaling_factor = si_get_smc_power_scaling_factor(adev);
2724
2725         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2726                 voltage = vddc_max - (vddc_step * j);
2727
2728                 si_calculate_leakage_for_v(adev,
2729                                            &si_pi->powertune_data->leakage_coefficients,
2730                                            si_pi->powertune_data->fixed_kt,
2731                                            voltage,
2732                                            si_pi->dyn_powertune_data.cac_leakage,
2733                                            &leakage);
2734
2735                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2736
2737                 if (smc_leakage > 0xFFFF)
2738                         smc_leakage = 0xFFFF;
2739
2740                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2741                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2742                                 cpu_to_be16((u16)smc_leakage);
2743         }
2744         return 0;
2745 }
2746
2747 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2748 {
2749         struct ni_power_info *ni_pi = ni_get_pi(adev);
2750         struct si_power_info *si_pi = si_get_pi(adev);
2751         PP_SIslands_CacConfig *cac_tables = NULL;
2752         u16 vddc_max, vddc_min, vddc_step;
2753         u16 t0, t_step;
2754         u32 load_line_slope, reg;
2755         int ret = 0;
2756         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2757
2758         if (ni_pi->enable_cac == false)
2759                 return 0;
2760
2761         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2762         if (!cac_tables)
2763                 return -ENOMEM;
2764
2765         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2766         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2767         WREG32(CG_CAC_CTRL, reg);
2768
2769         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2770         si_pi->dyn_powertune_data.dc_pwr_value =
2771                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2772         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2773         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2774
2775         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2776
2777         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2778         if (ret)
2779                 goto done_free;
2780
2781         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2782         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2783         t_step = 4;
2784         t0 = 60;
2785
2786         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2787                 ret = si_init_dte_leakage_table(adev, cac_tables,
2788                                                 vddc_max, vddc_min, vddc_step,
2789                                                 t0, t_step);
2790         else
2791                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2792                                                        vddc_max, vddc_min, vddc_step);
2793         if (ret)
2794                 goto done_free;
2795
2796         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2797
2798         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2799         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2800         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2801         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2802         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2803         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2804         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2805         cac_tables->calculation_repeats = cpu_to_be32(2);
2806         cac_tables->dc_cac = cpu_to_be32(0);
2807         cac_tables->log2_PG_LKG_SCALE = 12;
2808         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2809         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2810         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2811
2812         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2813                                           (u8 *)cac_tables,
2814                                           sizeof(PP_SIslands_CacConfig),
2815                                           si_pi->sram_end);
2816
2817         if (ret)
2818                 goto done_free;
2819
2820         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2821
2822 done_free:
2823         if (ret) {
2824                 ni_pi->enable_cac = false;
2825                 ni_pi->enable_power_containment = false;
2826         }
2827
2828         kfree(cac_tables);
2829
2830         return ret;
2831 }
2832
2833 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2834                                            const struct si_cac_config_reg *cac_config_regs)
2835 {
2836         const struct si_cac_config_reg *config_regs = cac_config_regs;
2837         u32 data = 0, offset;
2838
2839         if (!config_regs)
2840                 return -EINVAL;
2841
2842         while (config_regs->offset != 0xFFFFFFFF) {
2843                 switch (config_regs->type) {
2844                 case SISLANDS_CACCONFIG_CGIND:
2845                         offset = SMC_CG_IND_START + config_regs->offset;
2846                         if (offset < SMC_CG_IND_END)
2847                                 data = RREG32_SMC(offset);
2848                         break;
2849                 default:
2850                         data = RREG32(config_regs->offset);
2851                         break;
2852                 }
2853
2854                 data &= ~config_regs->mask;
2855                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2856
2857                 switch (config_regs->type) {
2858                 case SISLANDS_CACCONFIG_CGIND:
2859                         offset = SMC_CG_IND_START + config_regs->offset;
2860                         if (offset < SMC_CG_IND_END)
2861                                 WREG32_SMC(offset, data);
2862                         break;
2863                 default:
2864                         WREG32(config_regs->offset, data);
2865                         break;
2866                 }
2867                 config_regs++;
2868         }
2869         return 0;
2870 }
2871
2872 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2873 {
2874         struct ni_power_info *ni_pi = ni_get_pi(adev);
2875         struct si_power_info *si_pi = si_get_pi(adev);
2876         int ret;
2877
2878         if ((ni_pi->enable_cac == false) ||
2879             (ni_pi->cac_configuration_required == false))
2880                 return 0;
2881
2882         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2883         if (ret)
2884                 return ret;
2885         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2886         if (ret)
2887                 return ret;
2888         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2889         if (ret)
2890                 return ret;
2891
2892         return 0;
2893 }
2894
2895 static int si_enable_smc_cac(struct amdgpu_device *adev,
2896                              struct amdgpu_ps *amdgpu_new_state,
2897                              bool enable)
2898 {
2899         struct ni_power_info *ni_pi = ni_get_pi(adev);
2900         struct si_power_info *si_pi = si_get_pi(adev);
2901         PPSMC_Result smc_result;
2902         int ret = 0;
2903
2904         if (ni_pi->enable_cac) {
2905                 if (enable) {
2906                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2907                                 if (ni_pi->support_cac_long_term_average) {
2908                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2909                                         if (smc_result != PPSMC_Result_OK)
2910                                                 ni_pi->support_cac_long_term_average = false;
2911                                 }
2912
2913                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2914                                 if (smc_result != PPSMC_Result_OK) {
2915                                         ret = -EINVAL;
2916                                         ni_pi->cac_enabled = false;
2917                                 } else {
2918                                         ni_pi->cac_enabled = true;
2919                                 }
2920
2921                                 if (si_pi->enable_dte) {
2922                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2923                                         if (smc_result != PPSMC_Result_OK)
2924                                                 ret = -EINVAL;
2925                                 }
2926                         }
2927                 } else if (ni_pi->cac_enabled) {
2928                         if (si_pi->enable_dte)
2929                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2930
2931                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2932
2933                         ni_pi->cac_enabled = false;
2934
2935                         if (ni_pi->support_cac_long_term_average)
2936                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2937                 }
2938         }
2939         return ret;
2940 }
2941
2942 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2943 {
2944         struct ni_power_info *ni_pi = ni_get_pi(adev);
2945         struct si_power_info *si_pi = si_get_pi(adev);
2946         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2947         SISLANDS_SMC_SCLK_VALUE sclk_params;
2948         u32 fb_div, p_div;
2949         u32 clk_s, clk_v;
2950         u32 sclk = 0;
2951         int ret = 0;
2952         u32 tmp;
2953         int i;
2954
2955         if (si_pi->spll_table_start == 0)
2956                 return -EINVAL;
2957
2958         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2959         if (spll_table == NULL)
2960                 return -ENOMEM;
2961
2962         for (i = 0; i < 256; i++) {
2963                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2964                 if (ret)
2965                         break;
2966                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2967                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2968                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2969                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2970
2971                 fb_div &= ~0x00001FFF;
2972                 fb_div >>= 1;
2973                 clk_v >>= 6;
2974
2975                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2976                         ret = -EINVAL;
2977                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2978                         ret = -EINVAL;
2979                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2980                         ret = -EINVAL;
2981                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2982                         ret = -EINVAL;
2983
2984                 if (ret)
2985                         break;
2986
2987                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2988                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2989                 spll_table->freq[i] = cpu_to_be32(tmp);
2990
2991                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2992                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2993                 spll_table->ss[i] = cpu_to_be32(tmp);
2994
2995                 sclk += 512;
2996         }
2997
2998
2999         if (!ret)
3000                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3001                                                   (u8 *)spll_table,
3002                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3003                                                   si_pi->sram_end);
3004
3005         if (ret)
3006                 ni_pi->enable_power_containment = false;
3007
3008         kfree(spll_table);
3009
3010         return ret;
3011 }
3012
3013 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3014                                                    u16 vce_voltage)
3015 {
3016         u16 highest_leakage = 0;
3017         struct si_power_info *si_pi = si_get_pi(adev);
3018         int i;
3019
3020         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3021                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3022                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3023         }
3024
3025         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3026                 return highest_leakage;
3027
3028         return vce_voltage;
3029 }
3030
3031 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3032                                     u32 evclk, u32 ecclk, u16 *voltage)
3033 {
3034         u32 i;
3035         int ret = -EINVAL;
3036         struct amdgpu_vce_clock_voltage_dependency_table *table =
3037                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3038
3039         if (((evclk == 0) && (ecclk == 0)) ||
3040             (table && (table->count == 0))) {
3041                 *voltage = 0;
3042                 return 0;
3043         }
3044
3045         for (i = 0; i < table->count; i++) {
3046                 if ((evclk <= table->entries[i].evclk) &&
3047                     (ecclk <= table->entries[i].ecclk)) {
3048                         *voltage = table->entries[i].v;
3049                         ret = 0;
3050                         break;
3051                 }
3052         }
3053
3054         /* if no match return the highest voltage */
3055         if (ret)
3056                 *voltage = table->entries[table->count - 1].v;
3057
3058         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3059
3060         return ret;
3061 }
3062
3063 static bool si_dpm_vblank_too_short(void *handle)
3064 {
3065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3066         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3067         /* we never hit the non-gddr5 limit so disable it */
3068         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3069
3070         if (vblank_time < switch_limit)
3071                 return true;
3072         else
3073                 return false;
3074
3075 }
3076
3077 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3078                                 u32 arb_freq_src, u32 arb_freq_dest)
3079 {
3080         u32 mc_arb_dram_timing;
3081         u32 mc_arb_dram_timing2;
3082         u32 burst_time;
3083         u32 mc_cg_config;
3084
3085         switch (arb_freq_src) {
3086         case MC_CG_ARB_FREQ_F0:
3087                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3088                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3089                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3090                 break;
3091         case MC_CG_ARB_FREQ_F1:
3092                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3093                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3094                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3095                 break;
3096         case MC_CG_ARB_FREQ_F2:
3097                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3098                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3099                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3100                 break;
3101         case MC_CG_ARB_FREQ_F3:
3102                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3103                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3104                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3105                 break;
3106         default:
3107                 return -EINVAL;
3108         }
3109
3110         switch (arb_freq_dest) {
3111         case MC_CG_ARB_FREQ_F0:
3112                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3113                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3114                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3115                 break;
3116         case MC_CG_ARB_FREQ_F1:
3117                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3118                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3119                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3120                 break;
3121         case MC_CG_ARB_FREQ_F2:
3122                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3123                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3124                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3125                 break;
3126         case MC_CG_ARB_FREQ_F3:
3127                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3128                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3129                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3130                 break;
3131         default:
3132                 return -EINVAL;
3133         }
3134
3135         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3136         WREG32(MC_CG_CONFIG, mc_cg_config);
3137         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3138
3139         return 0;
3140 }
3141
3142 static void ni_update_current_ps(struct amdgpu_device *adev,
3143                           struct amdgpu_ps *rps)
3144 {
3145         struct si_ps *new_ps = si_get_ps(rps);
3146         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3147         struct ni_power_info *ni_pi = ni_get_pi(adev);
3148
3149         eg_pi->current_rps = *rps;
3150         ni_pi->current_ps = *new_ps;
3151         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3152         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3153 }
3154
3155 static void ni_update_requested_ps(struct amdgpu_device *adev,
3156                             struct amdgpu_ps *rps)
3157 {
3158         struct si_ps *new_ps = si_get_ps(rps);
3159         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3160         struct ni_power_info *ni_pi = ni_get_pi(adev);
3161
3162         eg_pi->requested_rps = *rps;
3163         ni_pi->requested_ps = *new_ps;
3164         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3165         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3166 }
3167
3168 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3169                                            struct amdgpu_ps *new_ps,
3170                                            struct amdgpu_ps *old_ps)
3171 {
3172         struct si_ps *new_state = si_get_ps(new_ps);
3173         struct si_ps *current_state = si_get_ps(old_ps);
3174
3175         if ((new_ps->vclk == old_ps->vclk) &&
3176             (new_ps->dclk == old_ps->dclk))
3177                 return;
3178
3179         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3180             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3181                 return;
3182
3183         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3184 }
3185
3186 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3187                                           struct amdgpu_ps *new_ps,
3188                                           struct amdgpu_ps *old_ps)
3189 {
3190         struct si_ps *new_state = si_get_ps(new_ps);
3191         struct si_ps *current_state = si_get_ps(old_ps);
3192
3193         if ((new_ps->vclk == old_ps->vclk) &&
3194             (new_ps->dclk == old_ps->dclk))
3195                 return;
3196
3197         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3198             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3199                 return;
3200
3201         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3202 }
3203
3204 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3205 {
3206         unsigned int i;
3207
3208         for (i = 0; i < table->count; i++)
3209                 if (voltage <= table->entries[i].value)
3210                         return table->entries[i].value;
3211
3212         return table->entries[table->count - 1].value;
3213 }
3214
3215 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3216                                 u32 max_clock, u32 requested_clock)
3217 {
3218         unsigned int i;
3219
3220         if ((clocks == NULL) || (clocks->count == 0))
3221                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3222
3223         for (i = 0; i < clocks->count; i++) {
3224                 if (clocks->values[i] >= requested_clock)
3225                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3226         }
3227
3228         return (clocks->values[clocks->count - 1] < max_clock) ?
3229                 clocks->values[clocks->count - 1] : max_clock;
3230 }
3231
3232 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3233                               u32 max_mclk, u32 requested_mclk)
3234 {
3235         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3236                                     max_mclk, requested_mclk);
3237 }
3238
3239 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3240                               u32 max_sclk, u32 requested_sclk)
3241 {
3242         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3243                                     max_sclk, requested_sclk);
3244 }
3245
3246 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3247                                                             u32 *max_clock)
3248 {
3249         u32 i, clock = 0;
3250
3251         if ((table == NULL) || (table->count == 0)) {
3252                 *max_clock = clock;
3253                 return;
3254         }
3255
3256         for (i = 0; i < table->count; i++) {
3257                 if (clock < table->entries[i].clk)
3258                         clock = table->entries[i].clk;
3259         }
3260         *max_clock = clock;
3261 }
3262
3263 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3264                                                u32 clock, u16 max_voltage, u16 *voltage)
3265 {
3266         u32 i;
3267
3268         if ((table == NULL) || (table->count == 0))
3269                 return;
3270
3271         for (i= 0; i < table->count; i++) {
3272                 if (clock <= table->entries[i].clk) {
3273                         if (*voltage < table->entries[i].v)
3274                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3275                                            table->entries[i].v : max_voltage);
3276                         return;
3277                 }
3278         }
3279
3280         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3281 }
3282
3283 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3284                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3285                                           struct rv7xx_pl *pl)
3286 {
3287
3288         if ((pl->mclk == 0) || (pl->sclk == 0))
3289                 return;
3290
3291         if (pl->mclk == pl->sclk)
3292                 return;
3293
3294         if (pl->mclk > pl->sclk) {
3295                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3296                         pl->sclk = btc_get_valid_sclk(adev,
3297                                                       max_limits->sclk,
3298                                                       (pl->mclk +
3299                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3300                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3301         } else {
3302                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3303                         pl->mclk = btc_get_valid_mclk(adev,
3304                                                       max_limits->mclk,
3305                                                       pl->sclk -
3306                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3307         }
3308 }
3309
3310 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3311                                           u16 max_vddc, u16 max_vddci,
3312                                           u16 *vddc, u16 *vddci)
3313 {
3314         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3315         u16 new_voltage;
3316
3317         if ((0 == *vddc) || (0 == *vddci))
3318                 return;
3319
3320         if (*vddc > *vddci) {
3321                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3322                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3323                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3324                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3325                 }
3326         } else {
3327                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3328                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3329                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3330                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3331                 }
3332         }
3333 }
3334
3335 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3336                             u32 *p, u32 *u)
3337 {
3338         u32 b_c = 0;
3339         u32 i_c;
3340         u32 tmp;
3341
3342         i_c = (i * r_c) / 100;
3343         tmp = i_c >> p_b;
3344
3345         while (tmp) {
3346                 b_c++;
3347                 tmp >>= 1;
3348         }
3349
3350         *u = (b_c + 1) / 2;
3351         *p = i_c / (1 << (2 * (*u)));
3352 }
3353
3354 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3355 {
3356         u32 k, a, ah, al;
3357         u32 t1;
3358
3359         if ((fl == 0) || (fh == 0) || (fl > fh))
3360                 return -EINVAL;
3361
3362         k = (100 * fh) / fl;
3363         t1 = (t * (k - 100));
3364         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3365         a = (a + 5) / 10;
3366         ah = ((a * t) + 5000) / 10000;
3367         al = a - ah;
3368
3369         *th = t - ah;
3370         *tl = t + al;
3371
3372         return 0;
3373 }
3374
3375 static bool r600_is_uvd_state(u32 class, u32 class2)
3376 {
3377         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3378                 return true;
3379         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3380                 return true;
3381         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3382                 return true;
3383         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3384                 return true;
3385         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3386                 return true;
3387         return false;
3388 }
3389
3390 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3391 {
3392         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3393 }
3394
3395 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3396 {
3397         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3398         u16 vddc;
3399
3400         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3401                 pi->max_vddc = 0;
3402         else
3403                 pi->max_vddc = vddc;
3404 }
3405
3406 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3407 {
3408         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3409         struct amdgpu_atom_ss ss;
3410
3411         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3412                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3413         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3414                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3415
3416         if (pi->sclk_ss || pi->mclk_ss)
3417                 pi->dynamic_ss = true;
3418         else
3419                 pi->dynamic_ss = false;
3420 }
3421
3422
3423 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3424                                         struct amdgpu_ps *rps)
3425 {
3426         struct  si_ps *ps = si_get_ps(rps);
3427         struct amdgpu_clock_and_voltage_limits *max_limits;
3428         bool disable_mclk_switching = false;
3429         bool disable_sclk_switching = false;
3430         u32 mclk, sclk;
3431         u16 vddc, vddci, min_vce_voltage = 0;
3432         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3433         u32 max_sclk = 0, max_mclk = 0;
3434         int i;
3435
3436         if (adev->asic_type == CHIP_HAINAN) {
3437                 if ((adev->pdev->revision == 0x81) ||
3438                     (adev->pdev->revision == 0x83) ||
3439                     (adev->pdev->revision == 0xC3) ||
3440                     (adev->pdev->device == 0x6664) ||
3441                     (adev->pdev->device == 0x6665) ||
3442                     (adev->pdev->device == 0x6667)) {
3443                         max_sclk = 75000;
3444                 }
3445                 if ((adev->pdev->revision == 0xC3) ||
3446                     (adev->pdev->device == 0x6665)) {
3447                         max_sclk = 60000;
3448                         max_mclk = 80000;
3449                 }
3450         } else if (adev->asic_type == CHIP_OLAND) {
3451                 if ((adev->pdev->revision == 0xC7) ||
3452                     (adev->pdev->revision == 0x80) ||
3453                     (adev->pdev->revision == 0x81) ||
3454                     (adev->pdev->revision == 0x83) ||
3455                     (adev->pdev->revision == 0x87) ||
3456                     (adev->pdev->device == 0x6604) ||
3457                     (adev->pdev->device == 0x6605)) {
3458                         max_sclk = 75000;
3459                 }
3460         }
3461
3462         if (rps->vce_active) {
3463                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3464                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3465                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3466                                          &min_vce_voltage);
3467         } else {
3468                 rps->evclk = 0;
3469                 rps->ecclk = 0;
3470         }
3471
3472         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3473             si_dpm_vblank_too_short(adev))
3474                 disable_mclk_switching = true;
3475
3476         if (rps->vclk || rps->dclk) {
3477                 disable_mclk_switching = true;
3478                 disable_sclk_switching = true;
3479         }
3480
3481         if (adev->pm.dpm.ac_power)
3482                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3483         else
3484                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3485
3486         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3487                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3488                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3489         }
3490         if (adev->pm.dpm.ac_power == false) {
3491                 for (i = 0; i < ps->performance_level_count; i++) {
3492                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3493                                 ps->performance_levels[i].mclk = max_limits->mclk;
3494                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3495                                 ps->performance_levels[i].sclk = max_limits->sclk;
3496                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3497                                 ps->performance_levels[i].vddc = max_limits->vddc;
3498                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3499                                 ps->performance_levels[i].vddci = max_limits->vddci;
3500                 }
3501         }
3502
3503         /* limit clocks to max supported clocks based on voltage dependency tables */
3504         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3505                                                         &max_sclk_vddc);
3506         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3507                                                         &max_mclk_vddci);
3508         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3509                                                         &max_mclk_vddc);
3510
3511         for (i = 0; i < ps->performance_level_count; i++) {
3512                 if (max_sclk_vddc) {
3513                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3514                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3515                 }
3516                 if (max_mclk_vddci) {
3517                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3518                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3519                 }
3520                 if (max_mclk_vddc) {
3521                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3522                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3523                 }
3524                 if (max_mclk) {
3525                         if (ps->performance_levels[i].mclk > max_mclk)
3526                                 ps->performance_levels[i].mclk = max_mclk;
3527                 }
3528                 if (max_sclk) {
3529                         if (ps->performance_levels[i].sclk > max_sclk)
3530                                 ps->performance_levels[i].sclk = max_sclk;
3531                 }
3532         }
3533
3534         /* XXX validate the min clocks required for display */
3535
3536         if (disable_mclk_switching) {
3537                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3538                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3539         } else {
3540                 mclk = ps->performance_levels[0].mclk;
3541                 vddci = ps->performance_levels[0].vddci;
3542         }
3543
3544         if (disable_sclk_switching) {
3545                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3546                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3547         } else {
3548                 sclk = ps->performance_levels[0].sclk;
3549                 vddc = ps->performance_levels[0].vddc;
3550         }
3551
3552         if (rps->vce_active) {
3553                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3554                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3555                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3556                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3557         }
3558
3559         /* adjusted low state */
3560         ps->performance_levels[0].sclk = sclk;
3561         ps->performance_levels[0].mclk = mclk;
3562         ps->performance_levels[0].vddc = vddc;
3563         ps->performance_levels[0].vddci = vddci;
3564
3565         if (disable_sclk_switching) {
3566                 sclk = ps->performance_levels[0].sclk;
3567                 for (i = 1; i < ps->performance_level_count; i++) {
3568                         if (sclk < ps->performance_levels[i].sclk)
3569                                 sclk = ps->performance_levels[i].sclk;
3570                 }
3571                 for (i = 0; i < ps->performance_level_count; i++) {
3572                         ps->performance_levels[i].sclk = sclk;
3573                         ps->performance_levels[i].vddc = vddc;
3574                 }
3575         } else {
3576                 for (i = 1; i < ps->performance_level_count; i++) {
3577                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3578                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3579                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3580                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3581                 }
3582         }
3583
3584         if (disable_mclk_switching) {
3585                 mclk = ps->performance_levels[0].mclk;
3586                 for (i = 1; i < ps->performance_level_count; i++) {
3587                         if (mclk < ps->performance_levels[i].mclk)
3588                                 mclk = ps->performance_levels[i].mclk;
3589                 }
3590                 for (i = 0; i < ps->performance_level_count; i++) {
3591                         ps->performance_levels[i].mclk = mclk;
3592                         ps->performance_levels[i].vddci = vddci;
3593                 }
3594         } else {
3595                 for (i = 1; i < ps->performance_level_count; i++) {
3596                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3597                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3598                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3599                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3600                 }
3601         }
3602
3603         for (i = 0; i < ps->performance_level_count; i++)
3604                 btc_adjust_clock_combinations(adev, max_limits,
3605                                               &ps->performance_levels[i]);
3606
3607         for (i = 0; i < ps->performance_level_count; i++) {
3608                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3609                         ps->performance_levels[i].vddc = min_vce_voltage;
3610                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3611                                                    ps->performance_levels[i].sclk,
3612                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3613                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3614                                                    ps->performance_levels[i].mclk,
3615                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3616                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3617                                                    ps->performance_levels[i].mclk,
3618                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3619                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3620                                                    adev->clock.current_dispclk,
3621                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3622         }
3623
3624         for (i = 0; i < ps->performance_level_count; i++) {
3625                 btc_apply_voltage_delta_rules(adev,
3626                                               max_limits->vddc, max_limits->vddci,
3627                                               &ps->performance_levels[i].vddc,
3628                                               &ps->performance_levels[i].vddci);
3629         }
3630
3631         ps->dc_compatible = true;
3632         for (i = 0; i < ps->performance_level_count; i++) {
3633                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3634                         ps->dc_compatible = false;
3635         }
3636 }
3637
3638 #if 0
3639 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3640                                      u16 reg_offset, u32 *value)
3641 {
3642         struct si_power_info *si_pi = si_get_pi(adev);
3643
3644         return amdgpu_si_read_smc_sram_dword(adev,
3645                                              si_pi->soft_regs_start + reg_offset, value,
3646                                              si_pi->sram_end);
3647 }
3648 #endif
3649
3650 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3651                                       u16 reg_offset, u32 value)
3652 {
3653         struct si_power_info *si_pi = si_get_pi(adev);
3654
3655         return amdgpu_si_write_smc_sram_dword(adev,
3656                                               si_pi->soft_regs_start + reg_offset,
3657                                               value, si_pi->sram_end);
3658 }
3659
3660 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3661 {
3662         bool ret = false;
3663         u32 tmp, width, row, column, bank, density;
3664         bool is_memory_gddr5, is_special;
3665
3666         tmp = RREG32(MC_SEQ_MISC0);
3667         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3668         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3669                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3670
3671         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3672         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3673
3674         tmp = RREG32(MC_ARB_RAMCFG);
3675         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3676         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3677         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3678
3679         density = (1 << (row + column - 20 + bank)) * width;
3680
3681         if ((adev->pdev->device == 0x6819) &&
3682             is_memory_gddr5 && is_special && (density == 0x400))
3683                 ret = true;
3684
3685         return ret;
3686 }
3687
3688 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3689 {
3690         struct si_power_info *si_pi = si_get_pi(adev);
3691         u16 vddc, count = 0;
3692         int i, ret;
3693
3694         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3695                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3696
3697                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3698                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3699                         si_pi->leakage_voltage.entries[count].leakage_index =
3700                                 SISLANDS_LEAKAGE_INDEX0 + i;
3701                         count++;
3702                 }
3703         }
3704         si_pi->leakage_voltage.count = count;
3705 }
3706
3707 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3708                                                      u32 index, u16 *leakage_voltage)
3709 {
3710         struct si_power_info *si_pi = si_get_pi(adev);
3711         int i;
3712
3713         if (leakage_voltage == NULL)
3714                 return -EINVAL;
3715
3716         if ((index & 0xff00) != 0xff00)
3717                 return -EINVAL;
3718
3719         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3720                 return -EINVAL;
3721
3722         if (index < SISLANDS_LEAKAGE_INDEX0)
3723                 return -EINVAL;
3724
3725         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3726                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3727                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3728                         return 0;
3729                 }
3730         }
3731         return -EAGAIN;
3732 }
3733
3734 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3735 {
3736         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3737         bool want_thermal_protection;
3738         enum amdgpu_dpm_event_src dpm_event_src;
3739
3740         switch (sources) {
3741         case 0:
3742         default:
3743                 want_thermal_protection = false;
3744                 break;
3745         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3746                 want_thermal_protection = true;
3747                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3748                 break;
3749         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3750                 want_thermal_protection = true;
3751                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3752                 break;
3753         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3754               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3755                 want_thermal_protection = true;
3756                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3757                 break;
3758         }
3759
3760         if (want_thermal_protection) {
3761                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3762                 if (pi->thermal_protection)
3763                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3764         } else {
3765                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3766         }
3767 }
3768
3769 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3770                                            enum amdgpu_dpm_auto_throttle_src source,
3771                                            bool enable)
3772 {
3773         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3774
3775         if (enable) {
3776                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3777                         pi->active_auto_throttle_sources |= 1 << source;
3778                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3779                 }
3780         } else {
3781                 if (pi->active_auto_throttle_sources & (1 << source)) {
3782                         pi->active_auto_throttle_sources &= ~(1 << source);
3783                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3784                 }
3785         }
3786 }
3787
3788 static void si_start_dpm(struct amdgpu_device *adev)
3789 {
3790         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3791 }
3792
3793 static void si_stop_dpm(struct amdgpu_device *adev)
3794 {
3795         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3796 }
3797
3798 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3799 {
3800         if (enable)
3801                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3802         else
3803                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3804
3805 }
3806
3807 #if 0
3808 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3809                                                u32 thermal_level)
3810 {
3811         PPSMC_Result ret;
3812
3813         if (thermal_level == 0) {
3814                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3815                 if (ret == PPSMC_Result_OK)
3816                         return 0;
3817                 else
3818                         return -EINVAL;
3819         }
3820         return 0;
3821 }
3822
3823 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3824 {
3825         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3826 }
3827 #endif
3828
3829 #if 0
3830 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3831 {
3832         if (ac_power)
3833                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3834                         0 : -EINVAL;
3835
3836         return 0;
3837 }
3838 #endif
3839
3840 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3841                                                       PPSMC_Msg msg, u32 parameter)
3842 {
3843         WREG32(SMC_SCRATCH0, parameter);
3844         return amdgpu_si_send_msg_to_smc(adev, msg);
3845 }
3846
3847 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3848 {
3849         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3850                 return -EINVAL;
3851
3852         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3853                 0 : -EINVAL;
3854 }
3855
3856 static int si_dpm_force_performance_level(void *handle,
3857                                    enum amd_dpm_forced_level level)
3858 {
3859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3860         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3861         struct  si_ps *ps = si_get_ps(rps);
3862         u32 levels = ps->performance_level_count;
3863
3864         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3865                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3866                         return -EINVAL;
3867
3868                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3869                         return -EINVAL;
3870         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3871                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3872                         return -EINVAL;
3873
3874                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3875                         return -EINVAL;
3876         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3877                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3878                         return -EINVAL;
3879
3880                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3881                         return -EINVAL;
3882         }
3883
3884         adev->pm.dpm.forced_level = level;
3885
3886         return 0;
3887 }
3888
3889 #if 0
3890 static int si_set_boot_state(struct amdgpu_device *adev)
3891 {
3892         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3893                 0 : -EINVAL;
3894 }
3895 #endif
3896
3897 static int si_set_sw_state(struct amdgpu_device *adev)
3898 {
3899         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3900                 0 : -EINVAL;
3901 }
3902
3903 static int si_halt_smc(struct amdgpu_device *adev)
3904 {
3905         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3906                 return -EINVAL;
3907
3908         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3909                 0 : -EINVAL;
3910 }
3911
3912 static int si_resume_smc(struct amdgpu_device *adev)
3913 {
3914         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3915                 return -EINVAL;
3916
3917         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3918                 0 : -EINVAL;
3919 }
3920
3921 static void si_dpm_start_smc(struct amdgpu_device *adev)
3922 {
3923         amdgpu_si_program_jump_on_start(adev);
3924         amdgpu_si_start_smc(adev);
3925         amdgpu_si_smc_clock(adev, true);
3926 }
3927
3928 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3929 {
3930         amdgpu_si_reset_smc(adev);
3931         amdgpu_si_smc_clock(adev, false);
3932 }
3933
3934 static int si_process_firmware_header(struct amdgpu_device *adev)
3935 {
3936         struct si_power_info *si_pi = si_get_pi(adev);
3937         u32 tmp;
3938         int ret;
3939
3940         ret = amdgpu_si_read_smc_sram_dword(adev,
3941                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3942                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3943                                             &tmp, si_pi->sram_end);
3944         if (ret)
3945                 return ret;
3946
3947         si_pi->state_table_start = tmp;
3948
3949         ret = amdgpu_si_read_smc_sram_dword(adev,
3950                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3951                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3952                                             &tmp, si_pi->sram_end);
3953         if (ret)
3954                 return ret;
3955
3956         si_pi->soft_regs_start = tmp;
3957
3958         ret = amdgpu_si_read_smc_sram_dword(adev,
3959                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3960                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3961                                             &tmp, si_pi->sram_end);
3962         if (ret)
3963                 return ret;
3964
3965         si_pi->mc_reg_table_start = tmp;
3966
3967         ret = amdgpu_si_read_smc_sram_dword(adev,
3968                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3969                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3970                                             &tmp, si_pi->sram_end);
3971         if (ret)
3972                 return ret;
3973
3974         si_pi->fan_table_start = tmp;
3975
3976         ret = amdgpu_si_read_smc_sram_dword(adev,
3977                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3978                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3979                                             &tmp, si_pi->sram_end);
3980         if (ret)
3981                 return ret;
3982
3983         si_pi->arb_table_start = tmp;
3984
3985         ret = amdgpu_si_read_smc_sram_dword(adev,
3986                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3987                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3988                                             &tmp, si_pi->sram_end);
3989         if (ret)
3990                 return ret;
3991
3992         si_pi->cac_table_start = tmp;
3993
3994         ret = amdgpu_si_read_smc_sram_dword(adev,
3995                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3996                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3997                                             &tmp, si_pi->sram_end);
3998         if (ret)
3999                 return ret;
4000
4001         si_pi->dte_table_start = tmp;
4002
4003         ret = amdgpu_si_read_smc_sram_dword(adev,
4004                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4005                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4006                                             &tmp, si_pi->sram_end);
4007         if (ret)
4008                 return ret;
4009
4010         si_pi->spll_table_start = tmp;
4011
4012         ret = amdgpu_si_read_smc_sram_dword(adev,
4013                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4014                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4015                                             &tmp, si_pi->sram_end);
4016         if (ret)
4017                 return ret;
4018
4019         si_pi->papm_cfg_table_start = tmp;
4020
4021         return ret;
4022 }
4023
4024 static void si_read_clock_registers(struct amdgpu_device *adev)
4025 {
4026         struct si_power_info *si_pi = si_get_pi(adev);
4027
4028         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4029         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4030         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4031         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4032         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4033         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4034         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4035         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4036         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4037         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4038         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4039         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4040         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4041         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4042         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4043 }
4044
4045 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4046                                           bool enable)
4047 {
4048         if (enable)
4049                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4050         else
4051                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4052 }
4053
4054 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4055 {
4056         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4057 }
4058
4059 #if 0
4060 static int si_enter_ulp_state(struct amdgpu_device *adev)
4061 {
4062         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4063
4064         udelay(25000);
4065
4066         return 0;
4067 }
4068
4069 static int si_exit_ulp_state(struct amdgpu_device *adev)
4070 {
4071         int i;
4072
4073         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4074
4075         udelay(7000);
4076
4077         for (i = 0; i < adev->usec_timeout; i++) {
4078                 if (RREG32(SMC_RESP_0) == 1)
4079                         break;
4080                 udelay(1000);
4081         }
4082
4083         return 0;
4084 }
4085 #endif
4086
4087 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4088                                      bool has_display)
4089 {
4090         PPSMC_Msg msg = has_display ?
4091                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4092
4093         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4094                 0 : -EINVAL;
4095 }
4096
4097 static void si_program_response_times(struct amdgpu_device *adev)
4098 {
4099         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4100         u32 vddc_dly, acpi_dly, vbi_dly;
4101         u32 reference_clock;
4102
4103         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4104
4105         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4106         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4107
4108         if (voltage_response_time == 0)
4109                 voltage_response_time = 1000;
4110
4111         acpi_delay_time = 15000;
4112         vbi_time_out = 100000;
4113
4114         reference_clock = amdgpu_asic_get_xclk(adev);
4115
4116         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4117         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4118         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4119
4120         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4121         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4122         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4123         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4124 }
4125
4126 static void si_program_ds_registers(struct amdgpu_device *adev)
4127 {
4128         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4129         u32 tmp;
4130
4131         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4132         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4133                 tmp = 0x10;
4134         else
4135                 tmp = 0x1;
4136
4137         if (eg_pi->sclk_deep_sleep) {
4138                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4139                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4140                          ~AUTOSCALE_ON_SS_CLEAR);
4141         }
4142 }
4143
4144 static void si_program_display_gap(struct amdgpu_device *adev)
4145 {
4146         u32 tmp, pipe;
4147         int i;
4148
4149         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4150         if (adev->pm.dpm.new_active_crtc_count > 0)
4151                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4152         else
4153                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4154
4155         if (adev->pm.dpm.new_active_crtc_count > 1)
4156                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4157         else
4158                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4159
4160         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4161
4162         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4163         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4164
4165         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4166             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4167                 /* find the first active crtc */
4168                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4169                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4170                                 break;
4171                 }
4172                 if (i == adev->mode_info.num_crtc)
4173                         pipe = 0;
4174                 else
4175                         pipe = i;
4176
4177                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4178                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4179                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4180         }
4181
4182         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4183          * This can be a problem on PowerXpress systems or if you want to use the card
4184          * for offscreen rendering or compute if there are no crtcs enabled.
4185          */
4186         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4187 }
4188
4189 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4190 {
4191         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4192
4193         if (enable) {
4194                 if (pi->sclk_ss)
4195                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4196         } else {
4197                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4198                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4199         }
4200 }
4201
4202 static void si_setup_bsp(struct amdgpu_device *adev)
4203 {
4204         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4205         u32 xclk = amdgpu_asic_get_xclk(adev);
4206
4207         r600_calculate_u_and_p(pi->asi,
4208                                xclk,
4209                                16,
4210                                &pi->bsp,
4211                                &pi->bsu);
4212
4213         r600_calculate_u_and_p(pi->pasi,
4214                                xclk,
4215                                16,
4216                                &pi->pbsp,
4217                                &pi->pbsu);
4218
4219
4220         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4221         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4222
4223         WREG32(CG_BSP, pi->dsp);
4224 }
4225
4226 static void si_program_git(struct amdgpu_device *adev)
4227 {
4228         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4229 }
4230
4231 static void si_program_tp(struct amdgpu_device *adev)
4232 {
4233         int i;
4234         enum r600_td td = R600_TD_DFLT;
4235
4236         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4237                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4238
4239         if (td == R600_TD_AUTO)
4240                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4241         else
4242                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4243
4244         if (td == R600_TD_UP)
4245                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4246
4247         if (td == R600_TD_DOWN)
4248                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4249 }
4250
4251 static void si_program_tpp(struct amdgpu_device *adev)
4252 {
4253         WREG32(CG_TPC, R600_TPC_DFLT);
4254 }
4255
4256 static void si_program_sstp(struct amdgpu_device *adev)
4257 {
4258         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4259 }
4260
4261 static void si_enable_display_gap(struct amdgpu_device *adev)
4262 {
4263         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4264
4265         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4266         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4267                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4268
4269         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4270         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4271                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4272         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4273 }
4274
4275 static void si_program_vc(struct amdgpu_device *adev)
4276 {
4277         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4278
4279         WREG32(CG_FTV, pi->vrc);
4280 }
4281
4282 static void si_clear_vc(struct amdgpu_device *adev)
4283 {
4284         WREG32(CG_FTV, 0);
4285 }
4286
4287 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4288 {
4289         u8 mc_para_index;
4290
4291         if (memory_clock < 10000)
4292                 mc_para_index = 0;
4293         else if (memory_clock >= 80000)
4294                 mc_para_index = 0x0f;
4295         else
4296                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4297         return mc_para_index;
4298 }
4299
4300 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4301 {
4302         u8 mc_para_index;
4303
4304         if (strobe_mode) {
4305                 if (memory_clock < 12500)
4306                         mc_para_index = 0x00;
4307                 else if (memory_clock > 47500)
4308                         mc_para_index = 0x0f;
4309                 else
4310                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4311         } else {
4312                 if (memory_clock < 65000)
4313                         mc_para_index = 0x00;
4314                 else if (memory_clock > 135000)
4315                         mc_para_index = 0x0f;
4316                 else
4317                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4318         }
4319         return mc_para_index;
4320 }
4321
4322 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4323 {
4324         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4325         bool strobe_mode = false;
4326         u8 result = 0;
4327
4328         if (mclk <= pi->mclk_strobe_mode_threshold)
4329                 strobe_mode = true;
4330
4331         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4332                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4333         else
4334                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4335
4336         if (strobe_mode)
4337                 result |= SISLANDS_SMC_STROBE_ENABLE;
4338
4339         return result;
4340 }
4341
4342 static int si_upload_firmware(struct amdgpu_device *adev)
4343 {
4344         struct si_power_info *si_pi = si_get_pi(adev);
4345
4346         amdgpu_si_reset_smc(adev);
4347         amdgpu_si_smc_clock(adev, false);
4348
4349         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4350 }
4351
4352 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4353                                               const struct atom_voltage_table *table,
4354                                               const struct amdgpu_phase_shedding_limits_table *limits)
4355 {
4356         u32 data, num_bits, num_levels;
4357
4358         if ((table == NULL) || (limits == NULL))
4359                 return false;
4360
4361         data = table->mask_low;
4362
4363         num_bits = hweight32(data);
4364
4365         if (num_bits == 0)
4366                 return false;
4367
4368         num_levels = (1 << num_bits);
4369
4370         if (table->count != num_levels)
4371                 return false;
4372
4373         if (limits->count != (num_levels - 1))
4374                 return false;
4375
4376         return true;
4377 }
4378
4379 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4380                                               u32 max_voltage_steps,
4381                                               struct atom_voltage_table *voltage_table)
4382 {
4383         unsigned int i, diff;
4384
4385         if (voltage_table->count <= max_voltage_steps)
4386                 return;
4387
4388         diff = voltage_table->count - max_voltage_steps;
4389
4390         for (i= 0; i < max_voltage_steps; i++)
4391                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4392
4393         voltage_table->count = max_voltage_steps;
4394 }
4395
4396 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4397                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4398                                      struct atom_voltage_table *voltage_table)
4399 {
4400         u32 i;
4401
4402         if (voltage_dependency_table == NULL)
4403                 return -EINVAL;
4404
4405         voltage_table->mask_low = 0;
4406         voltage_table->phase_delay = 0;
4407
4408         voltage_table->count = voltage_dependency_table->count;
4409         for (i = 0; i < voltage_table->count; i++) {
4410                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4411                 voltage_table->entries[i].smio_low = 0;
4412         }
4413
4414         return 0;
4415 }
4416
4417 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4418 {
4419         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4420         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4421         struct si_power_info *si_pi = si_get_pi(adev);
4422         int ret;
4423
4424         if (pi->voltage_control) {
4425                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4426                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4427                 if (ret)
4428                         return ret;
4429
4430                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4431                         si_trim_voltage_table_to_fit_state_table(adev,
4432                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4433                                                                  &eg_pi->vddc_voltage_table);
4434         } else if (si_pi->voltage_control_svi2) {
4435                 ret = si_get_svi2_voltage_table(adev,
4436                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4437                                                 &eg_pi->vddc_voltage_table);
4438                 if (ret)
4439                         return ret;
4440         } else {
4441                 return -EINVAL;
4442         }
4443
4444         if (eg_pi->vddci_control) {
4445                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4446                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4447                 if (ret)
4448                         return ret;
4449
4450                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4451                         si_trim_voltage_table_to_fit_state_table(adev,
4452                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4453                                                                  &eg_pi->vddci_voltage_table);
4454         }
4455         if (si_pi->vddci_control_svi2) {
4456                 ret = si_get_svi2_voltage_table(adev,
4457                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4458                                                 &eg_pi->vddci_voltage_table);
4459                 if (ret)
4460                         return ret;
4461         }
4462
4463         if (pi->mvdd_control) {
4464                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4465                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4466
4467                 if (ret) {
4468                         pi->mvdd_control = false;
4469                         return ret;
4470                 }
4471
4472                 if (si_pi->mvdd_voltage_table.count == 0) {
4473                         pi->mvdd_control = false;
4474                         return -EINVAL;
4475                 }
4476
4477                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4478                         si_trim_voltage_table_to_fit_state_table(adev,
4479                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4480                                                                  &si_pi->mvdd_voltage_table);
4481         }
4482
4483         if (si_pi->vddc_phase_shed_control) {
4484                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4485                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4486                 if (ret)
4487                         si_pi->vddc_phase_shed_control = false;
4488
4489                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4490                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4491                         si_pi->vddc_phase_shed_control = false;
4492         }
4493
4494         return 0;
4495 }
4496
4497 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4498                                           const struct atom_voltage_table *voltage_table,
4499                                           SISLANDS_SMC_STATETABLE *table)
4500 {
4501         unsigned int i;
4502
4503         for (i = 0; i < voltage_table->count; i++)
4504                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4505 }
4506
4507 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4508                                           SISLANDS_SMC_STATETABLE *table)
4509 {
4510         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4511         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4512         struct si_power_info *si_pi = si_get_pi(adev);
4513         u8 i;
4514
4515         if (si_pi->voltage_control_svi2) {
4516                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4517                         si_pi->svc_gpio_id);
4518                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4519                         si_pi->svd_gpio_id);
4520                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4521                                            2);
4522         } else {
4523                 if (eg_pi->vddc_voltage_table.count) {
4524                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4525                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4526                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4527
4528                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4529                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4530                                         table->maxVDDCIndexInPPTable = i;
4531                                         break;
4532                                 }
4533                         }
4534                 }
4535
4536                 if (eg_pi->vddci_voltage_table.count) {
4537                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4538
4539                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4540                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4541                 }
4542
4543
4544                 if (si_pi->mvdd_voltage_table.count) {
4545                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4546
4547                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4548                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4549                 }
4550
4551                 if (si_pi->vddc_phase_shed_control) {
4552                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4553                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4554                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4555
4556                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4557                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4558
4559                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4560                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4561                         } else {
4562                                 si_pi->vddc_phase_shed_control = false;
4563                         }
4564                 }
4565         }
4566
4567         return 0;
4568 }
4569
4570 static int si_populate_voltage_value(struct amdgpu_device *adev,
4571                                      const struct atom_voltage_table *table,
4572                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4573 {
4574         unsigned int i;
4575
4576         for (i = 0; i < table->count; i++) {
4577                 if (value <= table->entries[i].value) {
4578                         voltage->index = (u8)i;
4579                         voltage->value = cpu_to_be16(table->entries[i].value);
4580                         break;
4581                 }
4582         }
4583
4584         if (i >= table->count)
4585                 return -EINVAL;
4586
4587         return 0;
4588 }
4589
4590 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4591                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4592 {
4593         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4594         struct si_power_info *si_pi = si_get_pi(adev);
4595
4596         if (pi->mvdd_control) {
4597                 if (mclk <= pi->mvdd_split_frequency)
4598                         voltage->index = 0;
4599                 else
4600                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4601
4602                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4603         }
4604         return 0;
4605 }
4606
4607 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4608                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4609                                     u16 *std_voltage)
4610 {
4611         u16 v_index;
4612         bool voltage_found = false;
4613         *std_voltage = be16_to_cpu(voltage->value);
4614
4615         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4616                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4617                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4618                                 return -EINVAL;
4619
4620                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4621                                 if (be16_to_cpu(voltage->value) ==
4622                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4623                                         voltage_found = true;
4624                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4625                                                 *std_voltage =
4626                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4627                                         else
4628                                                 *std_voltage =
4629                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4630                                         break;
4631                                 }
4632                         }
4633
4634                         if (!voltage_found) {
4635                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4636                                         if (be16_to_cpu(voltage->value) <=
4637                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4638                                                 voltage_found = true;
4639                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4640                                                         *std_voltage =
4641                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4642                                                 else
4643                                                         *std_voltage =
4644                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4645                                                 break;
4646                                         }
4647                                 }
4648                         }
4649                 } else {
4650                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4651                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4652                 }
4653         }
4654
4655         return 0;
4656 }
4657
4658 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4659                                          u16 value, u8 index,
4660                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4661 {
4662         voltage->index = index;
4663         voltage->value = cpu_to_be16(value);
4664
4665         return 0;
4666 }
4667
4668 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4669                                             const struct amdgpu_phase_shedding_limits_table *limits,
4670                                             u16 voltage, u32 sclk, u32 mclk,
4671                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4672 {
4673         unsigned int i;
4674
4675         for (i = 0; i < limits->count; i++) {
4676                 if ((voltage <= limits->entries[i].voltage) &&
4677                     (sclk <= limits->entries[i].sclk) &&
4678                     (mclk <= limits->entries[i].mclk))
4679                         break;
4680         }
4681
4682         smc_voltage->phase_settings = (u8)i;
4683
4684         return 0;
4685 }
4686
4687 static int si_init_arb_table_index(struct amdgpu_device *adev)
4688 {
4689         struct si_power_info *si_pi = si_get_pi(adev);
4690         u32 tmp;
4691         int ret;
4692
4693         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4694                                             &tmp, si_pi->sram_end);
4695         if (ret)
4696                 return ret;
4697
4698         tmp &= 0x00FFFFFF;
4699         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4700
4701         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4702                                               tmp, si_pi->sram_end);
4703 }
4704
4705 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4706 {
4707         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4708 }
4709
4710 static int si_reset_to_default(struct amdgpu_device *adev)
4711 {
4712         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4713                 0 : -EINVAL;
4714 }
4715
4716 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4717 {
4718         struct si_power_info *si_pi = si_get_pi(adev);
4719         u32 tmp;
4720         int ret;
4721
4722         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4723                                             &tmp, si_pi->sram_end);
4724         if (ret)
4725                 return ret;
4726
4727         tmp = (tmp >> 24) & 0xff;
4728
4729         if (tmp == MC_CG_ARB_FREQ_F0)
4730                 return 0;
4731
4732         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4733 }
4734
4735 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4736                                             u32 engine_clock)
4737 {
4738         u32 dram_rows;
4739         u32 dram_refresh_rate;
4740         u32 mc_arb_rfsh_rate;
4741         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4742
4743         if (tmp >= 4)
4744                 dram_rows = 16384;
4745         else
4746                 dram_rows = 1 << (tmp + 10);
4747
4748         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4749         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4750
4751         return mc_arb_rfsh_rate;
4752 }
4753
4754 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4755                                                 struct rv7xx_pl *pl,
4756                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4757 {
4758         u32 dram_timing;
4759         u32 dram_timing2;
4760         u32 burst_time;
4761
4762         arb_regs->mc_arb_rfsh_rate =
4763                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4764
4765         amdgpu_atombios_set_engine_dram_timings(adev,
4766                                             pl->sclk,
4767                                             pl->mclk);
4768
4769         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4770         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4771         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4772
4773         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4774         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4775         arb_regs->mc_arb_burst_time = (u8)burst_time;
4776
4777         return 0;
4778 }
4779
4780 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4781                                                   struct amdgpu_ps *amdgpu_state,
4782                                                   unsigned int first_arb_set)
4783 {
4784         struct si_power_info *si_pi = si_get_pi(adev);
4785         struct  si_ps *state = si_get_ps(amdgpu_state);
4786         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4787         int i, ret = 0;
4788
4789         for (i = 0; i < state->performance_level_count; i++) {
4790                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4791                 if (ret)
4792                         break;
4793                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4794                                                   si_pi->arb_table_start +
4795                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4796                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4797                                                   (u8 *)&arb_regs,
4798                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4799                                                   si_pi->sram_end);
4800                 if (ret)
4801                         break;
4802         }
4803
4804         return ret;
4805 }
4806
4807 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4808                                                struct amdgpu_ps *amdgpu_new_state)
4809 {
4810         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4811                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4812 }
4813
4814 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4815                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4816 {
4817         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4818         struct si_power_info *si_pi = si_get_pi(adev);
4819
4820         if (pi->mvdd_control)
4821                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4822                                                  si_pi->mvdd_bootup_value, voltage);
4823
4824         return 0;
4825 }
4826
4827 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4828                                          struct amdgpu_ps *amdgpu_initial_state,
4829                                          SISLANDS_SMC_STATETABLE *table)
4830 {
4831         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4832         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4833         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4834         struct si_power_info *si_pi = si_get_pi(adev);
4835         u32 reg;
4836         int ret;
4837
4838         table->initialState.levels[0].mclk.vDLL_CNTL =
4839                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4840         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4841                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4842         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4843                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4844         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4845                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4846         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4847                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4848         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4849                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4850         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4851                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4852         table->initialState.levels[0].mclk.vMPLL_SS =
4853                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4854         table->initialState.levels[0].mclk.vMPLL_SS2 =
4855                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4856
4857         table->initialState.levels[0].mclk.mclk_value =
4858                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4859
4860         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4861                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4862         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4863                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4864         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4865                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4866         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4867                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4868         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4869                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4870         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4871                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4872
4873         table->initialState.levels[0].sclk.sclk_value =
4874                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4875
4876         table->initialState.levels[0].arbRefreshState =
4877                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4878
4879         table->initialState.levels[0].ACIndex = 0;
4880
4881         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4882                                         initial_state->performance_levels[0].vddc,
4883                                         &table->initialState.levels[0].vddc);
4884
4885         if (!ret) {
4886                 u16 std_vddc;
4887
4888                 ret = si_get_std_voltage_value(adev,
4889                                                &table->initialState.levels[0].vddc,
4890                                                &std_vddc);
4891                 if (!ret)
4892                         si_populate_std_voltage_value(adev, std_vddc,
4893                                                       table->initialState.levels[0].vddc.index,
4894                                                       &table->initialState.levels[0].std_vddc);
4895         }
4896
4897         if (eg_pi->vddci_control)
4898                 si_populate_voltage_value(adev,
4899                                           &eg_pi->vddci_voltage_table,
4900                                           initial_state->performance_levels[0].vddci,
4901                                           &table->initialState.levels[0].vddci);
4902
4903         if (si_pi->vddc_phase_shed_control)
4904                 si_populate_phase_shedding_value(adev,
4905                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4906                                                  initial_state->performance_levels[0].vddc,
4907                                                  initial_state->performance_levels[0].sclk,
4908                                                  initial_state->performance_levels[0].mclk,
4909                                                  &table->initialState.levels[0].vddc);
4910
4911         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4912
4913         reg = CG_R(0xffff) | CG_L(0);
4914         table->initialState.levels[0].aT = cpu_to_be32(reg);
4915         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4916         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4917
4918         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4919                 table->initialState.levels[0].strobeMode =
4920                         si_get_strobe_mode_settings(adev,
4921                                                     initial_state->performance_levels[0].mclk);
4922
4923                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4924                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4925                 else
4926                         table->initialState.levels[0].mcFlags =  0;
4927         }
4928
4929         table->initialState.levelCount = 1;
4930
4931         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4932
4933         table->initialState.levels[0].dpm2.MaxPS = 0;
4934         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4935         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4936         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4937         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4938
4939         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4940         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4941
4942         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4943         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4944
4945         return 0;
4946 }
4947
4948 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4949                                       SISLANDS_SMC_STATETABLE *table)
4950 {
4951         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4952         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4953         struct si_power_info *si_pi = si_get_pi(adev);
4954         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4955         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4956         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4957         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4958         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4959         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4960         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4961         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4962         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4963         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4964         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4965         u32 reg;
4966         int ret;
4967
4968         table->ACPIState = table->initialState;
4969
4970         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4971
4972         if (pi->acpi_vddc) {
4973                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4974                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4975                 if (!ret) {
4976                         u16 std_vddc;
4977
4978                         ret = si_get_std_voltage_value(adev,
4979                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4980                         if (!ret)
4981                                 si_populate_std_voltage_value(adev, std_vddc,
4982                                                               table->ACPIState.levels[0].vddc.index,
4983                                                               &table->ACPIState.levels[0].std_vddc);
4984                 }
4985                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4986
4987                 if (si_pi->vddc_phase_shed_control) {
4988                         si_populate_phase_shedding_value(adev,
4989                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4990                                                          pi->acpi_vddc,
4991                                                          0,
4992                                                          0,
4993                                                          &table->ACPIState.levels[0].vddc);
4994                 }
4995         } else {
4996                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4997                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4998                 if (!ret) {
4999                         u16 std_vddc;
5000
5001                         ret = si_get_std_voltage_value(adev,
5002                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5003
5004                         if (!ret)
5005                                 si_populate_std_voltage_value(adev, std_vddc,
5006                                                               table->ACPIState.levels[0].vddc.index,
5007                                                               &table->ACPIState.levels[0].std_vddc);
5008                 }
5009                 table->ACPIState.levels[0].gen2PCIE =
5010                         (u8)amdgpu_get_pcie_gen_support(adev,
5011                                                         si_pi->sys_pcie_mask,
5012                                                         si_pi->boot_pcie_gen,
5013                                                         AMDGPU_PCIE_GEN1);
5014
5015                 if (si_pi->vddc_phase_shed_control)
5016                         si_populate_phase_shedding_value(adev,
5017                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5018                                                          pi->min_vddc_in_table,
5019                                                          0,
5020                                                          0,
5021                                                          &table->ACPIState.levels[0].vddc);
5022         }
5023
5024         if (pi->acpi_vddc) {
5025                 if (eg_pi->acpi_vddci)
5026                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5027                                                   eg_pi->acpi_vddci,
5028                                                   &table->ACPIState.levels[0].vddci);
5029         }
5030
5031         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5032         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5033
5034         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5035
5036         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5037         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5038
5039         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5040                 cpu_to_be32(dll_cntl);
5041         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5042                 cpu_to_be32(mclk_pwrmgt_cntl);
5043         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5044                 cpu_to_be32(mpll_ad_func_cntl);
5045         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5046                 cpu_to_be32(mpll_dq_func_cntl);
5047         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5048                 cpu_to_be32(mpll_func_cntl);
5049         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5050                 cpu_to_be32(mpll_func_cntl_1);
5051         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5052                 cpu_to_be32(mpll_func_cntl_2);
5053         table->ACPIState.levels[0].mclk.vMPLL_SS =
5054                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5055         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5056                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5057
5058         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5059                 cpu_to_be32(spll_func_cntl);
5060         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5061                 cpu_to_be32(spll_func_cntl_2);
5062         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5063                 cpu_to_be32(spll_func_cntl_3);
5064         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5065                 cpu_to_be32(spll_func_cntl_4);
5066
5067         table->ACPIState.levels[0].mclk.mclk_value = 0;
5068         table->ACPIState.levels[0].sclk.sclk_value = 0;
5069
5070         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5071
5072         if (eg_pi->dynamic_ac_timing)
5073                 table->ACPIState.levels[0].ACIndex = 0;
5074
5075         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5076         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5077         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5078         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5079         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5080
5081         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5082         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5083
5084         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5085         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5086
5087         return 0;
5088 }
5089
5090 static int si_populate_ulv_state(struct amdgpu_device *adev,
5091                                  SISLANDS_SMC_SWSTATE *state)
5092 {
5093         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5094         struct si_power_info *si_pi = si_get_pi(adev);
5095         struct si_ulv_param *ulv = &si_pi->ulv;
5096         u32 sclk_in_sr = 1350; /* ??? */
5097         int ret;
5098
5099         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5100                                             &state->levels[0]);
5101         if (!ret) {
5102                 if (eg_pi->sclk_deep_sleep) {
5103                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5104                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5105                         else
5106                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5107                 }
5108                 if (ulv->one_pcie_lane_in_ulv)
5109                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5110                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5111                 state->levels[0].ACIndex = 1;
5112                 state->levels[0].std_vddc = state->levels[0].vddc;
5113                 state->levelCount = 1;
5114
5115                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5116         }
5117
5118         return ret;
5119 }
5120
5121 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5122 {
5123         struct si_power_info *si_pi = si_get_pi(adev);
5124         struct si_ulv_param *ulv = &si_pi->ulv;
5125         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5126         int ret;
5127
5128         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5129                                                    &arb_regs);
5130         if (ret)
5131                 return ret;
5132
5133         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5134                                    ulv->volt_change_delay);
5135
5136         ret = amdgpu_si_copy_bytes_to_smc(adev,
5137                                           si_pi->arb_table_start +
5138                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5139                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5140                                           (u8 *)&arb_regs,
5141                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5142                                           si_pi->sram_end);
5143
5144         return ret;
5145 }
5146
5147 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5148 {
5149         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5150
5151         pi->mvdd_split_frequency = 30000;
5152 }
5153
5154 static int si_init_smc_table(struct amdgpu_device *adev)
5155 {
5156         struct si_power_info *si_pi = si_get_pi(adev);
5157         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5158         const struct si_ulv_param *ulv = &si_pi->ulv;
5159         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5160         int ret;
5161         u32 lane_width;
5162         u32 vr_hot_gpio;
5163
5164         si_populate_smc_voltage_tables(adev, table);
5165
5166         switch (adev->pm.int_thermal_type) {
5167         case THERMAL_TYPE_SI:
5168         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5169                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5170                 break;
5171         case THERMAL_TYPE_NONE:
5172                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5173                 break;
5174         default:
5175                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5176                 break;
5177         }
5178
5179         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5180                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5181
5182         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5183                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5184                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5185         }
5186
5187         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5188                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5189
5190         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5191                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5192
5193         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5194                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5195
5196         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5197                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5198                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5199                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5200                                            vr_hot_gpio);
5201         }
5202
5203         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5204         if (ret)
5205                 return ret;
5206
5207         ret = si_populate_smc_acpi_state(adev, table);
5208         if (ret)
5209                 return ret;
5210
5211         table->driverState = table->initialState;
5212
5213         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5214                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5215         if (ret)
5216                 return ret;
5217
5218         if (ulv->supported && ulv->pl.vddc) {
5219                 ret = si_populate_ulv_state(adev, &table->ULVState);
5220                 if (ret)
5221                         return ret;
5222
5223                 ret = si_program_ulv_memory_timing_parameters(adev);
5224                 if (ret)
5225                         return ret;
5226
5227                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5228                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5229
5230                 lane_width = amdgpu_get_pcie_lanes(adev);
5231                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5232         } else {
5233                 table->ULVState = table->initialState;
5234         }
5235
5236         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5237                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5238                                            si_pi->sram_end);
5239 }
5240
5241 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5242                                     u32 engine_clock,
5243                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5244 {
5245         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5246         struct si_power_info *si_pi = si_get_pi(adev);
5247         struct atom_clock_dividers dividers;
5248         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5249         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5250         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5251         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5252         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5253         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5254         u64 tmp;
5255         u32 reference_clock = adev->clock.spll.reference_freq;
5256         u32 reference_divider;
5257         u32 fbdiv;
5258         int ret;
5259
5260         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5261                                              engine_clock, false, &dividers);
5262         if (ret)
5263                 return ret;
5264
5265         reference_divider = 1 + dividers.ref_div;
5266
5267         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5268         do_div(tmp, reference_clock);
5269         fbdiv = (u32) tmp;
5270
5271         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5272         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5273         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5274
5275         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5276         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5277
5278         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5279         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5280         spll_func_cntl_3 |= SPLL_DITHEN;
5281
5282         if (pi->sclk_ss) {
5283                 struct amdgpu_atom_ss ss;
5284                 u32 vco_freq = engine_clock * dividers.post_div;
5285
5286                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5287                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5288                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5289                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5290
5291                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5292                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5293                         cg_spll_spread_spectrum |= SSEN;
5294
5295                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5296                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5297                 }
5298         }
5299
5300         sclk->sclk_value = engine_clock;
5301         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5302         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5303         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5304         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5305         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5306         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5307
5308         return 0;
5309 }
5310
5311 static int si_populate_sclk_value(struct amdgpu_device *adev,
5312                                   u32 engine_clock,
5313                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5314 {
5315         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5316         int ret;
5317
5318         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5319         if (!ret) {
5320                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5321                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5322                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5323                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5324                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5325                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5326                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5327         }
5328
5329         return ret;
5330 }
5331
5332 static int si_populate_mclk_value(struct amdgpu_device *adev,
5333                                   u32 engine_clock,
5334                                   u32 memory_clock,
5335                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5336                                   bool strobe_mode,
5337                                   bool dll_state_on)
5338 {
5339         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5340         struct si_power_info *si_pi = si_get_pi(adev);
5341         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5342         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5343         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5344         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5345         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5346         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5347         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5348         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5349         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5350         struct atom_mpll_param mpll_param;
5351         int ret;
5352
5353         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5354         if (ret)
5355                 return ret;
5356
5357         mpll_func_cntl &= ~BWCTRL_MASK;
5358         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5359
5360         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5361         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5362                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5363
5364         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5365         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5366
5367         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5368                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5369                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5370                         YCLK_POST_DIV(mpll_param.post_div);
5371         }
5372
5373         if (pi->mclk_ss) {
5374                 struct amdgpu_atom_ss ss;
5375                 u32 freq_nom;
5376                 u32 tmp;
5377                 u32 reference_clock = adev->clock.mpll.reference_freq;
5378
5379                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5380                         freq_nom = memory_clock * 4;
5381                 else
5382                         freq_nom = memory_clock * 2;
5383
5384                 tmp = freq_nom / reference_clock;
5385                 tmp = tmp * tmp;
5386                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5387                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5388                         u32 clks = reference_clock * 5 / ss.rate;
5389                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5390
5391                         mpll_ss1 &= ~CLKV_MASK;
5392                         mpll_ss1 |= CLKV(clkv);
5393
5394                         mpll_ss2 &= ~CLKS_MASK;
5395                         mpll_ss2 |= CLKS(clks);
5396                 }
5397         }
5398
5399         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5400         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5401
5402         if (dll_state_on)
5403                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5404         else
5405                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5406
5407         mclk->mclk_value = cpu_to_be32(memory_clock);
5408         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5409         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5410         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5411         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5412         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5413         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5414         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5415         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5416         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5417
5418         return 0;
5419 }
5420
5421 static void si_populate_smc_sp(struct amdgpu_device *adev,
5422                                struct amdgpu_ps *amdgpu_state,
5423                                SISLANDS_SMC_SWSTATE *smc_state)
5424 {
5425         struct  si_ps *ps = si_get_ps(amdgpu_state);
5426         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5427         int i;
5428
5429         for (i = 0; i < ps->performance_level_count - 1; i++)
5430                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5431
5432         smc_state->levels[ps->performance_level_count - 1].bSP =
5433                 cpu_to_be32(pi->psp);
5434 }
5435
5436 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5437                                          struct rv7xx_pl *pl,
5438                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5439 {
5440         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5441         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5442         struct si_power_info *si_pi = si_get_pi(adev);
5443         int ret;
5444         bool dll_state_on;
5445         u16 std_vddc;
5446         bool gmc_pg = false;
5447
5448         if (eg_pi->pcie_performance_request &&
5449             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5450                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5451         else
5452                 level->gen2PCIE = (u8)pl->pcie_gen;
5453
5454         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5455         if (ret)
5456                 return ret;
5457
5458         level->mcFlags =  0;
5459
5460         if (pi->mclk_stutter_mode_threshold &&
5461             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5462             !eg_pi->uvd_enabled &&
5463             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5464             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5465                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5466
5467                 if (gmc_pg)
5468                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5469         }
5470
5471         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5472                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5473                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5474
5475                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5476                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5477
5478                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5479
5480                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5481                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5482                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5483                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5484                         else
5485                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5486                 } else {
5487                         dll_state_on = false;
5488                 }
5489         } else {
5490                 level->strobeMode = si_get_strobe_mode_settings(adev,
5491                                                                 pl->mclk);
5492
5493                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5494         }
5495
5496         ret = si_populate_mclk_value(adev,
5497                                      pl->sclk,
5498                                      pl->mclk,
5499                                      &level->mclk,
5500                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5501         if (ret)
5502                 return ret;
5503
5504         ret = si_populate_voltage_value(adev,
5505                                         &eg_pi->vddc_voltage_table,
5506                                         pl->vddc, &level->vddc);
5507         if (ret)
5508                 return ret;
5509
5510
5511         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5512         if (ret)
5513                 return ret;
5514
5515         ret = si_populate_std_voltage_value(adev, std_vddc,
5516                                             level->vddc.index, &level->std_vddc);
5517         if (ret)
5518                 return ret;
5519
5520         if (eg_pi->vddci_control) {
5521                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5522                                                 pl->vddci, &level->vddci);
5523                 if (ret)
5524                         return ret;
5525         }
5526
5527         if (si_pi->vddc_phase_shed_control) {
5528                 ret = si_populate_phase_shedding_value(adev,
5529                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5530                                                        pl->vddc,
5531                                                        pl->sclk,
5532                                                        pl->mclk,
5533                                                        &level->vddc);
5534                 if (ret)
5535                         return ret;
5536         }
5537
5538         level->MaxPoweredUpCU = si_pi->max_cu;
5539
5540         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5541
5542         return ret;
5543 }
5544
5545 static int si_populate_smc_t(struct amdgpu_device *adev,
5546                              struct amdgpu_ps *amdgpu_state,
5547                              SISLANDS_SMC_SWSTATE *smc_state)
5548 {
5549         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5550         struct  si_ps *state = si_get_ps(amdgpu_state);
5551         u32 a_t;
5552         u32 t_l, t_h;
5553         u32 high_bsp;
5554         int i, ret;
5555
5556         if (state->performance_level_count >= 9)
5557                 return -EINVAL;
5558
5559         if (state->performance_level_count < 2) {
5560                 a_t = CG_R(0xffff) | CG_L(0);
5561                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5562                 return 0;
5563         }
5564
5565         smc_state->levels[0].aT = cpu_to_be32(0);
5566
5567         for (i = 0; i <= state->performance_level_count - 2; i++) {
5568                 ret = r600_calculate_at(
5569                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5570                         100 * R600_AH_DFLT,
5571                         state->performance_levels[i + 1].sclk,
5572                         state->performance_levels[i].sclk,
5573                         &t_l,
5574                         &t_h);
5575
5576                 if (ret) {
5577                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5578                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5579                 }
5580
5581                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5582                 a_t |= CG_R(t_l * pi->bsp / 20000);
5583                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5584
5585                 high_bsp = (i == state->performance_level_count - 2) ?
5586                         pi->pbsp : pi->bsp;
5587                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5588                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5589         }
5590
5591         return 0;
5592 }
5593
5594 static int si_disable_ulv(struct amdgpu_device *adev)
5595 {
5596         struct si_power_info *si_pi = si_get_pi(adev);
5597         struct si_ulv_param *ulv = &si_pi->ulv;
5598
5599         if (ulv->supported)
5600                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5601                         0 : -EINVAL;
5602
5603         return 0;
5604 }
5605
5606 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5607                                        struct amdgpu_ps *amdgpu_state)
5608 {
5609         const struct si_power_info *si_pi = si_get_pi(adev);
5610         const struct si_ulv_param *ulv = &si_pi->ulv;
5611         const struct  si_ps *state = si_get_ps(amdgpu_state);
5612         int i;
5613
5614         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5615                 return false;
5616
5617         /* XXX validate against display requirements! */
5618
5619         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5620                 if (adev->clock.current_dispclk <=
5621                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5622                         if (ulv->pl.vddc <
5623                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5624                                 return false;
5625                 }
5626         }
5627
5628         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5629                 return false;
5630
5631         return true;
5632 }
5633
5634 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5635                                                        struct amdgpu_ps *amdgpu_new_state)
5636 {
5637         const struct si_power_info *si_pi = si_get_pi(adev);
5638         const struct si_ulv_param *ulv = &si_pi->ulv;
5639
5640         if (ulv->supported) {
5641                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5642                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5643                                 0 : -EINVAL;
5644         }
5645         return 0;
5646 }
5647
5648 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5649                                          struct amdgpu_ps *amdgpu_state,
5650                                          SISLANDS_SMC_SWSTATE *smc_state)
5651 {
5652         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5653         struct ni_power_info *ni_pi = ni_get_pi(adev);
5654         struct si_power_info *si_pi = si_get_pi(adev);
5655         struct  si_ps *state = si_get_ps(amdgpu_state);
5656         int i, ret;
5657         u32 threshold;
5658         u32 sclk_in_sr = 1350; /* ??? */
5659
5660         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5661                 return -EINVAL;
5662
5663         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5664
5665         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5666                 eg_pi->uvd_enabled = true;
5667                 if (eg_pi->smu_uvd_hs)
5668                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5669         } else {
5670                 eg_pi->uvd_enabled = false;
5671         }
5672
5673         if (state->dc_compatible)
5674                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5675
5676         smc_state->levelCount = 0;
5677         for (i = 0; i < state->performance_level_count; i++) {
5678                 if (eg_pi->sclk_deep_sleep) {
5679                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5680                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5681                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5682                                 else
5683                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5684                         }
5685                 }
5686
5687                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5688                                                     &smc_state->levels[i]);
5689                 smc_state->levels[i].arbRefreshState =
5690                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5691
5692                 if (ret)
5693                         return ret;
5694
5695                 if (ni_pi->enable_power_containment)
5696                         smc_state->levels[i].displayWatermark =
5697                                 (state->performance_levels[i].sclk < threshold) ?
5698                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5699                 else
5700                         smc_state->levels[i].displayWatermark = (i < 2) ?
5701                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5702
5703                 if (eg_pi->dynamic_ac_timing)
5704                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5705                 else
5706                         smc_state->levels[i].ACIndex = 0;
5707
5708                 smc_state->levelCount++;
5709         }
5710
5711         si_write_smc_soft_register(adev,
5712                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5713                                    threshold / 512);
5714
5715         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5716
5717         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5718         if (ret)
5719                 ni_pi->enable_power_containment = false;
5720
5721         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5722         if (ret)
5723                 ni_pi->enable_sq_ramping = false;
5724
5725         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5726 }
5727
5728 static int si_upload_sw_state(struct amdgpu_device *adev,
5729                               struct amdgpu_ps *amdgpu_new_state)
5730 {
5731         struct si_power_info *si_pi = si_get_pi(adev);
5732         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5733         int ret;
5734         u32 address = si_pi->state_table_start +
5735                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5736         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5737                 ((new_state->performance_level_count - 1) *
5738                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5739         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5740
5741         memset(smc_state, 0, state_size);
5742
5743         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5744         if (ret)
5745                 return ret;
5746
5747         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5748                                            state_size, si_pi->sram_end);
5749 }
5750
5751 static int si_upload_ulv_state(struct amdgpu_device *adev)
5752 {
5753         struct si_power_info *si_pi = si_get_pi(adev);
5754         struct si_ulv_param *ulv = &si_pi->ulv;
5755         int ret = 0;
5756
5757         if (ulv->supported && ulv->pl.vddc) {
5758                 u32 address = si_pi->state_table_start +
5759                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5760                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5761                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5762
5763                 memset(smc_state, 0, state_size);
5764
5765                 ret = si_populate_ulv_state(adev, smc_state);
5766                 if (!ret)
5767                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5768                                                           state_size, si_pi->sram_end);
5769         }
5770
5771         return ret;
5772 }
5773
5774 static int si_upload_smc_data(struct amdgpu_device *adev)
5775 {
5776         struct amdgpu_crtc *amdgpu_crtc = NULL;
5777         int i;
5778
5779         if (adev->pm.dpm.new_active_crtc_count == 0)
5780                 return 0;
5781
5782         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5783                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5784                         amdgpu_crtc = adev->mode_info.crtcs[i];
5785                         break;
5786                 }
5787         }
5788
5789         if (amdgpu_crtc == NULL)
5790                 return 0;
5791
5792         if (amdgpu_crtc->line_time <= 0)
5793                 return 0;
5794
5795         if (si_write_smc_soft_register(adev,
5796                                        SI_SMC_SOFT_REGISTER_crtc_index,
5797                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5798                 return 0;
5799
5800         if (si_write_smc_soft_register(adev,
5801                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5802                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5803                 return 0;
5804
5805         if (si_write_smc_soft_register(adev,
5806                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5807                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5808                 return 0;
5809
5810         return 0;
5811 }
5812
5813 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5814                                        struct si_mc_reg_table *table)
5815 {
5816         u8 i, j, k;
5817         u32 temp_reg;
5818
5819         for (i = 0, j = table->last; i < table->last; i++) {
5820                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5821                         return -EINVAL;
5822                 switch (table->mc_reg_address[i].s1) {
5823                 case MC_SEQ_MISC1:
5824                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5825                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5826                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5827                         for (k = 0; k < table->num_entries; k++)
5828                                 table->mc_reg_table_entry[k].mc_data[j] =
5829                                         ((temp_reg & 0xffff0000)) |
5830                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5831                         j++;
5832
5833                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5834                                 return -EINVAL;
5835                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5836                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5837                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5838                         for (k = 0; k < table->num_entries; k++) {
5839                                 table->mc_reg_table_entry[k].mc_data[j] =
5840                                         (temp_reg & 0xffff0000) |
5841                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5842                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5843                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5844                         }
5845                         j++;
5846
5847                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5848                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5849                                         return -EINVAL;
5850                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5851                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5852                                 for (k = 0; k < table->num_entries; k++)
5853                                         table->mc_reg_table_entry[k].mc_data[j] =
5854                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5855                                 j++;
5856                         }
5857                         break;
5858                 case MC_SEQ_RESERVE_M:
5859                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5860                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5861                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5862                         for(k = 0; k < table->num_entries; k++)
5863                                 table->mc_reg_table_entry[k].mc_data[j] =
5864                                         (temp_reg & 0xffff0000) |
5865                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5866                         j++;
5867                         break;
5868                 default:
5869                         break;
5870                 }
5871         }
5872
5873         table->last = j;
5874
5875         return 0;
5876 }
5877
5878 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5879 {
5880         bool result = true;
5881         switch (in_reg) {
5882         case  MC_SEQ_RAS_TIMING:
5883                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5884                 break;
5885         case MC_SEQ_CAS_TIMING:
5886                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5887                 break;
5888         case MC_SEQ_MISC_TIMING:
5889                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5890                 break;
5891         case MC_SEQ_MISC_TIMING2:
5892                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5893                 break;
5894         case MC_SEQ_RD_CTL_D0:
5895                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5896                 break;
5897         case MC_SEQ_RD_CTL_D1:
5898                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5899                 break;
5900         case MC_SEQ_WR_CTL_D0:
5901                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5902                 break;
5903         case MC_SEQ_WR_CTL_D1:
5904                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5905                 break;
5906         case MC_PMG_CMD_EMRS:
5907                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5908                 break;
5909         case MC_PMG_CMD_MRS:
5910                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5911                 break;
5912         case MC_PMG_CMD_MRS1:
5913                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5914                 break;
5915         case MC_SEQ_PMG_TIMING:
5916                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5917                 break;
5918         case MC_PMG_CMD_MRS2:
5919                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5920                 break;
5921         case MC_SEQ_WR_CTL_2:
5922                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5923                 break;
5924         default:
5925                 result = false;
5926                 break;
5927         }
5928
5929         return result;
5930 }
5931
5932 static void si_set_valid_flag(struct si_mc_reg_table *table)
5933 {
5934         u8 i, j;
5935
5936         for (i = 0; i < table->last; i++) {
5937                 for (j = 1; j < table->num_entries; j++) {
5938                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5939                                 table->valid_flag |= 1 << i;
5940                                 break;
5941                         }
5942                 }
5943         }
5944 }
5945
5946 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5947 {
5948         u32 i;
5949         u16 address;
5950
5951         for (i = 0; i < table->last; i++)
5952                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5953                         address : table->mc_reg_address[i].s1;
5954
5955 }
5956
5957 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5958                                       struct si_mc_reg_table *si_table)
5959 {
5960         u8 i, j;
5961
5962         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5963                 return -EINVAL;
5964         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5965                 return -EINVAL;
5966
5967         for (i = 0; i < table->last; i++)
5968                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5969         si_table->last = table->last;
5970
5971         for (i = 0; i < table->num_entries; i++) {
5972                 si_table->mc_reg_table_entry[i].mclk_max =
5973                         table->mc_reg_table_entry[i].mclk_max;
5974                 for (j = 0; j < table->last; j++) {
5975                         si_table->mc_reg_table_entry[i].mc_data[j] =
5976                                 table->mc_reg_table_entry[i].mc_data[j];
5977                 }
5978         }
5979         si_table->num_entries = table->num_entries;
5980
5981         return 0;
5982 }
5983
5984 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5985 {
5986         struct si_power_info *si_pi = si_get_pi(adev);
5987         struct atom_mc_reg_table *table;
5988         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5989         u8 module_index = rv770_get_memory_module_index(adev);
5990         int ret;
5991
5992         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5993         if (!table)
5994                 return -ENOMEM;
5995
5996         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5997         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5998         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5999         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6000         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6001         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6002         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6003         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6004         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6005         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6006         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6007         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6008         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6009         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6010
6011         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6012         if (ret)
6013                 goto init_mc_done;
6014
6015         ret = si_copy_vbios_mc_reg_table(table, si_table);
6016         if (ret)
6017                 goto init_mc_done;
6018
6019         si_set_s0_mc_reg_index(si_table);
6020
6021         ret = si_set_mc_special_registers(adev, si_table);
6022         if (ret)
6023                 goto init_mc_done;
6024
6025         si_set_valid_flag(si_table);
6026
6027 init_mc_done:
6028         kfree(table);
6029
6030         return ret;
6031
6032 }
6033
6034 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6035                                          SMC_SIslands_MCRegisters *mc_reg_table)
6036 {
6037         struct si_power_info *si_pi = si_get_pi(adev);
6038         u32 i, j;
6039
6040         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6041                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6042                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6043                                 break;
6044                         mc_reg_table->address[i].s0 =
6045                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6046                         mc_reg_table->address[i].s1 =
6047                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6048                         i++;
6049                 }
6050         }
6051         mc_reg_table->last = (u8)i;
6052 }
6053
6054 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6055                                     SMC_SIslands_MCRegisterSet *data,
6056                                     u32 num_entries, u32 valid_flag)
6057 {
6058         u32 i, j;
6059
6060         for(i = 0, j = 0; j < num_entries; j++) {
6061                 if (valid_flag & (1 << j)) {
6062                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6063                         i++;
6064                 }
6065         }
6066 }
6067
6068 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6069                                                  struct rv7xx_pl *pl,
6070                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6071 {
6072         struct si_power_info *si_pi = si_get_pi(adev);
6073         u32 i = 0;
6074
6075         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6076                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6077                         break;
6078         }
6079
6080         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6081                 --i;
6082
6083         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6084                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6085                                 si_pi->mc_reg_table.valid_flag);
6086 }
6087
6088 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6089                                            struct amdgpu_ps *amdgpu_state,
6090                                            SMC_SIslands_MCRegisters *mc_reg_table)
6091 {
6092         struct si_ps *state = si_get_ps(amdgpu_state);
6093         int i;
6094
6095         for (i = 0; i < state->performance_level_count; i++) {
6096                 si_convert_mc_reg_table_entry_to_smc(adev,
6097                                                      &state->performance_levels[i],
6098                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6099         }
6100 }
6101
6102 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6103                                     struct amdgpu_ps *amdgpu_boot_state)
6104 {
6105         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6106         struct si_power_info *si_pi = si_get_pi(adev);
6107         struct si_ulv_param *ulv = &si_pi->ulv;
6108         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6109
6110         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6111
6112         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6113
6114         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6115
6116         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6117                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6118
6119         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6120                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6121                                 si_pi->mc_reg_table.last,
6122                                 si_pi->mc_reg_table.valid_flag);
6123
6124         if (ulv->supported && ulv->pl.vddc != 0)
6125                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6126                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6127         else
6128                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6129                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6130                                         si_pi->mc_reg_table.last,
6131                                         si_pi->mc_reg_table.valid_flag);
6132
6133         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6134
6135         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6136                                            (u8 *)smc_mc_reg_table,
6137                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6138 }
6139
6140 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6141                                   struct amdgpu_ps *amdgpu_new_state)
6142 {
6143         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6144         struct si_power_info *si_pi = si_get_pi(adev);
6145         u32 address = si_pi->mc_reg_table_start +
6146                 offsetof(SMC_SIslands_MCRegisters,
6147                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6148         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6149
6150         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6151
6152         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6153
6154         return amdgpu_si_copy_bytes_to_smc(adev, address,
6155                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6156                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6157                                            si_pi->sram_end);
6158 }
6159
6160 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6161 {
6162         if (enable)
6163                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6164         else
6165                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6166 }
6167
6168 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6169                                                       struct amdgpu_ps *amdgpu_state)
6170 {
6171         struct si_ps *state = si_get_ps(amdgpu_state);
6172         int i;
6173         u16 pcie_speed, max_speed = 0;
6174
6175         for (i = 0; i < state->performance_level_count; i++) {
6176                 pcie_speed = state->performance_levels[i].pcie_gen;
6177                 if (max_speed < pcie_speed)
6178                         max_speed = pcie_speed;
6179         }
6180         return max_speed;
6181 }
6182
6183 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6184 {
6185         u32 speed_cntl;
6186
6187         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6188         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6189
6190         return (u16)speed_cntl;
6191 }
6192
6193 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6194                                                              struct amdgpu_ps *amdgpu_new_state,
6195                                                              struct amdgpu_ps *amdgpu_current_state)
6196 {
6197         struct si_power_info *si_pi = si_get_pi(adev);
6198         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6199         enum amdgpu_pcie_gen current_link_speed;
6200
6201         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6202                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6203         else
6204                 current_link_speed = si_pi->force_pcie_gen;
6205
6206         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6207         si_pi->pspp_notify_required = false;
6208         if (target_link_speed > current_link_speed) {
6209                 switch (target_link_speed) {
6210 #if defined(CONFIG_ACPI)
6211                 case AMDGPU_PCIE_GEN3:
6212                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6213                                 break;
6214                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6215                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6216                                 break;
6217                 case AMDGPU_PCIE_GEN2:
6218                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6219                                 break;
6220 #endif
6221                 default:
6222                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6223                         break;
6224                 }
6225         } else {
6226                 if (target_link_speed < current_link_speed)
6227                         si_pi->pspp_notify_required = true;
6228         }
6229 }
6230
6231 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6232                                                            struct amdgpu_ps *amdgpu_new_state,
6233                                                            struct amdgpu_ps *amdgpu_current_state)
6234 {
6235         struct si_power_info *si_pi = si_get_pi(adev);
6236         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6237         u8 request;
6238
6239         if (si_pi->pspp_notify_required) {
6240                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6241                         request = PCIE_PERF_REQ_PECI_GEN3;
6242                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6243                         request = PCIE_PERF_REQ_PECI_GEN2;
6244                 else
6245                         request = PCIE_PERF_REQ_PECI_GEN1;
6246
6247                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6248                     (si_get_current_pcie_speed(adev) > 0))
6249                         return;
6250
6251 #if defined(CONFIG_ACPI)
6252                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6253 #endif
6254         }
6255 }
6256
6257 #if 0
6258 static int si_ds_request(struct amdgpu_device *adev,
6259                          bool ds_status_on, u32 count_write)
6260 {
6261         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6262
6263         if (eg_pi->sclk_deep_sleep) {
6264                 if (ds_status_on)
6265                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6266                                 PPSMC_Result_OK) ?
6267                                 0 : -EINVAL;
6268                 else
6269                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6270                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6271         }
6272         return 0;
6273 }
6274 #endif
6275
6276 static void si_set_max_cu_value(struct amdgpu_device *adev)
6277 {
6278         struct si_power_info *si_pi = si_get_pi(adev);
6279
6280         if (adev->asic_type == CHIP_VERDE) {
6281                 switch (adev->pdev->device) {
6282                 case 0x6820:
6283                 case 0x6825:
6284                 case 0x6821:
6285                 case 0x6823:
6286                 case 0x6827:
6287                         si_pi->max_cu = 10;
6288                         break;
6289                 case 0x682D:
6290                 case 0x6824:
6291                 case 0x682F:
6292                 case 0x6826:
6293                         si_pi->max_cu = 8;
6294                         break;
6295                 case 0x6828:
6296                 case 0x6830:
6297                 case 0x6831:
6298                 case 0x6838:
6299                 case 0x6839:
6300                 case 0x683D:
6301                         si_pi->max_cu = 10;
6302                         break;
6303                 case 0x683B:
6304                 case 0x683F:
6305                 case 0x6829:
6306                         si_pi->max_cu = 8;
6307                         break;
6308                 default:
6309                         si_pi->max_cu = 0;
6310                         break;
6311                 }
6312         } else {
6313                 si_pi->max_cu = 0;
6314         }
6315 }
6316
6317 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6318                                                              struct amdgpu_clock_voltage_dependency_table *table)
6319 {
6320         u32 i;
6321         int j;
6322         u16 leakage_voltage;
6323
6324         if (table) {
6325                 for (i = 0; i < table->count; i++) {
6326                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6327                                                                           table->entries[i].v,
6328                                                                           &leakage_voltage)) {
6329                         case 0:
6330                                 table->entries[i].v = leakage_voltage;
6331                                 break;
6332                         case -EAGAIN:
6333                                 return -EINVAL;
6334                         case -EINVAL:
6335                         default:
6336                                 break;
6337                         }
6338                 }
6339
6340                 for (j = (table->count - 2); j >= 0; j--) {
6341                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6342                                 table->entries[j].v : table->entries[j + 1].v;
6343                 }
6344         }
6345         return 0;
6346 }
6347
6348 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6349 {
6350         int ret = 0;
6351
6352         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6353                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6354         if (ret)
6355                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6356         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6357                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6358         if (ret)
6359                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6360         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6361                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6362         if (ret)
6363                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6364         return ret;
6365 }
6366
6367 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6368                                           struct amdgpu_ps *amdgpu_new_state,
6369                                           struct amdgpu_ps *amdgpu_current_state)
6370 {
6371         u32 lane_width;
6372         u32 new_lane_width =
6373                 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6374         u32 current_lane_width =
6375                 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6376
6377         if (new_lane_width != current_lane_width) {
6378                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6379                 lane_width = amdgpu_get_pcie_lanes(adev);
6380                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6381         }
6382 }
6383
6384 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6385 {
6386         si_read_clock_registers(adev);
6387         si_enable_acpi_power_management(adev);
6388 }
6389
6390 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6391                                    bool enable)
6392 {
6393         u32 thermal_int = RREG32(CG_THERMAL_INT);
6394
6395         if (enable) {
6396                 PPSMC_Result result;
6397
6398                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6399                 WREG32(CG_THERMAL_INT, thermal_int);
6400                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6401                 if (result != PPSMC_Result_OK) {
6402                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6403                         return -EINVAL;
6404                 }
6405         } else {
6406                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6407                 WREG32(CG_THERMAL_INT, thermal_int);
6408         }
6409
6410         return 0;
6411 }
6412
6413 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6414                                             int min_temp, int max_temp)
6415 {
6416         int low_temp = 0 * 1000;
6417         int high_temp = 255 * 1000;
6418
6419         if (low_temp < min_temp)
6420                 low_temp = min_temp;
6421         if (high_temp > max_temp)
6422                 high_temp = max_temp;
6423         if (high_temp < low_temp) {
6424                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6425                 return -EINVAL;
6426         }
6427
6428         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6429         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6430         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6431
6432         adev->pm.dpm.thermal.min_temp = low_temp;
6433         adev->pm.dpm.thermal.max_temp = high_temp;
6434
6435         return 0;
6436 }
6437
6438 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6439 {
6440         struct si_power_info *si_pi = si_get_pi(adev);
6441         u32 tmp;
6442
6443         if (si_pi->fan_ctrl_is_in_default_mode) {
6444                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6445                 si_pi->fan_ctrl_default_mode = tmp;
6446                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6447                 si_pi->t_min = tmp;
6448                 si_pi->fan_ctrl_is_in_default_mode = false;
6449         }
6450
6451         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6452         tmp |= TMIN(0);
6453         WREG32(CG_FDO_CTRL2, tmp);
6454
6455         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6456         tmp |= FDO_PWM_MODE(mode);
6457         WREG32(CG_FDO_CTRL2, tmp);
6458 }
6459
6460 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6461 {
6462         struct si_power_info *si_pi = si_get_pi(adev);
6463         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6464         u32 duty100;
6465         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6466         u16 fdo_min, slope1, slope2;
6467         u32 reference_clock, tmp;
6468         int ret;
6469         u64 tmp64;
6470
6471         if (!si_pi->fan_table_start) {
6472                 adev->pm.dpm.fan.ucode_fan_control = false;
6473                 return 0;
6474         }
6475
6476         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6477
6478         if (duty100 == 0) {
6479                 adev->pm.dpm.fan.ucode_fan_control = false;
6480                 return 0;
6481         }
6482
6483         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6484         do_div(tmp64, 10000);
6485         fdo_min = (u16)tmp64;
6486
6487         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6488         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6489
6490         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6491         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6492
6493         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6494         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6495
6496         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6497         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6498         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6499         fan_table.slope1 = cpu_to_be16(slope1);
6500         fan_table.slope2 = cpu_to_be16(slope2);
6501         fan_table.fdo_min = cpu_to_be16(fdo_min);
6502         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6503         fan_table.hys_up = cpu_to_be16(1);
6504         fan_table.hys_slope = cpu_to_be16(1);
6505         fan_table.temp_resp_lim = cpu_to_be16(5);
6506         reference_clock = amdgpu_asic_get_xclk(adev);
6507
6508         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6509                                                 reference_clock) / 1600);
6510         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6511
6512         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6513         fan_table.temp_src = (uint8_t)tmp;
6514
6515         ret = amdgpu_si_copy_bytes_to_smc(adev,
6516                                           si_pi->fan_table_start,
6517                                           (u8 *)(&fan_table),
6518                                           sizeof(fan_table),
6519                                           si_pi->sram_end);
6520
6521         if (ret) {
6522                 DRM_ERROR("Failed to load fan table to the SMC.");
6523                 adev->pm.dpm.fan.ucode_fan_control = false;
6524         }
6525
6526         return ret;
6527 }
6528
6529 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6530 {
6531         struct si_power_info *si_pi = si_get_pi(adev);
6532         PPSMC_Result ret;
6533
6534         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6535         if (ret == PPSMC_Result_OK) {
6536                 si_pi->fan_is_controlled_by_smc = true;
6537                 return 0;
6538         } else {
6539                 return -EINVAL;
6540         }
6541 }
6542
6543 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6544 {
6545         struct si_power_info *si_pi = si_get_pi(adev);
6546         PPSMC_Result ret;
6547
6548         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6549
6550         if (ret == PPSMC_Result_OK) {
6551                 si_pi->fan_is_controlled_by_smc = false;
6552                 return 0;
6553         } else {
6554                 return -EINVAL;
6555         }
6556 }
6557
6558 static int si_dpm_get_fan_speed_percent(void *handle,
6559                                       u32 *speed)
6560 {
6561         u32 duty, duty100;
6562         u64 tmp64;
6563         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6564
6565         if (adev->pm.no_fan)
6566                 return -ENOENT;
6567
6568         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6569         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6570
6571         if (duty100 == 0)
6572                 return -EINVAL;
6573
6574         tmp64 = (u64)duty * 100;
6575         do_div(tmp64, duty100);
6576         *speed = (u32)tmp64;
6577
6578         if (*speed > 100)
6579                 *speed = 100;
6580
6581         return 0;
6582 }
6583
6584 static int si_dpm_set_fan_speed_percent(void *handle,
6585                                       u32 speed)
6586 {
6587         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6588         struct si_power_info *si_pi = si_get_pi(adev);
6589         u32 tmp;
6590         u32 duty, duty100;
6591         u64 tmp64;
6592
6593         if (adev->pm.no_fan)
6594                 return -ENOENT;
6595
6596         if (si_pi->fan_is_controlled_by_smc)
6597                 return -EINVAL;
6598
6599         if (speed > 100)
6600                 return -EINVAL;
6601
6602         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6603
6604         if (duty100 == 0)
6605                 return -EINVAL;
6606
6607         tmp64 = (u64)speed * duty100;
6608         do_div(tmp64, 100);
6609         duty = (u32)tmp64;
6610
6611         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6612         tmp |= FDO_STATIC_DUTY(duty);
6613         WREG32(CG_FDO_CTRL0, tmp);
6614
6615         return 0;
6616 }
6617
6618 static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
6619 {
6620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6621
6622         if (mode) {
6623                 /* stop auto-manage */
6624                 if (adev->pm.dpm.fan.ucode_fan_control)
6625                         si_fan_ctrl_stop_smc_fan_control(adev);
6626                 si_fan_ctrl_set_static_mode(adev, mode);
6627         } else {
6628                 /* restart auto-manage */
6629                 if (adev->pm.dpm.fan.ucode_fan_control)
6630                         si_thermal_start_smc_fan_control(adev);
6631                 else
6632                         si_fan_ctrl_set_default_mode(adev);
6633         }
6634 }
6635
6636 static u32 si_dpm_get_fan_control_mode(void *handle)
6637 {
6638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6639         struct si_power_info *si_pi = si_get_pi(adev);
6640         u32 tmp;
6641
6642         if (si_pi->fan_is_controlled_by_smc)
6643                 return 0;
6644
6645         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6646         return (tmp >> FDO_PWM_MODE_SHIFT);
6647 }
6648
6649 #if 0
6650 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6651                                          u32 *speed)
6652 {
6653         u32 tach_period;
6654         u32 xclk = amdgpu_asic_get_xclk(adev);
6655
6656         if (adev->pm.no_fan)
6657                 return -ENOENT;
6658
6659         if (adev->pm.fan_pulses_per_revolution == 0)
6660                 return -ENOENT;
6661
6662         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6663         if (tach_period == 0)
6664                 return -ENOENT;
6665
6666         *speed = 60 * xclk * 10000 / tach_period;
6667
6668         return 0;
6669 }
6670
6671 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6672                                          u32 speed)
6673 {
6674         u32 tach_period, tmp;
6675         u32 xclk = amdgpu_asic_get_xclk(adev);
6676
6677         if (adev->pm.no_fan)
6678                 return -ENOENT;
6679
6680         if (adev->pm.fan_pulses_per_revolution == 0)
6681                 return -ENOENT;
6682
6683         if ((speed < adev->pm.fan_min_rpm) ||
6684             (speed > adev->pm.fan_max_rpm))
6685                 return -EINVAL;
6686
6687         if (adev->pm.dpm.fan.ucode_fan_control)
6688                 si_fan_ctrl_stop_smc_fan_control(adev);
6689
6690         tach_period = 60 * xclk * 10000 / (8 * speed);
6691         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6692         tmp |= TARGET_PERIOD(tach_period);
6693         WREG32(CG_TACH_CTRL, tmp);
6694
6695         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6696
6697         return 0;
6698 }
6699 #endif
6700
6701 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6702 {
6703         struct si_power_info *si_pi = si_get_pi(adev);
6704         u32 tmp;
6705
6706         if (!si_pi->fan_ctrl_is_in_default_mode) {
6707                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6708                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6709                 WREG32(CG_FDO_CTRL2, tmp);
6710
6711                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6712                 tmp |= TMIN(si_pi->t_min);
6713                 WREG32(CG_FDO_CTRL2, tmp);
6714                 si_pi->fan_ctrl_is_in_default_mode = true;
6715         }
6716 }
6717
6718 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6719 {
6720         if (adev->pm.dpm.fan.ucode_fan_control) {
6721                 si_fan_ctrl_start_smc_fan_control(adev);
6722                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6723         }
6724 }
6725
6726 static void si_thermal_initialize(struct amdgpu_device *adev)
6727 {
6728         u32 tmp;
6729
6730         if (adev->pm.fan_pulses_per_revolution) {
6731                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6732                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6733                 WREG32(CG_TACH_CTRL, tmp);
6734         }
6735
6736         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6737         tmp |= TACH_PWM_RESP_RATE(0x28);
6738         WREG32(CG_FDO_CTRL2, tmp);
6739 }
6740
6741 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6742 {
6743         int ret;
6744
6745         si_thermal_initialize(adev);
6746         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6747         if (ret)
6748                 return ret;
6749         ret = si_thermal_enable_alert(adev, true);
6750         if (ret)
6751                 return ret;
6752         if (adev->pm.dpm.fan.ucode_fan_control) {
6753                 ret = si_halt_smc(adev);
6754                 if (ret)
6755                         return ret;
6756                 ret = si_thermal_setup_fan_table(adev);
6757                 if (ret)
6758                         return ret;
6759                 ret = si_resume_smc(adev);
6760                 if (ret)
6761                         return ret;
6762                 si_thermal_start_smc_fan_control(adev);
6763         }
6764
6765         return 0;
6766 }
6767
6768 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6769 {
6770         if (!adev->pm.no_fan) {
6771                 si_fan_ctrl_set_default_mode(adev);
6772                 si_fan_ctrl_stop_smc_fan_control(adev);
6773         }
6774 }
6775
6776 static int si_dpm_enable(struct amdgpu_device *adev)
6777 {
6778         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6779         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6780         struct si_power_info *si_pi = si_get_pi(adev);
6781         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6782         int ret;
6783
6784         if (amdgpu_si_is_smc_running(adev))
6785                 return -EINVAL;
6786         if (pi->voltage_control || si_pi->voltage_control_svi2)
6787                 si_enable_voltage_control(adev, true);
6788         if (pi->mvdd_control)
6789                 si_get_mvdd_configuration(adev);
6790         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6791                 ret = si_construct_voltage_tables(adev);
6792                 if (ret) {
6793                         DRM_ERROR("si_construct_voltage_tables failed\n");
6794                         return ret;
6795                 }
6796         }
6797         if (eg_pi->dynamic_ac_timing) {
6798                 ret = si_initialize_mc_reg_table(adev);
6799                 if (ret)
6800                         eg_pi->dynamic_ac_timing = false;
6801         }
6802         if (pi->dynamic_ss)
6803                 si_enable_spread_spectrum(adev, true);
6804         if (pi->thermal_protection)
6805                 si_enable_thermal_protection(adev, true);
6806         si_setup_bsp(adev);
6807         si_program_git(adev);
6808         si_program_tp(adev);
6809         si_program_tpp(adev);
6810         si_program_sstp(adev);
6811         si_enable_display_gap(adev);
6812         si_program_vc(adev);
6813         ret = si_upload_firmware(adev);
6814         if (ret) {
6815                 DRM_ERROR("si_upload_firmware failed\n");
6816                 return ret;
6817         }
6818         ret = si_process_firmware_header(adev);
6819         if (ret) {
6820                 DRM_ERROR("si_process_firmware_header failed\n");
6821                 return ret;
6822         }
6823         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6824         if (ret) {
6825                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6826                 return ret;
6827         }
6828         ret = si_init_smc_table(adev);
6829         if (ret) {
6830                 DRM_ERROR("si_init_smc_table failed\n");
6831                 return ret;
6832         }
6833         ret = si_init_smc_spll_table(adev);
6834         if (ret) {
6835                 DRM_ERROR("si_init_smc_spll_table failed\n");
6836                 return ret;
6837         }
6838         ret = si_init_arb_table_index(adev);
6839         if (ret) {
6840                 DRM_ERROR("si_init_arb_table_index failed\n");
6841                 return ret;
6842         }
6843         if (eg_pi->dynamic_ac_timing) {
6844                 ret = si_populate_mc_reg_table(adev, boot_ps);
6845                 if (ret) {
6846                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6847                         return ret;
6848                 }
6849         }
6850         ret = si_initialize_smc_cac_tables(adev);
6851         if (ret) {
6852                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6853                 return ret;
6854         }
6855         ret = si_initialize_hardware_cac_manager(adev);
6856         if (ret) {
6857                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6858                 return ret;
6859         }
6860         ret = si_initialize_smc_dte_tables(adev);
6861         if (ret) {
6862                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6863                 return ret;
6864         }
6865         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6866         if (ret) {
6867                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6868                 return ret;
6869         }
6870         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6871         if (ret) {
6872                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6873                 return ret;
6874         }
6875         si_program_response_times(adev);
6876         si_program_ds_registers(adev);
6877         si_dpm_start_smc(adev);
6878         ret = si_notify_smc_display_change(adev, false);
6879         if (ret) {
6880                 DRM_ERROR("si_notify_smc_display_change failed\n");
6881                 return ret;
6882         }
6883         si_enable_sclk_control(adev, true);
6884         si_start_dpm(adev);
6885
6886         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6887         si_thermal_start_thermal_controller(adev);
6888         ni_update_current_ps(adev, boot_ps);
6889
6890         return 0;
6891 }
6892
6893 static int si_set_temperature_range(struct amdgpu_device *adev)
6894 {
6895         int ret;
6896
6897         ret = si_thermal_enable_alert(adev, false);
6898         if (ret)
6899                 return ret;
6900         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6901         if (ret)
6902                 return ret;
6903         ret = si_thermal_enable_alert(adev, true);
6904         if (ret)
6905                 return ret;
6906
6907         return ret;
6908 }
6909
6910 static void si_dpm_disable(struct amdgpu_device *adev)
6911 {
6912         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6913         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6914
6915         if (!amdgpu_si_is_smc_running(adev))
6916                 return;
6917         si_thermal_stop_thermal_controller(adev);
6918         si_disable_ulv(adev);
6919         si_clear_vc(adev);
6920         if (pi->thermal_protection)
6921                 si_enable_thermal_protection(adev, false);
6922         si_enable_power_containment(adev, boot_ps, false);
6923         si_enable_smc_cac(adev, boot_ps, false);
6924         si_enable_spread_spectrum(adev, false);
6925         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6926         si_stop_dpm(adev);
6927         si_reset_to_default(adev);
6928         si_dpm_stop_smc(adev);
6929         si_force_switch_to_arb_f0(adev);
6930
6931         ni_update_current_ps(adev, boot_ps);
6932 }
6933
6934 static int si_dpm_pre_set_power_state(void *handle)
6935 {
6936         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6937         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6938         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6939         struct amdgpu_ps *new_ps = &requested_ps;
6940
6941         ni_update_requested_ps(adev, new_ps);
6942         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6943
6944         return 0;
6945 }
6946
6947 static int si_power_control_set_level(struct amdgpu_device *adev)
6948 {
6949         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6950         int ret;
6951
6952         ret = si_restrict_performance_levels_before_switch(adev);
6953         if (ret)
6954                 return ret;
6955         ret = si_halt_smc(adev);
6956         if (ret)
6957                 return ret;
6958         ret = si_populate_smc_tdp_limits(adev, new_ps);
6959         if (ret)
6960                 return ret;
6961         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6962         if (ret)
6963                 return ret;
6964         ret = si_resume_smc(adev);
6965         if (ret)
6966                 return ret;
6967         ret = si_set_sw_state(adev);
6968         if (ret)
6969                 return ret;
6970         return 0;
6971 }
6972
6973 static int si_dpm_set_power_state(void *handle)
6974 {
6975         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6976         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6977         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6978         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6979         int ret;
6980
6981         ret = si_disable_ulv(adev);
6982         if (ret) {
6983                 DRM_ERROR("si_disable_ulv failed\n");
6984                 return ret;
6985         }
6986         ret = si_restrict_performance_levels_before_switch(adev);
6987         if (ret) {
6988                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6989                 return ret;
6990         }
6991         if (eg_pi->pcie_performance_request)
6992                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6993         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6994         ret = si_enable_power_containment(adev, new_ps, false);
6995         if (ret) {
6996                 DRM_ERROR("si_enable_power_containment failed\n");
6997                 return ret;
6998         }
6999         ret = si_enable_smc_cac(adev, new_ps, false);
7000         if (ret) {
7001                 DRM_ERROR("si_enable_smc_cac failed\n");
7002                 return ret;
7003         }
7004         ret = si_halt_smc(adev);
7005         if (ret) {
7006                 DRM_ERROR("si_halt_smc failed\n");
7007                 return ret;
7008         }
7009         ret = si_upload_sw_state(adev, new_ps);
7010         if (ret) {
7011                 DRM_ERROR("si_upload_sw_state failed\n");
7012                 return ret;
7013         }
7014         ret = si_upload_smc_data(adev);
7015         if (ret) {
7016                 DRM_ERROR("si_upload_smc_data failed\n");
7017                 return ret;
7018         }
7019         ret = si_upload_ulv_state(adev);
7020         if (ret) {
7021                 DRM_ERROR("si_upload_ulv_state failed\n");
7022                 return ret;
7023         }
7024         if (eg_pi->dynamic_ac_timing) {
7025                 ret = si_upload_mc_reg_table(adev, new_ps);
7026                 if (ret) {
7027                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7028                         return ret;
7029                 }
7030         }
7031         ret = si_program_memory_timing_parameters(adev, new_ps);
7032         if (ret) {
7033                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7034                 return ret;
7035         }
7036         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7037
7038         ret = si_resume_smc(adev);
7039         if (ret) {
7040                 DRM_ERROR("si_resume_smc failed\n");
7041                 return ret;
7042         }
7043         ret = si_set_sw_state(adev);
7044         if (ret) {
7045                 DRM_ERROR("si_set_sw_state failed\n");
7046                 return ret;
7047         }
7048         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7049         if (eg_pi->pcie_performance_request)
7050                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7051         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7052         if (ret) {
7053                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7054                 return ret;
7055         }
7056         ret = si_enable_smc_cac(adev, new_ps, true);
7057         if (ret) {
7058                 DRM_ERROR("si_enable_smc_cac failed\n");
7059                 return ret;
7060         }
7061         ret = si_enable_power_containment(adev, new_ps, true);
7062         if (ret) {
7063                 DRM_ERROR("si_enable_power_containment failed\n");
7064                 return ret;
7065         }
7066
7067         ret = si_power_control_set_level(adev);
7068         if (ret) {
7069                 DRM_ERROR("si_power_control_set_level failed\n");
7070                 return ret;
7071         }
7072
7073         return 0;
7074 }
7075
7076 static void si_dpm_post_set_power_state(void *handle)
7077 {
7078         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7079         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7080         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7081
7082         ni_update_current_ps(adev, new_ps);
7083 }
7084
7085 #if 0
7086 void si_dpm_reset_asic(struct amdgpu_device *adev)
7087 {
7088         si_restrict_performance_levels_before_switch(adev);
7089         si_disable_ulv(adev);
7090         si_set_boot_state(adev);
7091 }
7092 #endif
7093
7094 static void si_dpm_display_configuration_changed(void *handle)
7095 {
7096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7097
7098         si_program_display_gap(adev);
7099 }
7100
7101
7102 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7103                                           struct amdgpu_ps *rps,
7104                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7105                                           u8 table_rev)
7106 {
7107         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7108         rps->class = le16_to_cpu(non_clock_info->usClassification);
7109         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7110
7111         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7112                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7113                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7114         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7115                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7116                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7117         } else {
7118                 rps->vclk = 0;
7119                 rps->dclk = 0;
7120         }
7121
7122         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7123                 adev->pm.dpm.boot_ps = rps;
7124         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7125                 adev->pm.dpm.uvd_ps = rps;
7126 }
7127
7128 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7129                                       struct amdgpu_ps *rps, int index,
7130                                       union pplib_clock_info *clock_info)
7131 {
7132         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7133         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7134         struct si_power_info *si_pi = si_get_pi(adev);
7135         struct  si_ps *ps = si_get_ps(rps);
7136         u16 leakage_voltage;
7137         struct rv7xx_pl *pl = &ps->performance_levels[index];
7138         int ret;
7139
7140         ps->performance_level_count = index + 1;
7141
7142         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7143         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7144         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7145         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7146
7147         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7148         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7149         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7150         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7151                                                    si_pi->sys_pcie_mask,
7152                                                    si_pi->boot_pcie_gen,
7153                                                    clock_info->si.ucPCIEGen);
7154
7155         /* patch up vddc if necessary */
7156         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7157                                                         &leakage_voltage);
7158         if (ret == 0)
7159                 pl->vddc = leakage_voltage;
7160
7161         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7162                 pi->acpi_vddc = pl->vddc;
7163                 eg_pi->acpi_vddci = pl->vddci;
7164                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7165         }
7166
7167         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7168             index == 0) {
7169                 /* XXX disable for A0 tahiti */
7170                 si_pi->ulv.supported = false;
7171                 si_pi->ulv.pl = *pl;
7172                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7173                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7174                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7175                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7176         }
7177
7178         if (pi->min_vddc_in_table > pl->vddc)
7179                 pi->min_vddc_in_table = pl->vddc;
7180
7181         if (pi->max_vddc_in_table < pl->vddc)
7182                 pi->max_vddc_in_table = pl->vddc;
7183
7184         /* patch up boot state */
7185         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7186                 u16 vddc, vddci, mvdd;
7187                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7188                 pl->mclk = adev->clock.default_mclk;
7189                 pl->sclk = adev->clock.default_sclk;
7190                 pl->vddc = vddc;
7191                 pl->vddci = vddci;
7192                 si_pi->mvdd_bootup_value = mvdd;
7193         }
7194
7195         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7196             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7197                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7198                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7199                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7200                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7201         }
7202 }
7203
7204 union pplib_power_state {
7205         struct _ATOM_PPLIB_STATE v1;
7206         struct _ATOM_PPLIB_STATE_V2 v2;
7207 };
7208
7209 static int si_parse_power_table(struct amdgpu_device *adev)
7210 {
7211         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7212         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7213         union pplib_power_state *power_state;
7214         int i, j, k, non_clock_array_index, clock_array_index;
7215         union pplib_clock_info *clock_info;
7216         struct _StateArray *state_array;
7217         struct _ClockInfoArray *clock_info_array;
7218         struct _NonClockInfoArray *non_clock_info_array;
7219         union power_info *power_info;
7220         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7221         u16 data_offset;
7222         u8 frev, crev;
7223         u8 *power_state_offset;
7224         struct  si_ps *ps;
7225
7226         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7227                                    &frev, &crev, &data_offset))
7228                 return -EINVAL;
7229         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7230
7231         amdgpu_add_thermal_controller(adev);
7232
7233         state_array = (struct _StateArray *)
7234                 (mode_info->atom_context->bios + data_offset +
7235                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7236         clock_info_array = (struct _ClockInfoArray *)
7237                 (mode_info->atom_context->bios + data_offset +
7238                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7239         non_clock_info_array = (struct _NonClockInfoArray *)
7240                 (mode_info->atom_context->bios + data_offset +
7241                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7242
7243         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7244                                   state_array->ucNumEntries, GFP_KERNEL);
7245         if (!adev->pm.dpm.ps)
7246                 return -ENOMEM;
7247         power_state_offset = (u8 *)state_array->states;
7248         for (i = 0; i < state_array->ucNumEntries; i++) {
7249                 u8 *idx;
7250                 power_state = (union pplib_power_state *)power_state_offset;
7251                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7252                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7253                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7254                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7255                 if (ps == NULL) {
7256                         kfree(adev->pm.dpm.ps);
7257                         return -ENOMEM;
7258                 }
7259                 adev->pm.dpm.ps[i].ps_priv = ps;
7260                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7261                                               non_clock_info,
7262                                               non_clock_info_array->ucEntrySize);
7263                 k = 0;
7264                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7265                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7266                         clock_array_index = idx[j];
7267                         if (clock_array_index >= clock_info_array->ucNumEntries)
7268                                 continue;
7269                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7270                                 break;
7271                         clock_info = (union pplib_clock_info *)
7272                                 ((u8 *)&clock_info_array->clockInfo[0] +
7273                                  (clock_array_index * clock_info_array->ucEntrySize));
7274                         si_parse_pplib_clock_info(adev,
7275                                                   &adev->pm.dpm.ps[i], k,
7276                                                   clock_info);
7277                         k++;
7278                 }
7279                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7280         }
7281         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7282
7283         /* fill in the vce power states */
7284         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7285                 u32 sclk, mclk;
7286                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7287                 clock_info = (union pplib_clock_info *)
7288                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7289                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7290                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7291                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7292                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7293                 adev->pm.dpm.vce_states[i].sclk = sclk;
7294                 adev->pm.dpm.vce_states[i].mclk = mclk;
7295         }
7296
7297         return 0;
7298 }
7299
7300 static int si_dpm_init(struct amdgpu_device *adev)
7301 {
7302         struct rv7xx_power_info *pi;
7303         struct evergreen_power_info *eg_pi;
7304         struct ni_power_info *ni_pi;
7305         struct si_power_info *si_pi;
7306         struct atom_clock_dividers dividers;
7307         int ret;
7308
7309         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7310         if (si_pi == NULL)
7311                 return -ENOMEM;
7312         adev->pm.dpm.priv = si_pi;
7313         ni_pi = &si_pi->ni;
7314         eg_pi = &ni_pi->eg;
7315         pi = &eg_pi->rv7xx;
7316
7317         si_pi->sys_pcie_mask =
7318                 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7319                 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7320         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7321         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7322
7323         si_set_max_cu_value(adev);
7324
7325         rv770_get_max_vddc(adev);
7326         si_get_leakage_vddc(adev);
7327         si_patch_dependency_tables_based_on_leakage(adev);
7328
7329         pi->acpi_vddc = 0;
7330         eg_pi->acpi_vddci = 0;
7331         pi->min_vddc_in_table = 0;
7332         pi->max_vddc_in_table = 0;
7333
7334         ret = amdgpu_get_platform_caps(adev);
7335         if (ret)
7336                 return ret;
7337
7338         ret = amdgpu_parse_extended_power_table(adev);
7339         if (ret)
7340                 return ret;
7341
7342         ret = si_parse_power_table(adev);
7343         if (ret)
7344                 return ret;
7345
7346         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7347                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7348         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7349                 amdgpu_free_extended_power_table(adev);
7350                 return -ENOMEM;
7351         }
7352         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7353         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7354         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7355         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7356         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7357         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7358         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7359         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7360         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7361
7362         if (adev->pm.dpm.voltage_response_time == 0)
7363                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7364         if (adev->pm.dpm.backbias_response_time == 0)
7365                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7366
7367         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7368                                              0, false, &dividers);
7369         if (ret)
7370                 pi->ref_div = dividers.ref_div + 1;
7371         else
7372                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7373
7374         eg_pi->smu_uvd_hs = false;
7375
7376         pi->mclk_strobe_mode_threshold = 40000;
7377         if (si_is_special_1gb_platform(adev))
7378                 pi->mclk_stutter_mode_threshold = 0;
7379         else
7380                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7381         pi->mclk_edc_enable_threshold = 40000;
7382         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7383
7384         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7385
7386         pi->voltage_control =
7387                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7388                                             VOLTAGE_OBJ_GPIO_LUT);
7389         if (!pi->voltage_control) {
7390                 si_pi->voltage_control_svi2 =
7391                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7392                                                     VOLTAGE_OBJ_SVID2);
7393                 if (si_pi->voltage_control_svi2)
7394                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7395                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7396         }
7397
7398         pi->mvdd_control =
7399                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7400                                             VOLTAGE_OBJ_GPIO_LUT);
7401
7402         eg_pi->vddci_control =
7403                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7404                                             VOLTAGE_OBJ_GPIO_LUT);
7405         if (!eg_pi->vddci_control)
7406                 si_pi->vddci_control_svi2 =
7407                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7408                                                     VOLTAGE_OBJ_SVID2);
7409
7410         si_pi->vddc_phase_shed_control =
7411                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7412                                             VOLTAGE_OBJ_PHASE_LUT);
7413
7414         rv770_get_engine_memory_ss(adev);
7415
7416         pi->asi = RV770_ASI_DFLT;
7417         pi->pasi = CYPRESS_HASI_DFLT;
7418         pi->vrc = SISLANDS_VRC_DFLT;
7419
7420         pi->gfx_clock_gating = true;
7421
7422         eg_pi->sclk_deep_sleep = true;
7423         si_pi->sclk_deep_sleep_above_low = false;
7424
7425         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7426                 pi->thermal_protection = true;
7427         else
7428                 pi->thermal_protection = false;
7429
7430         eg_pi->dynamic_ac_timing = true;
7431
7432         eg_pi->light_sleep = true;
7433 #if defined(CONFIG_ACPI)
7434         eg_pi->pcie_performance_request =
7435                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7436 #else
7437         eg_pi->pcie_performance_request = false;
7438 #endif
7439
7440         si_pi->sram_end = SMC_RAM_END;
7441
7442         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7443         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7444         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7445         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7446         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7447         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7448         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7449
7450         si_initialize_powertune_defaults(adev);
7451
7452         /* make sure dc limits are valid */
7453         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7454             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7455                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7456                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7457
7458         si_pi->fan_ctrl_is_in_default_mode = true;
7459
7460         return 0;
7461 }
7462
7463 static void si_dpm_fini(struct amdgpu_device *adev)
7464 {
7465         int i;
7466
7467         if (adev->pm.dpm.ps)
7468                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7469                         kfree(adev->pm.dpm.ps[i].ps_priv);
7470         kfree(adev->pm.dpm.ps);
7471         kfree(adev->pm.dpm.priv);
7472         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7473         amdgpu_free_extended_power_table(adev);
7474 }
7475
7476 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7477                                                     struct seq_file *m)
7478 {
7479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7480         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7481         struct amdgpu_ps *rps = &eg_pi->current_rps;
7482         struct  si_ps *ps = si_get_ps(rps);
7483         struct rv7xx_pl *pl;
7484         u32 current_index =
7485                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7486                 CURRENT_STATE_INDEX_SHIFT;
7487
7488         if (current_index >= ps->performance_level_count) {
7489                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7490         } else {
7491                 pl = &ps->performance_levels[current_index];
7492                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7493                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7494                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7495         }
7496 }
7497
7498 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7499                                       struct amdgpu_irq_src *source,
7500                                       unsigned type,
7501                                       enum amdgpu_interrupt_state state)
7502 {
7503         u32 cg_thermal_int;
7504
7505         switch (type) {
7506         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7507                 switch (state) {
7508                 case AMDGPU_IRQ_STATE_DISABLE:
7509                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7510                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7511                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7512                         break;
7513                 case AMDGPU_IRQ_STATE_ENABLE:
7514                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7515                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7516                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7517                         break;
7518                 default:
7519                         break;
7520                 }
7521                 break;
7522
7523         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7524                 switch (state) {
7525                 case AMDGPU_IRQ_STATE_DISABLE:
7526                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7527                         cg_thermal_int |= THERM_INT_MASK_LOW;
7528                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7529                         break;
7530                 case AMDGPU_IRQ_STATE_ENABLE:
7531                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7532                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7533                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7534                         break;
7535                 default:
7536                         break;
7537                 }
7538                 break;
7539
7540         default:
7541                 break;
7542         }
7543         return 0;
7544 }
7545
7546 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7547                                     struct amdgpu_irq_src *source,
7548                                     struct amdgpu_iv_entry *entry)
7549 {
7550         bool queue_thermal = false;
7551
7552         if (entry == NULL)
7553                 return -EINVAL;
7554
7555         switch (entry->src_id) {
7556         case 230: /* thermal low to high */
7557                 DRM_DEBUG("IH: thermal low to high\n");
7558                 adev->pm.dpm.thermal.high_to_low = false;
7559                 queue_thermal = true;
7560                 break;
7561         case 231: /* thermal high to low */
7562                 DRM_DEBUG("IH: thermal high to low\n");
7563                 adev->pm.dpm.thermal.high_to_low = true;
7564                 queue_thermal = true;
7565                 break;
7566         default:
7567                 break;
7568         }
7569
7570         if (queue_thermal)
7571                 schedule_work(&adev->pm.dpm.thermal.work);
7572
7573         return 0;
7574 }
7575
7576 static int si_dpm_late_init(void *handle)
7577 {
7578         int ret;
7579         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7580
7581         if (!amdgpu_dpm)
7582                 return 0;
7583
7584         ret = si_set_temperature_range(adev);
7585         if (ret)
7586                 return ret;
7587 #if 0 //TODO ?
7588         si_dpm_powergate_uvd(adev, true);
7589 #endif
7590         return 0;
7591 }
7592
7593 /**
7594  * si_dpm_init_microcode - load ucode images from disk
7595  *
7596  * @adev: amdgpu_device pointer
7597  *
7598  * Use the firmware interface to load the ucode images into
7599  * the driver (not loaded into hw).
7600  * Returns 0 on success, error on failure.
7601  */
7602 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7603 {
7604         const char *chip_name;
7605         char fw_name[30];
7606         int err;
7607
7608         DRM_DEBUG("\n");
7609         switch (adev->asic_type) {
7610         case CHIP_TAHITI:
7611                 chip_name = "tahiti";
7612                 break;
7613         case CHIP_PITCAIRN:
7614                 if ((adev->pdev->revision == 0x81) &&
7615                     ((adev->pdev->device == 0x6810) ||
7616                     (adev->pdev->device == 0x6811)))
7617                         chip_name = "pitcairn_k";
7618                 else
7619                         chip_name = "pitcairn";
7620                 break;
7621         case CHIP_VERDE:
7622                 if (((adev->pdev->device == 0x6820) &&
7623                         ((adev->pdev->revision == 0x81) ||
7624                         (adev->pdev->revision == 0x83))) ||
7625                     ((adev->pdev->device == 0x6821) &&
7626                         ((adev->pdev->revision == 0x83) ||
7627                         (adev->pdev->revision == 0x87))) ||
7628                     ((adev->pdev->revision == 0x87) &&
7629                         ((adev->pdev->device == 0x6823) ||
7630                         (adev->pdev->device == 0x682b))))
7631                         chip_name = "verde_k";
7632                 else
7633                         chip_name = "verde";
7634                 break;
7635         case CHIP_OLAND:
7636                 if (((adev->pdev->revision == 0x81) &&
7637                         ((adev->pdev->device == 0x6600) ||
7638                         (adev->pdev->device == 0x6604) ||
7639                         (adev->pdev->device == 0x6605) ||
7640                         (adev->pdev->device == 0x6610))) ||
7641                     ((adev->pdev->revision == 0x83) &&
7642                         (adev->pdev->device == 0x6610)))
7643                         chip_name = "oland_k";
7644                 else
7645                         chip_name = "oland";
7646                 break;
7647         case CHIP_HAINAN:
7648                 if (((adev->pdev->revision == 0x81) &&
7649                         (adev->pdev->device == 0x6660)) ||
7650                     ((adev->pdev->revision == 0x83) &&
7651                         ((adev->pdev->device == 0x6660) ||
7652                         (adev->pdev->device == 0x6663) ||
7653                         (adev->pdev->device == 0x6665) ||
7654                          (adev->pdev->device == 0x6667))))
7655                         chip_name = "hainan_k";
7656                 else if ((adev->pdev->revision == 0xc3) &&
7657                          (adev->pdev->device == 0x6665))
7658                         chip_name = "banks_k_2";
7659                 else
7660                         chip_name = "hainan";
7661                 break;
7662         default: BUG();
7663         }
7664
7665         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7666         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7667         if (err)
7668                 goto out;
7669         err = amdgpu_ucode_validate(adev->pm.fw);
7670
7671 out:
7672         if (err) {
7673                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7674                           err, fw_name);
7675                 release_firmware(adev->pm.fw);
7676                 adev->pm.fw = NULL;
7677         }
7678         return err;
7679
7680 }
7681
7682 static int si_dpm_sw_init(void *handle)
7683 {
7684         int ret;
7685         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7686
7687         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7688         if (ret)
7689                 return ret;
7690
7691         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7692         if (ret)
7693                 return ret;
7694
7695         /* default to balanced state */
7696         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7697         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7698         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7699         adev->pm.default_sclk = adev->clock.default_sclk;
7700         adev->pm.default_mclk = adev->clock.default_mclk;
7701         adev->pm.current_sclk = adev->clock.default_sclk;
7702         adev->pm.current_mclk = adev->clock.default_mclk;
7703         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7704
7705         if (amdgpu_dpm == 0)
7706                 return 0;
7707
7708         ret = si_dpm_init_microcode(adev);
7709         if (ret)
7710                 return ret;
7711
7712         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7713         mutex_lock(&adev->pm.mutex);
7714         ret = si_dpm_init(adev);
7715         if (ret)
7716                 goto dpm_failed;
7717         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7718         if (amdgpu_dpm == 1)
7719                 amdgpu_pm_print_power_states(adev);
7720         mutex_unlock(&adev->pm.mutex);
7721         DRM_INFO("amdgpu: dpm initialized\n");
7722
7723         return 0;
7724
7725 dpm_failed:
7726         si_dpm_fini(adev);
7727         mutex_unlock(&adev->pm.mutex);
7728         DRM_ERROR("amdgpu: dpm initialization failed\n");
7729         return ret;
7730 }
7731
7732 static int si_dpm_sw_fini(void *handle)
7733 {
7734         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7735
7736         flush_work(&adev->pm.dpm.thermal.work);
7737
7738         mutex_lock(&adev->pm.mutex);
7739         si_dpm_fini(adev);
7740         mutex_unlock(&adev->pm.mutex);
7741
7742         return 0;
7743 }
7744
7745 static int si_dpm_hw_init(void *handle)
7746 {
7747         int ret;
7748
7749         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7750
7751         if (!amdgpu_dpm)
7752                 return 0;
7753
7754         mutex_lock(&adev->pm.mutex);
7755         si_dpm_setup_asic(adev);
7756         ret = si_dpm_enable(adev);
7757         if (ret)
7758                 adev->pm.dpm_enabled = false;
7759         else
7760                 adev->pm.dpm_enabled = true;
7761         mutex_unlock(&adev->pm.mutex);
7762
7763         return ret;
7764 }
7765
7766 static int si_dpm_hw_fini(void *handle)
7767 {
7768         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7769
7770         if (adev->pm.dpm_enabled) {
7771                 mutex_lock(&adev->pm.mutex);
7772                 si_dpm_disable(adev);
7773                 mutex_unlock(&adev->pm.mutex);
7774         }
7775
7776         return 0;
7777 }
7778
7779 static int si_dpm_suspend(void *handle)
7780 {
7781         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7782
7783         if (adev->pm.dpm_enabled) {
7784                 mutex_lock(&adev->pm.mutex);
7785                 /* disable dpm */
7786                 si_dpm_disable(adev);
7787                 /* reset the power state */
7788                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7789                 mutex_unlock(&adev->pm.mutex);
7790         }
7791         return 0;
7792 }
7793
7794 static int si_dpm_resume(void *handle)
7795 {
7796         int ret;
7797         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7798
7799         if (adev->pm.dpm_enabled) {
7800                 /* asic init will reset to the boot state */
7801                 mutex_lock(&adev->pm.mutex);
7802                 si_dpm_setup_asic(adev);
7803                 ret = si_dpm_enable(adev);
7804                 if (ret)
7805                         adev->pm.dpm_enabled = false;
7806                 else
7807                         adev->pm.dpm_enabled = true;
7808                 mutex_unlock(&adev->pm.mutex);
7809                 if (adev->pm.dpm_enabled)
7810                         amdgpu_pm_compute_clocks(adev);
7811         }
7812         return 0;
7813 }
7814
7815 static bool si_dpm_is_idle(void *handle)
7816 {
7817         /* XXX */
7818         return true;
7819 }
7820
7821 static int si_dpm_wait_for_idle(void *handle)
7822 {
7823         /* XXX */
7824         return 0;
7825 }
7826
7827 static int si_dpm_soft_reset(void *handle)
7828 {
7829         return 0;
7830 }
7831
7832 static int si_dpm_set_clockgating_state(void *handle,
7833                                         enum amd_clockgating_state state)
7834 {
7835         return 0;
7836 }
7837
7838 static int si_dpm_set_powergating_state(void *handle,
7839                                         enum amd_powergating_state state)
7840 {
7841         return 0;
7842 }
7843
7844 /* get temperature in millidegrees */
7845 static int si_dpm_get_temp(void *handle)
7846 {
7847         u32 temp;
7848         int actual_temp = 0;
7849         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7850
7851         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7852                 CTF_TEMP_SHIFT;
7853
7854         if (temp & 0x200)
7855                 actual_temp = 255;
7856         else
7857                 actual_temp = temp & 0x1ff;
7858
7859         actual_temp = (actual_temp * 1000);
7860
7861         return actual_temp;
7862 }
7863
7864 static u32 si_dpm_get_sclk(void *handle, bool low)
7865 {
7866         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7867         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7868         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7869
7870         if (low)
7871                 return requested_state->performance_levels[0].sclk;
7872         else
7873                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7874 }
7875
7876 static u32 si_dpm_get_mclk(void *handle, bool low)
7877 {
7878         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7879         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7880         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7881
7882         if (low)
7883                 return requested_state->performance_levels[0].mclk;
7884         else
7885                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7886 }
7887
7888 static void si_dpm_print_power_state(void *handle,
7889                                      void *current_ps)
7890 {
7891         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7892         struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7893         struct  si_ps *ps = si_get_ps(rps);
7894         struct rv7xx_pl *pl;
7895         int i;
7896
7897         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7898         amdgpu_dpm_print_cap_info(rps->caps);
7899         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7900         for (i = 0; i < ps->performance_level_count; i++) {
7901                 pl = &ps->performance_levels[i];
7902                 if (adev->asic_type >= CHIP_TAHITI)
7903                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7904                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7905                 else
7906                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7907                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7908         }
7909         amdgpu_dpm_print_ps_status(adev, rps);
7910 }
7911
7912 static int si_dpm_early_init(void *handle)
7913 {
7914
7915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7916
7917         si_dpm_set_irq_funcs(adev);
7918         return 0;
7919 }
7920
7921 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7922                                                 const struct rv7xx_pl *si_cpl2)
7923 {
7924         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7925                   (si_cpl1->sclk == si_cpl2->sclk) &&
7926                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7927                   (si_cpl1->vddc == si_cpl2->vddc) &&
7928                   (si_cpl1->vddci == si_cpl2->vddci));
7929 }
7930
7931 static int si_check_state_equal(void *handle,
7932                                 void *current_ps,
7933                                 void *request_ps,
7934                                 bool *equal)
7935 {
7936         struct si_ps *si_cps;
7937         struct si_ps *si_rps;
7938         int i;
7939         struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
7940         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
7941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7942
7943         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7944                 return -EINVAL;
7945
7946         si_cps = si_get_ps((struct amdgpu_ps *)cps);
7947         si_rps = si_get_ps((struct amdgpu_ps *)rps);
7948
7949         if (si_cps == NULL) {
7950                 printk("si_cps is NULL\n");
7951                 *equal = false;
7952                 return 0;
7953         }
7954
7955         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7956                 *equal = false;
7957                 return 0;
7958         }
7959
7960         for (i = 0; i < si_cps->performance_level_count; i++) {
7961                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7962                                         &(si_rps->performance_levels[i]))) {
7963                         *equal = false;
7964                         return 0;
7965                 }
7966         }
7967
7968         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7969         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7970         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7971
7972         return 0;
7973 }
7974
7975 static int si_dpm_read_sensor(void *handle, int idx,
7976                               void *value, int *size)
7977 {
7978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7979         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7980         struct amdgpu_ps *rps = &eg_pi->current_rps;
7981         struct  si_ps *ps = si_get_ps(rps);
7982         uint32_t sclk, mclk;
7983         u32 pl_index =
7984                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7985                 CURRENT_STATE_INDEX_SHIFT;
7986
7987         /* size must be at least 4 bytes for all sensors */
7988         if (*size < 4)
7989                 return -EINVAL;
7990
7991         switch (idx) {
7992         case AMDGPU_PP_SENSOR_GFX_SCLK:
7993                 if (pl_index < ps->performance_level_count) {
7994                         sclk = ps->performance_levels[pl_index].sclk;
7995                         *((uint32_t *)value) = sclk;
7996                         *size = 4;
7997                         return 0;
7998                 }
7999                 return -EINVAL;
8000         case AMDGPU_PP_SENSOR_GFX_MCLK:
8001                 if (pl_index < ps->performance_level_count) {
8002                         mclk = ps->performance_levels[pl_index].mclk;
8003                         *((uint32_t *)value) = mclk;
8004                         *size = 4;
8005                         return 0;
8006                 }
8007                 return -EINVAL;
8008         case AMDGPU_PP_SENSOR_GPU_TEMP:
8009                 *((uint32_t *)value) = si_dpm_get_temp(adev);
8010                 *size = 4;
8011                 return 0;
8012         default:
8013                 return -EINVAL;
8014         }
8015 }
8016
8017 const struct amd_ip_funcs si_dpm_ip_funcs = {
8018         .name = "si_dpm",
8019         .early_init = si_dpm_early_init,
8020         .late_init = si_dpm_late_init,
8021         .sw_init = si_dpm_sw_init,
8022         .sw_fini = si_dpm_sw_fini,
8023         .hw_init = si_dpm_hw_init,
8024         .hw_fini = si_dpm_hw_fini,
8025         .suspend = si_dpm_suspend,
8026         .resume = si_dpm_resume,
8027         .is_idle = si_dpm_is_idle,
8028         .wait_for_idle = si_dpm_wait_for_idle,
8029         .soft_reset = si_dpm_soft_reset,
8030         .set_clockgating_state = si_dpm_set_clockgating_state,
8031         .set_powergating_state = si_dpm_set_powergating_state,
8032 };
8033
8034 const struct amd_pm_funcs si_dpm_funcs = {
8035         .get_temperature = &si_dpm_get_temp,
8036         .pre_set_power_state = &si_dpm_pre_set_power_state,
8037         .set_power_state = &si_dpm_set_power_state,
8038         .post_set_power_state = &si_dpm_post_set_power_state,
8039         .display_configuration_changed = &si_dpm_display_configuration_changed,
8040         .get_sclk = &si_dpm_get_sclk,
8041         .get_mclk = &si_dpm_get_mclk,
8042         .print_power_state = &si_dpm_print_power_state,
8043         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8044         .force_performance_level = &si_dpm_force_performance_level,
8045         .vblank_too_short = &si_dpm_vblank_too_short,
8046         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8047         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8048         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8049         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8050         .check_state_equal = &si_check_state_equal,
8051         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8052         .read_sensor = &si_dpm_read_sensor,
8053 };
8054
8055 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8056         .set = si_dpm_set_interrupt_state,
8057         .process = si_dpm_process_interrupt,
8058 };
8059
8060 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8061 {
8062         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8063         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8064 }
8065