1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
5 * DOC: Broadcom V3D Graphics Driver
7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
8 * For V3D 2.x support, see the VC4 driver.
10 * The V3D GPU includes a tiled render (composed of a bin and render
11 * pipelines), the TFU (texture formatting unit), and the CSD (compute
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/dma-mapping.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched/clock.h>
23 #include <linux/reset.h>
25 #include <drm/drm_drv.h>
26 #include <drm/drm_managed.h>
27 #include <uapi/drm/v3d_drm.h>
32 #define DRIVER_NAME "v3d"
33 #define DRIVER_DESC "Broadcom V3D graphics"
34 #define DRIVER_DATE "20180419"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
40 struct drm_file *file_priv)
42 struct v3d_dev *v3d = to_v3d_dev(dev);
43 struct drm_v3d_get_param *args = data;
44 static const u32 reg_map[] = {
45 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
46 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
47 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
48 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
49 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
50 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
51 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
57 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
58 * to explicitly allow it in the "the register in our
59 * parameter map" check.
61 if (args->param < ARRAY_SIZE(reg_map) &&
62 (reg_map[args->param] ||
63 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
64 u32 offset = reg_map[args->param];
69 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
70 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
71 args->value = V3D_CORE_READ(0, offset);
73 args->value = V3D_READ(offset);
78 switch (args->param) {
79 case DRM_V3D_PARAM_SUPPORTS_TFU:
82 case DRM_V3D_PARAM_SUPPORTS_CSD:
83 args->value = v3d_has_csd(v3d);
85 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
88 case DRM_V3D_PARAM_SUPPORTS_PERFMON:
89 args->value = (v3d->ver >= 40);
91 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
94 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:
98 DRM_DEBUG("Unknown parameter %d\n", args->param);
104 v3d_open(struct drm_device *dev, struct drm_file *file)
106 struct v3d_dev *v3d = to_v3d_dev(dev);
107 struct v3d_file_priv *v3d_priv;
108 struct drm_gpu_scheduler *sched;
111 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
117 for (i = 0; i < V3D_MAX_QUEUES; i++) {
118 sched = &v3d->queue[i].sched;
119 drm_sched_entity_init(&v3d_priv->sched_entity[i],
120 DRM_SCHED_PRIORITY_NORMAL, &sched,
123 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i]));
124 seqcount_init(&v3d_priv->stats[i].lock);
127 v3d_perfmon_open_file(v3d_priv);
128 file->driver_priv = v3d_priv;
134 v3d_postclose(struct drm_device *dev, struct drm_file *file)
136 struct v3d_file_priv *v3d_priv = file->driver_priv;
139 for (q = 0; q < V3D_MAX_QUEUES; q++)
140 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
142 v3d_perfmon_close_file(v3d_priv);
146 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp,
147 u64 *active_runtime, u64 *jobs_completed)
152 seq = read_seqcount_begin(&stats->lock);
153 *active_runtime = stats->enabled_ns;
155 *active_runtime += timestamp - stats->start_ns;
156 *jobs_completed = stats->jobs_completed;
157 } while (read_seqcount_retry(&stats->lock, seq));
160 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file)
162 struct v3d_file_priv *file_priv = file->driver_priv;
163 u64 timestamp = local_clock();
164 enum v3d_queue queue;
166 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) {
167 struct v3d_stats *stats = &file_priv->stats[queue];
168 u64 active_runtime, jobs_completed;
170 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed);
172 /* Note that, in case of a GPU reset, the time spent during an
173 * attempt of executing the job is not computed in the runtime.
175 drm_printf(p, "drm-engine-%s: \t%llu ns\n",
176 v3d_queue_to_string(queue), active_runtime);
178 /* Note that we only count jobs that completed. Therefore, jobs
179 * that were resubmitted due to a GPU reset are not computed.
181 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n",
182 v3d_queue_to_string(queue), jobs_completed);
186 static const struct file_operations v3d_drm_fops = {
187 .owner = THIS_MODULE,
189 .show_fdinfo = drm_show_fdinfo,
192 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
193 * protection between clients. Note that render nodes would be
194 * able to submit CLs that could access BOs from clients authenticated
195 * with the master node. The TFU doesn't use the GMP, so it would
196 * need to stay DRM_AUTH until we do buffer size/offset validation.
198 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
199 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
200 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
201 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
202 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
203 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
204 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
205 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
206 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
207 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
208 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
209 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
210 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
213 static const struct drm_driver v3d_drm_driver = {
214 .driver_features = (DRIVER_GEM |
219 .postclose = v3d_postclose,
221 #if defined(CONFIG_DEBUG_FS)
222 .debugfs_init = v3d_debugfs_init,
225 .gem_create_object = v3d_create_object,
226 .gem_prime_import_sg_table = v3d_prime_import_sg_table,
228 .ioctls = v3d_drm_ioctls,
229 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
230 .fops = &v3d_drm_fops,
231 .show_fdinfo = v3d_show_fdinfo,
236 .major = DRIVER_MAJOR,
237 .minor = DRIVER_MINOR,
238 .patchlevel = DRIVER_PATCHLEVEL,
241 static const struct of_device_id v3d_of_match[] = {
242 { .compatible = "brcm,2711-v3d" },
243 { .compatible = "brcm,2712-v3d" },
244 { .compatible = "brcm,7268-v3d" },
245 { .compatible = "brcm,7278-v3d" },
248 MODULE_DEVICE_TABLE(of, v3d_of_match);
251 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
253 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
254 return PTR_ERR_OR_ZERO(*regs);
257 static int v3d_platform_drm_probe(struct platform_device *pdev)
259 struct device *dev = &pdev->dev;
260 struct drm_device *drm;
267 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
273 platform_set_drvdata(pdev, drm);
275 ret = map_regs(v3d, &v3d->hub_regs, "hub");
279 ret = map_regs(v3d, &v3d->core_regs[0], "core0");
283 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
284 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
285 ret = dma_set_mask_and_coherent(dev, mask);
289 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
291 ident1 = V3D_READ(V3D_HUB_IDENT1);
292 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
293 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
294 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
295 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
297 v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
298 if (IS_ERR(v3d->reset)) {
299 ret = PTR_ERR(v3d->reset);
301 if (ret == -EPROBE_DEFER)
305 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
308 "Failed to get reset control or bridge regs\n");
314 ret = map_regs(v3d, &v3d->gca_regs, "gca");
319 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
320 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
321 if (!v3d->mmu_scratch) {
322 dev_err(dev, "Failed to allocate MMU scratch page\n");
326 ret = v3d_gem_init(drm);
330 ret = v3d_irq_init(v3d);
334 ret = drm_dev_register(drm, 0);
338 ret = v3d_sysfs_init(dev);
345 drm_dev_unregister(drm);
347 v3d_irq_disable(v3d);
349 v3d_gem_destroy(drm);
351 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
355 static void v3d_platform_drm_remove(struct platform_device *pdev)
357 struct drm_device *drm = platform_get_drvdata(pdev);
358 struct v3d_dev *v3d = to_v3d_dev(drm);
359 struct device *dev = &pdev->dev;
361 v3d_sysfs_destroy(dev);
363 drm_dev_unregister(drm);
365 v3d_gem_destroy(drm);
367 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
368 v3d->mmu_scratch_paddr);
371 static struct platform_driver v3d_platform_driver = {
372 .probe = v3d_platform_drm_probe,
373 .remove_new = v3d_platform_drm_remove,
376 .of_match_table = v3d_of_match,
380 module_platform_driver(v3d_platform_driver);
382 MODULE_ALIAS("platform:v3d-drm");
383 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
385 MODULE_LICENSE("GPL v2");