drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_4.h"
  26 #include "amdgpu_ras.h"
  27
  28 #include "nbio/nbio_7_4_offset.h"
  29 #include "nbio/nbio_7_4_sh_mask.h"
  30 #include "nbio/nbio_7_4_0_smn.h"
  31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  32 #include <uapi/linux/kfd_ioctl.h>
  33
  34 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
  35
  36 /*
  37  * These are nbio v7_4_1 registers mask. Temporarily define these here since
  38  * nbio v7_4_1 header is incomplete.
  39  */
  40 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK      0x00001000L
  41 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK      0x00002000L
  42 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK      0x00004000L
  43 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK      0x00008000L
  44 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK      0x00010000L
  45 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK      0x00020000L
  46
  47 #define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
  48 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
  49 //BIF_MMSCH1_DOORBELL_RANGE
  50 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
  51 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
  52 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
  53 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
  54
  55 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
  56                                         void *ras_error_status);
  57
  58 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
  59 {
  60         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
  61                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
  62         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
  63                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
  64 }
  65
  66 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
  67 {
  68         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  69
  70         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  71         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  72
  73         return tmp;
  74 }
  75
  76 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
  77 {
  78         if (enable)
  79                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  80                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  81         else
  82                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  83 }
  84
  85 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
  86 {
  87         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  88 }
  89
  90 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  91                         bool use_doorbell, int doorbell_index, int doorbell_size)
  92 {
  93         u32 reg, doorbell_range;
  94
  95         if (instance < 2)
  96                 reg = instance +
  97                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
  98         else
  99                 /*
 100                  * These registers address of SDMA2~7 is not consecutive
 101                  * from SDMA0~1. Need plus 4 dwords offset.
 102                  *
 103                  *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
 104                  *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
 105                  *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
 106                  */
 107                 reg = instance + 0x4 +
 108                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 109
 110         doorbell_range = RREG32(reg);
 111
 112         if (use_doorbell) {
 113                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
 114                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
 115         } else
 116                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 117
 118         WREG32(reg, doorbell_range);
 119 }
 120
 121 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
 122                                          int doorbell_index, int instance)
 123 {
 124         u32 reg;
 125         u32 doorbell_range;
 126
 127         if (instance)
 128                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
 129         else
 130                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
 131
 132         doorbell_range = RREG32(reg);
 133
 134         if (use_doorbell) {
 135                 doorbell_range = REG_SET_FIELD(doorbell_range,
 136                                                BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
 137                                                doorbell_index);
 138                 doorbell_range = REG_SET_FIELD(doorbell_range,
 139                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
 140         } else
 141                 doorbell_range = REG_SET_FIELD(doorbell_range,
 142                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
 143
 144         WREG32(reg, doorbell_range);
 145 }
 146
 147 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
 148                                                bool enable)
 149 {
 150         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 151 }
 152
 153 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 154                                                         bool enable)
 155 {
 156         u32 tmp = 0;
 157
 158         if (enable) {
 159                 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 160                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 161                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 162
 163                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
 164                              lower_32_bits(adev->doorbell.base));
 165                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 166                              upper_32_bits(adev->doorbell.base));
 167         }
 168
 169         WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 170 }
 171
 172 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
 173                                         bool use_doorbell, int doorbell_index)
 174 {
 175         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 176
 177         if (use_doorbell) {
 178                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 179                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
 180         } else
 181                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 182
 183         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 184 }
 185
 186
 187 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 188                                                        bool enable)
 189 {
 190         //TODO: Add support for v7.4
 191 }
 192
 193 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 194                                                       bool enable)
 195 {
 196         uint32_t def, data;
 197
 198         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 199         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 200                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 201                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 202                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 203         } else {
 204                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 205                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 206                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 207         }
 208
 209         if (def != data)
 210                 WREG32_PCIE(smnPCIE_CNTL2, data);
 211 }
 212
 213 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
 214                                             u32 *flags)
 215 {
 216         int data;
 217
 218         /* AMD_CG_SUPPORT_BIF_MGCG */
 219         data = RREG32_PCIE(smnCPM_CONTROL);
 220         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 221                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 222
 223         /* AMD_CG_SUPPORT_BIF_LS */
 224         data = RREG32_PCIE(smnPCIE_CNTL2);
 225         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 226                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 227 }
 228
 229 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
 230 {
 231         u32 interrupt_cntl;
 232
 233         /* setup interrupt control */
 234         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 235         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 236         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 237          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 238          */
 239         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 240         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 241         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 242         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 243 }
 244
 245 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 246 {
 247         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 248 }
 249
 250 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 251 {
 252         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 253 }
 254
 255 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
 256 {
 257         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 258 }
 259
 260 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 261 {
 262         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 263 }
 264
 265 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
 266         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 267         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 268         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 269         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 270         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 271         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 272         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 273         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 274         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 275         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 276         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 277         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 278         .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
 279         .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
 280         .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
 281         .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
 282         .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
 283         .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
 284 };
 285
 286 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 287 {
 288
 289 }
 290
 291 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
 292 {
 293         uint32_t bif_doorbell_intr_cntl;
 294         struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
 295         struct ras_err_data err_data = {0, 0, 0, NULL};
 296         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 297
 298         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 299         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 300                 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
 301                 /* driver has to clear the interrupt status when bif ring is disabled */
 302                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 303                                                 BIF_DOORBELL_INT_CNTL,
 304                                                 RAS_CNTLR_INTERRUPT_CLEAR, 1);
 305                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 306
 307                 if (!ras->disable_ras_err_cnt_harvest) {
 308                         /*
 309                          * clear error status after ras_controller_intr
 310                          * according to hw team and count ue number
 311                          * for query
 312                          */
 313                         nbio_v7_4_query_ras_error_count(adev, &err_data);
 314
 315                         /* logging on error cnt and printing for awareness */
 316                         obj->err_data.ue_count += err_data.ue_count;
 317                         obj->err_data.ce_count += err_data.ce_count;
 318
 319                         if (err_data.ce_count)
 320                                 dev_info(adev->dev, "%ld correctable hardware "
 321                                                 "errors detected in %s block, "
 322                                                 "no user action is needed.\n",
 323                                                 obj->err_data.ce_count,
 324                                                 adev->nbio.ras_if->name);
 325
 326                         if (err_data.ue_count)
 327                                 dev_info(adev->dev, "%ld uncorrectable hardware "
 328                                                 "errors detected in %s block\n",
 329                                                 obj->err_data.ue_count,
 330                                                 adev->nbio.ras_if->name);
 331                 }
 332
 333                 dev_info(adev->dev, "RAS controller interrupt triggered "
 334                                         "by NBIF error\n");
 335
 336                 /* ras_controller_int is dedicated for nbif ras error,
 337                  * not the global interrupt for sync flood
 338                  */
 339                 amdgpu_ras_reset_gpu(adev);
 340         }
 341 }
 342
 343 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
 344 {
 345         uint32_t bif_doorbell_intr_cntl;
 346
 347         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 348         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 349                 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
 350                 /* driver has to clear the interrupt status when bif ring is disabled */
 351                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 352                                                 BIF_DOORBELL_INT_CNTL,
 353                                                 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
 354                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 355
 356                 amdgpu_ras_global_ras_isr(adev);
 357         }
 358 }
 359
 360
 361 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
 362                                                   struct amdgpu_irq_src *src,
 363                                                   unsigned type,
 364                                                   enum amdgpu_interrupt_state state)
 365 {
 366         /* The ras_controller_irq enablement should be done in psp bl when it
 367          * tries to enable ras feature. Driver only need to set the correct interrupt
 368          * vector for bare-metal and sriov use case respectively
 369          */
 370         uint32_t bif_intr_cntl;
 371
 372         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 373         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 374                 /* set interrupt vector select bit to 0 to select
 375                  * vetcor 1 for bare metal case */
 376                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 377                                               BIF_INTR_CNTL,
 378                                               RAS_INTR_VEC_SEL, 0);
 379                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
 386                                                 struct amdgpu_irq_src *source,
 387                                                 struct amdgpu_iv_entry *entry)
 388 {
 389         /* By design, the ih cookie for ras_controller_irq should be written
 390          * to BIFring instead of general iv ring. However, due to known bif ring
 391          * hw bug, it has to be disabled. There is no chance the process function
 392          * will be involked. Just left it as a dummy one.
 393          */
 394         return 0;
 395 }
 396
 397 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
 398                                                        struct amdgpu_irq_src *src,
 399                                                        unsigned type,
 400                                                        enum amdgpu_interrupt_state state)
 401 {
 402         /* The ras_controller_irq enablement should be done in psp bl when it
 403          * tries to enable ras feature. Driver only need to set the correct interrupt
 404          * vector for bare-metal and sriov use case respectively
 405          */
 406         uint32_t bif_intr_cntl;
 407
 408         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 409         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 410                 /* set interrupt vector select bit to 0 to select
 411                  * vetcor 1 for bare metal case */
 412                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 413                                               BIF_INTR_CNTL,
 414                                               RAS_INTR_VEC_SEL, 0);
 415                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
 422                                                  struct amdgpu_irq_src *source,
 423                                                  struct amdgpu_iv_entry *entry)
 424 {
 425         /* By design, the ih cookie for err_event_athub_irq should be written
 426          * to BIFring instead of general iv ring. However, due to known bif ring
 427          * hw bug, it has to be disabled. There is no chance the process function
 428          * will be involked. Just left it as a dummy one.
 429          */
 430         return 0;
 431 }
 432
 433 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
 434         .set = nbio_v7_4_set_ras_controller_irq_state,
 435         .process = nbio_v7_4_process_ras_controller_irq,
 436 };
 437
 438 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
 439         .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
 440         .process = nbio_v7_4_process_err_event_athub_irq,
 441 };
 442
 443 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
 444 {
 445         int r;
 446
 447         /* init the irq funcs */
 448         adev->nbio.ras_controller_irq.funcs =
 449                 &nbio_v7_4_ras_controller_irq_funcs;
 450         adev->nbio.ras_controller_irq.num_types = 1;
 451
 452         /* register ras controller interrupt */
 453         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 454                               NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
 455                               &adev->nbio.ras_controller_irq);
 456
 457         return r;
 458 }
 459
 460 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
 461 {
 462
 463         int r;
 464
 465         /* init the irq funcs */
 466         adev->nbio.ras_err_event_athub_irq.funcs =
 467                 &nbio_v7_4_ras_err_event_athub_irq_funcs;
 468         adev->nbio.ras_err_event_athub_irq.num_types = 1;
 469
 470         /* register ras err event athub interrupt */
 471         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 472                               NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
 473                               &adev->nbio.ras_err_event_athub_irq);
 474
 475         return r;
 476 }
 477
 478 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2      0x13a20030
 479
 480 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
 481                                         void *ras_error_status)
 482 {
 483         uint32_t global_sts, central_sts, int_eoi, parity_sts;
 484         uint32_t corr, fatal, non_fatal;
 485         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 486
 487         global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
 488         corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
 489         fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
 490         non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
 491                                 ParityErrNonFatal);
 492         parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
 493
 494         if (corr)
 495                 err_data->ce_count++;
 496         if (fatal)
 497                 err_data->ue_count++;
 498
 499         if (corr || fatal || non_fatal) {
 500                 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
 501                 /* clear error status register */
 502                 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
 503
 504                 if (fatal)
 505                         /* clear parity fatal error indication field */
 506                         WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
 507                                     parity_sts);
 508
 509                 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
 510                                 BIFL_RasContller_Intr_Recv)) {
 511                         /* clear interrupt status register */
 512                         WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
 513                         int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
 514                         int_eoi = REG_SET_FIELD(int_eoi,
 515                                         IOHC_INTERRUPT_EOI, SMI_EOI, 1);
 516                         WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
 517                 }
 518         }
 519 }
 520
 521 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
 522                                                 bool enable)
 523 {
 524         WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
 525                        DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
 526 }
 527
 528 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 529         .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 530         .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
 531         .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
 532         .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
 533         .get_rev_id = nbio_v7_4_get_rev_id,
 534         .mc_access_enable = nbio_v7_4_mc_access_enable,
 535         .get_memsize = nbio_v7_4_get_memsize,
 536         .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
 537         .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
 538         .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
 539         .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
 540         .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
 541         .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
 542         .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
 543         .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
 544         .get_clockgating_state = nbio_v7_4_get_clockgating_state,
 545         .ih_control = nbio_v7_4_ih_control,
 546         .init_registers = nbio_v7_4_init_registers,
 547         .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 548         .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
 549         .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
 550         .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
 551         .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
 552         .query_ras_error_count = nbio_v7_4_query_ras_error_count,
 553         .ras_late_init = amdgpu_nbio_ras_late_init,
 554 };