2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/cec.h>
33 #include <linux/hdmi.h>
34 #include <linux/i2c.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <drm/drm_displayid.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_edid.h>
44 #include <drm/drm_encoder.h>
45 #include <drm/drm_print.h>
47 #include "drm_crtc_internal.h"
49 static int oui(u8 first, u8 second, u8 third)
51 return (first << 16) | (second << 8) | third;
54 #define EDID_EST_TIMINGS 16
55 #define EDID_STD_TIMINGS 8
56 #define EDID_DETAILED_TIMINGS 4
59 * EDID blocks out in the wild have a variety of bugs, try to collect
60 * them here (note that userspace may work around broken monitors first,
61 * but fixes should make their way here so that the kernel "just works"
62 * on as many displays as possible).
65 /* First detailed mode wrong, use largest 60Hz mode */
66 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
67 /* Reported 135MHz pixel clock is too high, needs adjustment */
68 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
69 /* Prefer the largest mode at 75 Hz */
70 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
71 /* Detail timing is in cm not mm */
72 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
73 /* Detailed timing descriptors have bogus size values, so just take the
74 * maximum size and use that.
76 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
77 /* use +hsync +vsync for detailed mode */
78 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
79 /* Force reduced-blanking timings for detailed modes */
80 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
82 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
84 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
86 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
88 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
89 /* Non desktop display (i.e. HMD) */
90 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 /* Cap the DSC target bitrate to 15bpp */
92 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
94 #define MICROSOFT_IEEE_OUI 0xca125c
96 struct detailed_mode_closure {
97 struct drm_connector *connector;
98 const struct drm_edid *drm_edid;
108 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
110 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
115 static const struct edid_quirk {
118 } edid_quirk_list[] = {
120 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
122 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
124 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
125 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
142 /* Belinea 10 15 55 */
143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
146 /* Envision Peripherals, Inc. EN-7100e */
147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
148 /* Envision EN2028 */
149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
151 /* Funai Electronics PM36B */
152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
153 EDID_QUIRK_DETAILED_IN_CM),
156 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
159 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
161 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
162 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
164 /* LG Philips LCD LP154W01-A5 */
165 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
166 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
168 /* Samsung SyncMaster 205BW. Note: irony */
169 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
170 /* Samsung SyncMaster 22[5-6]BW */
171 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
172 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
174 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
175 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
177 /* ViewSonic VA2026w */
178 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
180 /* Medion MD 30217 PG */
181 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
184 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
186 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
187 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
189 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
190 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
192 /* Valve Index Headset */
193 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
211 /* HTC Vive and Vive Pro VR Headsets */
212 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
215 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
216 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
221 /* Windows Mixed Reality Headsets */
222 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
227 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
229 /* Sony PlayStation VR Headset */
230 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
232 /* Sensics VR Headsets */
233 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
235 /* OSVR HDK and HDK2 VR Headsets */
236 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
241 * Autogenerated from the DMT spec.
242 * This table is copied from xfree86/modes/xf86EdidModes.c.
244 static const struct drm_display_mode drm_dmt_modes[] = {
245 /* 0x01 - 640x350@85Hz */
246 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
247 736, 832, 0, 350, 382, 385, 445, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x02 - 640x400@85Hz */
250 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
251 736, 832, 0, 400, 401, 404, 445, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x03 - 720x400@85Hz */
254 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
255 828, 936, 0, 400, 401, 404, 446, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x04 - 640x480@60Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
259 752, 800, 0, 480, 490, 492, 525, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x05 - 640x480@72Hz */
262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
263 704, 832, 0, 480, 489, 492, 520, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x06 - 640x480@75Hz */
266 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
267 720, 840, 0, 480, 481, 484, 500, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
269 /* 0x07 - 640x480@85Hz */
270 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
271 752, 832, 0, 480, 481, 484, 509, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 0x08 - 800x600@56Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
275 896, 1024, 0, 600, 601, 603, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x09 - 800x600@60Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
279 968, 1056, 0, 600, 601, 605, 628, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0a - 800x600@72Hz */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
283 976, 1040, 0, 600, 637, 643, 666, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x0b - 800x600@75Hz */
286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
287 896, 1056, 0, 600, 601, 604, 625, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0c - 800x600@85Hz */
290 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
291 896, 1048, 0, 600, 601, 604, 631, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 0x0d - 800x600@120Hz RB */
294 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
295 880, 960, 0, 600, 603, 607, 636, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
297 /* 0x0e - 848x480@60Hz */
298 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
299 976, 1088, 0, 480, 486, 494, 517, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x0f - 1024x768@43Hz, interlace */
302 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
303 1208, 1264, 0, 768, 768, 776, 817, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
305 DRM_MODE_FLAG_INTERLACE) },
306 /* 0x10 - 1024x768@60Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
308 1184, 1344, 0, 768, 771, 777, 806, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x11 - 1024x768@70Hz */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
312 1184, 1328, 0, 768, 771, 777, 806, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x12 - 1024x768@75Hz */
315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
316 1136, 1312, 0, 768, 769, 772, 800, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x13 - 1024x768@85Hz */
319 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
320 1168, 1376, 0, 768, 769, 772, 808, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x14 - 1024x768@120Hz RB */
323 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
324 1104, 1184, 0, 768, 771, 775, 813, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x15 - 1152x864@75Hz */
327 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
328 1344, 1600, 0, 864, 865, 868, 900, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x55 - 1280x720@60Hz */
331 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
332 1430, 1650, 0, 720, 725, 730, 750, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x16 - 1280x768@60Hz RB */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
336 1360, 1440, 0, 768, 771, 778, 790, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x17 - 1280x768@60Hz */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
340 1472, 1664, 0, 768, 771, 778, 798, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x18 - 1280x768@75Hz */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
344 1488, 1696, 0, 768, 771, 778, 805, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x19 - 1280x768@85Hz */
347 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
348 1496, 1712, 0, 768, 771, 778, 809, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1a - 1280x768@120Hz RB */
351 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
352 1360, 1440, 0, 768, 771, 778, 813, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x1b - 1280x800@60Hz RB */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
356 1360, 1440, 0, 800, 803, 809, 823, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 0x1c - 1280x800@60Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
360 1480, 1680, 0, 800, 803, 809, 831, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x1d - 1280x800@75Hz */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
364 1488, 1696, 0, 800, 803, 809, 838, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x1e - 1280x800@85Hz */
367 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
368 1496, 1712, 0, 800, 803, 809, 843, 0,
369 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x1f - 1280x800@120Hz RB */
371 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
372 1360, 1440, 0, 800, 803, 809, 847, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x20 - 1280x960@60Hz */
375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
376 1488, 1800, 0, 960, 961, 964, 1000, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x21 - 1280x960@85Hz */
379 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
380 1504, 1728, 0, 960, 961, 964, 1011, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x22 - 1280x960@120Hz RB */
383 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
384 1360, 1440, 0, 960, 963, 967, 1017, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x23 - 1280x1024@60Hz */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
388 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x24 - 1280x1024@75Hz */
391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
392 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x25 - 1280x1024@85Hz */
395 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
396 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x26 - 1280x1024@120Hz RB */
399 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
400 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x27 - 1360x768@60Hz */
403 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
404 1536, 1792, 0, 768, 771, 777, 795, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x28 - 1360x768@120Hz RB */
407 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
408 1440, 1520, 0, 768, 771, 776, 813, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x51 - 1366x768@60Hz */
411 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
412 1579, 1792, 0, 768, 771, 774, 798, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x56 - 1366x768@60Hz */
415 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
416 1436, 1500, 0, 768, 769, 772, 800, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x29 - 1400x1050@60Hz RB */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
420 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2a - 1400x1050@60Hz */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
424 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x2b - 1400x1050@75Hz */
427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
428 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x2c - 1400x1050@85Hz */
431 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
432 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x2d - 1400x1050@120Hz RB */
435 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
436 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x2e - 1440x900@60Hz RB */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
440 1520, 1600, 0, 900, 903, 909, 926, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
442 /* 0x2f - 1440x900@60Hz */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
444 1672, 1904, 0, 900, 903, 909, 934, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x30 - 1440x900@75Hz */
447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
448 1688, 1936, 0, 900, 903, 909, 942, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x31 - 1440x900@85Hz */
451 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
452 1696, 1952, 0, 900, 903, 909, 948, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x32 - 1440x900@120Hz RB */
455 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
456 1520, 1600, 0, 900, 903, 909, 953, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
458 /* 0x53 - 1600x900@60Hz */
459 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
460 1704, 1800, 0, 900, 901, 904, 1000, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x33 - 1600x1200@60Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x34 - 1600x1200@65Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x35 - 1600x1200@70Hz */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x36 - 1600x1200@75Hz */
475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
476 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x37 - 1600x1200@85Hz */
479 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
480 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x38 - 1600x1200@120Hz RB */
483 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
484 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x39 - 1680x1050@60Hz RB */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
488 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x3a - 1680x1050@60Hz */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
492 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x3b - 1680x1050@75Hz */
495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
496 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3c - 1680x1050@85Hz */
499 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
500 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x3d - 1680x1050@120Hz RB */
503 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
504 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x3e - 1792x1344@60Hz */
507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
508 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x3f - 1792x1344@75Hz */
511 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
512 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x40 - 1792x1344@120Hz RB */
515 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
516 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x41 - 1856x1392@60Hz */
519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
520 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x42 - 1856x1392@75Hz */
523 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
524 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x43 - 1856x1392@120Hz RB */
527 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
528 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x52 - 1920x1080@60Hz */
531 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
532 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x44 - 1920x1200@60Hz RB */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
536 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
538 /* 0x45 - 1920x1200@60Hz */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
540 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x46 - 1920x1200@75Hz */
543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
544 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x47 - 1920x1200@85Hz */
547 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
548 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x48 - 1920x1200@120Hz RB */
551 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
552 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x49 - 1920x1440@60Hz */
555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
556 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4a - 1920x1440@75Hz */
559 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
560 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4b - 1920x1440@120Hz RB */
563 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
564 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566 /* 0x54 - 2048x1152@60Hz */
567 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
568 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4c - 2560x1600@60Hz RB */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
572 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x4d - 2560x1600@60Hz */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
576 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 0x4e - 2560x1600@75Hz */
579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
580 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
582 /* 0x4f - 2560x1600@85Hz */
583 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
584 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
586 /* 0x50 - 2560x1600@120Hz RB */
587 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
588 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
590 /* 0x57 - 4096x2160@60Hz RB */
591 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
592 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
595 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
596 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 * These more or less come from the DMT spec. The 720x400 modes are
602 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
603 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
604 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
607 * The DMT modes have been fact-checked; the rest are mild guesses.
609 static const struct drm_display_mode edid_est_modes[] = {
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
611 968, 1056, 0, 600, 601, 605, 628, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
613 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
614 896, 1024, 0, 600, 601, 603, 625, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
616 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
617 720, 840, 0, 480, 481, 484, 500, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
619 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
620 704, 832, 0, 480, 489, 492, 520, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
622 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
623 768, 864, 0, 480, 483, 486, 525, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
625 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
626 752, 800, 0, 480, 490, 492, 525, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
628 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
629 846, 900, 0, 400, 421, 423, 449, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
631 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
632 846, 900, 0, 400, 412, 414, 449, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
634 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
635 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
637 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
638 1136, 1312, 0, 768, 769, 772, 800, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
640 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
641 1184, 1328, 0, 768, 771, 777, 806, 0,
642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
643 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
644 1184, 1344, 0, 768, 771, 777, 806, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
646 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
647 1208, 1264, 0, 768, 768, 776, 817, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
649 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
650 928, 1152, 0, 624, 625, 628, 667, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
652 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
653 896, 1056, 0, 600, 601, 604, 625, 0,
654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
655 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
656 976, 1040, 0, 600, 637, 643, 666, 0,
657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
658 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
659 1344, 1600, 0, 864, 865, 868, 900, 0,
660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
670 static const struct minimode est3_modes[] = {
678 { 1024, 768, 85, 0 },
679 { 1152, 864, 75, 0 },
681 { 1280, 768, 60, 1 },
682 { 1280, 768, 60, 0 },
683 { 1280, 768, 75, 0 },
684 { 1280, 768, 85, 0 },
685 { 1280, 960, 60, 0 },
686 { 1280, 960, 85, 0 },
687 { 1280, 1024, 60, 0 },
688 { 1280, 1024, 85, 0 },
690 { 1360, 768, 60, 0 },
691 { 1440, 900, 60, 1 },
692 { 1440, 900, 60, 0 },
693 { 1440, 900, 75, 0 },
694 { 1440, 900, 85, 0 },
695 { 1400, 1050, 60, 1 },
696 { 1400, 1050, 60, 0 },
697 { 1400, 1050, 75, 0 },
699 { 1400, 1050, 85, 0 },
700 { 1680, 1050, 60, 1 },
701 { 1680, 1050, 60, 0 },
702 { 1680, 1050, 75, 0 },
703 { 1680, 1050, 85, 0 },
704 { 1600, 1200, 60, 0 },
705 { 1600, 1200, 65, 0 },
706 { 1600, 1200, 70, 0 },
708 { 1600, 1200, 75, 0 },
709 { 1600, 1200, 85, 0 },
710 { 1792, 1344, 60, 0 },
711 { 1792, 1344, 75, 0 },
712 { 1856, 1392, 60, 0 },
713 { 1856, 1392, 75, 0 },
714 { 1920, 1200, 60, 1 },
715 { 1920, 1200, 60, 0 },
717 { 1920, 1200, 75, 0 },
718 { 1920, 1200, 85, 0 },
719 { 1920, 1440, 60, 0 },
720 { 1920, 1440, 75, 0 },
723 static const struct minimode extra_modes[] = {
724 { 1024, 576, 60, 0 },
725 { 1366, 768, 60, 0 },
726 { 1600, 900, 60, 0 },
727 { 1680, 945, 60, 0 },
728 { 1920, 1080, 60, 0 },
729 { 2048, 1152, 60, 0 },
730 { 2048, 1536, 60, 0 },
734 * From CEA/CTA-861 spec.
736 * Do not access directly, instead always use cea_mode_for_vic().
738 static const struct drm_display_mode edid_cea_modes_1[] = {
739 /* 1 - 640x480@60Hz 4:3 */
740 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
741 752, 800, 0, 480, 490, 492, 525, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744 /* 2 - 720x480@60Hz 4:3 */
745 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
746 798, 858, 0, 480, 489, 495, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
749 /* 3 - 720x480@60Hz 16:9 */
750 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
751 798, 858, 0, 480, 489, 495, 525, 0,
752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
753 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754 /* 4 - 1280x720@60Hz 16:9 */
755 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
756 1430, 1650, 0, 720, 725, 730, 750, 0,
757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 5 - 1920x1080i@60Hz 16:9 */
760 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
761 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
762 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
763 DRM_MODE_FLAG_INTERLACE),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 6 - 720(1440)x480i@60Hz 4:3 */
766 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 480, 488, 494, 525, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 7 - 720(1440)x480i@60Hz 16:9 */
772 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 480, 488, 494, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 8 - 720(1440)x240@60Hz 4:3 */
778 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
779 801, 858, 0, 240, 244, 247, 262, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_DBLCLK),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 9 - 720(1440)x240@60Hz 16:9 */
784 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
785 801, 858, 0, 240, 244, 247, 262, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_DBLCLK),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 10 - 2880x480i@60Hz 4:3 */
790 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 480, 488, 494, 525, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
793 DRM_MODE_FLAG_INTERLACE),
794 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 11 - 2880x480i@60Hz 16:9 */
796 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
797 3204, 3432, 0, 480, 488, 494, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
799 DRM_MODE_FLAG_INTERLACE),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 12 - 2880x240@60Hz 4:3 */
802 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
803 3204, 3432, 0, 240, 244, 247, 262, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 13 - 2880x240@60Hz 16:9 */
807 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 240, 244, 247, 262, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811 /* 14 - 1440x480@60Hz 4:3 */
812 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
813 1596, 1716, 0, 480, 489, 495, 525, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
816 /* 15 - 1440x480@60Hz 16:9 */
817 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
818 1596, 1716, 0, 480, 489, 495, 525, 0,
819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 16 - 1920x1080@60Hz 16:9 */
822 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
823 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 17 - 720x576@50Hz 4:3 */
827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
828 796, 864, 0, 576, 581, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
831 /* 18 - 720x576@50Hz 16:9 */
832 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
833 796, 864, 0, 576, 581, 586, 625, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
836 /* 19 - 1280x720@50Hz 16:9 */
837 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
838 1760, 1980, 0, 720, 725, 730, 750, 0,
839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 20 - 1920x1080i@50Hz 16:9 */
842 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
843 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
845 DRM_MODE_FLAG_INTERLACE),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 21 - 720(1440)x576i@50Hz 4:3 */
848 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 576, 580, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 22 - 720(1440)x576i@50Hz 16:9 */
854 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 576, 580, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 23 - 720(1440)x288@50Hz 4:3 */
860 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
861 795, 864, 0, 288, 290, 293, 312, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_DBLCLK),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 24 - 720(1440)x288@50Hz 16:9 */
866 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
867 795, 864, 0, 288, 290, 293, 312, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_DBLCLK),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 25 - 2880x576i@50Hz 4:3 */
872 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 576, 580, 586, 625, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
875 DRM_MODE_FLAG_INTERLACE),
876 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 26 - 2880x576i@50Hz 16:9 */
878 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
879 3180, 3456, 0, 576, 580, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
881 DRM_MODE_FLAG_INTERLACE),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 27 - 2880x288@50Hz 4:3 */
884 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
885 3180, 3456, 0, 288, 290, 293, 312, 0,
886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 28 - 2880x288@50Hz 16:9 */
889 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 288, 290, 293, 312, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 29 - 1440x576@50Hz 4:3 */
894 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
895 1592, 1728, 0, 576, 581, 586, 625, 0,
896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
898 /* 30 - 1440x576@50Hz 16:9 */
899 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
900 1592, 1728, 0, 576, 581, 586, 625, 0,
901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 31 - 1920x1080@50Hz 16:9 */
904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
905 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 32 - 1920x1080@24Hz 16:9 */
909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
910 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 33 - 1920x1080@25Hz 16:9 */
914 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
915 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 34 - 1920x1080@30Hz 16:9 */
919 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
920 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 35 - 2880x480@60Hz 4:3 */
924 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
925 3192, 3432, 0, 480, 489, 495, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 36 - 2880x480@60Hz 16:9 */
929 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
930 3192, 3432, 0, 480, 489, 495, 525, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 37 - 2880x576@50Hz 4:3 */
934 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
935 3184, 3456, 0, 576, 581, 586, 625, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
938 /* 38 - 2880x576@50Hz 16:9 */
939 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
940 3184, 3456, 0, 576, 581, 586, 625, 0,
941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 39 - 1920x1080i@50Hz 16:9 */
944 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
945 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 40 - 1920x1080i@100Hz 16:9 */
950 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
951 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
953 DRM_MODE_FLAG_INTERLACE),
954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 41 - 1280x720@100Hz 16:9 */
956 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
957 1760, 1980, 0, 720, 725, 730, 750, 0,
958 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 42 - 720x576@100Hz 4:3 */
961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
965 /* 43 - 720x576@100Hz 16:9 */
966 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
967 796, 864, 0, 576, 581, 586, 625, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 44 - 720(1440)x576i@100Hz 4:3 */
971 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
972 795, 864, 0, 576, 580, 586, 625, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
974 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 45 - 720(1440)x576i@100Hz 16:9 */
977 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
978 795, 864, 0, 576, 580, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
980 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 46 - 1920x1080i@120Hz 16:9 */
983 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
984 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
986 DRM_MODE_FLAG_INTERLACE),
987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 47 - 1280x720@120Hz 16:9 */
989 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
990 1430, 1650, 0, 720, 725, 730, 750, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 48 - 720x480@120Hz 4:3 */
994 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
995 798, 858, 0, 480, 489, 495, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
997 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
998 /* 49 - 720x480@120Hz 16:9 */
999 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1000 798, 858, 0, 480, 489, 495, 525, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 50 - 720(1440)x480i@120Hz 4:3 */
1004 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1005 801, 858, 0, 480, 488, 494, 525, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1007 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 51 - 720(1440)x480i@120Hz 16:9 */
1010 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1011 801, 858, 0, 480, 488, 494, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1013 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1014 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1015 /* 52 - 720x576@200Hz 4:3 */
1016 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1017 796, 864, 0, 576, 581, 586, 625, 0,
1018 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 53 - 720x576@200Hz 16:9 */
1021 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1022 796, 864, 0, 576, 581, 586, 625, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 54 - 720(1440)x576i@200Hz 4:3 */
1026 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1027 795, 864, 0, 576, 580, 586, 625, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1029 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 55 - 720(1440)x576i@200Hz 16:9 */
1032 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1033 795, 864, 0, 576, 580, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1035 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1036 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1037 /* 56 - 720x480@240Hz 4:3 */
1038 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1039 798, 858, 0, 480, 489, 495, 525, 0,
1040 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 57 - 720x480@240Hz 16:9 */
1043 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1044 798, 858, 0, 480, 489, 495, 525, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 58 - 720(1440)x480i@240Hz 4:3 */
1048 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1049 801, 858, 0, 480, 488, 494, 525, 0,
1050 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1051 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 59 - 720(1440)x480i@240Hz 16:9 */
1054 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1055 801, 858, 0, 480, 488, 494, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1057 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 60 - 1280x720@24Hz 16:9 */
1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1061 3080, 3300, 0, 720, 725, 730, 750, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 61 - 1280x720@25Hz 16:9 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1066 3740, 3960, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1069 /* 62 - 1280x720@30Hz 16:9 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1071 3080, 3300, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1074 /* 63 - 1920x1080@120Hz 16:9 */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1076 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1079 /* 64 - 1920x1080@100Hz 16:9 */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1081 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1084 /* 65 - 1280x720@24Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1086 3080, 3300, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 66 - 1280x720@25Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1091 3740, 3960, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 67 - 1280x720@30Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1096 3080, 3300, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 68 - 1280x720@50Hz 64:27 */
1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1101 1760, 1980, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 69 - 1280x720@60Hz 64:27 */
1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1106 1430, 1650, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 70 - 1280x720@100Hz 64:27 */
1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1111 1760, 1980, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 71 - 1280x720@120Hz 64:27 */
1115 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1116 1430, 1650, 0, 720, 725, 730, 750, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 72 - 1920x1080@24Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1121 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 73 - 1920x1080@25Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 74 - 1920x1080@30Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 75 - 1920x1080@50Hz 64:27 */
1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1136 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 76 - 1920x1080@60Hz 64:27 */
1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1141 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 77 - 1920x1080@100Hz 64:27 */
1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1146 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 78 - 1920x1080@120Hz 64:27 */
1150 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1151 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 79 - 1680x720@24Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1156 3080, 3300, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 80 - 1680x720@25Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1161 2948, 3168, 0, 720, 725, 730, 750, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 81 - 1680x720@30Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1166 2420, 2640, 0, 720, 725, 730, 750, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 82 - 1680x720@50Hz 64:27 */
1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1171 1980, 2200, 0, 720, 725, 730, 750, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 83 - 1680x720@60Hz 64:27 */
1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1176 1980, 2200, 0, 720, 725, 730, 750, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 84 - 1680x720@100Hz 64:27 */
1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1181 1780, 2000, 0, 720, 725, 730, 825, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 85 - 1680x720@120Hz 64:27 */
1185 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1186 1780, 2000, 0, 720, 725, 730, 825, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 86 - 2560x1080@24Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1191 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 87 - 2560x1080@25Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1196 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 88 - 2560x1080@30Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1201 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 89 - 2560x1080@50Hz 64:27 */
1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1206 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 90 - 2560x1080@60Hz 64:27 */
1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1211 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 91 - 2560x1080@100Hz 64:27 */
1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1216 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 92 - 2560x1080@120Hz 64:27 */
1220 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1221 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 93 - 3840x2160@24Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1226 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 94 - 3840x2160@25Hz 16:9 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1231 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1234 /* 95 - 3840x2160@30Hz 16:9 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1236 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1239 /* 96 - 3840x2160@50Hz 16:9 */
1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1241 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1244 /* 97 - 3840x2160@60Hz 16:9 */
1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1246 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1249 /* 98 - 4096x2160@24Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1251 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 99 - 4096x2160@25Hz 256:135 */
1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1256 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1259 /* 100 - 4096x2160@30Hz 256:135 */
1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1261 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1264 /* 101 - 4096x2160@50Hz 256:135 */
1265 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1266 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1269 /* 102 - 4096x2160@60Hz 256:135 */
1270 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1271 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1274 /* 103 - 3840x2160@24Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1276 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 104 - 3840x2160@25Hz 64:27 */
1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1281 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1284 /* 105 - 3840x2160@30Hz 64:27 */
1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1286 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 106 - 3840x2160@50Hz 64:27 */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1291 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 107 - 3840x2160@60Hz 64:27 */
1295 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1296 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1299 /* 108 - 1280x720@48Hz 16:9 */
1300 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1301 2280, 2500, 0, 720, 725, 730, 750, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1304 /* 109 - 1280x720@48Hz 64:27 */
1305 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1306 2280, 2500, 0, 720, 725, 730, 750, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 110 - 1680x720@48Hz 64:27 */
1310 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1311 2530, 2750, 0, 720, 725, 730, 750, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1314 /* 111 - 1920x1080@48Hz 16:9 */
1315 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1316 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1319 /* 112 - 1920x1080@48Hz 64:27 */
1320 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1321 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 113 - 2560x1080@48Hz 64:27 */
1325 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1326 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1329 /* 114 - 3840x2160@48Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1331 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 115 - 4096x2160@48Hz 256:135 */
1335 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1336 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1339 /* 116 - 3840x2160@48Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1341 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 117 - 3840x2160@100Hz 16:9 */
1345 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1346 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1349 /* 118 - 3840x2160@120Hz 16:9 */
1350 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1351 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1354 /* 119 - 3840x2160@100Hz 64:27 */
1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1356 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 120 - 3840x2160@120Hz 64:27 */
1360 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1361 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 121 - 5120x2160@24Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1366 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 122 - 5120x2160@25Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1371 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 123 - 5120x2160@30Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1376 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379 /* 124 - 5120x2160@48Hz 64:27 */
1380 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1381 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1384 /* 125 - 5120x2160@50Hz 64:27 */
1385 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1386 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1389 /* 126 - 5120x2160@60Hz 64:27 */
1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1391 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1394 /* 127 - 5120x2160@100Hz 64:27 */
1395 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1396 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1398 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1402 * From CEA/CTA-861 spec.
1404 * Do not access directly, instead always use cea_mode_for_vic().
1406 static const struct drm_display_mode edid_cea_modes_193[] = {
1407 /* 193 - 5120x2160@120Hz 64:27 */
1408 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1409 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1412 /* 194 - 7680x4320@24Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1414 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 195 - 7680x4320@25Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1419 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 196 - 7680x4320@30Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1424 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 197 - 7680x4320@48Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1429 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 198 - 7680x4320@50Hz 16:9 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1434 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1437 /* 199 - 7680x4320@60Hz 16:9 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1439 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1442 /* 200 - 7680x4320@100Hz 16:9 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1444 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1447 /* 201 - 7680x4320@120Hz 16:9 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1449 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1452 /* 202 - 7680x4320@24Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1454 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 203 - 7680x4320@25Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1459 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 204 - 7680x4320@30Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1464 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 205 - 7680x4320@48Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1469 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 206 - 7680x4320@50Hz 64:27 */
1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1474 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 207 - 7680x4320@60Hz 64:27 */
1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1479 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 208 - 7680x4320@100Hz 64:27 */
1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1484 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 209 - 7680x4320@120Hz 64:27 */
1488 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1489 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 210 - 10240x4320@24Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1494 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 211 - 10240x4320@25Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1499 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 212 - 10240x4320@30Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1504 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 213 - 10240x4320@48Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1509 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 214 - 10240x4320@50Hz 64:27 */
1513 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1514 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1517 /* 215 - 10240x4320@60Hz 64:27 */
1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1519 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1522 /* 216 - 10240x4320@100Hz 64:27 */
1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1524 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1527 /* 217 - 10240x4320@120Hz 64:27 */
1528 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1529 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1532 /* 218 - 4096x2160@100Hz 256:135 */
1533 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1534 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1537 /* 219 - 4096x2160@120Hz 256:135 */
1538 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1539 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1545 * HDMI 1.4 4k modes. Index using the VIC.
1547 static const struct drm_display_mode edid_4k_modes[] = {
1548 /* 0 - dummy, VICs start at 1 */
1550 /* 1 - 3840x2160@30Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 4016, 4104, 4400, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 2 - 3840x2160@25Hz */
1557 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 3840, 4896, 4984, 5280, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1562 /* 3 - 3840x2160@24Hz */
1563 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1564 3840, 5116, 5204, 5500, 0,
1565 2160, 2168, 2178, 2250, 0,
1566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1567 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1568 /* 4 - 4096x2160@24Hz (SMPTE) */
1569 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1570 4096, 5116, 5204, 5500, 0,
1571 2160, 2168, 2178, 2250, 0,
1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1573 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1576 /*** DDC fetch and block validation ***/
1579 * The opaque EDID type, internal to drm_edid.c.
1582 /* Size allocated for edid */
1584 const struct edid *edid;
1587 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1589 static int edid_hfeeodb_block_count(const struct edid *edid)
1591 int eeodb = edid_hfeeodb_extension_block_count(edid);
1593 return eeodb ? eeodb + 1 : 0;
1596 static int edid_extension_block_count(const struct edid *edid)
1598 return edid->extensions;
1601 static int edid_block_count(const struct edid *edid)
1603 return edid_extension_block_count(edid) + 1;
1606 static int edid_size_by_blocks(int num_blocks)
1608 return num_blocks * EDID_LENGTH;
1611 static int edid_size(const struct edid *edid)
1613 return edid_size_by_blocks(edid_block_count(edid));
1616 static const void *edid_block_data(const struct edid *edid, int index)
1618 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1620 return edid + index;
1623 static const void *edid_extension_block_data(const struct edid *edid, int index)
1625 return edid_block_data(edid, index + 1);
1628 /* EDID block count indicated in EDID, may exceed allocated size */
1629 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1633 /* Starting point */
1634 num_blocks = edid_block_count(drm_edid->edid);
1636 /* HF-EEODB override */
1637 if (drm_edid->size >= edid_size_by_blocks(2)) {
1641 * Note: HF-EEODB may specify a smaller extension count than the
1642 * regular one. Unlike in buffer allocation, here we can use it.
1644 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1652 /* EDID block count, limited by allocated size */
1653 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1655 /* Limit by allocated size */
1656 return min(__drm_edid_block_count(drm_edid),
1657 (int)drm_edid->size / EDID_LENGTH);
1660 /* EDID extension block count, limited by allocated size */
1661 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1663 return drm_edid_block_count(drm_edid) - 1;
1666 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1668 return edid_block_data(drm_edid->edid, index);
1671 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1674 return edid_extension_block_data(drm_edid->edid, index);
1678 * Initializer helper for legacy interfaces, where we have no choice but to
1679 * trust edid size. Not for general purpose use.
1681 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1682 const struct edid *edid)
1687 memset(drm_edid, 0, sizeof(*drm_edid));
1689 drm_edid->edid = edid;
1690 drm_edid->size = edid_size(edid);
1696 * EDID base and extension block iterator.
1698 * struct drm_edid_iter iter;
1701 * drm_edid_iter_begin(drm_edid, &iter);
1702 * drm_edid_iter_for_each(block, &iter) {
1703 * // do stuff with block
1705 * drm_edid_iter_end(&iter);
1707 struct drm_edid_iter {
1708 const struct drm_edid *drm_edid;
1710 /* Current block index. */
1714 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1715 struct drm_edid_iter *iter)
1717 memset(iter, 0, sizeof(*iter));
1719 iter->drm_edid = drm_edid;
1722 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1724 const void *block = NULL;
1726 if (!iter->drm_edid)
1729 if (iter->index < drm_edid_block_count(iter->drm_edid))
1730 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1735 #define drm_edid_iter_for_each(__block, __iter) \
1736 while (((__block) = __drm_edid_iter_next(__iter)))
1738 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1740 memset(iter, 0, sizeof(*iter));
1743 static const u8 edid_header[] = {
1744 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1747 static void edid_header_fix(void *edid)
1749 memcpy(edid, edid_header, sizeof(edid_header));
1753 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1754 * @_edid: pointer to raw base EDID block
1756 * Sanity check the header of the base EDID block.
1758 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1760 int drm_edid_header_is_valid(const void *_edid)
1762 const struct edid *edid = _edid;
1765 for (i = 0; i < sizeof(edid_header); i++) {
1766 if (edid->header[i] == edid_header[i])
1772 EXPORT_SYMBOL(drm_edid_header_is_valid);
1774 static int edid_fixup __read_mostly = 6;
1775 module_param_named(edid_fixup, edid_fixup, int, 0400);
1776 MODULE_PARM_DESC(edid_fixup,
1777 "Minimum number of valid EDID header bytes (0-8, default 6)");
1779 static int edid_block_compute_checksum(const void *_block)
1781 const u8 *block = _block;
1783 u8 csum = 0, crc = 0;
1785 for (i = 0; i < EDID_LENGTH - 1; i++)
1793 static int edid_block_get_checksum(const void *_block)
1795 const struct edid *block = _block;
1797 return block->checksum;
1800 static int edid_block_tag(const void *_block)
1802 const u8 *block = _block;
1807 static bool edid_block_is_zero(const void *edid)
1809 return !memchr_inv(edid, 0, EDID_LENGTH);
1813 * drm_edid_are_equal - compare two edid blobs.
1814 * @edid1: pointer to first blob
1815 * @edid2: pointer to second blob
1816 * This helper can be used during probing to determine if
1819 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1821 int edid1_len, edid2_len;
1822 bool edid1_present = edid1 != NULL;
1823 bool edid2_present = edid2 != NULL;
1825 if (edid1_present != edid2_present)
1829 edid1_len = edid_size(edid1);
1830 edid2_len = edid_size(edid2);
1832 if (edid1_len != edid2_len)
1835 if (memcmp(edid1, edid2, edid1_len))
1841 EXPORT_SYMBOL(drm_edid_are_equal);
1843 enum edid_block_status {
1845 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1855 static enum edid_block_status edid_block_check(const void *_block,
1858 const struct edid *block = _block;
1861 return EDID_BLOCK_NULL;
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1870 return EDID_BLOCK_HEADER_CORRUPT;
1874 return EDID_BLOCK_HEADER_REPAIR;
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1881 return EDID_BLOCK_CHECKSUM;
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1889 return EDID_BLOCK_OK;
1892 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899 static bool edid_block_valid(const void *block, bool base)
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1905 static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1952 static void edid_block_dump(const char *level, const void *block, int block_num)
1954 enum edid_block_status status;
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 sprintf(prefix, "\t[%02x] BAD ", block_num);
1963 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1970 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1971 * @_block: pointer to raw EDID block
1972 * @block_num: type of block to validate (0 for base, extension otherwise)
1973 * @print_bad_edid: if true, dump bad EDID blocks to the console
1974 * @edid_corrupt: if true, the header or checksum is invalid
1976 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * Return: True if the block is valid, false otherwise.
1981 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 struct edid *block = (struct edid *)_block;
1985 enum edid_block_status status;
1986 bool is_base_block = block_num == 0;
1989 if (WARN_ON(!block))
1992 status = edid_block_check(block, is_base_block);
1993 if (status == EDID_BLOCK_HEADER_REPAIR) {
1994 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1995 edid_header_fix(block);
1997 /* Retry with fixed header, update status if that worked. */
1998 status = edid_block_check(block, is_base_block);
1999 if (status == EDID_BLOCK_OK)
2000 status = EDID_BLOCK_HEADER_FIXED;
2005 * Unknown major version isn't corrupt but we can't use it. Only
2006 * the base block can reset edid_corrupt to false.
2008 if (is_base_block &&
2009 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2010 *edid_corrupt = false;
2011 else if (status != EDID_BLOCK_OK)
2012 *edid_corrupt = true;
2015 edid_block_status_print(status, block, block_num);
2017 /* Determine whether we can use this block with this status. */
2018 valid = edid_block_status_valid(status, edid_block_tag(block));
2020 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2021 pr_notice("Raw EDID:\n");
2022 edid_block_dump(KERN_NOTICE, block, block_num);
2027 EXPORT_SYMBOL(drm_edid_block_valid);
2030 * drm_edid_is_valid - sanity check EDID data
2033 * Sanity-check an entire EDID record (including extensions)
2035 * Return: True if the EDID data is valid, false otherwise.
2037 bool drm_edid_is_valid(struct edid *edid)
2044 for (i = 0; i < edid_block_count(edid); i++) {
2045 void *block = (void *)edid_block_data(edid, i);
2047 if (!drm_edid_block_valid(block, i, true, NULL))
2053 EXPORT_SYMBOL(drm_edid_is_valid);
2056 * drm_edid_valid - sanity check EDID data
2057 * @drm_edid: EDID data
2059 * Sanity check an EDID. Cross check block count against allocated size and
2060 * checksum the blocks.
2062 * Return: True if the EDID data is valid, false otherwise.
2064 bool drm_edid_valid(const struct drm_edid *drm_edid)
2071 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2075 const void *block = drm_edid_block_data(drm_edid, i);
2077 if (!edid_block_valid(block, i == 0))
2083 EXPORT_SYMBOL(drm_edid_valid);
2085 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2089 int i, valid_blocks = 0;
2092 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2093 * back to regular extension count here. We don't want to start
2094 * modifying the HF-EEODB extension too.
2096 for (i = 0; i < edid_block_count(edid); i++) {
2097 const void *src_block = edid_block_data(edid, i);
2099 if (edid_block_valid(src_block, i == 0)) {
2100 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2102 memmove(dst_block, src_block, EDID_LENGTH);
2107 /* We already trusted the base block to be valid here... */
2108 if (WARN_ON(!valid_blocks)) {
2113 edid->extensions = valid_blocks - 1;
2114 edid->checksum = edid_block_compute_checksum(edid);
2116 *alloc_size = edid_size_by_blocks(valid_blocks);
2118 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2125 #define DDC_SEGMENT_ADDR 0x30
2127 * drm_do_probe_ddc_edid() - get EDID information via I2C
2128 * @data: I2C device adapter
2129 * @buf: EDID data buffer to be filled
2130 * @block: 128 byte EDID block to start fetching from
2131 * @len: EDID data buffer length to fetch
2133 * Try to fetch EDID information by calling I2C driver functions.
2135 * Return: 0 on success or -1 on failure.
2138 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2140 struct i2c_adapter *adapter = data;
2141 unsigned char start = block * EDID_LENGTH;
2142 unsigned char segment = block >> 1;
2143 unsigned char xfers = segment ? 3 : 2;
2144 int ret, retries = 5;
2147 * The core I2C driver will automatically retry the transfer if the
2148 * adapter reports EAGAIN. However, we find that bit-banging transfers
2149 * are susceptible to errors under a heavily loaded machine and
2150 * generate spurious NAKs and timeouts. Retrying the transfer
2151 * of the individual block a few times seems to overcome this.
2154 struct i2c_msg msgs[] = {
2156 .addr = DDC_SEGMENT_ADDR,
2174 * Avoid sending the segment addr to not upset non-compliant
2177 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2179 if (ret == -ENXIO) {
2180 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2184 } while (ret != xfers && --retries);
2186 return ret == xfers ? 0 : -1;
2189 static void connector_bad_edid(struct drm_connector *connector,
2190 const struct edid *edid, int num_blocks)
2196 * 0x7e in the EDID is the number of extension blocks. The EDID
2197 * is 1 (base block) + num_ext_blocks big. That means we can think
2198 * of 0x7e in the EDID of the _index_ of the last block in the
2199 * combined chunk of memory.
2201 last_block = edid->extensions;
2203 /* Calculate real checksum for the last edid extension block data */
2204 if (last_block < num_blocks)
2205 connector->real_edid_checksum =
2206 edid_block_compute_checksum(edid + last_block);
2208 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2212 connector->base.id, connector->name);
2213 for (i = 0; i < num_blocks; i++)
2214 edid_block_dump(KERN_DEBUG, edid + i, i);
2217 /* Get override or firmware EDID */
2218 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2220 const struct drm_edid *override = NULL;
2222 mutex_lock(&connector->edid_override_mutex);
2224 if (connector->edid_override)
2225 override = drm_edid_dup(connector->edid_override);
2227 mutex_unlock(&connector->edid_override_mutex);
2230 override = drm_edid_load_firmware(connector);
2232 return IS_ERR(override) ? NULL : override;
2235 /* For debugfs edid_override implementation */
2236 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2238 const struct drm_edid *drm_edid;
2240 mutex_lock(&connector->edid_override_mutex);
2242 drm_edid = connector->edid_override;
2244 seq_write(m, drm_edid->edid, drm_edid->size);
2246 mutex_unlock(&connector->edid_override_mutex);
2251 /* For debugfs edid_override implementation */
2252 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 const struct drm_edid *drm_edid;
2257 drm_edid = drm_edid_alloc(edid, size);
2258 if (!drm_edid_valid(drm_edid)) {
2259 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2260 connector->base.id, connector->name);
2261 drm_edid_free(drm_edid);
2265 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2266 connector->base.id, connector->name);
2268 mutex_lock(&connector->edid_override_mutex);
2270 drm_edid_free(connector->edid_override);
2271 connector->edid_override = drm_edid;
2273 mutex_unlock(&connector->edid_override_mutex);
2278 /* For debugfs edid_override implementation */
2279 int drm_edid_override_reset(struct drm_connector *connector)
2281 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2282 connector->base.id, connector->name);
2284 mutex_lock(&connector->edid_override_mutex);
2286 drm_edid_free(connector->edid_override);
2287 connector->edid_override = NULL;
2289 mutex_unlock(&connector->edid_override_mutex);
2295 * drm_edid_override_connector_update - add modes from override/firmware EDID
2296 * @connector: connector we're probing
2298 * Add modes from the override/firmware EDID, if available. Only to be used from
2299 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2300 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * Return: The number of modes added or 0 if we couldn't find any.
2305 int drm_edid_override_connector_update(struct drm_connector *connector)
2307 const struct drm_edid *override;
2310 override = drm_edid_override_get(connector);
2312 num_modes = drm_edid_connector_update(connector, override);
2314 drm_edid_free(override);
2316 drm_dbg_kms(connector->dev,
2317 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2318 connector->base.id, connector->name, num_modes);
2323 EXPORT_SYMBOL(drm_edid_override_connector_update);
2325 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2327 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2328 read_block_fn read_block,
2331 enum edid_block_status status;
2332 bool is_base_block = block_num == 0;
2335 for (try = 0; try < 4; try++) {
2336 if (read_block(context, block, block_num, EDID_LENGTH))
2337 return EDID_BLOCK_READ_FAIL;
2339 status = edid_block_check(block, is_base_block);
2340 if (status == EDID_BLOCK_HEADER_REPAIR) {
2341 edid_header_fix(block);
2343 /* Retry with fixed header, update status if that worked. */
2344 status = edid_block_check(block, is_base_block);
2345 if (status == EDID_BLOCK_OK)
2346 status = EDID_BLOCK_HEADER_FIXED;
2349 if (edid_block_status_valid(status, edid_block_tag(block)))
2352 /* Fail early for unrepairable base block all zeros. */
2353 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2360 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2361 read_block_fn read_block, void *context,
2364 enum edid_block_status status;
2365 int i, num_blocks, invalid_blocks = 0;
2366 const struct drm_edid *override;
2367 struct edid *edid, *new;
2368 size_t alloc_size = EDID_LENGTH;
2370 override = drm_edid_override_get(connector);
2372 alloc_size = override->size;
2373 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2374 drm_edid_free(override);
2380 edid = kmalloc(alloc_size, GFP_KERNEL);
2384 status = edid_block_read(edid, 0, read_block, context);
2386 edid_block_status_print(status, edid, 0);
2388 if (status == EDID_BLOCK_READ_FAIL)
2391 /* FIXME: Clarify what a corrupt EDID actually means. */
2392 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2393 connector->edid_corrupt = false;
2395 connector->edid_corrupt = true;
2397 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2398 if (status == EDID_BLOCK_ZERO)
2399 connector->null_edid_counter++;
2401 connector_bad_edid(connector, edid, 1);
2405 if (!edid_extension_block_count(edid))
2408 alloc_size = edid_size(edid);
2409 new = krealloc(edid, alloc_size, GFP_KERNEL);
2414 num_blocks = edid_block_count(edid);
2415 for (i = 1; i < num_blocks; i++) {
2416 void *block = (void *)edid_block_data(edid, i);
2418 status = edid_block_read(block, i, read_block, context);
2420 edid_block_status_print(status, block, i);
2422 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2423 if (status == EDID_BLOCK_READ_FAIL)
2426 } else if (i == 1) {
2428 * If the first EDID extension is a CTA extension, and
2429 * the first Data Block is HF-EEODB, override the
2430 * extension block count.
2432 * Note: HF-EEODB could specify a smaller extension
2433 * count too, but we can't risk allocating a smaller
2436 int eeodb = edid_hfeeodb_block_count(edid);
2438 if (eeodb > num_blocks) {
2440 alloc_size = edid_size_by_blocks(num_blocks);
2441 new = krealloc(edid, alloc_size, GFP_KERNEL);
2449 if (invalid_blocks) {
2450 connector_bad_edid(connector, edid, num_blocks);
2452 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2467 * drm_do_get_edid - get EDID data using a custom EDID block read function
2468 * @connector: connector we're probing
2469 * @read_block: EDID block read function
2470 * @context: private data passed to the block read function
2472 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2473 * exposes a different interface to read EDID blocks this function can be used
2474 * to get EDID data using a custom block read function.
2476 * As in the general case the DDC bus is accessible by the kernel at the I2C
2477 * level, drivers must make all reasonable efforts to expose it as an I2C
2478 * adapter and use drm_get_edid() instead of abusing this function.
2480 * The EDID may be overridden using debugfs override_edid or firmware EDID
2481 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2482 * order. Having either of them bypasses actual EDID reads.
2484 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2486 struct edid *drm_do_get_edid(struct drm_connector *connector,
2487 read_block_fn read_block,
2490 return _drm_do_get_edid(connector, read_block, context, NULL);
2492 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2495 * drm_edid_raw - Get a pointer to the raw EDID data.
2496 * @drm_edid: drm_edid container
2498 * Get a pointer to the raw EDID data.
2500 * This is for transition only. Avoid using this like the plague.
2502 * Return: Pointer to raw EDID data.
2504 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2506 if (!drm_edid || !drm_edid->size)
2510 * Do not return pointers where relying on EDID extension count would
2511 * lead to buffer overflow.
2513 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2516 return drm_edid->edid;
2518 EXPORT_SYMBOL(drm_edid_raw);
2520 /* Allocate struct drm_edid container *without* duplicating the edid data */
2521 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2523 struct drm_edid *drm_edid;
2525 if (!edid || !size || size < EDID_LENGTH)
2528 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2530 drm_edid->edid = edid;
2531 drm_edid->size = size;
2538 * drm_edid_alloc - Allocate a new drm_edid container
2539 * @edid: Pointer to raw EDID data
2540 * @size: Size of memory allocated for EDID
2542 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2543 * the actual size that has been allocated for the data. There is no validation
2544 * of the raw EDID data against the size, but at least the EDID base block must
2545 * fit in the buffer.
2547 * The returned pointer must be freed using drm_edid_free().
2549 * Return: drm_edid container, or NULL on errors
2551 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2553 const struct drm_edid *drm_edid;
2555 if (!edid || !size || size < EDID_LENGTH)
2558 edid = kmemdup(edid, size, GFP_KERNEL);
2562 drm_edid = _drm_edid_alloc(edid, size);
2568 EXPORT_SYMBOL(drm_edid_alloc);
2571 * drm_edid_dup - Duplicate a drm_edid container
2572 * @drm_edid: EDID to duplicate
2574 * The returned pointer must be freed using drm_edid_free().
2576 * Returns: drm_edid container copy, or NULL on errors
2578 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2583 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2585 EXPORT_SYMBOL(drm_edid_dup);
2588 * drm_edid_free - Free the drm_edid container
2589 * @drm_edid: EDID to free
2591 void drm_edid_free(const struct drm_edid *drm_edid)
2596 kfree(drm_edid->edid);
2599 EXPORT_SYMBOL(drm_edid_free);
2602 * drm_probe_ddc() - probe DDC presence
2603 * @adapter: I2C adapter to probe
2605 * Return: True on success, false on failure.
2608 drm_probe_ddc(struct i2c_adapter *adapter)
2612 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2614 EXPORT_SYMBOL(drm_probe_ddc);
2617 * drm_get_edid - get EDID data, if available
2618 * @connector: connector we're probing
2619 * @adapter: I2C adapter to use for DDC
2621 * Poke the given I2C channel to grab EDID data if possible. If found,
2622 * attach it to the connector.
2624 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2626 struct edid *drm_get_edid(struct drm_connector *connector,
2627 struct i2c_adapter *adapter)
2631 if (connector->force == DRM_FORCE_OFF)
2634 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2637 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2638 drm_connector_update_edid_property(connector, edid);
2641 EXPORT_SYMBOL(drm_get_edid);
2644 * drm_edid_read_custom - Read EDID data using given EDID block read function
2645 * @connector: Connector to use
2646 * @read_block: EDID block read function
2647 * @context: Private data passed to the block read function
2649 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2650 * exposes a different interface to read EDID blocks this function can be used
2651 * to get EDID data using a custom block read function.
2653 * As in the general case the DDC bus is accessible by the kernel at the I2C
2654 * level, drivers must make all reasonable efforts to expose it as an I2C
2655 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2658 * The EDID may be overridden using debugfs override_edid or firmware EDID
2659 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2660 * order. Having either of them bypasses actual EDID reads.
2662 * The returned pointer must be freed using drm_edid_free().
2664 * Return: Pointer to EDID, or NULL if probe/read failed.
2666 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2667 read_block_fn read_block,
2670 const struct drm_edid *drm_edid;
2674 edid = _drm_do_get_edid(connector, read_block, context, &size);
2678 /* Sanity check for now */
2679 drm_WARN_ON(connector->dev, !size);
2681 drm_edid = _drm_edid_alloc(edid, size);
2687 EXPORT_SYMBOL(drm_edid_read_custom);
2690 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2691 * @connector: Connector to use
2692 * @adapter: I2C adapter to use for DDC
2694 * Read EDID using the given I2C adapter.
2696 * The EDID may be overridden using debugfs override_edid or firmware EDID
2697 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2698 * order. Having either of them bypasses actual EDID reads.
2700 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2701 * using drm_edid_read() instead of this function.
2703 * The returned pointer must be freed using drm_edid_free().
2705 * Return: Pointer to EDID, or NULL if probe/read failed.
2707 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2708 struct i2c_adapter *adapter)
2710 const struct drm_edid *drm_edid;
2712 if (connector->force == DRM_FORCE_OFF)
2715 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2718 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2720 /* Note: Do *not* call connector updates here. */
2724 EXPORT_SYMBOL(drm_edid_read_ddc);
2727 * drm_edid_read - Read EDID data using connector's I2C adapter
2728 * @connector: Connector to use
2730 * Read EDID using the connector's I2C adapter.
2732 * The EDID may be overridden using debugfs override_edid or firmware EDID
2733 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2734 * order. Having either of them bypasses actual EDID reads.
2736 * The returned pointer must be freed using drm_edid_free().
2738 * Return: Pointer to EDID, or NULL if probe/read failed.
2740 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2742 if (drm_WARN_ON(connector->dev, !connector->ddc))
2745 return drm_edid_read_ddc(connector, connector->ddc);
2747 EXPORT_SYMBOL(drm_edid_read);
2749 static u32 edid_extract_panel_id(const struct edid *edid)
2752 * We represent the ID as a 32-bit number so it can easily be compared
2755 * NOTE that we deal with endianness differently for the top half
2756 * of this ID than for the bottom half. The bottom half (the product
2757 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2758 * that's how everyone seems to interpret it. The top half (the mfg_id)
2759 * gets stored as big endian because that makes
2760 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2761 * to write (it's easier to extract the ASCII). It doesn't really
2762 * matter, though, as long as the number here is unique.
2764 return (u32)edid->mfg_id[0] << 24 |
2765 (u32)edid->mfg_id[1] << 16 |
2766 (u32)EDID_PRODUCT_ID(edid);
2770 * drm_edid_get_panel_id - Get a panel's ID through DDC
2771 * @adapter: I2C adapter to use for DDC
2773 * This function reads the first block of the EDID of a panel and (assuming
2774 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2775 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2776 * supposed to be different for each different modem of panel.
2778 * This function is intended to be used during early probing on devices where
2779 * more than one panel might be present. Because of its intended use it must
2780 * assume that the EDID of the panel is correct, at least as far as the ID
2781 * is concerned (in other words, we don't process any overrides here).
2783 * NOTE: it's expected that this function and drm_do_get_edid() will both
2784 * be read the EDID, but there is no caching between them. Since we're only
2785 * reading the first block, hopefully this extra overhead won't be too big.
2787 * Return: A 32-bit ID that should be different for each make/model of panel.
2788 * See the functions drm_edid_encode_panel_id() and
2789 * drm_edid_decode_panel_id() for some details on the structure of this
2793 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2795 enum edid_block_status status;
2800 * There are no manufacturer IDs of 0, so if there is a problem reading
2801 * the EDID then we'll just return 0.
2804 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2808 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2810 edid_block_status_print(status, base_block, 0);
2812 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2813 panel_id = edid_extract_panel_id(base_block);
2815 edid_block_dump(KERN_NOTICE, base_block, 0);
2821 EXPORT_SYMBOL(drm_edid_get_panel_id);
2824 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2825 * @connector: connector we're probing
2826 * @adapter: I2C adapter to use for DDC
2828 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2829 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2830 * switch DDC to the GPU which is retrieving EDID.
2832 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2834 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2835 struct i2c_adapter *adapter)
2837 struct drm_device *dev = connector->dev;
2838 struct pci_dev *pdev = to_pci_dev(dev->dev);
2841 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2844 vga_switcheroo_lock_ddc(pdev);
2845 edid = drm_get_edid(connector, adapter);
2846 vga_switcheroo_unlock_ddc(pdev);
2850 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2853 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2854 * @connector: connector we're probing
2855 * @adapter: I2C adapter to use for DDC
2857 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2858 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2859 * temporarily switch DDC to the GPU which is retrieving EDID.
2861 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2863 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2864 struct i2c_adapter *adapter)
2866 struct drm_device *dev = connector->dev;
2867 struct pci_dev *pdev = to_pci_dev(dev->dev);
2868 const struct drm_edid *drm_edid;
2870 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2873 vga_switcheroo_lock_ddc(pdev);
2874 drm_edid = drm_edid_read_ddc(connector, adapter);
2875 vga_switcheroo_unlock_ddc(pdev);
2879 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2882 * drm_edid_duplicate - duplicate an EDID and the extensions
2883 * @edid: EDID to duplicate
2885 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2887 struct edid *drm_edid_duplicate(const struct edid *edid)
2892 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2894 EXPORT_SYMBOL(drm_edid_duplicate);
2896 /*** EDID parsing ***/
2899 * edid_get_quirks - return quirk flags for a given EDID
2900 * @drm_edid: EDID to process
2902 * This tells subsequent routines what fixes they need to apply.
2904 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2906 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2907 const struct edid_quirk *quirk;
2910 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2911 quirk = &edid_quirk_list[i];
2912 if (quirk->panel_id == panel_id)
2913 return quirk->quirks;
2919 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2920 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2923 * Walk the mode list for connector, clearing the preferred status on existing
2924 * modes and setting it anew for the right mode ala quirks.
2926 static void edid_fixup_preferred(struct drm_connector *connector)
2928 const struct drm_display_info *info = &connector->display_info;
2929 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2930 int target_refresh = 0;
2931 int cur_vrefresh, preferred_vrefresh;
2933 if (list_empty(&connector->probed_modes))
2936 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2937 target_refresh = 60;
2938 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2939 target_refresh = 75;
2941 preferred_mode = list_first_entry(&connector->probed_modes,
2942 struct drm_display_mode, head);
2944 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2945 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2947 if (cur_mode == preferred_mode)
2950 /* Largest mode is preferred */
2951 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2952 preferred_mode = cur_mode;
2954 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2955 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2956 /* At a given size, try to get closest to target refresh */
2957 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2958 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2959 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2960 preferred_mode = cur_mode;
2964 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2968 mode_is_rb(const struct drm_display_mode *mode)
2970 return (mode->htotal - mode->hdisplay == 160) &&
2971 (mode->hsync_end - mode->hdisplay == 80) &&
2972 (mode->hsync_end - mode->hsync_start == 32) &&
2973 (mode->vsync_start - mode->vdisplay == 3);
2977 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2978 * @dev: Device to duplicate against
2979 * @hsize: Mode width
2980 * @vsize: Mode height
2981 * @fresh: Mode refresh rate
2982 * @rb: Mode reduced-blanking-ness
2984 * Walk the DMT mode list looking for a match for the given parameters.
2986 * Return: A newly allocated copy of the mode, or NULL if not found.
2988 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2989 int hsize, int vsize, int fresh,
2994 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2995 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2997 if (hsize != ptr->hdisplay)
2999 if (vsize != ptr->vdisplay)
3001 if (fresh != drm_mode_vrefresh(ptr))
3003 if (rb != mode_is_rb(ptr))
3006 return drm_mode_duplicate(dev, ptr);
3011 EXPORT_SYMBOL(drm_mode_find_dmt);
3013 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3016 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3017 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3019 return descriptor->pixel_clock == 0 &&
3020 descriptor->data.other_data.pad1 == 0 &&
3021 descriptor->data.other_data.type == type;
3024 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3026 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3028 return descriptor->pixel_clock != 0;
3031 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3034 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3038 const u8 *det_base = ext + d;
3040 if (d < 4 || d > 127)
3044 for (i = 0; i < n; i++)
3045 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3049 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3051 unsigned int i, n = min((int)ext[0x02], 6);
3052 const u8 *det_base = ext + 5;
3055 return; /* unknown version */
3057 for (i = 0; i < n; i++)
3058 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3061 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3062 detailed_cb *cb, void *closure)
3064 struct drm_edid_iter edid_iter;
3071 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3072 cb(&drm_edid->edid->detailed_timings[i], closure);
3074 drm_edid_iter_begin(drm_edid, &edid_iter);
3075 drm_edid_iter_for_each(ext, &edid_iter) {
3078 cea_for_each_detailed_block(ext, cb, closure);
3081 vtb_for_each_detailed_block(ext, cb, closure);
3087 drm_edid_iter_end(&edid_iter);
3091 is_rb(const struct detailed_timing *descriptor, void *data)
3095 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3099 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3101 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3102 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3106 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3108 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3110 if (drm_edid->edid->revision >= 4) {
3113 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3117 return drm_edid_is_digital(drm_edid);
3121 find_gtf2(const struct detailed_timing *descriptor, void *data)
3123 const struct detailed_timing **res = data;
3125 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3128 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3130 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3134 /* Secondary GTF curve kicks in above some break frequency */
3136 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3138 const struct detailed_timing *descriptor = NULL;
3140 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3142 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3144 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3148 drm_gtf2_2c(const struct drm_edid *drm_edid)
3150 const struct detailed_timing *descriptor = NULL;
3152 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3154 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3156 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3160 drm_gtf2_m(const struct drm_edid *drm_edid)
3162 const struct detailed_timing *descriptor = NULL;
3164 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3166 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3168 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3172 drm_gtf2_k(const struct drm_edid *drm_edid)
3174 const struct detailed_timing *descriptor = NULL;
3176 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3178 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3180 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3184 drm_gtf2_2j(const struct drm_edid *drm_edid)
3186 const struct detailed_timing *descriptor = NULL;
3188 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3190 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3192 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3196 get_timing_level(const struct detailed_timing *descriptor, void *data)
3200 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3203 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3205 switch (descriptor->data.other_data.data.range.flags) {
3206 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3209 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3212 case DRM_EDID_CVT_SUPPORT_FLAG:
3220 /* Get standard timing level (CVT/GTF/DMT). */
3221 static int standard_timing_level(const struct drm_edid *drm_edid)
3223 const struct edid *edid = drm_edid->edid;
3225 if (edid->revision >= 4) {
3227 * If the range descriptor doesn't
3228 * indicate otherwise default to CVT
3230 int ret = LEVEL_CVT;
3232 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3235 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3237 } else if (edid->revision >= 2) {
3245 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3246 * monitors fill with ascii space (0x20) instead.
3249 bad_std_timing(u8 a, u8 b)
3251 return (a == 0x00 && b == 0x00) ||
3252 (a == 0x01 && b == 0x01) ||
3253 (a == 0x20 && b == 0x20);
3256 static int drm_mode_hsync(const struct drm_display_mode *mode)
3258 if (mode->htotal <= 0)
3261 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3264 static struct drm_display_mode *
3265 drm_gtf2_mode(struct drm_device *dev,
3266 const struct drm_edid *drm_edid,
3267 int hsize, int vsize, int vrefresh_rate)
3269 struct drm_display_mode *mode;
3272 * This is potentially wrong if there's ever a monitor with
3273 * more than one ranges section, each claiming a different
3274 * secondary GTF curve. Please don't do that.
3276 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3280 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3281 drm_mode_destroy(dev, mode);
3282 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3283 vrefresh_rate, 0, 0,
3284 drm_gtf2_m(drm_edid),
3285 drm_gtf2_2c(drm_edid),
3286 drm_gtf2_k(drm_edid),
3287 drm_gtf2_2j(drm_edid));
3294 * Take the standard timing params (in this case width, aspect, and refresh)
3295 * and convert them into a real mode using CVT/GTF/DMT.
3297 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3298 const struct drm_edid *drm_edid,
3299 const struct std_timing *t)
3301 struct drm_device *dev = connector->dev;
3302 struct drm_display_mode *m, *mode = NULL;
3305 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3306 >> EDID_TIMING_ASPECT_SHIFT;
3307 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3308 >> EDID_TIMING_VFREQ_SHIFT;
3309 int timing_level = standard_timing_level(drm_edid);
3311 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3314 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3315 hsize = t->hsize * 8 + 248;
3316 /* vrefresh_rate = vfreq + 60 */
3317 vrefresh_rate = vfreq + 60;
3318 /* the vdisplay is calculated based on the aspect ratio */
3319 if (aspect_ratio == 0) {
3320 if (drm_edid->edid->revision < 3)
3323 vsize = (hsize * 10) / 16;
3324 } else if (aspect_ratio == 1)
3325 vsize = (hsize * 3) / 4;
3326 else if (aspect_ratio == 2)
3327 vsize = (hsize * 4) / 5;
3329 vsize = (hsize * 9) / 16;
3331 /* HDTV hack, part 1 */
3332 if (vrefresh_rate == 60 &&
3333 ((hsize == 1360 && vsize == 765) ||
3334 (hsize == 1368 && vsize == 769))) {
3340 * If this connector already has a mode for this size and refresh
3341 * rate (because it came from detailed or CVT info), use that
3342 * instead. This way we don't have to guess at interlace or
3345 list_for_each_entry(m, &connector->probed_modes, head)
3346 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3347 drm_mode_vrefresh(m) == vrefresh_rate)
3350 /* HDTV hack, part 2 */
3351 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3352 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3356 mode->hdisplay = 1366;
3357 mode->hsync_start = mode->hsync_start - 1;
3358 mode->hsync_end = mode->hsync_end - 1;
3362 /* check whether it can be found in default mode table */
3363 if (drm_monitor_supports_rb(drm_edid)) {
3364 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3369 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3373 /* okay, generate it */
3374 switch (timing_level) {
3378 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3381 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3384 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3392 * EDID is delightfully ambiguous about how interlaced modes are to be
3393 * encoded. Our internal representation is of frame height, but some
3394 * HDTV detailed timings are encoded as field height.
3396 * The format list here is from CEA, in frame size. Technically we
3397 * should be checking refresh rate too. Whatever.
3400 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3401 const struct detailed_pixel_timing *pt)
3404 static const struct {
3406 } cea_interlaced[] = {
3416 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3419 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3420 if ((mode->hdisplay == cea_interlaced[i].w) &&
3421 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3422 mode->vdisplay *= 2;
3423 mode->vsync_start *= 2;
3424 mode->vsync_end *= 2;
3430 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3434 * Create a new mode from an EDID detailed timing section. An EDID detailed
3435 * timing block contains enough info for us to create and return a new struct
3438 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3439 const struct drm_edid *drm_edid,
3440 const struct detailed_timing *timing)
3442 const struct drm_display_info *info = &connector->display_info;
3443 struct drm_device *dev = connector->dev;
3444 struct drm_display_mode *mode;
3445 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3446 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3447 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3448 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3449 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3450 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3451 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3452 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3453 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3455 /* ignore tiny modes */
3456 if (hactive < 64 || vactive < 64)
3459 if (pt->misc & DRM_EDID_PT_STEREO) {
3460 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3461 connector->base.id, connector->name);
3464 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3465 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3466 connector->base.id, connector->name);
3469 /* it is incorrect if hsync/vsync width is zero */
3470 if (!hsync_pulse_width || !vsync_pulse_width) {
3471 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3472 connector->base.id, connector->name);
3476 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3477 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3484 mode = drm_mode_create(dev);
3488 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3489 mode->clock = 1088 * 10;
3491 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3493 mode->hdisplay = hactive;
3494 mode->hsync_start = mode->hdisplay + hsync_offset;
3495 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3496 mode->htotal = mode->hdisplay + hblank;
3498 mode->vdisplay = vactive;
3499 mode->vsync_start = mode->vdisplay + vsync_offset;
3500 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3501 mode->vtotal = mode->vdisplay + vblank;
3503 /* Some EDIDs have bogus h/vsync_end values */
3504 if (mode->hsync_end > mode->htotal) {
3505 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3506 connector->base.id, connector->name,
3507 mode->hsync_end, mode->htotal);
3508 mode->hsync_end = mode->htotal;
3510 if (mode->vsync_end > mode->vtotal) {
3511 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3512 connector->base.id, connector->name,
3513 mode->vsync_end, mode->vtotal);
3514 mode->vsync_end = mode->vtotal;
3517 drm_mode_do_interlace_quirk(mode, pt);
3519 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3520 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3522 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3523 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3524 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3525 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3529 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3530 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3532 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3533 mode->width_mm *= 10;
3534 mode->height_mm *= 10;
3537 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3538 mode->width_mm = drm_edid->edid->width_cm * 10;
3539 mode->height_mm = drm_edid->edid->height_cm * 10;
3542 mode->type = DRM_MODE_TYPE_DRIVER;
3543 drm_mode_set_name(mode);
3549 mode_in_hsync_range(const struct drm_display_mode *mode,
3550 const struct edid *edid, const u8 *t)
3552 int hsync, hmin, hmax;
3555 if (edid->revision >= 4)
3556 hmin += ((t[4] & 0x04) ? 255 : 0);
3558 if (edid->revision >= 4)
3559 hmax += ((t[4] & 0x08) ? 255 : 0);
3560 hsync = drm_mode_hsync(mode);
3562 return (hsync <= hmax && hsync >= hmin);
3566 mode_in_vsync_range(const struct drm_display_mode *mode,
3567 const struct edid *edid, const u8 *t)
3569 int vsync, vmin, vmax;
3572 if (edid->revision >= 4)
3573 vmin += ((t[4] & 0x01) ? 255 : 0);
3575 if (edid->revision >= 4)
3576 vmax += ((t[4] & 0x02) ? 255 : 0);
3577 vsync = drm_mode_vrefresh(mode);
3579 return (vsync <= vmax && vsync >= vmin);
3583 range_pixel_clock(const struct edid *edid, const u8 *t)
3586 if (t[9] == 0 || t[9] == 255)
3589 /* 1.4 with CVT support gives us real precision, yay */
3590 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3591 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3593 /* 1.3 is pathetic, so fuzz up a bit */
3594 return t[9] * 10000 + 5001;
3597 static bool mode_in_range(const struct drm_display_mode *mode,
3598 const struct drm_edid *drm_edid,
3599 const struct detailed_timing *timing)
3601 const struct edid *edid = drm_edid->edid;
3603 const u8 *t = (const u8 *)timing;
3605 if (!mode_in_hsync_range(mode, edid, t))
3608 if (!mode_in_vsync_range(mode, edid, t))
3611 if ((max_clock = range_pixel_clock(edid, t)))
3612 if (mode->clock > max_clock)
3615 /* 1.4 max horizontal check */
3616 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3617 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3620 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3626 static bool valid_inferred_mode(const struct drm_connector *connector,
3627 const struct drm_display_mode *mode)
3629 const struct drm_display_mode *m;
3632 list_for_each_entry(m, &connector->probed_modes, head) {
3633 if (mode->hdisplay == m->hdisplay &&
3634 mode->vdisplay == m->vdisplay &&
3635 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3636 return false; /* duplicated */
3637 if (mode->hdisplay <= m->hdisplay &&
3638 mode->vdisplay <= m->vdisplay)
3644 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3645 const struct drm_edid *drm_edid,
3646 const struct detailed_timing *timing)
3649 struct drm_display_mode *newmode;
3650 struct drm_device *dev = connector->dev;
3652 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3653 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3654 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3655 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3657 drm_mode_probed_add(connector, newmode);
3666 /* fix up 1366x768 mode from 1368x768;
3667 * GFT/CVT can't express 1366 width which isn't dividable by 8
3669 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3671 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3672 mode->hdisplay = 1366;
3673 mode->hsync_start--;
3675 drm_mode_set_name(mode);
3679 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3680 const struct drm_edid *drm_edid,
3681 const struct detailed_timing *timing)
3684 struct drm_display_mode *newmode;
3685 struct drm_device *dev = connector->dev;
3687 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3688 const struct minimode *m = &extra_modes[i];
3690 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3694 drm_mode_fixup_1366x768(newmode);
3695 if (!mode_in_range(newmode, drm_edid, timing) ||
3696 !valid_inferred_mode(connector, newmode)) {
3697 drm_mode_destroy(dev, newmode);
3701 drm_mode_probed_add(connector, newmode);
3708 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3709 const struct drm_edid *drm_edid,
3710 const struct detailed_timing *timing)
3713 struct drm_display_mode *newmode;
3714 struct drm_device *dev = connector->dev;
3716 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3717 const struct minimode *m = &extra_modes[i];
3719 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3723 drm_mode_fixup_1366x768(newmode);
3724 if (!mode_in_range(newmode, drm_edid, timing) ||
3725 !valid_inferred_mode(connector, newmode)) {
3726 drm_mode_destroy(dev, newmode);
3730 drm_mode_probed_add(connector, newmode);
3737 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3738 const struct drm_edid *drm_edid,
3739 const struct detailed_timing *timing)
3742 struct drm_display_mode *newmode;
3743 struct drm_device *dev = connector->dev;
3744 bool rb = drm_monitor_supports_rb(drm_edid);
3746 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3747 const struct minimode *m = &extra_modes[i];
3749 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3753 drm_mode_fixup_1366x768(newmode);
3754 if (!mode_in_range(newmode, drm_edid, timing) ||
3755 !valid_inferred_mode(connector, newmode)) {
3756 drm_mode_destroy(dev, newmode);
3760 drm_mode_probed_add(connector, newmode);
3768 do_inferred_modes(const struct detailed_timing *timing, void *c)
3770 struct detailed_mode_closure *closure = c;
3771 const struct detailed_non_pixel *data = &timing->data.other_data;
3772 const struct detailed_data_monitor_range *range = &data->data.range;
3774 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3777 closure->modes += drm_dmt_modes_for_range(closure->connector,
3781 if (closure->drm_edid->edid->revision < 2)
3782 return; /* GTF not defined yet */
3784 switch (range->flags) {
3785 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3786 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3790 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3791 closure->modes += drm_gtf_modes_for_range(closure->connector,
3795 case DRM_EDID_CVT_SUPPORT_FLAG:
3796 if (closure->drm_edid->edid->revision < 4)
3799 closure->modes += drm_cvt_modes_for_range(closure->connector,
3803 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3809 static int add_inferred_modes(struct drm_connector *connector,
3810 const struct drm_edid *drm_edid)
3812 struct detailed_mode_closure closure = {
3813 .connector = connector,
3814 .drm_edid = drm_edid,
3817 if (drm_edid->edid->revision >= 1)
3818 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3820 return closure.modes;
3824 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3826 int i, j, m, modes = 0;
3827 struct drm_display_mode *mode;
3828 const u8 *est = ((const u8 *)timing) + 6;
3830 for (i = 0; i < 6; i++) {
3831 for (j = 7; j >= 0; j--) {
3832 m = (i * 8) + (7 - j);
3833 if (m >= ARRAY_SIZE(est3_modes))
3835 if (est[i] & (1 << j)) {
3836 mode = drm_mode_find_dmt(connector->dev,
3842 drm_mode_probed_add(connector, mode);
3853 do_established_modes(const struct detailed_timing *timing, void *c)
3855 struct detailed_mode_closure *closure = c;
3857 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3860 closure->modes += drm_est3_modes(closure->connector, timing);
3864 * Get established modes from EDID and add them. Each EDID block contains a
3865 * bitmap of the supported "established modes" list (defined above). Tease them
3866 * out and add them to the global modes list.
3868 static int add_established_modes(struct drm_connector *connector,
3869 const struct drm_edid *drm_edid)
3871 struct drm_device *dev = connector->dev;
3872 const struct edid *edid = drm_edid->edid;
3873 unsigned long est_bits = edid->established_timings.t1 |
3874 (edid->established_timings.t2 << 8) |
3875 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3877 struct detailed_mode_closure closure = {
3878 .connector = connector,
3879 .drm_edid = drm_edid,
3882 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3883 if (est_bits & (1<<i)) {
3884 struct drm_display_mode *newmode;
3886 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3888 drm_mode_probed_add(connector, newmode);
3894 if (edid->revision >= 1)
3895 drm_for_each_detailed_block(drm_edid, do_established_modes,
3898 return modes + closure.modes;
3902 do_standard_modes(const struct detailed_timing *timing, void *c)
3904 struct detailed_mode_closure *closure = c;
3905 const struct detailed_non_pixel *data = &timing->data.other_data;
3906 struct drm_connector *connector = closure->connector;
3909 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3912 for (i = 0; i < 6; i++) {
3913 const struct std_timing *std = &data->data.timings[i];
3914 struct drm_display_mode *newmode;
3916 newmode = drm_mode_std(connector, closure->drm_edid, std);
3918 drm_mode_probed_add(connector, newmode);
3925 * Get standard modes from EDID and add them. Standard modes can be calculated
3926 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3927 * add them to the list.
3929 static int add_standard_modes(struct drm_connector *connector,
3930 const struct drm_edid *drm_edid)
3933 struct detailed_mode_closure closure = {
3934 .connector = connector,
3935 .drm_edid = drm_edid,
3938 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3939 struct drm_display_mode *newmode;
3941 newmode = drm_mode_std(connector, drm_edid,
3942 &drm_edid->edid->standard_timings[i]);
3944 drm_mode_probed_add(connector, newmode);
3949 if (drm_edid->edid->revision >= 1)
3950 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3953 /* XXX should also look for standard codes in VTB blocks */
3955 return modes + closure.modes;
3958 static int drm_cvt_modes(struct drm_connector *connector,
3959 const struct detailed_timing *timing)
3961 int i, j, modes = 0;
3962 struct drm_display_mode *newmode;
3963 struct drm_device *dev = connector->dev;
3964 const struct cvt_timing *cvt;
3965 static const int rates[] = { 60, 85, 75, 60, 50 };
3966 const u8 empty[3] = { 0, 0, 0 };
3968 for (i = 0; i < 4; i++) {
3971 cvt = &(timing->data.other_data.data.cvt[i]);
3973 if (!memcmp(cvt->code, empty, 3))
3976 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3977 switch (cvt->code[1] & 0x0c) {
3978 /* default - because compiler doesn't see that we've enumerated all cases */
3981 width = height * 4 / 3;
3984 width = height * 16 / 9;
3987 width = height * 16 / 10;
3990 width = height * 15 / 9;
3994 for (j = 1; j < 5; j++) {
3995 if (cvt->code[2] & (1 << j)) {
3996 newmode = drm_cvt_mode(dev, width, height,
4000 drm_mode_probed_add(connector, newmode);
4011 do_cvt_mode(const struct detailed_timing *timing, void *c)
4013 struct detailed_mode_closure *closure = c;
4015 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4018 closure->modes += drm_cvt_modes(closure->connector, timing);
4022 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4024 struct detailed_mode_closure closure = {
4025 .connector = connector,
4026 .drm_edid = drm_edid,
4029 if (drm_edid->edid->revision >= 3)
4030 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4032 /* XXX should also look for CVT codes in VTB blocks */
4034 return closure.modes;
4037 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4038 struct drm_display_mode *mode);
4041 do_detailed_mode(const struct detailed_timing *timing, void *c)
4043 struct detailed_mode_closure *closure = c;
4044 struct drm_display_mode *newmode;
4046 if (!is_detailed_timing_descriptor(timing))
4049 newmode = drm_mode_detailed(closure->connector,
4050 closure->drm_edid, timing);
4054 if (closure->preferred)
4055 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4058 * Detailed modes are limited to 10kHz pixel clock resolution,
4059 * so fix up anything that looks like CEA/HDMI mode, but the clock
4060 * is just slightly off.
4062 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4064 drm_mode_probed_add(closure->connector, newmode);
4066 closure->preferred = false;
4070 * add_detailed_modes - Add modes from detailed timings
4071 * @connector: attached connector
4072 * @drm_edid: EDID block to scan
4074 static int add_detailed_modes(struct drm_connector *connector,
4075 const struct drm_edid *drm_edid)
4077 struct detailed_mode_closure closure = {
4078 .connector = connector,
4079 .drm_edid = drm_edid,
4082 if (drm_edid->edid->revision >= 4)
4083 closure.preferred = true; /* first detailed timing is always preferred */
4086 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4088 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4090 return closure.modes;
4093 /* CTA-861-H Table 60 - CTA Tag Codes */
4094 #define CTA_DB_AUDIO 1
4095 #define CTA_DB_VIDEO 2
4096 #define CTA_DB_VENDOR 3
4097 #define CTA_DB_SPEAKER 4
4098 #define CTA_DB_EXTENDED_TAG 7
4100 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4101 #define CTA_EXT_DB_VIDEO_CAP 0
4102 #define CTA_EXT_DB_VENDOR 1
4103 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4104 #define CTA_EXT_DB_420_VIDEO_DATA 14
4105 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4106 #define CTA_EXT_DB_HF_EEODB 0x78
4107 #define CTA_EXT_DB_HF_SCDB 0x79
4109 #define EDID_BASIC_AUDIO (1 << 6)
4110 #define EDID_CEA_YCRCB444 (1 << 5)
4111 #define EDID_CEA_YCRCB422 (1 << 4)
4112 #define EDID_CEA_VCDB_QS (1 << 6)
4115 * Search EDID for CEA extension block.
4117 * FIXME: Prefer not returning pointers to raw EDID data.
4119 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4120 int ext_id, int *ext_index)
4122 const u8 *edid_ext = NULL;
4125 /* No EDID or EDID extensions */
4126 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4129 /* Find CEA extension */
4130 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4131 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4132 if (edid_block_tag(edid_ext) == ext_id)
4136 if (i >= drm_edid_extension_block_count(drm_edid))
4144 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4145 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4147 const struct displayid_block *block;
4148 struct displayid_iter iter;
4152 /* Look for a top level CEA extension block */
4153 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4156 /* CEA blocks can also be found embedded in a DisplayID block */
4157 displayid_iter_edid_begin(drm_edid, &iter);
4158 displayid_iter_for_each(block, &iter) {
4159 if (block->tag == DATA_BLOCK_CTA) {
4164 displayid_iter_end(&iter);
4169 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4171 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4172 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4174 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4175 return &edid_cea_modes_1[vic - 1];
4176 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4177 return &edid_cea_modes_193[vic - 193];
4181 static u8 cea_num_vics(void)
4183 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4186 static u8 cea_next_vic(u8 vic)
4188 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4194 * Calculate the alternate clock for the CEA mode
4195 * (60Hz vs. 59.94Hz etc.)
4198 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4200 unsigned int clock = cea_mode->clock;
4202 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4206 * edid_cea_modes contains the 59.94Hz
4207 * variant for 240 and 480 line modes,
4208 * and the 60Hz variant otherwise.
4210 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4211 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4213 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4219 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4222 * For certain VICs the spec allows the vertical
4223 * front porch to vary by one or two lines.
4225 * cea_modes[] stores the variant with the shortest
4226 * vertical front porch. We can adjust the mode to
4227 * get the other variants by simply increasing the
4228 * vertical front porch length.
4230 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4231 cea_mode_for_vic(9)->vtotal != 262 ||
4232 cea_mode_for_vic(12)->vtotal != 262 ||
4233 cea_mode_for_vic(13)->vtotal != 262 ||
4234 cea_mode_for_vic(23)->vtotal != 312 ||
4235 cea_mode_for_vic(24)->vtotal != 312 ||
4236 cea_mode_for_vic(27)->vtotal != 312 ||
4237 cea_mode_for_vic(28)->vtotal != 312);
4239 if (((vic == 8 || vic == 9 ||
4240 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4241 ((vic == 23 || vic == 24 ||
4242 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4243 mode->vsync_start++;
4253 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4254 unsigned int clock_tolerance)
4256 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4259 if (!to_match->clock)
4262 if (to_match->picture_aspect_ratio)
4263 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4265 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4266 struct drm_display_mode cea_mode;
4267 unsigned int clock1, clock2;
4269 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4271 /* Check both 60Hz and 59.94Hz */
4272 clock1 = cea_mode.clock;
4273 clock2 = cea_mode_alternate_clock(&cea_mode);
4275 if (abs(to_match->clock - clock1) > clock_tolerance &&
4276 abs(to_match->clock - clock2) > clock_tolerance)
4280 if (drm_mode_match(to_match, &cea_mode, match_flags))
4282 } while (cea_mode_alternate_timings(vic, &cea_mode));
4289 * drm_match_cea_mode - look for a CEA mode matching given mode
4290 * @to_match: display mode
4292 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4295 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4297 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4300 if (!to_match->clock)
4303 if (to_match->picture_aspect_ratio)
4304 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4306 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4307 struct drm_display_mode cea_mode;
4308 unsigned int clock1, clock2;
4310 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4312 /* Check both 60Hz and 59.94Hz */
4313 clock1 = cea_mode.clock;
4314 clock2 = cea_mode_alternate_clock(&cea_mode);
4316 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4317 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4321 if (drm_mode_match(to_match, &cea_mode, match_flags))
4323 } while (cea_mode_alternate_timings(vic, &cea_mode));
4328 EXPORT_SYMBOL(drm_match_cea_mode);
4330 static bool drm_valid_cea_vic(u8 vic)
4332 return cea_mode_for_vic(vic) != NULL;
4335 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4337 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4340 return mode->picture_aspect_ratio;
4342 return HDMI_PICTURE_ASPECT_NONE;
4345 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4347 return edid_4k_modes[video_code].picture_aspect_ratio;
4351 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4355 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4357 return cea_mode_alternate_clock(hdmi_mode);
4360 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4361 unsigned int clock_tolerance)
4363 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4366 if (!to_match->clock)
4369 if (to_match->picture_aspect_ratio)
4370 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4372 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4373 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4374 unsigned int clock1, clock2;
4376 /* Make sure to also match alternate clocks */
4377 clock1 = hdmi_mode->clock;
4378 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4380 if (abs(to_match->clock - clock1) > clock_tolerance &&
4381 abs(to_match->clock - clock2) > clock_tolerance)
4384 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4392 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4393 * @to_match: display mode
4395 * An HDMI mode is one defined in the HDMI vendor specific block.
4397 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4399 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4401 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4404 if (!to_match->clock)
4407 if (to_match->picture_aspect_ratio)
4408 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4410 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4411 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4412 unsigned int clock1, clock2;
4414 /* Make sure to also match alternate clocks */
4415 clock1 = hdmi_mode->clock;
4416 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4418 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4419 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4420 drm_mode_match(to_match, hdmi_mode, match_flags))
4426 static bool drm_valid_hdmi_vic(u8 vic)
4428 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4431 static int add_alternate_cea_modes(struct drm_connector *connector,
4432 const struct drm_edid *drm_edid)
4434 struct drm_device *dev = connector->dev;
4435 struct drm_display_mode *mode, *tmp;
4439 /* Don't add CTA modes if the CTA extension block is missing */
4440 if (!drm_edid_has_cta_extension(drm_edid))
4444 * Go through all probed modes and create a new mode
4445 * with the alternate clock for certain CEA modes.
4447 list_for_each_entry(mode, &connector->probed_modes, head) {
4448 const struct drm_display_mode *cea_mode = NULL;
4449 struct drm_display_mode *newmode;
4450 u8 vic = drm_match_cea_mode(mode);
4451 unsigned int clock1, clock2;
4453 if (drm_valid_cea_vic(vic)) {
4454 cea_mode = cea_mode_for_vic(vic);
4455 clock2 = cea_mode_alternate_clock(cea_mode);
4457 vic = drm_match_hdmi_mode(mode);
4458 if (drm_valid_hdmi_vic(vic)) {
4459 cea_mode = &edid_4k_modes[vic];
4460 clock2 = hdmi_mode_alternate_clock(cea_mode);
4467 clock1 = cea_mode->clock;
4469 if (clock1 == clock2)
4472 if (mode->clock != clock1 && mode->clock != clock2)
4475 newmode = drm_mode_duplicate(dev, cea_mode);
4479 /* Carry over the stereo flags */
4480 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4483 * The current mode could be either variant. Make
4484 * sure to pick the "other" clock for the new mode.
4486 if (mode->clock != clock1)
4487 newmode->clock = clock1;
4489 newmode->clock = clock2;
4491 list_add_tail(&newmode->head, &list);
4494 list_for_each_entry_safe(mode, tmp, &list, head) {
4495 list_del(&mode->head);
4496 drm_mode_probed_add(connector, mode);
4503 static u8 svd_to_vic(u8 svd)
4505 /* 0-6 bit vic, 7th bit native mode indicator */
4506 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4513 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4514 * the EDID, or NULL on errors.
4516 static struct drm_display_mode *
4517 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4519 const struct drm_display_info *info = &connector->display_info;
4520 struct drm_device *dev = connector->dev;
4522 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4525 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4529 * do_y420vdb_modes - Parse YCBCR 420 only modes
4530 * @connector: connector corresponding to the HDMI sink
4531 * @svds: start of the data block of CEA YCBCR 420 VDB
4532 * @len: length of the CEA YCBCR 420 VDB
4534 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4535 * which contains modes which can be supported in YCBCR 420
4536 * output format only.
4538 static int do_y420vdb_modes(struct drm_connector *connector,
4539 const u8 *svds, u8 svds_len)
4541 struct drm_device *dev = connector->dev;
4544 for (i = 0; i < svds_len; i++) {
4545 u8 vic = svd_to_vic(svds[i]);
4546 struct drm_display_mode *newmode;
4548 if (!drm_valid_cea_vic(vic))
4551 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4554 drm_mode_probed_add(connector, newmode);
4562 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4564 * @video_code: CEA VIC of the mode
4566 * Creates a new mode matching the specified CEA VIC.
4568 * Returns: A new drm_display_mode on success or NULL on failure
4570 struct drm_display_mode *
4571 drm_display_mode_from_cea_vic(struct drm_device *dev,
4574 const struct drm_display_mode *cea_mode;
4575 struct drm_display_mode *newmode;
4577 cea_mode = cea_mode_for_vic(video_code);
4581 newmode = drm_mode_duplicate(dev, cea_mode);
4587 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4589 /* Add modes based on VICs parsed in parse_cta_vdb() */
4590 static int add_cta_vdb_modes(struct drm_connector *connector)
4592 const struct drm_display_info *info = &connector->display_info;
4598 for (i = 0; i < info->vics_len; i++) {
4599 struct drm_display_mode *mode;
4601 mode = drm_display_mode_from_vic_index(connector, i);
4603 drm_mode_probed_add(connector, mode);
4611 struct stereo_mandatory_mode {
4612 int width, height, vrefresh;
4616 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4617 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4618 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4620 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4622 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4623 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4624 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4625 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4626 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4630 stereo_match_mandatory(const struct drm_display_mode *mode,
4631 const struct stereo_mandatory_mode *stereo_mode)
4633 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4635 return mode->hdisplay == stereo_mode->width &&
4636 mode->vdisplay == stereo_mode->height &&
4637 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4638 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4641 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4643 struct drm_device *dev = connector->dev;
4644 const struct drm_display_mode *mode;
4645 struct list_head stereo_modes;
4648 INIT_LIST_HEAD(&stereo_modes);
4650 list_for_each_entry(mode, &connector->probed_modes, head) {
4651 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4652 const struct stereo_mandatory_mode *mandatory;
4653 struct drm_display_mode *new_mode;
4655 if (!stereo_match_mandatory(mode,
4656 &stereo_mandatory_modes[i]))
4659 mandatory = &stereo_mandatory_modes[i];
4660 new_mode = drm_mode_duplicate(dev, mode);
4664 new_mode->flags |= mandatory->flags;
4665 list_add_tail(&new_mode->head, &stereo_modes);
4670 list_splice_tail(&stereo_modes, &connector->probed_modes);
4675 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4677 struct drm_device *dev = connector->dev;
4678 struct drm_display_mode *newmode;
4680 if (!drm_valid_hdmi_vic(vic)) {
4681 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4682 connector->base.id, connector->name, vic);
4686 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4690 drm_mode_probed_add(connector, newmode);
4695 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4698 struct drm_display_mode *newmode;
4701 if (structure & (1 << 0)) {
4702 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4704 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4705 drm_mode_probed_add(connector, newmode);
4709 if (structure & (1 << 6)) {
4710 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4712 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4713 drm_mode_probed_add(connector, newmode);
4717 if (structure & (1 << 8)) {
4718 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4720 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4721 drm_mode_probed_add(connector, newmode);
4729 static bool hdmi_vsdb_latency_present(const u8 *db)
4731 return db[8] & BIT(7);
4734 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4736 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4739 static int hdmi_vsdb_latency_length(const u8 *db)
4741 if (hdmi_vsdb_i_latency_present(db))
4743 else if (hdmi_vsdb_latency_present(db))
4750 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4751 * @connector: connector corresponding to the HDMI sink
4752 * @db: start of the CEA vendor specific block
4753 * @len: length of the CEA block payload, ie. one can access up to db[len]
4755 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4756 * also adds the stereo 3d modes when applicable.
4759 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4761 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4762 u8 vic_len, hdmi_3d_len = 0;
4769 /* no HDMI_Video_Present */
4770 if (!(db[8] & (1 << 5)))
4773 offset += hdmi_vsdb_latency_length(db);
4775 /* the declared length is not long enough for the 2 first bytes
4776 * of additional video format capabilities */
4777 if (len < (8 + offset + 2))
4782 if (db[8 + offset] & (1 << 7)) {
4783 modes += add_hdmi_mandatory_stereo_modes(connector);
4785 /* 3D_Multi_present */
4786 multi_present = (db[8 + offset] & 0x60) >> 5;
4790 vic_len = db[8 + offset] >> 5;
4791 hdmi_3d_len = db[8 + offset] & 0x1f;
4793 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4796 vic = db[9 + offset + i];
4797 modes += add_hdmi_mode(connector, vic);
4799 offset += 1 + vic_len;
4801 if (multi_present == 1)
4803 else if (multi_present == 2)
4808 if (len < (8 + offset + hdmi_3d_len - 1))
4811 if (hdmi_3d_len < multi_len)
4814 if (multi_present == 1 || multi_present == 2) {
4815 /* 3D_Structure_ALL */
4816 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4818 /* check if 3D_MASK is present */
4819 if (multi_present == 2)
4820 mask = (db[10 + offset] << 8) | db[11 + offset];
4824 for (i = 0; i < 16; i++) {
4825 if (mask & (1 << i))
4826 modes += add_3d_struct_modes(connector,
4831 offset += multi_len;
4833 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4835 struct drm_display_mode *newmode = NULL;
4836 unsigned int newflag = 0;
4837 bool detail_present;
4839 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4841 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4844 /* 2D_VIC_order_X */
4845 vic_index = db[8 + offset + i] >> 4;
4847 /* 3D_Structure_X */
4848 switch (db[8 + offset + i] & 0x0f) {
4850 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4853 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4857 if ((db[9 + offset + i] >> 4) == 1)
4858 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4863 newmode = drm_display_mode_from_vic_index(connector,
4867 newmode->flags |= newflag;
4868 drm_mode_probed_add(connector, newmode);
4882 cea_revision(const u8 *cea)
4885 * FIXME is this correct for the DispID variant?
4886 * The DispID spec doesn't really specify whether
4887 * this is the revision of the CEA extension or
4888 * the DispID CEA data block. And the only value
4889 * given as an example is 0.
4895 * CTA Data Block iterator.
4897 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4900 * struct cea_db *db:
4901 * struct cea_db_iter iter;
4903 * cea_db_iter_edid_begin(edid, &iter);
4904 * cea_db_iter_for_each(db, &iter) {
4905 * // do stuff with db
4907 * cea_db_iter_end(&iter);
4909 struct cea_db_iter {
4910 struct drm_edid_iter edid_iter;
4911 struct displayid_iter displayid_iter;
4913 /* Current Data Block Collection. */
4914 const u8 *collection;
4916 /* Current Data Block index in current collection. */
4919 /* End index in current collection. */
4923 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4929 static int cea_db_tag(const struct cea_db *db)
4931 return db->tag_length >> 5;
4934 static int cea_db_payload_len(const void *_db)
4936 /* FIXME: Transition to passing struct cea_db * everywhere. */
4937 const struct cea_db *db = _db;
4939 return db->tag_length & 0x1f;
4942 static const void *cea_db_data(const struct cea_db *db)
4947 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4949 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4950 cea_db_payload_len(db) >= 1 &&
4954 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4956 const u8 *data = cea_db_data(db);
4958 return cea_db_tag(db) == CTA_DB_VENDOR &&
4959 cea_db_payload_len(db) >= 3 &&
4960 oui(data[2], data[1], data[0]) == vendor_oui;
4963 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4964 struct cea_db_iter *iter)
4966 memset(iter, 0, sizeof(*iter));
4968 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4969 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4972 static const struct cea_db *
4973 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4975 const struct cea_db *db;
4977 if (!iter->collection)
4980 db = (const struct cea_db *)&iter->collection[iter->index];
4982 if (iter->index + sizeof(*db) <= iter->end &&
4983 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4991 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4993 static int cea_db_collection_size(const u8 *cta)
4997 if (d < 4 || d > 127)
5005 * - VESA E-EDID v1.4
5006 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5008 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5012 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5015 /* Only support CTA Extension revision 3+ */
5016 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5019 size = cea_db_collection_size(ext);
5024 iter->end = iter->index + size;
5034 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5035 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5037 * Note that the above do not specify any connection between DisplayID Data
5038 * Block revision and CTA Extension versions.
5040 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5042 const struct displayid_block *block;
5044 displayid_iter_for_each(block, &iter->displayid_iter) {
5045 if (block->tag != DATA_BLOCK_CTA)
5049 * The displayid iterator has already verified the block bounds
5050 * in displayid_iter_block().
5052 iter->index = sizeof(*block);
5053 iter->end = iter->index + block->num_bytes;
5061 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5063 const struct cea_db *db;
5065 if (iter->collection) {
5066 /* Current collection should always be valid. */
5067 db = __cea_db_iter_current_block(iter);
5069 iter->collection = NULL;
5073 /* Next block in CTA Data Block Collection */
5074 iter->index += sizeof(*db) + cea_db_payload_len(db);
5076 db = __cea_db_iter_current_block(iter);
5083 * Find the next CTA Data Block Collection. First iterate all
5084 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5086 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5087 * Extension, it's recommended that DisplayID extensions are
5088 * exposed after all of the CTA Extensions.
5090 iter->collection = __cea_db_iter_edid_next(iter);
5091 if (!iter->collection)
5092 iter->collection = __cea_db_iter_displayid_next(iter);
5094 if (!iter->collection)
5097 db = __cea_db_iter_current_block(iter);
5103 #define cea_db_iter_for_each(__db, __iter) \
5104 while (((__db) = __cea_db_iter_next(__iter)))
5106 static void cea_db_iter_end(struct cea_db_iter *iter)
5108 displayid_iter_end(&iter->displayid_iter);
5109 drm_edid_iter_end(&iter->edid_iter);
5111 memset(iter, 0, sizeof(*iter));
5114 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5116 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5117 cea_db_payload_len(db) >= 5;
5120 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5122 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5123 cea_db_payload_len(db) >= 7;
5126 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5128 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5129 cea_db_payload_len(db) >= 2;
5132 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5134 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5135 cea_db_payload_len(db) == 21;
5138 static bool cea_db_is_vcdb(const struct cea_db *db)
5140 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5141 cea_db_payload_len(db) == 2;
5144 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5146 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5147 cea_db_payload_len(db) >= 7;
5150 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5152 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5155 static bool cea_db_is_y420vdb(const struct cea_db *db)
5157 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5160 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5162 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5163 cea_db_payload_len(db) >= 3;
5167 * Get the HF-EEODB override extension block count from EDID.
5169 * The passed in EDID may be partially read, as long as it has at least two
5170 * blocks (base block and one extension block) if EDID extension count is > 0.
5172 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5173 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5174 * iterators instead.
5177 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5179 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5183 /* No extensions according to base block, no HF-EEODB. */
5184 if (!edid_extension_block_count(edid))
5187 /* HF-EEODB is always in the first EDID extension block only */
5188 cta = edid_extension_block_data(edid, 0);
5189 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5192 /* Need to have the data block collection, and at least 3 bytes. */
5193 if (cea_db_collection_size(cta) < 3)
5197 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5198 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5199 * through 6 of Block 1 of the E-EDID.
5201 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5208 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5210 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5211 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5212 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5213 * support YCBCR420 output too.
5215 static void parse_cta_y420cmdb(struct drm_connector *connector,
5216 const struct cea_db *db, u64 *y420cmdb_map)
5218 struct drm_display_info *info = &connector->display_info;
5219 int i, map_len = cea_db_payload_len(db) - 1;
5220 const u8 *data = cea_db_data(db) + 1;
5224 /* All CEA modes support ycbcr420 sampling also.*/
5230 * This map indicates which of the existing CEA block modes
5231 * from VDB can support YCBCR420 output too. So if bit=0 is
5232 * set, first mode from VDB can support YCBCR420 output too.
5233 * We will parse and keep this map, before parsing VDB itself
5234 * to avoid going through the same block again and again.
5236 * Spec is not clear about max possible size of this block.
5237 * Clamping max bitmap block size at 8 bytes. Every byte can
5238 * address 8 CEA modes, in this way this map can address
5239 * 8*8 = first 64 SVDs.
5241 if (WARN_ON_ONCE(map_len > 8))
5244 for (i = 0; i < map_len; i++)
5245 map |= (u64)data[i] << (8 * i);
5249 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5251 *y420cmdb_map = map;
5254 static int add_cea_modes(struct drm_connector *connector,
5255 const struct drm_edid *drm_edid)
5257 const struct cea_db *db;
5258 struct cea_db_iter iter;
5261 /* CTA VDB block VICs parsed earlier */
5262 modes = add_cta_vdb_modes(connector);
5264 cea_db_iter_edid_begin(drm_edid, &iter);
5265 cea_db_iter_for_each(db, &iter) {
5266 if (cea_db_is_hdmi_vsdb(db)) {
5267 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5268 cea_db_payload_len(db));
5269 } else if (cea_db_is_y420vdb(db)) {
5270 const u8 *vdb420 = cea_db_data(db) + 1;
5272 /* Add 4:2:0(only) modes present in EDID */
5273 modes += do_y420vdb_modes(connector, vdb420,
5274 cea_db_payload_len(db) - 1);
5277 cea_db_iter_end(&iter);
5282 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5283 struct drm_display_mode *mode)
5285 const struct drm_display_mode *cea_mode;
5286 int clock1, clock2, clock;
5291 * allow 5kHz clock difference either way to account for
5292 * the 10kHz clock resolution limit of detailed timings.
5294 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5295 if (drm_valid_cea_vic(vic)) {
5297 cea_mode = cea_mode_for_vic(vic);
5298 clock1 = cea_mode->clock;
5299 clock2 = cea_mode_alternate_clock(cea_mode);
5301 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5302 if (drm_valid_hdmi_vic(vic)) {
5304 cea_mode = &edid_4k_modes[vic];
5305 clock1 = cea_mode->clock;
5306 clock2 = hdmi_mode_alternate_clock(cea_mode);
5312 /* pick whichever is closest */
5313 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5318 if (mode->clock == clock)
5321 drm_dbg_kms(connector->dev,
5322 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5323 connector->base.id, connector->name,
5324 type, vic, mode->clock, clock);
5325 mode->clock = clock;
5328 static void drm_calculate_luminance_range(struct drm_connector *connector)
5330 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5331 struct drm_luminance_range_info *luminance_range =
5332 &connector->display_info.luminance_range;
5333 static const u8 pre_computed_values[] = {
5334 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5335 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5337 u32 max_avg, min_cll, max, min, q, r;
5339 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5342 max_avg = hdr_metadata->max_fall;
5343 min_cll = hdr_metadata->min_cll;
5346 * From the specification (CTA-861-G), for calculating the maximum
5347 * luminance we need to use:
5348 * Luminance = 50*2**(CV/32)
5349 * Where CV is a one-byte value.
5350 * For calculating this expression we may need float point precision;
5351 * to avoid this complexity level, we take advantage that CV is divided
5352 * by a constant. From the Euclids division algorithm, we know that CV
5353 * can be written as: CV = 32*q + r. Next, we replace CV in the
5354 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5355 * need to pre-compute the value of r/32. For pre-computing the values
5356 * We just used the following Ruby line:
5357 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5358 * The results of the above expressions can be verified at
5359 * pre_computed_values.
5363 max = (1 << q) * pre_computed_values[r];
5365 /* min luminance: maxLum * (CV/255)^2 / 100 */
5366 q = DIV_ROUND_CLOSEST(min_cll, 255);
5367 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5369 luminance_range->min_luminance = min;
5370 luminance_range->max_luminance = max;
5373 static uint8_t eotf_supported(const u8 *edid_ext)
5375 return edid_ext[2] &
5376 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5377 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5378 BIT(HDMI_EOTF_SMPTE_ST2084) |
5379 BIT(HDMI_EOTF_BT_2100_HLG));
5382 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5384 return edid_ext[3] &
5385 BIT(HDMI_STATIC_METADATA_TYPE1);
5389 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5393 len = cea_db_payload_len(db);
5395 connector->hdr_sink_metadata.hdmi_type1.eotf =
5397 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5398 hdr_metadata_type(db);
5401 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5403 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5405 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5407 /* Calculate only when all values are available */
5408 drm_calculate_luminance_range(connector);
5412 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5414 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5416 u8 len = cea_db_payload_len(db);
5418 if (len >= 6 && (db[6] & (1 << 7)))
5419 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5421 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5422 connector->latency_present[0] = true;
5423 connector->video_latency[0] = db[9];
5424 connector->audio_latency[0] = db[10];
5427 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5428 connector->latency_present[1] = true;
5429 connector->video_latency[1] = db[11];
5430 connector->audio_latency[1] = db[12];
5433 drm_dbg_kms(connector->dev,
5434 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5435 connector->base.id, connector->name,
5436 connector->latency_present[0], connector->latency_present[1],
5437 connector->video_latency[0], connector->video_latency[1],
5438 connector->audio_latency[0], connector->audio_latency[1]);
5442 monitor_name(const struct detailed_timing *timing, void *data)
5444 const char **res = data;
5446 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5449 *res = timing->data.other_data.data.str.str;
5452 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5454 const char *edid_name = NULL;
5457 if (!drm_edid || !name)
5460 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5461 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5462 if (edid_name[mnl] == 0x0a)
5465 name[mnl] = edid_name[mnl];
5472 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5473 * @edid: monitor EDID information
5474 * @name: pointer to a character array to hold the name of the monitor
5475 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5478 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5480 int name_length = 0;
5487 struct drm_edid drm_edid = {
5489 .size = edid_size(edid),
5492 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5493 memcpy(name, buf, name_length);
5496 name[name_length] = '\0';
5498 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5500 static void clear_eld(struct drm_connector *connector)
5502 memset(connector->eld, 0, sizeof(connector->eld));
5504 connector->latency_present[0] = false;
5505 connector->latency_present[1] = false;
5506 connector->video_latency[0] = 0;
5507 connector->audio_latency[0] = 0;
5508 connector->video_latency[1] = 0;
5509 connector->audio_latency[1] = 0;
5513 * drm_edid_to_eld - build ELD from EDID
5514 * @connector: connector corresponding to the HDMI/DP sink
5515 * @drm_edid: EDID to parse
5517 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5518 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5520 static void drm_edid_to_eld(struct drm_connector *connector,
5521 const struct drm_edid *drm_edid)
5523 const struct drm_display_info *info = &connector->display_info;
5524 const struct cea_db *db;
5525 struct cea_db_iter iter;
5526 uint8_t *eld = connector->eld;
5527 int total_sad_count = 0;
5533 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5534 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5535 connector->base.id, connector->name,
5536 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5538 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5539 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5541 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5543 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5544 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5545 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5546 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5548 cea_db_iter_edid_begin(drm_edid, &iter);
5549 cea_db_iter_for_each(db, &iter) {
5550 const u8 *data = cea_db_data(db);
5551 int len = cea_db_payload_len(db);
5554 switch (cea_db_tag(db)) {
5556 /* Audio Data Block, contains SADs */
5557 sad_count = min(len / 3, 15 - total_sad_count);
5559 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5560 data, sad_count * 3);
5561 total_sad_count += sad_count;
5563 case CTA_DB_SPEAKER:
5564 /* Speaker Allocation Data Block */
5566 eld[DRM_ELD_SPEAKER] = data[0];
5569 /* HDMI Vendor-Specific Data Block */
5570 if (cea_db_is_hdmi_vsdb(db))
5571 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5577 cea_db_iter_end(&iter);
5579 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5581 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5582 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5583 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5585 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5587 eld[DRM_ELD_BASELINE_ELD_LEN] =
5588 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5590 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5591 connector->base.id, connector->name,
5592 drm_eld_size(eld), total_sad_count);
5595 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5596 struct cea_sad **sads)
5598 const struct cea_db *db;
5599 struct cea_db_iter iter;
5602 cea_db_iter_edid_begin(drm_edid, &iter);
5603 cea_db_iter_for_each(db, &iter) {
5604 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5607 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5608 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5611 for (j = 0; j < count; j++) {
5612 const u8 *sad = &db->data[j * 3];
5614 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5615 (*sads)[j].channels = sad[0] & 0x7;
5616 (*sads)[j].freq = sad[1] & 0x7F;
5617 (*sads)[j].byte2 = sad[2];
5622 cea_db_iter_end(&iter);
5624 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5630 * drm_edid_to_sad - extracts SADs from EDID
5631 * @edid: EDID to parse
5632 * @sads: pointer that will be set to the extracted SADs
5634 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5636 * Note: The returned pointer needs to be freed using kfree().
5638 * Return: The number of found SADs or negative number on error.
5640 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5642 struct drm_edid drm_edid;
5644 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5646 EXPORT_SYMBOL(drm_edid_to_sad);
5648 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5651 const struct cea_db *db;
5652 struct cea_db_iter iter;
5655 cea_db_iter_edid_begin(drm_edid, &iter);
5656 cea_db_iter_for_each(db, &iter) {
5657 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5658 cea_db_payload_len(db) == 3) {
5659 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5663 count = cea_db_payload_len(db);
5667 cea_db_iter_end(&iter);
5669 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5675 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5676 * @edid: EDID to parse
5677 * @sadb: pointer to the speaker block
5679 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5681 * Note: The returned pointer needs to be freed using kfree().
5683 * Return: The number of found Speaker Allocation Blocks or negative number on
5686 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5688 struct drm_edid drm_edid;
5690 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5693 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5696 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5697 * @connector: connector associated with the HDMI/DP sink
5698 * @mode: the display mode
5700 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5701 * the sink doesn't support audio or video.
5703 int drm_av_sync_delay(struct drm_connector *connector,
5704 const struct drm_display_mode *mode)
5706 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5709 if (!connector->latency_present[0])
5711 if (!connector->latency_present[1])
5714 a = connector->audio_latency[i];
5715 v = connector->video_latency[i];
5718 * HDMI/DP sink doesn't support audio or video?
5720 if (a == 255 || v == 255)
5724 * Convert raw EDID values to millisecond.
5725 * Treat unknown latency as 0ms.
5728 a = min(2 * (a - 1), 500);
5730 v = min(2 * (v - 1), 500);
5732 return max(v - a, 0);
5734 EXPORT_SYMBOL(drm_av_sync_delay);
5736 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5738 const struct cea_db *db;
5739 struct cea_db_iter iter;
5743 * Because HDMI identifier is in Vendor Specific Block,
5744 * search it from all data blocks of CEA extension.
5746 cea_db_iter_edid_begin(drm_edid, &iter);
5747 cea_db_iter_for_each(db, &iter) {
5748 if (cea_db_is_hdmi_vsdb(db)) {
5753 cea_db_iter_end(&iter);
5759 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5760 * @edid: monitor EDID information
5762 * Parse the CEA extension according to CEA-861-B.
5764 * Drivers that have added the modes parsed from EDID to drm_display_info
5765 * should use &drm_display_info.is_hdmi instead of calling this function.
5767 * Return: True if the monitor is HDMI, false if not or unknown.
5769 bool drm_detect_hdmi_monitor(const struct edid *edid)
5771 struct drm_edid drm_edid;
5773 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5775 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5777 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5779 struct drm_edid_iter edid_iter;
5780 const struct cea_db *db;
5781 struct cea_db_iter iter;
5783 bool has_audio = false;
5785 drm_edid_iter_begin(drm_edid, &edid_iter);
5786 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5787 if (edid_ext[0] == CEA_EXT) {
5788 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5793 drm_edid_iter_end(&edid_iter);
5796 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5800 cea_db_iter_edid_begin(drm_edid, &iter);
5801 cea_db_iter_for_each(db, &iter) {
5802 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5803 const u8 *data = cea_db_data(db);
5806 for (i = 0; i < cea_db_payload_len(db); i += 3)
5807 DRM_DEBUG_KMS("CEA audio format %d\n",
5808 (data[i] >> 3) & 0xf);
5813 cea_db_iter_end(&iter);
5820 * drm_detect_monitor_audio - check monitor audio capability
5821 * @edid: EDID block to scan
5823 * Monitor should have CEA extension block.
5824 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5825 * audio' only. If there is any audio extension block and supported
5826 * audio format, assume at least 'basic audio' support, even if 'basic
5827 * audio' is not defined in EDID.
5829 * Return: True if the monitor supports audio, false otherwise.
5831 bool drm_detect_monitor_audio(const struct edid *edid)
5833 struct drm_edid drm_edid;
5835 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5837 EXPORT_SYMBOL(drm_detect_monitor_audio);
5841 * drm_default_rgb_quant_range - default RGB quantization range
5842 * @mode: display mode
5844 * Determine the default RGB quantization range for the mode,
5845 * as specified in CEA-861.
5847 * Return: The default RGB quantization range for the mode
5849 enum hdmi_quantization_range
5850 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5852 /* All CEA modes other than VIC 1 use limited quantization range. */
5853 return drm_match_cea_mode(mode) > 1 ?
5854 HDMI_QUANTIZATION_RANGE_LIMITED :
5855 HDMI_QUANTIZATION_RANGE_FULL;
5857 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5859 /* CTA-861 Video Data Block (CTA VDB) */
5860 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5862 struct drm_display_info *info = &connector->display_info;
5863 int i, vic_index, len = cea_db_payload_len(db);
5864 const u8 *svds = cea_db_data(db);
5870 /* Gracefully handle multiple VDBs, however unlikely that is */
5871 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5875 vic_index = info->vics_len;
5876 info->vics_len += len;
5879 for (i = 0; i < len; i++) {
5880 u8 vic = svd_to_vic(svds[i]);
5882 if (!drm_valid_cea_vic(vic))
5885 info->vics[vic_index++] = vic;
5890 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5892 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5893 * using the VICs themselves.
5895 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5897 struct drm_display_info *info = &connector->display_info;
5898 struct drm_hdmi_info *hdmi = &info->hdmi;
5899 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5901 for (i = 0; i < len; i++) {
5902 u8 vic = info->vics[i];
5904 if (vic && y420cmdb_map & BIT_ULL(i))
5905 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5909 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5911 const struct drm_display_info *info = &connector->display_info;
5914 if (!vic || !info->vics)
5917 for (i = 0; i < info->vics_len; i++) {
5918 if (info->vics[i] == vic)
5925 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5926 static void parse_cta_y420vdb(struct drm_connector *connector,
5927 const struct cea_db *db)
5929 struct drm_display_info *info = &connector->display_info;
5930 struct drm_hdmi_info *hdmi = &info->hdmi;
5931 const u8 *svds = cea_db_data(db) + 1;
5934 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5935 u8 vic = svd_to_vic(svds[i]);
5937 if (!drm_valid_cea_vic(vic))
5940 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5941 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5945 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5947 struct drm_display_info *info = &connector->display_info;
5949 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5950 connector->base.id, connector->name, db[2]);
5952 if (db[2] & EDID_CEA_VCDB_QS)
5953 info->rgb_quant_range_selectable = true;
5957 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5959 switch (max_frl_rate) {
5962 *max_rate_per_lane = 3;
5966 *max_rate_per_lane = 6;
5970 *max_rate_per_lane = 6;
5974 *max_rate_per_lane = 8;
5978 *max_rate_per_lane = 10;
5982 *max_rate_per_lane = 12;
5987 *max_rate_per_lane = 0;
5991 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5995 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5997 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5998 hdmi->y420_dc_modes = dc_mask;
6001 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6004 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6006 if (!hdmi_dsc->v_1p2)
6009 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6010 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6012 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6013 hdmi_dsc->bpc_supported = 16;
6014 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6015 hdmi_dsc->bpc_supported = 12;
6016 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6017 hdmi_dsc->bpc_supported = 10;
6019 /* Supports min 8 BPC if DSC 1.2 is supported*/
6020 hdmi_dsc->bpc_supported = 8;
6022 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6024 u8 dsc_max_frl_rate;
6026 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6027 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6028 &hdmi_dsc->max_frl_rate_per_lane);
6030 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6032 switch (dsc_max_slices) {
6034 hdmi_dsc->max_slices = 1;
6035 hdmi_dsc->clk_per_slice = 340;
6038 hdmi_dsc->max_slices = 2;
6039 hdmi_dsc->clk_per_slice = 340;
6042 hdmi_dsc->max_slices = 4;
6043 hdmi_dsc->clk_per_slice = 340;
6046 hdmi_dsc->max_slices = 8;
6047 hdmi_dsc->clk_per_slice = 340;
6050 hdmi_dsc->max_slices = 8;
6051 hdmi_dsc->clk_per_slice = 400;
6054 hdmi_dsc->max_slices = 12;
6055 hdmi_dsc->clk_per_slice = 400;
6058 hdmi_dsc->max_slices = 16;
6059 hdmi_dsc->clk_per_slice = 400;
6063 hdmi_dsc->max_slices = 0;
6064 hdmi_dsc->clk_per_slice = 0;
6068 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6069 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6072 /* Sink Capability Data Structure */
6073 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6076 struct drm_display_info *info = &connector->display_info;
6077 struct drm_hdmi_info *hdmi = &info->hdmi;
6078 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6079 int max_tmds_clock = 0;
6080 u8 max_frl_rate = 0;
6081 bool dsc_support = false;
6083 info->has_hdmi_infoframe = true;
6085 if (hf_scds[6] & 0x80) {
6086 hdmi->scdc.supported = true;
6087 if (hf_scds[6] & 0x40)
6088 hdmi->scdc.read_request = true;
6092 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6093 * And as per the spec, three factors confirm this:
6094 * * Availability of a HF-VSDB block in EDID (check)
6095 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6096 * * SCDC support available (let's check)
6097 * Lets check it out.
6101 struct drm_scdc *scdc = &hdmi->scdc;
6103 /* max clock is 5000 KHz times block value */
6104 max_tmds_clock = hf_scds[5] * 5000;
6106 if (max_tmds_clock > 340000) {
6107 info->max_tmds_clock = max_tmds_clock;
6110 if (scdc->supported) {
6111 scdc->scrambling.supported = true;
6113 /* Few sinks support scrambling for clocks < 340M */
6114 if ((hf_scds[6] & 0x8))
6115 scdc->scrambling.low_rates = true;
6120 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6121 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6122 &hdmi->max_frl_rate_per_lane);
6125 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6127 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6128 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6132 drm_dbg_kms(connector->dev,
6133 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6134 connector->base.id, connector->name,
6135 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6138 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6141 struct drm_display_info *info = &connector->display_info;
6142 unsigned int dc_bpc = 0;
6144 /* HDMI supports at least 8 bpc */
6147 if (cea_db_payload_len(hdmi) < 6)
6150 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6152 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6153 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6154 connector->base.id, connector->name);
6157 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6159 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6160 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6161 connector->base.id, connector->name);
6164 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6166 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6167 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6168 connector->base.id, connector->name);
6172 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6173 connector->base.id, connector->name);
6177 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6178 connector->base.id, connector->name, dc_bpc);
6181 /* YCRCB444 is optional according to spec. */
6182 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6183 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6184 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6185 connector->base.id, connector->name);
6189 * Spec says that if any deep color mode is supported at all,
6190 * then deep color 36 bit must be supported.
6192 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6193 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6194 connector->base.id, connector->name);
6198 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6200 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6202 struct drm_display_info *info = &connector->display_info;
6203 u8 len = cea_db_payload_len(db);
6205 info->is_hdmi = true;
6207 info->source_physical_address = (db[4] << 8) | db[5];
6210 info->dvi_dual = db[6] & 1;
6212 info->max_tmds_clock = db[7] * 5000;
6215 * Try to infer whether the sink supports HDMI infoframes.
6217 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6218 * supports infoframes if HDMI_Video_present is set.
6220 if (len >= 8 && db[8] & BIT(5))
6221 info->has_hdmi_infoframe = true;
6223 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6224 connector->base.id, connector->name,
6225 info->dvi_dual, info->max_tmds_clock);
6227 drm_parse_hdmi_deep_color_info(connector, db);
6231 * See EDID extension for head-mounted and specialized monitors, specified at:
6232 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6234 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6237 struct drm_display_info *info = &connector->display_info;
6239 bool desktop_usage = db[5] & BIT(6);
6241 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6242 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6243 info->non_desktop = true;
6245 drm_dbg_kms(connector->dev,
6246 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6247 connector->base.id, connector->name, version, db[5]);
6250 static void drm_parse_cea_ext(struct drm_connector *connector,
6251 const struct drm_edid *drm_edid)
6253 struct drm_display_info *info = &connector->display_info;
6254 struct drm_edid_iter edid_iter;
6255 const struct cea_db *db;
6256 struct cea_db_iter iter;
6258 u64 y420cmdb_map = 0;
6260 drm_edid_iter_begin(drm_edid, &edid_iter);
6261 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6262 if (edid_ext[0] != CEA_EXT)
6266 info->cea_rev = edid_ext[1];
6268 if (info->cea_rev != edid_ext[1])
6269 drm_dbg_kms(connector->dev,
6270 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6271 connector->base.id, connector->name,
6272 info->cea_rev, edid_ext[1]);
6274 /* The existence of a CTA extension should imply RGB support */
6275 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6276 if (edid_ext[3] & EDID_CEA_YCRCB444)
6277 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6278 if (edid_ext[3] & EDID_CEA_YCRCB422)
6279 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6280 if (edid_ext[3] & EDID_BASIC_AUDIO)
6281 info->has_audio = true;
6284 drm_edid_iter_end(&edid_iter);
6286 cea_db_iter_edid_begin(drm_edid, &iter);
6287 cea_db_iter_for_each(db, &iter) {
6288 /* FIXME: convert parsers to use struct cea_db */
6289 const u8 *data = (const u8 *)db;
6291 if (cea_db_is_hdmi_vsdb(db))
6292 drm_parse_hdmi_vsdb_video(connector, data);
6293 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6294 cea_db_is_hdmi_forum_scdb(db))
6295 drm_parse_hdmi_forum_scds(connector, data);
6296 else if (cea_db_is_microsoft_vsdb(db))
6297 drm_parse_microsoft_vsdb(connector, data);
6298 else if (cea_db_is_y420cmdb(db))
6299 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6300 else if (cea_db_is_y420vdb(db))
6301 parse_cta_y420vdb(connector, db);
6302 else if (cea_db_is_vcdb(db))
6303 drm_parse_vcdb(connector, data);
6304 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6305 drm_parse_hdr_metadata_block(connector, data);
6306 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6307 parse_cta_vdb(connector, db);
6308 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6309 info->has_audio = true;
6311 cea_db_iter_end(&iter);
6314 update_cta_y420cmdb(connector, y420cmdb_map);
6318 void get_monitor_range(const struct detailed_timing *timing, void *c)
6320 struct detailed_mode_closure *closure = c;
6321 struct drm_display_info *info = &closure->connector->display_info;
6322 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6323 const struct detailed_non_pixel *data = &timing->data.other_data;
6324 const struct detailed_data_monitor_range *range = &data->data.range;
6325 const struct edid *edid = closure->drm_edid->edid;
6327 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6331 * These limits are used to determine the VRR refresh
6332 * rate range. Only the "range limits only" variant
6333 * of the range descriptor seems to guarantee that
6334 * any and all timings are accepted by the sink, as
6335 * opposed to just timings conforming to the indicated
6336 * formula (GTF/GTF2/CVT). Thus other variants of the
6337 * range descriptor are not accepted here.
6339 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6342 monitor_range->min_vfreq = range->min_vfreq;
6343 monitor_range->max_vfreq = range->max_vfreq;
6345 if (edid->revision >= 4) {
6346 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6347 monitor_range->min_vfreq += 255;
6348 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6349 monitor_range->max_vfreq += 255;
6353 static void drm_get_monitor_range(struct drm_connector *connector,
6354 const struct drm_edid *drm_edid)
6356 const struct drm_display_info *info = &connector->display_info;
6357 struct detailed_mode_closure closure = {
6358 .connector = connector,
6359 .drm_edid = drm_edid,
6362 if (drm_edid->edid->revision < 4)
6365 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6368 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6370 drm_dbg_kms(connector->dev,
6371 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6372 connector->base.id, connector->name,
6373 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6376 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6377 const struct displayid_block *block)
6379 struct displayid_vesa_vendor_specific_block *vesa =
6380 (struct displayid_vesa_vendor_specific_block *)block;
6381 struct drm_display_info *info = &connector->display_info;
6383 if (block->num_bytes < 3) {
6384 drm_dbg_kms(connector->dev,
6385 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6386 connector->base.id, connector->name, block->num_bytes);
6390 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6393 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6394 drm_dbg_kms(connector->dev,
6395 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6396 connector->base.id, connector->name);
6400 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6402 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6403 connector->base.id, connector->name);
6406 info->mso_stream_count = 0;
6409 info->mso_stream_count = 2; /* 2 or 4 links */
6412 info->mso_stream_count = 4; /* 4 links */
6416 if (!info->mso_stream_count) {
6417 info->mso_pixel_overlap = 0;
6421 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6422 if (info->mso_pixel_overlap > 8) {
6423 drm_dbg_kms(connector->dev,
6424 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6425 connector->base.id, connector->name,
6426 info->mso_pixel_overlap);
6427 info->mso_pixel_overlap = 8;
6430 drm_dbg_kms(connector->dev,
6431 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6432 connector->base.id, connector->name,
6433 info->mso_stream_count, info->mso_pixel_overlap);
6436 static void drm_update_mso(struct drm_connector *connector,
6437 const struct drm_edid *drm_edid)
6439 const struct displayid_block *block;
6440 struct displayid_iter iter;
6442 displayid_iter_edid_begin(drm_edid, &iter);
6443 displayid_iter_for_each(block, &iter) {
6444 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6445 drm_parse_vesa_mso_data(connector, block);
6447 displayid_iter_end(&iter);
6450 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6451 * all of the values which would have been set from EDID
6453 static void drm_reset_display_info(struct drm_connector *connector)
6455 struct drm_display_info *info = &connector->display_info;
6458 info->height_mm = 0;
6461 info->color_formats = 0;
6463 info->max_tmds_clock = 0;
6464 info->dvi_dual = false;
6465 info->is_hdmi = false;
6466 info->has_audio = false;
6467 info->has_hdmi_infoframe = false;
6468 info->rgb_quant_range_selectable = false;
6469 memset(&info->hdmi, 0, sizeof(info->hdmi));
6471 info->edid_hdmi_rgb444_dc_modes = 0;
6472 info->edid_hdmi_ycbcr444_dc_modes = 0;
6474 info->non_desktop = 0;
6475 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6476 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6478 info->mso_stream_count = 0;
6479 info->mso_pixel_overlap = 0;
6480 info->max_dsc_bpp = 0;
6488 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6491 static void update_displayid_info(struct drm_connector *connector,
6492 const struct drm_edid *drm_edid)
6494 struct drm_display_info *info = &connector->display_info;
6495 const struct displayid_block *block;
6496 struct displayid_iter iter;
6498 displayid_iter_edid_begin(drm_edid, &iter);
6499 displayid_iter_for_each(block, &iter) {
6500 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6501 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6502 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6503 info->non_desktop = true;
6506 * We're only interested in the base section here, no need to
6511 displayid_iter_end(&iter);
6514 static void update_display_info(struct drm_connector *connector,
6515 const struct drm_edid *drm_edid)
6517 struct drm_display_info *info = &connector->display_info;
6518 const struct edid *edid;
6520 drm_reset_display_info(connector);
6521 clear_eld(connector);
6526 edid = drm_edid->edid;
6528 info->quirks = edid_get_quirks(drm_edid);
6530 info->width_mm = edid->width_cm * 10;
6531 info->height_mm = edid->height_cm * 10;
6533 drm_get_monitor_range(connector, drm_edid);
6535 if (edid->revision < 3)
6538 if (!drm_edid_is_digital(drm_edid))
6541 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6542 drm_parse_cea_ext(connector, drm_edid);
6544 update_displayid_info(connector, drm_edid);
6547 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6549 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6550 * tells us to assume 8 bpc color depth if the EDID doesn't have
6551 * extensions which tell otherwise.
6553 if (info->bpc == 0 && edid->revision == 3 &&
6554 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6556 drm_dbg_kms(connector->dev,
6557 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6558 connector->base.id, connector->name, info->bpc);
6561 /* Only defined for 1.4 with digital displays */
6562 if (edid->revision < 4)
6565 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6566 case DRM_EDID_DIGITAL_DEPTH_6:
6569 case DRM_EDID_DIGITAL_DEPTH_8:
6572 case DRM_EDID_DIGITAL_DEPTH_10:
6575 case DRM_EDID_DIGITAL_DEPTH_12:
6578 case DRM_EDID_DIGITAL_DEPTH_14:
6581 case DRM_EDID_DIGITAL_DEPTH_16:
6584 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6590 drm_dbg_kms(connector->dev,
6591 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6592 connector->base.id, connector->name, info->bpc);
6594 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6595 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6596 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6597 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6599 drm_update_mso(connector, drm_edid);
6602 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6603 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6604 connector->base.id, connector->name,
6605 info->non_desktop ? " (redundant quirk)" : "");
6606 info->non_desktop = true;
6609 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6610 info->max_dsc_bpp = 15;
6612 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6615 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6618 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6621 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6624 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6625 drm_edid_to_eld(connector, drm_edid);
6628 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6629 struct displayid_detailed_timings_1 *timings,
6632 struct drm_display_mode *mode;
6633 unsigned pixel_clock = (timings->pixel_clock[0] |
6634 (timings->pixel_clock[1] << 8) |
6635 (timings->pixel_clock[2] << 16)) + 1;
6636 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6637 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6638 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6639 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6640 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6641 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6642 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6643 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6644 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6645 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6647 mode = drm_mode_create(dev);
6651 /* resolution is kHz for type VII, and 10 kHz for type I */
6652 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6653 mode->hdisplay = hactive;
6654 mode->hsync_start = mode->hdisplay + hsync;
6655 mode->hsync_end = mode->hsync_start + hsync_width;
6656 mode->htotal = mode->hdisplay + hblank;
6658 mode->vdisplay = vactive;
6659 mode->vsync_start = mode->vdisplay + vsync;
6660 mode->vsync_end = mode->vsync_start + vsync_width;
6661 mode->vtotal = mode->vdisplay + vblank;
6664 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6665 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6666 mode->type = DRM_MODE_TYPE_DRIVER;
6668 if (timings->flags & 0x80)
6669 mode->type |= DRM_MODE_TYPE_PREFERRED;
6670 drm_mode_set_name(mode);
6675 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6676 const struct displayid_block *block)
6678 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6681 struct drm_display_mode *newmode;
6683 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6684 /* blocks must be multiple of 20 bytes length */
6685 if (block->num_bytes % 20)
6688 num_timings = block->num_bytes / 20;
6689 for (i = 0; i < num_timings; i++) {
6690 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6692 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6696 drm_mode_probed_add(connector, newmode);
6702 static int add_displayid_detailed_modes(struct drm_connector *connector,
6703 const struct drm_edid *drm_edid)
6705 const struct displayid_block *block;
6706 struct displayid_iter iter;
6709 displayid_iter_edid_begin(drm_edid, &iter);
6710 displayid_iter_for_each(block, &iter) {
6711 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6712 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6713 num_modes += add_displayid_detailed_1_modes(connector, block);
6715 displayid_iter_end(&iter);
6720 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6721 const struct drm_edid *drm_edid)
6723 const struct drm_display_info *info = &connector->display_info;
6730 * EDID spec says modes should be preferred in this order:
6731 * - preferred detailed mode
6732 * - other detailed modes from base block
6733 * - detailed modes from extension blocks
6734 * - CVT 3-byte code modes
6735 * - standard timing codes
6736 * - established timing codes
6737 * - modes inferred from GTF or CVT range information
6739 * We get this pretty much right.
6741 * XXX order for additional mode types in extension blocks?
6743 num_modes += add_detailed_modes(connector, drm_edid);
6744 num_modes += add_cvt_modes(connector, drm_edid);
6745 num_modes += add_standard_modes(connector, drm_edid);
6746 num_modes += add_established_modes(connector, drm_edid);
6747 num_modes += add_cea_modes(connector, drm_edid);
6748 num_modes += add_alternate_cea_modes(connector, drm_edid);
6749 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6750 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6751 num_modes += add_inferred_modes(connector, drm_edid);
6753 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6754 edid_fixup_preferred(connector);
6759 static void _drm_update_tile_info(struct drm_connector *connector,
6760 const struct drm_edid *drm_edid);
6762 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6763 const struct drm_edid *drm_edid)
6765 struct drm_device *dev = connector->dev;
6768 if (connector->edid_blob_ptr) {
6769 const struct edid *old_edid = connector->edid_blob_ptr->data;
6772 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6773 connector->epoch_counter++;
6774 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6775 connector->base.id, connector->name,
6776 connector->epoch_counter);
6781 ret = drm_property_replace_global_blob(dev,
6782 &connector->edid_blob_ptr,
6783 drm_edid ? drm_edid->size : 0,
6784 drm_edid ? drm_edid->edid : NULL,
6786 dev->mode_config.edid_property);
6788 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6789 connector->base.id, connector->name, ret);
6793 ret = drm_object_property_set_value(&connector->base,
6794 dev->mode_config.non_desktop_property,
6795 connector->display_info.non_desktop);
6797 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6798 connector->base.id, connector->name, ret);
6802 ret = drm_connector_set_tile_property(connector);
6804 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6805 connector->base.id, connector->name, ret);
6814 * drm_edid_connector_update - Update connector information from EDID
6815 * @connector: Connector
6818 * Update the connector display info, ELD, HDR metadata, relevant properties,
6819 * etc. from the passed in EDID.
6821 * If EDID is NULL, reset the information.
6823 * Must be called before calling drm_edid_connector_add_modes().
6825 * Return: 0 on success, negative error on errors.
6827 int drm_edid_connector_update(struct drm_connector *connector,
6828 const struct drm_edid *drm_edid)
6830 update_display_info(connector, drm_edid);
6832 _drm_update_tile_info(connector, drm_edid);
6834 return _drm_edid_connector_property_update(connector, drm_edid);
6836 EXPORT_SYMBOL(drm_edid_connector_update);
6839 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6840 * @connector: Connector
6842 * Add the modes from the previously updated EDID property to the connector
6843 * probed modes list.
6845 * drm_edid_connector_update() must have been called before this to update the
6848 * Return: The number of modes added, or 0 if we couldn't find any.
6850 int drm_edid_connector_add_modes(struct drm_connector *connector)
6852 const struct drm_edid *drm_edid = NULL;
6855 if (connector->edid_blob_ptr)
6856 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6857 connector->edid_blob_ptr->length);
6859 count = _drm_edid_connector_add_modes(connector, drm_edid);
6861 drm_edid_free(drm_edid);
6865 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6868 * drm_connector_update_edid_property - update the edid property of a connector
6869 * @connector: drm connector
6870 * @edid: new value of the edid property
6872 * This function creates a new blob modeset object and assigns its id to the
6873 * connector's edid property.
6874 * Since we also parse tile information from EDID's displayID block, we also
6875 * set the connector's tile property here. See drm_connector_set_tile_property()
6878 * This function is deprecated. Use drm_edid_connector_update() instead.
6881 * Zero on success, negative errno on failure.
6883 int drm_connector_update_edid_property(struct drm_connector *connector,
6884 const struct edid *edid)
6886 struct drm_edid drm_edid;
6888 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6890 EXPORT_SYMBOL(drm_connector_update_edid_property);
6893 * drm_add_edid_modes - add modes from EDID data, if available
6894 * @connector: connector we're probing
6897 * Add the specified modes to the connector's mode list. Also fills out the
6898 * &drm_display_info structure and ELD in @connector with any information which
6899 * can be derived from the edid.
6901 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6903 * Return: The number of modes added or 0 if we couldn't find any.
6905 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6907 struct drm_edid _drm_edid;
6908 const struct drm_edid *drm_edid;
6910 if (edid && !drm_edid_is_valid(edid)) {
6911 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6912 connector->base.id, connector->name);
6916 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6918 update_display_info(connector, drm_edid);
6920 return _drm_edid_connector_add_modes(connector, drm_edid);
6922 EXPORT_SYMBOL(drm_add_edid_modes);
6925 * drm_add_modes_noedid - add modes for the connectors without EDID
6926 * @connector: connector we're probing
6927 * @hdisplay: the horizontal display limit
6928 * @vdisplay: the vertical display limit
6930 * Add the specified modes to the connector's mode list. Only when the
6931 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6933 * Return: The number of modes added or 0 if we couldn't find any.
6935 int drm_add_modes_noedid(struct drm_connector *connector,
6936 int hdisplay, int vdisplay)
6938 int i, count, num_modes = 0;
6939 struct drm_display_mode *mode;
6940 struct drm_device *dev = connector->dev;
6942 count = ARRAY_SIZE(drm_dmt_modes);
6948 for (i = 0; i < count; i++) {
6949 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6951 if (hdisplay && vdisplay) {
6953 * Only when two are valid, they will be used to check
6954 * whether the mode should be added to the mode list of
6957 if (ptr->hdisplay > hdisplay ||
6958 ptr->vdisplay > vdisplay)
6961 if (drm_mode_vrefresh(ptr) > 61)
6963 mode = drm_mode_duplicate(dev, ptr);
6965 drm_mode_probed_add(connector, mode);
6971 EXPORT_SYMBOL(drm_add_modes_noedid);
6974 * drm_set_preferred_mode - Sets the preferred mode of a connector
6975 * @connector: connector whose mode list should be processed
6976 * @hpref: horizontal resolution of preferred mode
6977 * @vpref: vertical resolution of preferred mode
6979 * Marks a mode as preferred if it matches the resolution specified by @hpref
6982 void drm_set_preferred_mode(struct drm_connector *connector,
6983 int hpref, int vpref)
6985 struct drm_display_mode *mode;
6987 list_for_each_entry(mode, &connector->probed_modes, head) {
6988 if (mode->hdisplay == hpref &&
6989 mode->vdisplay == vpref)
6990 mode->type |= DRM_MODE_TYPE_PREFERRED;
6993 EXPORT_SYMBOL(drm_set_preferred_mode);
6995 static bool is_hdmi2_sink(const struct drm_connector *connector)
6998 * FIXME: sil-sii8620 doesn't have a connector around when
6999 * we need one, so we have to be prepared for a NULL connector.
7004 return connector->display_info.hdmi.scdc.supported ||
7005 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7008 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7009 const struct drm_display_mode *mode)
7011 bool has_hdmi_infoframe = connector ?
7012 connector->display_info.has_hdmi_infoframe : false;
7014 if (!has_hdmi_infoframe)
7017 /* No HDMI VIC when signalling 3D video format */
7018 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7021 return drm_match_hdmi_mode(mode);
7024 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7025 const struct drm_display_mode *mode)
7028 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7029 * we should send its VIC in vendor infoframes, else send the
7030 * VIC in AVI infoframes. Lets check if this mode is present in
7031 * HDMI 1.4b 4K modes
7033 if (drm_mode_hdmi_vic(connector, mode))
7036 return drm_match_cea_mode(mode);
7040 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7041 * conform to HDMI 1.4.
7043 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7044 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7046 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7049 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7051 if (!is_hdmi2_sink(connector) && vic > 64 &&
7052 !cta_vdb_has_vic(connector, vic))
7059 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7060 * data from a DRM display mode
7061 * @frame: HDMI AVI infoframe
7062 * @connector: the connector
7063 * @mode: DRM display mode
7065 * Return: 0 on success or a negative error code on failure.
7068 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7069 const struct drm_connector *connector,
7070 const struct drm_display_mode *mode)
7072 enum hdmi_picture_aspect picture_aspect;
7075 if (!frame || !mode)
7078 hdmi_avi_infoframe_init(frame);
7080 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7081 frame->pixel_repeat = 1;
7083 vic = drm_mode_cea_vic(connector, mode);
7084 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7086 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7089 * As some drivers don't support atomic, we can't use connector state.
7090 * So just initialize the frame with default values, just the same way
7091 * as it's done with other properties here.
7093 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7097 * Populate picture aspect ratio from either
7098 * user input (if specified) or from the CEA/HDMI mode lists.
7100 picture_aspect = mode->picture_aspect_ratio;
7101 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7103 picture_aspect = drm_get_cea_aspect_ratio(vic);
7105 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7109 * The infoframe can't convey anything but none, 4:3
7110 * and 16:9, so if the user has asked for anything else
7111 * we can only satisfy it by specifying the right VIC.
7113 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7115 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7117 } else if (hdmi_vic) {
7118 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7124 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7127 frame->video_code = vic_for_avi_infoframe(connector, vic);
7128 frame->picture_aspect = picture_aspect;
7129 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7130 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7134 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7137 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7138 * quantization range information
7139 * @frame: HDMI AVI infoframe
7140 * @connector: the connector
7141 * @mode: DRM display mode
7142 * @rgb_quant_range: RGB quantization range (Q)
7145 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7146 const struct drm_connector *connector,
7147 const struct drm_display_mode *mode,
7148 enum hdmi_quantization_range rgb_quant_range)
7150 const struct drm_display_info *info = &connector->display_info;
7154 * "A Source shall not send a non-zero Q value that does not correspond
7155 * to the default RGB Quantization Range for the transmitted Picture
7156 * unless the Sink indicates support for the Q bit in a Video
7157 * Capabilities Data Block."
7159 * HDMI 2.0 recommends sending non-zero Q when it does match the
7160 * default RGB quantization range for the mode, even when QS=0.
7162 if (info->rgb_quant_range_selectable ||
7163 rgb_quant_range == drm_default_rgb_quant_range(mode))
7164 frame->quantization_range = rgb_quant_range;
7166 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7170 * "When transmitting any RGB colorimetry, the Source should set the
7171 * YQ-field to match the RGB Quantization Range being transmitted
7172 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7173 * set YQ=1) and the Sink shall ignore the YQ-field."
7175 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7176 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7177 * good way to tell which version of CEA-861 the sink supports, so
7178 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7181 if (!is_hdmi2_sink(connector) ||
7182 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7183 frame->ycc_quantization_range =
7184 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7186 frame->ycc_quantization_range =
7187 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7189 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7191 static enum hdmi_3d_structure
7192 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7194 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7197 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7198 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7199 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7200 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7201 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7202 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7203 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7204 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7205 case DRM_MODE_FLAG_3D_L_DEPTH:
7206 return HDMI_3D_STRUCTURE_L_DEPTH;
7207 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7208 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7209 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7210 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7211 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7212 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7214 return HDMI_3D_STRUCTURE_INVALID;
7219 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7220 * data from a DRM display mode
7221 * @frame: HDMI vendor infoframe
7222 * @connector: the connector
7223 * @mode: DRM display mode
7225 * Note that there's is a need to send HDMI vendor infoframes only when using a
7226 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7227 * function will return -EINVAL, error that can be safely ignored.
7229 * Return: 0 on success or a negative error code on failure.
7232 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7233 const struct drm_connector *connector,
7234 const struct drm_display_mode *mode)
7237 * FIXME: sil-sii8620 doesn't have a connector around when
7238 * we need one, so we have to be prepared for a NULL connector.
7240 bool has_hdmi_infoframe = connector ?
7241 connector->display_info.has_hdmi_infoframe : false;
7244 if (!frame || !mode)
7247 if (!has_hdmi_infoframe)
7250 err = hdmi_vendor_infoframe_init(frame);
7255 * Even if it's not absolutely necessary to send the infoframe
7256 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7257 * know that the sink can handle it. This is based on a
7258 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7259 * have trouble realizing that they should switch from 3D to 2D
7260 * mode if the source simply stops sending the infoframe when
7261 * it wants to switch from 3D to 2D.
7263 frame->vic = drm_mode_hdmi_vic(connector, mode);
7264 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7268 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7270 static void drm_parse_tiled_block(struct drm_connector *connector,
7271 const struct displayid_block *block)
7273 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7275 u8 tile_v_loc, tile_h_loc;
7276 u8 num_v_tile, num_h_tile;
7277 struct drm_tile_group *tg;
7279 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7280 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7282 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7283 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7284 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7285 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7287 connector->has_tile = true;
7288 if (tile->tile_cap & 0x80)
7289 connector->tile_is_single_monitor = true;
7291 connector->num_h_tile = num_h_tile + 1;
7292 connector->num_v_tile = num_v_tile + 1;
7293 connector->tile_h_loc = tile_h_loc;
7294 connector->tile_v_loc = tile_v_loc;
7295 connector->tile_h_size = w + 1;
7296 connector->tile_v_size = h + 1;
7298 drm_dbg_kms(connector->dev,
7299 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7300 connector->base.id, connector->name,
7302 connector->tile_h_size, connector->tile_v_size,
7303 connector->num_h_tile, connector->num_v_tile,
7304 connector->tile_h_loc, connector->tile_v_loc,
7305 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7307 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7309 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7313 if (connector->tile_group != tg) {
7314 /* if we haven't got a pointer,
7315 take the reference, drop ref to old tile group */
7316 if (connector->tile_group)
7317 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7318 connector->tile_group = tg;
7320 /* if same tile group, then release the ref we just took. */
7321 drm_mode_put_tile_group(connector->dev, tg);
7325 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7326 const struct displayid_block *block)
7328 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7329 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7330 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7331 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7334 static void _drm_update_tile_info(struct drm_connector *connector,
7335 const struct drm_edid *drm_edid)
7337 const struct displayid_block *block;
7338 struct displayid_iter iter;
7340 connector->has_tile = false;
7342 displayid_iter_edid_begin(drm_edid, &iter);
7343 displayid_iter_for_each(block, &iter) {
7344 if (displayid_is_tiled_block(&iter, block))
7345 drm_parse_tiled_block(connector, block);
7347 displayid_iter_end(&iter);
7349 if (!connector->has_tile && connector->tile_group) {
7350 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7351 connector->tile_group = NULL;
7356 * drm_edid_is_digital - is digital?
7357 * @drm_edid: The EDID
7359 * Return true if input is digital.
7361 bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7363 return drm_edid && drm_edid->edid &&
7364 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7366 EXPORT_SYMBOL(drm_edid_is_digital);
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