drivers/scsi/mpt3sas/mpi/mpi2_ioc.h

   1 /*
   2  * Copyright 2000-2015 Avago Technologies.  All rights reserved.
   3  *
   4  *
   5  *          Name:  mpi2_ioc.h
   6  *         Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7  * Creation Date:  October 11, 2006
   8  *
   9  * mpi2_ioc.h Version:  02.00.26
  10  *
  11  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12  *       prefix are for use only on MPI v2.5 products, and must not be used
  13  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  14  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15  *
  16  * Version History
  17  * ---------------
  18  *
  19  * Date      Version   Description
  20  * --------  --------  ------------------------------------------------------
  21  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  22  * 06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  23  *                     MaxTargets.
  24  *                     Added TotalImageSize field to FWDownload Request.
  25  *                     Added reserved words to FWUpload Request.
  26  * 06-26-07  02.00.02  Added IR Configuration Change List Event.
  27  * 08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  28  *                     request and replaced it with
  29  *                     ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  30  *                     Replaced the MinReplyQueueDepth field of the IOCFacts
  31  *                     reply with MaxReplyDescriptorPostQueueDepth.
  32  *                     Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  33  *                     depth for the Reply Descriptor Post Queue.
  34  *                     Added SASAddress field to Initiator Device Table
  35  *                     Overflow Event data.
  36  * 10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  37  *                     for SAS Initiator Device Status Change Event data.
  38  *                     Modified Reason Code defines for SAS Topology Change
  39  *                     List Event data, including adding a bit for PHY Vacant
  40  *                     status, and adding a mask for the Reason Code.
  41  *                     Added define for
  42  *                     MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  43  *                     Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  44  * 12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  45  *                     the IOCFacts Reply.
  46  *                     Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  47  *                     Moved MPI2_VERSION_UNION to mpi2.h.
  48  *                     Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  49  *                     instead of enables, and added SASBroadcastPrimitiveMasks
  50  *                     field.
  51  *                     Added Log Entry Added Event and related structure.
  52  * 02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  53  *                     Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  54  *                     Added MaxVolumes and MaxPersistentEntries fields to
  55  *                     IOCFacts reply.
  56  *                     Added ProtocalFlags and IOCCapabilities fields to
  57  *                     MPI2_FW_IMAGE_HEADER.
  58  *                     Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  59  * 03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  60  *                     a U16 (from a U32).
  61  *                     Removed extra 's' from EventMasks name.
  62  * 06-27-08  02.00.08  Fixed an offset in a comment.
  63  * 10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  64  *                     Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  65  *                     renamed MinReplyFrameSize to ReplyFrameSize.
  66  *                     Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  67  *                     Added two new RAIDOperation values for Integrated RAID
  68  *                     Operations Status Event data.
  69  *                     Added four new IR Configuration Change List Event data
  70  *                     ReasonCode values.
  71  *                     Added two new ReasonCode defines for SAS Device Status
  72  *                     Change Event data.
  73  *                     Added three new DiscoveryStatus bits for the SAS
  74  *                     Discovery event data.
  75  *                     Added Multiplexing Status Change bit to the PhyStatus
  76  *                     field of the SAS Topology Change List event data.
  77  *                     Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  78  *                     BootFlags are now product-specific.
  79  *                     Added defines for the indivdual signature bytes
  80  *                     for MPI2_INIT_IMAGE_FOOTER.
  81  * 01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  82  *                     Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  83  *                     define.
  84  *                     Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  85  *                     define.
  86  *                     Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  87  * 05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  88  *                     Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  89  *                     Added two new reason codes for SAS Device Status Change
  90  *                     Event.
  91  *                     Added new event: SAS PHY Counter.
  92  * 07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  93  *                     Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  94  *                     Added new product id family for 2208.
  95  * 10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  96  *                     Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  97  *                     Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  98  *                     Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  99  *                     Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
 100  *                     Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
 101  *                     Added Host Based Discovery Phy Event data.
 102  *                     Added defines for ProductID Product field
 103  *                     (MPI2_FW_HEADER_PID_).
 104  *                     Modified values for SAS ProductID Family
 105  *                     (MPI2_FW_HEADER_PID_FAMILY_).
 106  * 02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 107  *                     Added PowerManagementControl Request structures and
 108  *                     defines.
 109  * 05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 110  *                     Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 111  * 11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 112  * 02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 113  *                     SASNotifyPrimitiveMasks field to
 114  *                     MPI2_EVENT_NOTIFICATION_REQUEST.
 115  *                     Added Temperature Threshold Event.
 116  *                     Added Host Message Event.
 117  *                     Added Send Host Message request and reply.
 118  * 05-25-11  02.00.18  For Extended Image Header, added
 119  *                     MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 120  *                     MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 121  *                     Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 122  * 08-24-11  02.00.19  Added PhysicalPort field to
 123  *                     MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 124  *                     Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 125  * 11-18-11  02.00.20  Incorporating additions for MPI v2.5.
 126  * 03-29-12  02.00.21  Added a product specific range to event values.
 127  * 07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 128  *                     Added ElapsedSeconds field to
 129  *                     MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 130  * 08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 131  *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 132  *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 133  *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 134  *                      Added Encrypted Hash Extended Image.
 135  * 12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
 136  * 11-18-14  02.00.25  Updated copyright information.
 137  * 03-16-15  02.00.26  Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
 138  *                     MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
 139  *                     Added MPI26_CTRL_OP_SHUTDOWN.
 140  * --------------------------------------------------------------------------
 141  */
 142
 143 #ifndef MPI2_IOC_H
 144 #define MPI2_IOC_H
 145
 146 /*****************************************************************************
 147 *
 148 *              IOC Messages
 149 *
 150 *****************************************************************************/
 151
 152 /****************************************************************************
 153 * IOCInit message
 154 ****************************************************************************/
 155
 156 /*IOCInit Request message */
 157 typedef struct _MPI2_IOC_INIT_REQUEST {
 158         U8 WhoInit;             /*0x00 */
 159         U8 Reserved1;           /*0x01 */
 160         U8 ChainOffset;         /*0x02 */
 161         U8 Function;            /*0x03 */
 162         U16 Reserved2;          /*0x04 */
 163         U8 Reserved3;           /*0x06 */
 164         U8 MsgFlags;            /*0x07 */
 165         U8 VP_ID;               /*0x08 */
 166         U8 VF_ID;               /*0x09 */
 167         U16 Reserved4;          /*0x0A */
 168         U16 MsgVersion;         /*0x0C */
 169         U16 HeaderVersion;      /*0x0E */
 170         U32 Reserved5;          /*0x10 */
 171         U16 Reserved6;          /*0x14 */
 172         U8 HostPageSize;        /*0x16 */
 173         U8 HostMSIxVectors;     /*0x17 */
 174         U16 Reserved8;          /*0x18 */
 175         U16 SystemRequestFrameSize;     /*0x1A */
 176         U16 ReplyDescriptorPostQueueDepth;      /*0x1C */
 177         U16 ReplyFreeQueueDepth;        /*0x1E */
 178         U32 SenseBufferAddressHigh;     /*0x20 */
 179         U32 SystemReplyAddressHigh;     /*0x24 */
 180         U64 SystemRequestFrameBaseAddress;      /*0x28 */
 181         U64 ReplyDescriptorPostQueueAddress;    /*0x30 */
 182         U64 ReplyFreeQueueAddress;      /*0x38 */
 183         U64 TimeStamp;          /*0x40 */
 184 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
 185         Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
 186
 187 /*WhoInit values */
 188 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 189 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 190 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 191 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 192 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 193 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 194
 195 /* MsgFlags */
 196 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 197
 198
 199 /*MsgVersion */
 200 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 201 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 202 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 203 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 204
 205 /*HeaderVersion */
 206 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 207 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 208 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 209 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 210
 211 /*minimum depth for a Reply Descriptor Post Queue */
 212 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 213
 214 /* Reply Descriptor Post Queue Array Entry */
 215 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 216         U64                 RDPQBaseAddress;                    /* 0x00 */
 217         U32                 Reserved1;                          /* 0x08 */
 218         U32                 Reserved2;                          /* 0x0C */
 219 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 220 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 221 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
 222
 223
 224 /*IOCInit Reply message */
 225 typedef struct _MPI2_IOC_INIT_REPLY {
 226         U8 WhoInit;             /*0x00 */
 227         U8 Reserved1;           /*0x01 */
 228         U8 MsgLength;           /*0x02 */
 229         U8 Function;            /*0x03 */
 230         U16 Reserved2;          /*0x04 */
 231         U8 Reserved3;           /*0x06 */
 232         U8 MsgFlags;            /*0x07 */
 233         U8 VP_ID;               /*0x08 */
 234         U8 VF_ID;               /*0x09 */
 235         U16 Reserved4;          /*0x0A */
 236         U16 Reserved5;          /*0x0C */
 237         U16 IOCStatus;          /*0x0E */
 238         U32 IOCLogInfo;         /*0x10 */
 239 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
 240         Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
 241
 242 /****************************************************************************
 243 * IOCFacts message
 244 ****************************************************************************/
 245
 246 /*IOCFacts Request message */
 247 typedef struct _MPI2_IOC_FACTS_REQUEST {
 248         U16 Reserved1;          /*0x00 */
 249         U8 ChainOffset;         /*0x02 */
 250         U8 Function;            /*0x03 */
 251         U16 Reserved2;          /*0x04 */
 252         U8 Reserved3;           /*0x06 */
 253         U8 MsgFlags;            /*0x07 */
 254         U8 VP_ID;               /*0x08 */
 255         U8 VF_ID;               /*0x09 */
 256         U16 Reserved4;          /*0x0A */
 257 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
 258         Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
 259
 260 /*IOCFacts Reply message */
 261 typedef struct _MPI2_IOC_FACTS_REPLY {
 262         U16 MsgVersion;         /*0x00 */
 263         U8 MsgLength;           /*0x02 */
 264         U8 Function;            /*0x03 */
 265         U16 HeaderVersion;      /*0x04 */
 266         U8 IOCNumber;           /*0x06 */
 267         U8 MsgFlags;            /*0x07 */
 268         U8 VP_ID;               /*0x08 */
 269         U8 VF_ID;               /*0x09 */
 270         U16 Reserved1;          /*0x0A */
 271         U16 IOCExceptions;      /*0x0C */
 272         U16 IOCStatus;          /*0x0E */
 273         U32 IOCLogInfo;         /*0x10 */
 274         U8 MaxChainDepth;       /*0x14 */
 275         U8 WhoInit;             /*0x15 */
 276         U8 NumberOfPorts;       /*0x16 */
 277         U8 MaxMSIxVectors;      /*0x17 */
 278         U16 RequestCredit;      /*0x18 */
 279         U16 ProductID;          /*0x1A */
 280         U32 IOCCapabilities;    /*0x1C */
 281         MPI2_VERSION_UNION FWVersion;   /*0x20 */
 282         U16 IOCRequestFrameSize;        /*0x24 */
 283         U16 IOCMaxChainSegmentSize;     /*0x26 */
 284         U16 MaxInitiators;      /*0x28 */
 285         U16 MaxTargets;         /*0x2A */
 286         U16 MaxSasExpanders;    /*0x2C */
 287         U16 MaxEnclosures;      /*0x2E */
 288         U16 ProtocolFlags;      /*0x30 */
 289         U16 HighPriorityCredit; /*0x32 */
 290         U16 MaxReplyDescriptorPostQueueDepth;   /*0x34 */
 291         U8 ReplyFrameSize;      /*0x36 */
 292         U8 MaxVolumes;          /*0x37 */
 293         U16 MaxDevHandle;       /*0x38 */
 294         U16 MaxPersistentEntries;       /*0x3A */
 295         U16 MinDevHandle;       /*0x3C */
 296         U8 CurrentHostPageSize; /* 0x3E */
 297         U8 Reserved4;           /* 0x3F */
 298 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
 299         Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
 300
 301 /*MsgVersion */
 302 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 303 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 304 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 305 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 306
 307 /*HeaderVersion */
 308 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 309 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 310 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 311 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 312
 313 /*IOCExceptions */
 314 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 315 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 316
 317 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 318 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 319 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 320 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 321 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 322
 323 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 324 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 325 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 326 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 327 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 328
 329 /*defines for WhoInit field are after the IOCInit Request */
 330
 331 /*ProductID field uses MPI2_FW_HEADER_PID_ */
 332
 333 /*IOCCapabilities */
 334 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ            (0x00080000)
 335 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 336 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
 337 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 338 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 339 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 340 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 341 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 342 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 343 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 344 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 345 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 346 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 347 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 348 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 349 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 350
 351 /*ProtocolFlags */
 352 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 353 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 354
 355 /****************************************************************************
 356 * PortFacts message
 357 ****************************************************************************/
 358
 359 /*PortFacts Request message */
 360 typedef struct _MPI2_PORT_FACTS_REQUEST {
 361         U16 Reserved1;          /*0x00 */
 362         U8 ChainOffset;         /*0x02 */
 363         U8 Function;            /*0x03 */
 364         U16 Reserved2;          /*0x04 */
 365         U8 PortNumber;          /*0x06 */
 366         U8 MsgFlags;            /*0x07 */
 367         U8 VP_ID;               /*0x08 */
 368         U8 VF_ID;               /*0x09 */
 369         U16 Reserved3;          /*0x0A */
 370 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
 371         Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
 372
 373 /*PortFacts Reply message */
 374 typedef struct _MPI2_PORT_FACTS_REPLY {
 375         U16 Reserved1;          /*0x00 */
 376         U8 MsgLength;           /*0x02 */
 377         U8 Function;            /*0x03 */
 378         U16 Reserved2;          /*0x04 */
 379         U8 PortNumber;          /*0x06 */
 380         U8 MsgFlags;            /*0x07 */
 381         U8 VP_ID;               /*0x08 */
 382         U8 VF_ID;               /*0x09 */
 383         U16 Reserved3;          /*0x0A */
 384         U16 Reserved4;          /*0x0C */
 385         U16 IOCStatus;          /*0x0E */
 386         U32 IOCLogInfo;         /*0x10 */
 387         U8 Reserved5;           /*0x14 */
 388         U8 PortType;            /*0x15 */
 389         U16 Reserved6;          /*0x16 */
 390         U16 MaxPostedCmdBuffers;        /*0x18 */
 391         U16 Reserved7;          /*0x1A */
 392 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
 393         Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
 394
 395 /*PortType values */
 396 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 397 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 398 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 399 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 400 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 401
 402 /****************************************************************************
 403 * PortEnable message
 404 ****************************************************************************/
 405
 406 /*PortEnable Request message */
 407 typedef struct _MPI2_PORT_ENABLE_REQUEST {
 408         U16 Reserved1;          /*0x00 */
 409         U8 ChainOffset;         /*0x02 */
 410         U8 Function;            /*0x03 */
 411         U8 Reserved2;           /*0x04 */
 412         U8 PortFlags;           /*0x05 */
 413         U8 Reserved3;           /*0x06 */
 414         U8 MsgFlags;            /*0x07 */
 415         U8 VP_ID;               /*0x08 */
 416         U8 VF_ID;               /*0x09 */
 417         U16 Reserved4;          /*0x0A */
 418 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
 419         Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
 420
 421 /*PortEnable Reply message */
 422 typedef struct _MPI2_PORT_ENABLE_REPLY {
 423         U16 Reserved1;          /*0x00 */
 424         U8 MsgLength;           /*0x02 */
 425         U8 Function;            /*0x03 */
 426         U8 Reserved2;           /*0x04 */
 427         U8 PortFlags;           /*0x05 */
 428         U8 Reserved3;           /*0x06 */
 429         U8 MsgFlags;            /*0x07 */
 430         U8 VP_ID;               /*0x08 */
 431         U8 VF_ID;               /*0x09 */
 432         U16 Reserved4;          /*0x0A */
 433         U16 Reserved5;          /*0x0C */
 434         U16 IOCStatus;          /*0x0E */
 435         U32 IOCLogInfo;         /*0x10 */
 436 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
 437         Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
 438
 439 /****************************************************************************
 440 * EventNotification message
 441 ****************************************************************************/
 442
 443 /*EventNotification Request message */
 444 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 445
 446 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
 447         U16 Reserved1;          /*0x00 */
 448         U8 ChainOffset;         /*0x02 */
 449         U8 Function;            /*0x03 */
 450         U16 Reserved2;          /*0x04 */
 451         U8 Reserved3;           /*0x06 */
 452         U8 MsgFlags;            /*0x07 */
 453         U8 VP_ID;               /*0x08 */
 454         U8 VF_ID;               /*0x09 */
 455         U16 Reserved4;          /*0x0A */
 456         U32 Reserved5;          /*0x0C */
 457         U32 Reserved6;          /*0x10 */
 458         U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];      /*0x14 */
 459         U16 SASBroadcastPrimitiveMasks; /*0x24 */
 460         U16 SASNotifyPrimitiveMasks;    /*0x26 */
 461         U32 Reserved8;          /*0x28 */
 462 } MPI2_EVENT_NOTIFICATION_REQUEST,
 463         *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 464         Mpi2EventNotificationRequest_t,
 465         *pMpi2EventNotificationRequest_t;
 466
 467 /*EventNotification Reply message */
 468 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
 469         U16 EventDataLength;    /*0x00 */
 470         U8 MsgLength;           /*0x02 */
 471         U8 Function;            /*0x03 */
 472         U16 Reserved1;          /*0x04 */
 473         U8 AckRequired;         /*0x06 */
 474         U8 MsgFlags;            /*0x07 */
 475         U8 VP_ID;               /*0x08 */
 476         U8 VF_ID;               /*0x09 */
 477         U16 Reserved2;          /*0x0A */
 478         U16 Reserved3;          /*0x0C */
 479         U16 IOCStatus;          /*0x0E */
 480         U32 IOCLogInfo;         /*0x10 */
 481         U16 Event;              /*0x14 */
 482         U16 Reserved4;          /*0x16 */
 483         U32 EventContext;       /*0x18 */
 484         U32 EventData[1];       /*0x1C */
 485 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 486         Mpi2EventNotificationReply_t,
 487         *pMpi2EventNotificationReply_t;
 488
 489 /*AckRequired */
 490 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 491 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 492
 493 /*Event */
 494 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 495 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 496 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 497 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 498 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E)    /*obsolete */
 499 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 500 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 501 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 502 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 503 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 504 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 505 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 506 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 507 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 508 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 509 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 510 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 511 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 512 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 513 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 514 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 515 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 516 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 517 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 518 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
 519 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 520 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 521
 522 /*Log Entry Added Event data */
 523
 524 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 525 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 526
 527 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
 528         U64 TimeStamp;          /*0x00 */
 529         U32 Reserved1;          /*0x08 */
 530         U16 LogSequence;        /*0x0C */
 531         U16 LogEntryQualifier;  /*0x0E */
 532         U8 VP_ID;               /*0x10 */
 533         U8 VF_ID;               /*0x11 */
 534         U16 Reserved2;          /*0x12 */
 535         U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];    /*0x14 */
 536 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 537         *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 538         Mpi2EventDataLogEntryAdded_t,
 539         *pMpi2EventDataLogEntryAdded_t;
 540
 541 /*GPIO Interrupt Event data */
 542
 543 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 544         U8 GPIONum;             /*0x00 */
 545         U8 Reserved1;           /*0x01 */
 546         U16 Reserved2;          /*0x02 */
 547 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 548         *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 549         Mpi2EventDataGpioInterrupt_t,
 550         *pMpi2EventDataGpioInterrupt_t;
 551
 552 /*Temperature Threshold Event data */
 553
 554 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 555         U16 Status;             /*0x00 */
 556         U8 SensorNum;           /*0x02 */
 557         U8 Reserved1;           /*0x03 */
 558         U16 CurrentTemperature; /*0x04 */
 559         U16 Reserved2;          /*0x06 */
 560         U32 Reserved3;          /*0x08 */
 561         U32 Reserved4;          /*0x0C */
 562 } MPI2_EVENT_DATA_TEMPERATURE,
 563         *PTR_MPI2_EVENT_DATA_TEMPERATURE,
 564         Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
 565
 566 /*Temperature Threshold Event data Status bits */
 567 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 568 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 569 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 570 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 571
 572 /*Host Message Event data */
 573
 574 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 575         U8 SourceVF_ID;         /*0x00 */
 576         U8 Reserved1;           /*0x01 */
 577         U16 Reserved2;          /*0x02 */
 578         U32 Reserved3;          /*0x04 */
 579         U32 HostData[1];        /*0x08 */
 580 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 581         Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
 582
 583 /*Power Performance Change Event */
 584
 585 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
 586         U8 CurrentPowerMode;    /*0x00 */
 587         U8 PreviousPowerMode;   /*0x01 */
 588         U16 Reserved1;          /*0x02 */
 589 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 590         *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 591         Mpi2EventDataPowerPerfChange_t,
 592         *pMpi2EventDataPowerPerfChange_t;
 593
 594 /*defines for CurrentPowerMode and PreviousPowerMode fields */
 595 #define MPI2_EVENT_PM_INIT_MASK              (0xC0)
 596 #define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
 597 #define MPI2_EVENT_PM_INIT_HOST              (0x40)
 598 #define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
 599 #define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
 600
 601 #define MPI2_EVENT_PM_MODE_MASK              (0x07)
 602 #define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
 603 #define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
 604 #define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
 605 #define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
 606 #define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
 607
 608 /*Hard Reset Received Event data */
 609
 610 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
 611         U8 Reserved1;           /*0x00 */
 612         U8 Port;                /*0x01 */
 613         U16 Reserved2;          /*0x02 */
 614 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 615         *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 616         Mpi2EventDataHardResetReceived_t,
 617         *pMpi2EventDataHardResetReceived_t;
 618
 619 /*Task Set Full Event data */
 620 /*  this event is obsolete */
 621
 622 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
 623         U16 DevHandle;          /*0x00 */
 624         U16 CurrentDepth;       /*0x02 */
 625 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 626         Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
 627
 628 /*SAS Device Status Change Event data */
 629
 630 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
 631         U16 TaskTag;            /*0x00 */
 632         U8 ReasonCode;          /*0x02 */
 633         U8 PhysicalPort;        /*0x03 */
 634         U8 ASC;                 /*0x04 */
 635         U8 ASCQ;                /*0x05 */
 636         U16 DevHandle;          /*0x06 */
 637         U32 Reserved2;          /*0x08 */
 638         U64 SASAddress;         /*0x0C */
 639         U8 LUN[8];              /*0x14 */
 640 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 641         *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 642         Mpi2EventDataSasDeviceStatusChange_t,
 643         *pMpi2EventDataSasDeviceStatusChange_t;
 644
 645 /*SAS Device Status Change Event data ReasonCode values */
 646 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 647 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 648 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 649 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 650 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 651 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 652 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 653 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 654 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 655 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 656 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 657 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 658 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 659
 660 /*Integrated RAID Operation Status Event data */
 661
 662 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
 663         U16 VolDevHandle;       /*0x00 */
 664         U16 Reserved1;          /*0x02 */
 665         U8 RAIDOperation;       /*0x04 */
 666         U8 PercentComplete;     /*0x05 */
 667         U16 Reserved2;          /*0x06 */
 668         U32 ElapsedSeconds;     /*0x08 */
 669 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 670         *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 671         Mpi2EventDataIrOperationStatus_t,
 672         *pMpi2EventDataIrOperationStatus_t;
 673
 674 /*Integrated RAID Operation Status Event data RAIDOperation values */
 675 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 676 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 677 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 678 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 679 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 680
 681 /*Integrated RAID Volume Event data */
 682
 683 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
 684         U16 VolDevHandle;       /*0x00 */
 685         U8 ReasonCode;          /*0x02 */
 686         U8 Reserved1;           /*0x03 */
 687         U32 NewValue;           /*0x04 */
 688         U32 PreviousValue;      /*0x08 */
 689 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
 690         Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
 691
 692 /*Integrated RAID Volume Event data ReasonCode values */
 693 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 694 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 695 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 696
 697 /*Integrated RAID Physical Disk Event data */
 698
 699 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
 700         U16 Reserved1;          /*0x00 */
 701         U8 ReasonCode;          /*0x02 */
 702         U8 PhysDiskNum;         /*0x03 */
 703         U16 PhysDiskDevHandle;  /*0x04 */
 704         U16 Reserved2;          /*0x06 */
 705         U16 Slot;               /*0x08 */
 706         U16 EnclosureHandle;    /*0x0A */
 707         U32 NewValue;           /*0x0C */
 708         U32 PreviousValue;      /*0x10 */
 709 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 710         *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 711         Mpi2EventDataIrPhysicalDisk_t,
 712         *pMpi2EventDataIrPhysicalDisk_t;
 713
 714 /*Integrated RAID Physical Disk Event data ReasonCode values */
 715 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 716 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 717 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 718
 719 /*Integrated RAID Configuration Change List Event data */
 720
 721 /*
 722  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 723  *one and check NumElements at runtime.
 724  */
 725 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 726 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 727 #endif
 728
 729 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
 730         U16 ElementFlags;       /*0x00 */
 731         U16 VolDevHandle;       /*0x02 */
 732         U8 ReasonCode;          /*0x04 */
 733         U8 PhysDiskNum;         /*0x05 */
 734         U16 PhysDiskDevHandle;  /*0x06 */
 735 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 736         Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
 737
 738 /*IR Configuration Change List Event data ElementFlags values */
 739 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 740 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 741 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 742 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 743
 744 /*IR Configuration Change List Event data ReasonCode values */
 745 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 746 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 747 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 748 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 749 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 750 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 751 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 752 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 753 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 754
 755 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
 756         U8 NumElements;         /*0x00 */
 757         U8 Reserved1;           /*0x01 */
 758         U8 Reserved2;           /*0x02 */
 759         U8 ConfigNum;           /*0x03 */
 760         U32 Flags;              /*0x04 */
 761         MPI2_EVENT_IR_CONFIG_ELEMENT
 762                 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
 763 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 764         *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 765         Mpi2EventDataIrConfigChangeList_t,
 766         *pMpi2EventDataIrConfigChangeList_t;
 767
 768 /*IR Configuration Change List Event data Flags values */
 769 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 770
 771 /*SAS Discovery Event data */
 772
 773 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
 774         U8 Flags;               /*0x00 */
 775         U8 ReasonCode;          /*0x01 */
 776         U8 PhysicalPort;        /*0x02 */
 777         U8 Reserved1;           /*0x03 */
 778         U32 DiscoveryStatus;    /*0x04 */
 779 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 780         *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 781         Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
 782
 783 /*SAS Discovery Event data Flags values */
 784 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 785 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 786
 787 /*SAS Discovery Event data ReasonCode values */
 788 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 789 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 790
 791 /*SAS Discovery Event data DiscoveryStatus values */
 792 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 793 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 794 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 795 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 796 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 797 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 798 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 799 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 800 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 801 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 802 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 803 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 804 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 805 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 806 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 807 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 808 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 809 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 810 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 811 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 812
 813 /*SAS Broadcast Primitive Event data */
 814
 815 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
 816         U8 PhyNum;              /*0x00 */
 817         U8 Port;                /*0x01 */
 818         U8 PortWidth;           /*0x02 */
 819         U8 Primitive;           /*0x03 */
 820 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 821         *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 822         Mpi2EventDataSasBroadcastPrimitive_t,
 823         *pMpi2EventDataSasBroadcastPrimitive_t;
 824
 825 /*defines for the Primitive field */
 826 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 827 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 828 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 829 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 830 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 831 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 832 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 833 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 834
 835 /*SAS Notify Primitive Event data */
 836
 837 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 838         U8 PhyNum;              /*0x00 */
 839         U8 Port;                /*0x01 */
 840         U8 Reserved1;           /*0x02 */
 841         U8 Primitive;           /*0x03 */
 842 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 843         *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 844         Mpi2EventDataSasNotifyPrimitive_t,
 845         *pMpi2EventDataSasNotifyPrimitive_t;
 846
 847 /*defines for the Primitive field */
 848 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 849 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 850 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 851 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 852
 853 /*SAS Initiator Device Status Change Event data */
 854
 855 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
 856         U8 ReasonCode;          /*0x00 */
 857         U8 PhysicalPort;        /*0x01 */
 858         U16 DevHandle;          /*0x02 */
 859         U64 SASAddress;         /*0x04 */
 860 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 861         *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 862         Mpi2EventDataSasInitDevStatusChange_t,
 863         *pMpi2EventDataSasInitDevStatusChange_t;
 864
 865 /*SAS Initiator Device Status Change event ReasonCode values */
 866 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 867 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 868
 869 /*SAS Initiator Device Table Overflow Event data */
 870
 871 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
 872         U16 MaxInit;            /*0x00 */
 873         U16 CurrentInit;        /*0x02 */
 874         U64 SASAddress;         /*0x04 */
 875 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 876         *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 877         Mpi2EventDataSasInitTableOverflow_t,
 878         *pMpi2EventDataSasInitTableOverflow_t;
 879
 880 /*SAS Topology Change List Event data */
 881
 882 /*
 883  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 884  *one and check NumEntries at runtime.
 885  */
 886 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 887 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 888 #endif
 889
 890 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
 891         U16 AttachedDevHandle;  /*0x00 */
 892         U8 LinkRate;            /*0x02 */
 893         U8 PhyStatus;           /*0x03 */
 894 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 895         Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
 896
 897 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
 898         U16 EnclosureHandle;    /*0x00 */
 899         U16 ExpanderDevHandle;  /*0x02 */
 900         U8 NumPhys;             /*0x04 */
 901         U8 Reserved1;           /*0x05 */
 902         U16 Reserved2;          /*0x06 */
 903         U8 NumEntries;          /*0x08 */
 904         U8 StartPhyNum;         /*0x09 */
 905         U8 ExpStatus;           /*0x0A */
 906         U8 PhysicalPort;        /*0x0B */
 907         MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 908         PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT];     /*0x0C */
 909 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 910         *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 911         Mpi2EventDataSasTopologyChangeList_t,
 912         *pMpi2EventDataSasTopologyChangeList_t;
 913
 914 /*values for the ExpStatus field */
 915 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 916 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 917 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 918 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 919 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 920
 921 /*defines for the LinkRate field */
 922 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 923 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 924 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 925 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 926
 927 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 928 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 929 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 930 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 931 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 932 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 933 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 934 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 935 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 936 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 937 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
 938
 939 /*values for the PhyStatus field */
 940 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 941 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 942 /*values for the PhyStatus ReasonCode sub-field */
 943 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 944 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 945 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 946 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 947 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 948 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 949
 950 /*SAS Enclosure Device Status Change Event data */
 951
 952 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
 953         U16 EnclosureHandle;    /*0x00 */
 954         U8 ReasonCode;          /*0x02 */
 955         U8 PhysicalPort;        /*0x03 */
 956         U64 EnclosureLogicalID; /*0x04 */
 957         U16 NumSlots;           /*0x0C */
 958         U16 StartSlot;          /*0x0E */
 959         U32 PhyBits;            /*0x10 */
 960 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 961         *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 962         Mpi2EventDataSasEnclDevStatusChange_t,
 963         *pMpi2EventDataSasEnclDevStatusChange_t;
 964
 965 /*SAS Enclosure Device Status Change event ReasonCode values */
 966 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 967 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 968
 969 /*SAS PHY Counter Event data */
 970
 971 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 972         U64 TimeStamp;          /*0x00 */
 973         U32 Reserved1;          /*0x08 */
 974         U8 PhyEventCode;        /*0x0C */
 975         U8 PhyNum;              /*0x0D */
 976         U16 Reserved2;          /*0x0E */
 977         U32 PhyEventInfo;       /*0x10 */
 978         U8 CounterType;         /*0x14 */
 979         U8 ThresholdWindow;     /*0x15 */
 980         U8 TimeUnits;           /*0x16 */
 981         U8 Reserved3;           /*0x17 */
 982         U32 EventThreshold;     /*0x18 */
 983         U16 ThresholdFlags;     /*0x1C */
 984         U16 Reserved4;          /*0x1E */
 985 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 986         *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 987         Mpi2EventDataSasPhyCounter_t,
 988         *pMpi2EventDataSasPhyCounter_t;
 989
 990 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
 991  *for the PhyEventCode field */
 992
 993 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
 994  *for the CounterType field */
 995
 996 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
 997  *for the TimeUnits field */
 998
 999 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1000  *for the ThresholdFlags field */
1001
1002 /*SAS Quiesce Event data */
1003
1004 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1005         U8 ReasonCode;          /*0x00 */
1006         U8 Reserved1;           /*0x01 */
1007         U16 Reserved2;          /*0x02 */
1008         U32 Reserved3;          /*0x04 */
1009 } MPI2_EVENT_DATA_SAS_QUIESCE,
1010         *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1011         Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1012
1013 /*SAS Quiesce Event data ReasonCode values */
1014 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1015 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1016
1017 /*Host Based Discovery Phy Event data */
1018
1019 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1020         U8 Flags;               /*0x00 */
1021         U8 NegotiatedLinkRate;  /*0x01 */
1022         U8 PhyNum;              /*0x02 */
1023         U8 PhysicalPort;        /*0x03 */
1024         U32 Reserved1;          /*0x04 */
1025         U8 InitialFrame[28];    /*0x08 */
1026 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1027         Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1028
1029 /*values for the Flags field */
1030 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1031 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1032
1033 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1034  *for the NegotiatedLinkRate field */
1035
1036 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1037         MPI2_EVENT_HBD_PHY_SAS Sas;
1038 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1039         Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1040
1041 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1042         U8 DescriptorType;      /*0x00 */
1043         U8 Reserved1;           /*0x01 */
1044         U16 Reserved2;          /*0x02 */
1045         U32 Reserved3;          /*0x04 */
1046         MPI2_EVENT_HBD_DESCRIPTOR Descriptor;   /*0x08 */
1047 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1048         Mpi2EventDataHbdPhy_t,
1049         *pMpi2EventDataMpi2EventDataHbdPhy_t;
1050
1051 /*values for the DescriptorType field */
1052 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1053
1054 /****************************************************************************
1055 * EventAck message
1056 ****************************************************************************/
1057
1058 /*EventAck Request message */
1059 typedef struct _MPI2_EVENT_ACK_REQUEST {
1060         U16 Reserved1;          /*0x00 */
1061         U8 ChainOffset;         /*0x02 */
1062         U8 Function;            /*0x03 */
1063         U16 Reserved2;          /*0x04 */
1064         U8 Reserved3;           /*0x06 */
1065         U8 MsgFlags;            /*0x07 */
1066         U8 VP_ID;               /*0x08 */
1067         U8 VF_ID;               /*0x09 */
1068         U16 Reserved4;          /*0x0A */
1069         U16 Event;              /*0x0C */
1070         U16 Reserved5;          /*0x0E */
1071         U32 EventContext;       /*0x10 */
1072 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1073         Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1074
1075 /*EventAck Reply message */
1076 typedef struct _MPI2_EVENT_ACK_REPLY {
1077         U16 Reserved1;          /*0x00 */
1078         U8 MsgLength;           /*0x02 */
1079         U8 Function;            /*0x03 */
1080         U16 Reserved2;          /*0x04 */
1081         U8 Reserved3;           /*0x06 */
1082         U8 MsgFlags;            /*0x07 */
1083         U8 VP_ID;               /*0x08 */
1084         U8 VF_ID;               /*0x09 */
1085         U16 Reserved4;          /*0x0A */
1086         U16 Reserved5;          /*0x0C */
1087         U16 IOCStatus;          /*0x0E */
1088         U32 IOCLogInfo;         /*0x10 */
1089 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1090         Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1091
1092 /****************************************************************************
1093 * SendHostMessage message
1094 ****************************************************************************/
1095
1096 /*SendHostMessage Request message */
1097 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1098         U16 HostDataLength;     /*0x00 */
1099         U8 ChainOffset;         /*0x02 */
1100         U8 Function;            /*0x03 */
1101         U16 Reserved1;          /*0x04 */
1102         U8 Reserved2;           /*0x06 */
1103         U8 MsgFlags;            /*0x07 */
1104         U8 VP_ID;               /*0x08 */
1105         U8 VF_ID;               /*0x09 */
1106         U16 Reserved3;          /*0x0A */
1107         U8 Reserved4;           /*0x0C */
1108         U8 DestVF_ID;           /*0x0D */
1109         U16 Reserved5;          /*0x0E */
1110         U32 Reserved6;          /*0x10 */
1111         U32 Reserved7;          /*0x14 */
1112         U32 Reserved8;          /*0x18 */
1113         U32 Reserved9;          /*0x1C */
1114         U32 Reserved10;         /*0x20 */
1115         U32 HostData[1];        /*0x24 */
1116 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1117         *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1118         Mpi2SendHostMessageRequest_t,
1119         *pMpi2SendHostMessageRequest_t;
1120
1121 /*SendHostMessage Reply message */
1122 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1123         U16 HostDataLength;     /*0x00 */
1124         U8 MsgLength;           /*0x02 */
1125         U8 Function;            /*0x03 */
1126         U16 Reserved1;          /*0x04 */
1127         U8 Reserved2;           /*0x06 */
1128         U8 MsgFlags;            /*0x07 */
1129         U8 VP_ID;               /*0x08 */
1130         U8 VF_ID;               /*0x09 */
1131         U16 Reserved3;          /*0x0A */
1132         U16 Reserved4;          /*0x0C */
1133         U16 IOCStatus;          /*0x0E */
1134         U32 IOCLogInfo;         /*0x10 */
1135 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1136         Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1137
1138 /****************************************************************************
1139 * FWDownload message
1140 ****************************************************************************/
1141
1142 /*MPI v2.0 FWDownload Request message */
1143 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1144         U8 ImageType;           /*0x00 */
1145         U8 Reserved1;           /*0x01 */
1146         U8 ChainOffset;         /*0x02 */
1147         U8 Function;            /*0x03 */
1148         U16 Reserved2;          /*0x04 */
1149         U8 Reserved3;           /*0x06 */
1150         U8 MsgFlags;            /*0x07 */
1151         U8 VP_ID;               /*0x08 */
1152         U8 VF_ID;               /*0x09 */
1153         U16 Reserved4;          /*0x0A */
1154         U32 TotalImageSize;     /*0x0C */
1155         U32 Reserved5;          /*0x10 */
1156         MPI2_MPI_SGE_UNION SGL; /*0x14 */
1157 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1158         Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1159
1160 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1161
1162 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1163 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1164 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1165 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1166 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1167 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1168 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1169 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1170 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1171 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1172
1173 /*MPI v2.0 FWDownload TransactionContext Element */
1174 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1175         U8 Reserved1;           /*0x00 */
1176         U8 ContextSize;         /*0x01 */
1177         U8 DetailsLength;       /*0x02 */
1178         U8 Flags;               /*0x03 */
1179         U32 Reserved2;          /*0x04 */
1180         U32 ImageOffset;        /*0x08 */
1181         U32 ImageSize;          /*0x0C */
1182 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1183         Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1184
1185 /*MPI v2.5 FWDownload Request message */
1186 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1187         U8 ImageType;           /*0x00 */
1188         U8 Reserved1;           /*0x01 */
1189         U8 ChainOffset;         /*0x02 */
1190         U8 Function;            /*0x03 */
1191         U16 Reserved2;          /*0x04 */
1192         U8 Reserved3;           /*0x06 */
1193         U8 MsgFlags;            /*0x07 */
1194         U8 VP_ID;               /*0x08 */
1195         U8 VF_ID;               /*0x09 */
1196         U16 Reserved4;          /*0x0A */
1197         U32 TotalImageSize;     /*0x0C */
1198         U32 Reserved5;          /*0x10 */
1199         U32 Reserved6;          /*0x14 */
1200         U32 ImageOffset;        /*0x18 */
1201         U32 ImageSize;          /*0x1C */
1202         MPI25_SGE_IO_UNION SGL; /*0x20 */
1203 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1204         Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1205
1206 /*FWDownload Reply message */
1207 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1208         U8 ImageType;           /*0x00 */
1209         U8 Reserved1;           /*0x01 */
1210         U8 MsgLength;           /*0x02 */
1211         U8 Function;            /*0x03 */
1212         U16 Reserved2;          /*0x04 */
1213         U8 Reserved3;           /*0x06 */
1214         U8 MsgFlags;            /*0x07 */
1215         U8 VP_ID;               /*0x08 */
1216         U8 VF_ID;               /*0x09 */
1217         U16 Reserved4;          /*0x0A */
1218         U16 Reserved5;          /*0x0C */
1219         U16 IOCStatus;          /*0x0E */
1220         U32 IOCLogInfo;         /*0x10 */
1221 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1222         Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1223
1224 /****************************************************************************
1225 * FWUpload message
1226 ****************************************************************************/
1227
1228 /*MPI v2.0 FWUpload Request message */
1229 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1230         U8 ImageType;           /*0x00 */
1231         U8 Reserved1;           /*0x01 */
1232         U8 ChainOffset;         /*0x02 */
1233         U8 Function;            /*0x03 */
1234         U16 Reserved2;          /*0x04 */
1235         U8 Reserved3;           /*0x06 */
1236         U8 MsgFlags;            /*0x07 */
1237         U8 VP_ID;               /*0x08 */
1238         U8 VF_ID;               /*0x09 */
1239         U16 Reserved4;          /*0x0A */
1240         U32 Reserved5;          /*0x0C */
1241         U32 Reserved6;          /*0x10 */
1242         MPI2_MPI_SGE_UNION SGL; /*0x14 */
1243 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1244         Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1245
1246 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1247 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1248 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1249 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1250 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1251 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1252 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1253 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1254 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1255 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1256 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP         (0x0D)
1257
1258 /*MPI v2.0 FWUpload TransactionContext Element */
1259 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1260         U8 Reserved1;           /*0x00 */
1261         U8 ContextSize;         /*0x01 */
1262         U8 DetailsLength;       /*0x02 */
1263         U8 Flags;               /*0x03 */
1264         U32 Reserved2;          /*0x04 */
1265         U32 ImageOffset;        /*0x08 */
1266         U32 ImageSize;          /*0x0C */
1267 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1268         Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1269
1270 /*MPI v2.5 FWUpload Request message */
1271 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1272         U8 ImageType;           /*0x00 */
1273         U8 Reserved1;           /*0x01 */
1274         U8 ChainOffset;         /*0x02 */
1275         U8 Function;            /*0x03 */
1276         U16 Reserved2;          /*0x04 */
1277         U8 Reserved3;           /*0x06 */
1278         U8 MsgFlags;            /*0x07 */
1279         U8 VP_ID;               /*0x08 */
1280         U8 VF_ID;               /*0x09 */
1281         U16 Reserved4;          /*0x0A */
1282         U32 Reserved5;          /*0x0C */
1283         U32 Reserved6;          /*0x10 */
1284         U32 Reserved7;          /*0x14 */
1285         U32 ImageOffset;        /*0x18 */
1286         U32 ImageSize;          /*0x1C */
1287         MPI25_SGE_IO_UNION SGL; /*0x20 */
1288 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1289         Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1290
1291 /*FWUpload Reply message */
1292 typedef struct _MPI2_FW_UPLOAD_REPLY {
1293         U8 ImageType;           /*0x00 */
1294         U8 Reserved1;           /*0x01 */
1295         U8 MsgLength;           /*0x02 */
1296         U8 Function;            /*0x03 */
1297         U16 Reserved2;          /*0x04 */
1298         U8 Reserved3;           /*0x06 */
1299         U8 MsgFlags;            /*0x07 */
1300         U8 VP_ID;               /*0x08 */
1301         U8 VF_ID;               /*0x09 */
1302         U16 Reserved4;          /*0x0A */
1303         U16 Reserved5;          /*0x0C */
1304         U16 IOCStatus;          /*0x0E */
1305         U32 IOCLogInfo;         /*0x10 */
1306         U32 ActualImageSize;    /*0x14 */
1307 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1308         Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1309
1310 /*FW Image Header */
1311 typedef struct _MPI2_FW_IMAGE_HEADER {
1312         U32 Signature;          /*0x00 */
1313         U32 Signature0;         /*0x04 */
1314         U32 Signature1;         /*0x08 */
1315         U32 Signature2;         /*0x0C */
1316         MPI2_VERSION_UNION MPIVersion;  /*0x10 */
1317         MPI2_VERSION_UNION FWVersion;   /*0x14 */
1318         MPI2_VERSION_UNION NVDATAVersion;       /*0x18 */
1319         MPI2_VERSION_UNION PackageVersion;      /*0x1C */
1320         U16 VendorID;           /*0x20 */
1321         U16 ProductID;          /*0x22 */
1322         U16 ProtocolFlags;      /*0x24 */
1323         U16 Reserved26;         /*0x26 */
1324         U32 IOCCapabilities;    /*0x28 */
1325         U32 ImageSize;          /*0x2C */
1326         U32 NextImageHeaderOffset;      /*0x30 */
1327         U32 Checksum;           /*0x34 */
1328         U32 Reserved38;         /*0x38 */
1329         U32 Reserved3C;         /*0x3C */
1330         U32 Reserved40;         /*0x40 */
1331         U32 Reserved44;         /*0x44 */
1332         U32 Reserved48;         /*0x48 */
1333         U32 Reserved4C;         /*0x4C */
1334         U32 Reserved50;         /*0x50 */
1335         U32 Reserved54;         /*0x54 */
1336         U32 Reserved58;         /*0x58 */
1337         U32 Reserved5C;         /*0x5C */
1338         U32 BootFlags;          /*0x60 */
1339         U32 FirmwareVersionNameWhat;    /*0x64 */
1340         U8 FirmwareVersionName[32];     /*0x68 */
1341         U32 VendorNameWhat;     /*0x88 */
1342         U8 VendorName[32];      /*0x8C */
1343         U32 PackageNameWhat;    /*0x88 */
1344         U8 PackageName[32];     /*0x8C */
1345         U32 ReservedD0;         /*0xD0 */
1346         U32 ReservedD4;         /*0xD4 */
1347         U32 ReservedD8;         /*0xD8 */
1348         U32 ReservedDC;         /*0xDC */
1349         U32 ReservedE0;         /*0xE0 */
1350         U32 ReservedE4;         /*0xE4 */
1351         U32 ReservedE8;         /*0xE8 */
1352         U32 ReservedEC;         /*0xEC */
1353         U32 ReservedF0;         /*0xF0 */
1354         U32 ReservedF4;         /*0xF4 */
1355         U32 ReservedF8;         /*0xF8 */
1356         U32 ReservedFC;         /*0xFC */
1357 } MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1358         Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1359
1360 /*Signature field */
1361 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1362 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1363 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1364 #define MPI26_FW_HEADER_SIGNATURE               (0xEB000000)
1365
1366 /*Signature0 field */
1367 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1368 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1369 #define MPI26_FW_HEADER_SIGNATURE0              (0x5AEAA55A)
1370
1371 /*Signature1 field */
1372 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1373 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1374 #define MPI26_FW_HEADER_SIGNATURE1              (0xA55AEAA5)
1375
1376 /*Signature2 field */
1377 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1378 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1379 #define MPI26_FW_HEADER_SIGNATURE2              (0x5AA55AEA)
1380
1381 /*defines for using the ProductID field */
1382 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1383 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1384
1385 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1386 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1387 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1388 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1389
1390 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1391 /*SAS ProductID Family bits */
1392 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1393 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1394 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS     (0x0021)
1395 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS     (0x0028)
1396 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS     (0x0031)
1397
1398 /*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1399
1400 /*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1401
1402 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1403 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1404 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET        (0x60)
1405 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1406
1407 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1408
1409 #define MPI2_FW_HEADER_SIZE                     (0x100)
1410
1411 /*Extended Image Header */
1412 typedef struct _MPI2_EXT_IMAGE_HEADER {
1413         U8 ImageType;           /*0x00 */
1414         U8 Reserved1;           /*0x01 */
1415         U16 Reserved2;          /*0x02 */
1416         U32 Checksum;           /*0x04 */
1417         U32 ImageSize;          /*0x08 */
1418         U32 NextImageHeaderOffset;      /*0x0C */
1419         U32 PackageVersion;     /*0x10 */
1420         U32 Reserved3;          /*0x14 */
1421         U32 Reserved4;          /*0x18 */
1422         U32 Reserved5;          /*0x1C */
1423         U8 IdentifyString[32];  /*0x20 */
1424 } MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1425         Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1426
1427 /*useful offsets */
1428 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1429 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1430 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1431
1432 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1433
1434 /*defines for the ImageType field */
1435 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1436 #define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1437 #define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1438 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1439 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1440 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1441 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1442 #define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1443 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
1444 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1445 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1446
1447 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1448
1449 /*FLASH Layout Extended Image Data */
1450
1451 /*
1452  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1453  *one and check RegionsPerLayout at runtime.
1454  */
1455 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1456 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1457 #endif
1458
1459 /*
1460  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1461  *one and check NumberOfLayouts at runtime.
1462  */
1463 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1464 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1465 #endif
1466
1467 typedef struct _MPI2_FLASH_REGION {
1468         U8 RegionType;          /*0x00 */
1469         U8 Reserved1;           /*0x01 */
1470         U16 Reserved2;          /*0x02 */
1471         U32 RegionOffset;       /*0x04 */
1472         U32 RegionSize;         /*0x08 */
1473         U32 Reserved3;          /*0x0C */
1474 } MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1475         Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1476
1477 typedef struct _MPI2_FLASH_LAYOUT {
1478         U32 FlashSize;          /*0x00 */
1479         U32 Reserved1;          /*0x04 */
1480         U32 Reserved2;          /*0x08 */
1481         U32 Reserved3;          /*0x0C */
1482         MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1483 } MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1484         Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1485
1486 typedef struct _MPI2_FLASH_LAYOUT_DATA {
1487         U8 ImageRevision;       /*0x00 */
1488         U8 Reserved1;           /*0x01 */
1489         U8 SizeOfRegion;        /*0x02 */
1490         U8 Reserved2;           /*0x03 */
1491         U16 NumberOfLayouts;    /*0x04 */
1492         U16 RegionsPerLayout;   /*0x06 */
1493         U16 MinimumSectorAlignment;     /*0x08 */
1494         U16 Reserved3;          /*0x0A */
1495         U32 Reserved4;          /*0x0C */
1496         MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1497 } MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1498         Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1499
1500 /*defines for the RegionType field */
1501 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1502 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1503 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1504 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1505 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1506 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1507 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1508 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1509 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1510 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK     (0x0A)
1511 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1512 #define MPI2_FLASH_REGION_CBB_BACKUP            (0x0D)
1513
1514 /*ImageRevision */
1515 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1516
1517 /*Supported Devices Extended Image Data */
1518
1519 /*
1520  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1521  *one and check NumberOfDevices at runtime.
1522  */
1523 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1524 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1525 #endif
1526
1527 typedef struct _MPI2_SUPPORTED_DEVICE {
1528         U16 DeviceID;           /*0x00 */
1529         U16 VendorID;           /*0x02 */
1530         U16 DeviceIDMask;       /*0x04 */
1531         U16 Reserved1;          /*0x06 */
1532         U8 LowPCIRev;           /*0x08 */
1533         U8 HighPCIRev;          /*0x09 */
1534         U16 Reserved2;          /*0x0A */
1535         U32 Reserved3;          /*0x0C */
1536 } MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1537         Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1538
1539 typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1540         U8 ImageRevision;       /*0x00 */
1541         U8 Reserved1;           /*0x01 */
1542         U8 NumberOfDevices;     /*0x02 */
1543         U8 Reserved2;           /*0x03 */
1544         U32 Reserved3;          /*0x04 */
1545         MPI2_SUPPORTED_DEVICE
1546         SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1547 } MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1548         Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1549
1550 /*ImageRevision */
1551 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1552
1553 /*Init Extended Image Data */
1554
1555 typedef struct _MPI2_INIT_IMAGE_FOOTER {
1556         U32 BootFlags;          /*0x00 */
1557         U32 ImageSize;          /*0x04 */
1558         U32 Signature0;         /*0x08 */
1559         U32 Signature1;         /*0x0C */
1560         U32 Signature2;         /*0x10 */
1561         U32 ResetVector;        /*0x14 */
1562 } MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1563         Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1564
1565 /*defines for the BootFlags field */
1566 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1567
1568 /*defines for the ImageSize field */
1569 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1570
1571 /*defines for the Signature0 field */
1572 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1573 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1574
1575 /*defines for the Signature1 field */
1576 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1577 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1578
1579 /*defines for the Signature2 field */
1580 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1581 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1582
1583 /*Signature fields as individual bytes */
1584 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1585 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1586 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1587 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1588
1589 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1590 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1591 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1592 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1593
1594 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1595 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1596 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1597 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1598
1599 /*defines for the ResetVector field */
1600 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1601
1602
1603 /* Encrypted Hash Extended Image Data */
1604
1605 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1606         U8              HashImageType;          /* 0x00 */
1607         U8              HashAlgorithm;          /* 0x01 */
1608         U8              EncryptionAlgorithm;    /* 0x02 */
1609         U8              Reserved1;              /* 0x03 */
1610         U32             Reserved2;              /* 0x04 */
1611         U32             EncryptedHash[1];       /* 0x08 */ /* variable length */
1612 } MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1613 Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1614
1615 /* values for HashImageType */
1616 #define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1617 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1618 #define MPI25_HASH_IMAGE_TYPE_BIOS              (0x02)
1619
1620 /* values for HashAlgorithm */
1621 #define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1622 #define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1623
1624 /* values for EncryptionAlgorithm */
1625 #define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1626 #define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1627
1628 typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1629         U8                              ImageVersion;           /* 0x00 */
1630         U8                              NumHash;                /* 0x01 */
1631         U16                             Reserved1;              /* 0x02 */
1632         U32                             Reserved2;              /* 0x04 */
1633         MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */
1634 } MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1635 Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1636
1637
1638 /****************************************************************************
1639 * PowerManagementControl message
1640 ****************************************************************************/
1641
1642 /*PowerManagementControl Request message */
1643 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1644         U8 Feature;             /*0x00 */
1645         U8 Reserved1;           /*0x01 */
1646         U8 ChainOffset;         /*0x02 */
1647         U8 Function;            /*0x03 */
1648         U16 Reserved2;          /*0x04 */
1649         U8 Reserved3;           /*0x06 */
1650         U8 MsgFlags;            /*0x07 */
1651         U8 VP_ID;               /*0x08 */
1652         U8 VF_ID;               /*0x09 */
1653         U16 Reserved4;          /*0x0A */
1654         U8 Parameter1;          /*0x0C */
1655         U8 Parameter2;          /*0x0D */
1656         U8 Parameter3;          /*0x0E */
1657         U8 Parameter4;          /*0x0F */
1658         U32 Reserved5;          /*0x10 */
1659         U32 Reserved6;          /*0x14 */
1660 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1661         Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1662
1663 /*defines for the Feature field */
1664 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1665 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1666 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)  /*obsolete */
1667 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1668 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05)
1669 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1670 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1671
1672 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1673 /*Parameter1 contains a PHY number */
1674 /*Parameter2 indicates power condition action using these defines */
1675 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1676 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1677 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1678 /*Parameter3 and Parameter4 are reserved */
1679
1680 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1681  * Feature */
1682 /*Parameter1 contains SAS port width modulation group number */
1683 /*Parameter2 indicates IOC action using these defines */
1684 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1685 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1686 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1687 /*Parameter3 indicates desired modulation level using these defines */
1688 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1689 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1690 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1691 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1692 /*Parameter4 is reserved */
1693
1694 /*this next set (_PCIE_LINK) is obsolete */
1695 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1696 /*Parameter1 indicates desired PCIe link speed using these defines */
1697 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)  /*obsolete */
1698 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)  /*obsolete */
1699 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)  /*obsolete */
1700 /*Parameter2 indicates desired PCIe link width using these defines */
1701 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)  /*obsolete */
1702 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)  /*obsolete */
1703 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)  /*obsolete */
1704 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)  /*obsolete */
1705 /*Parameter3 and Parameter4 are reserved */
1706
1707 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1708 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
1709 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1710 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1711 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1712 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1713 /*Parameter2, Parameter3, and Parameter4 are reserved */
1714
1715 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1716 /*Parameter1 indicates host action regarding global power management mode */
1717 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1718 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1719 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1720 /*Parameter2 indicates the requested global power management mode */
1721 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1722 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1723 #define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1724 /*Parameter3 and Parameter4 are reserved */
1725
1726 /*PowerManagementControl Reply message */
1727 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1728         U8 Feature;             /*0x00 */
1729         U8 Reserved1;           /*0x01 */
1730         U8 MsgLength;           /*0x02 */
1731         U8 Function;            /*0x03 */
1732         U16 Reserved2;          /*0x04 */
1733         U8 Reserved3;           /*0x06 */
1734         U8 MsgFlags;            /*0x07 */
1735         U8 VP_ID;               /*0x08 */
1736         U8 VF_ID;               /*0x09 */
1737         U16 Reserved4;          /*0x0A */
1738         U16 Reserved5;          /*0x0C */
1739         U16 IOCStatus;          /*0x0E */
1740         U32 IOCLogInfo;         /*0x10 */
1741 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1742         Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1743
1744 /****************************************************************************
1745 *  IO Unit Control messages (MPI v2.6 and later only.)
1746 ****************************************************************************/
1747
1748 /* IO Unit Control Request Message */
1749 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1750         U8                      Operation;          /* 0x00 */
1751         U8                      Reserved1;          /* 0x01 */
1752         U8                      ChainOffset;        /* 0x02 */
1753         U8                      Function;           /* 0x03 */
1754         U16                     DevHandle;          /* 0x04 */
1755         U8                      IOCParameter;       /* 0x06 */
1756         U8                      MsgFlags;           /* 0x07 */
1757         U8                      VP_ID;              /* 0x08 */
1758         U8                      VF_ID;              /* 0x09 */
1759         U16                     Reserved3;          /* 0x0A */
1760         U16                     Reserved4;          /* 0x0C */
1761         U8                      PhyNum;             /* 0x0E */
1762         U8                      PrimFlags;          /* 0x0F */
1763         U32                     Primitive;          /* 0x10 */
1764         U8                      LookupMethod;       /* 0x14 */
1765         U8                      Reserved5;          /* 0x15 */
1766         U16                     SlotNumber;         /* 0x16 */
1767         U64                     LookupAddress;      /* 0x18 */
1768         U32                     IOCParameterValue;  /* 0x20 */
1769         U32                     Reserved7;          /* 0x24 */
1770         U32                     Reserved8;          /* 0x28 */
1771 } MPI26_IOUNIT_CONTROL_REQUEST,
1772         *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1773         Mpi26IoUnitControlRequest_t,
1774         *pMpi26IoUnitControlRequest_t;
1775
1776 /* values for the Operation field */
1777 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT              (0x02)
1778 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET                (0x06)
1779 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET                (0x07)
1780 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG               (0x08)
1781 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE                (0x0A)
1782 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY              (0x0B)
1783 #define MPI26_CTRL_OP_REMOVE_DEVICE                     (0x0D)
1784 #define MPI26_CTRL_OP_LOOKUP_MAPPING                    (0x0E)
1785 #define MPI26_CTRL_OP_SET_IOC_PARAMETER                 (0x0F)
1786 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE                  (0x10)
1787 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE                 (0x11)
1788 #define MPI26_CTRL_OP_ENABLE_FP_ALL                     (0x12)
1789 #define MPI26_CTRL_OP_DISABLE_FP_ALL                    (0x13)
1790 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ                    (0x14)
1791 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ                   (0x15)
1792 #define MPI26_CTRL_OP_SHUTDOWN                          (0x16)
1793 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION     (0x17)
1794 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION    (0x18)
1795 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION      (0x19)
1796 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN              (0x80)
1797
1798 /* values for the PrimFlags field */
1799 #define MPI26_CTRL_PRIMFLAGS_SINGLE                     (0x08)
1800 #define MPI26_CTRL_PRIMFLAGS_TRIPLE                     (0x02)
1801 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT                  (0x01)
1802
1803 /* values for the LookupMethod field */
1804 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS           (0x01)
1805 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT         (0x02)
1806 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME        (0x03)
1807
1808
1809 /* IO Unit Control Reply Message */
1810 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1811         U8                      Operation;          /* 0x00 */
1812         U8                      Reserved1;          /* 0x01 */
1813         U8                      MsgLength;          /* 0x02 */
1814         U8                      Function;           /* 0x03 */
1815         U16                     DevHandle;          /* 0x04 */
1816         U8                      IOCParameter;       /* 0x06 */
1817         U8                      MsgFlags;           /* 0x07 */
1818         U8                      VP_ID;              /* 0x08 */
1819         U8                      VF_ID;              /* 0x09 */
1820         U16                     Reserved3;          /* 0x0A */
1821         U16                     Reserved4;          /* 0x0C */
1822         U16                     IOCStatus;          /* 0x0E */
1823         U32                     IOCLogInfo;         /* 0x10 */
1824 } MPI26_IOUNIT_CONTROL_REPLY,
1825         *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1826         Mpi26IoUnitControlReply_t,
1827         *pMpi26IoUnitControlReply_t;
1828
1829
1830 #endif