drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34 #include "amdgpu_gmc.h"
  35
  36 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  37                                       struct drm_amdgpu_cs_chunk_fence *data,
  38                                       uint32_t *offset)
  39 {
  40         struct drm_gem_object *gobj;
  41         unsigned long size;
  42
  43         gobj = drm_gem_object_lookup(p->filp, data->handle);
  44         if (gobj == NULL)
  45                 return -EINVAL;
  46
  47         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  48         p->uf_entry.priority = 0;
  49         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  50         p->uf_entry.tv.shared = true;
  51         p->uf_entry.user_pages = NULL;
  52
  53         size = amdgpu_bo_size(p->uf_entry.robj);
  54         if (size != PAGE_SIZE || (data->offset + 8) > size)
  55                 return -EINVAL;
  56
  57         *offset = data->offset;
  58
  59         drm_gem_object_put_unlocked(gobj);
  60
  61         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  62                 amdgpu_bo_unref(&p->uf_entry.robj);
  63                 return -EINVAL;
  64         }
  65
  66         return 0;
  67 }
  68
  69 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  70 {
  71         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  72         struct amdgpu_vm *vm = &fpriv->vm;
  73         union drm_amdgpu_cs *cs = data;
  74         uint64_t *chunk_array_user;
  75         uint64_t *chunk_array;
  76         unsigned size, num_ibs = 0;
  77         uint32_t uf_offset = 0;
  78         int i;
  79         int ret;
  80
  81         if (cs->in.num_chunks == 0)
  82                 return 0;
  83
  84         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  85         if (!chunk_array)
  86                 return -ENOMEM;
  87
  88         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  89         if (!p->ctx) {
  90                 ret = -EINVAL;
  91                 goto free_chunk;
  92         }
  93
  94         /* skip guilty context job */
  95         if (atomic_read(&p->ctx->guilty) == 1) {
  96                 ret = -ECANCELED;
  97                 goto free_chunk;
  98         }
  99
 100         mutex_lock(&p->ctx->lock);
 101
 102         /* get chunks */
 103         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 104         if (copy_from_user(chunk_array, chunk_array_user,
 105                            sizeof(uint64_t)*cs->in.num_chunks)) {
 106                 ret = -EFAULT;
 107                 goto free_chunk;
 108         }
 109
 110         p->nchunks = cs->in.num_chunks;
 111         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 112                             GFP_KERNEL);
 113         if (!p->chunks) {
 114                 ret = -ENOMEM;
 115                 goto free_chunk;
 116         }
 117
 118         for (i = 0; i < p->nchunks; i++) {
 119                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 120                 struct drm_amdgpu_cs_chunk user_chunk;
 121                 uint32_t __user *cdata;
 122
 123                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 124                 if (copy_from_user(&user_chunk, chunk_ptr,
 125                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 126                         ret = -EFAULT;
 127                         i--;
 128                         goto free_partial_kdata;
 129                 }
 130                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 131                 p->chunks[i].length_dw = user_chunk.length_dw;
 132
 133                 size = p->chunks[i].length_dw;
 134                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 135
 136                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 137                 if (p->chunks[i].kdata == NULL) {
 138                         ret = -ENOMEM;
 139                         i--;
 140                         goto free_partial_kdata;
 141                 }
 142                 size *= sizeof(uint32_t);
 143                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 144                         ret = -EFAULT;
 145                         goto free_partial_kdata;
 146                 }
 147
 148                 switch (p->chunks[i].chunk_id) {
 149                 case AMDGPU_CHUNK_ID_IB:
 150                         ++num_ibs;
 151                         break;
 152
 153                 case AMDGPU_CHUNK_ID_FENCE:
 154                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 155                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 156                                 ret = -EINVAL;
 157                                 goto free_partial_kdata;
 158                         }
 159
 160                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 161                                                          &uf_offset);
 162                         if (ret)
 163                                 goto free_partial_kdata;
 164
 165                         break;
 166
 167                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 168                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 169                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 170                         break;
 171
 172                 default:
 173                         ret = -EINVAL;
 174                         goto free_partial_kdata;
 175                 }
 176         }
 177
 178         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 179         if (ret)
 180                 goto free_all_kdata;
 181
 182         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 183                 ret = -ECANCELED;
 184                 goto free_all_kdata;
 185         }
 186
 187         if (p->uf_entry.robj)
 188                 p->job->uf_addr = uf_offset;
 189         kfree(chunk_array);
 190         return 0;
 191
 192 free_all_kdata:
 193         i = p->nchunks - 1;
 194 free_partial_kdata:
 195         for (; i >= 0; i--)
 196                 kvfree(p->chunks[i].kdata);
 197         kfree(p->chunks);
 198         p->chunks = NULL;
 199         p->nchunks = 0;
 200 free_chunk:
 201         kfree(chunk_array);
 202
 203         return ret;
 204 }
 205
 206 /* Convert microseconds to bytes. */
 207 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 208 {
 209         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 210                 return 0;
 211
 212         /* Since accum_us is incremented by a million per second, just
 213          * multiply it by the number of MB/s to get the number of bytes.
 214          */
 215         return us << adev->mm_stats.log2_max_MBps;
 216 }
 217
 218 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 219 {
 220         if (!adev->mm_stats.log2_max_MBps)
 221                 return 0;
 222
 223         return bytes >> adev->mm_stats.log2_max_MBps;
 224 }
 225
 226 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 227  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 228  * which means it can go over the threshold once. If that happens, the driver
 229  * will be in debt and no other buffer migrations can be done until that debt
 230  * is repaid.
 231  *
 232  * This approach allows moving a buffer of any size (it's important to allow
 233  * that).
 234  *
 235  * The currency is simply time in microseconds and it increases as the clock
 236  * ticks. The accumulated microseconds (us) are converted to bytes and
 237  * returned.
 238  */
 239 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 240                                               u64 *max_bytes,
 241                                               u64 *max_vis_bytes)
 242 {
 243         s64 time_us, increment_us;
 244         u64 free_vram, total_vram, used_vram;
 245
 246         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 247          * throttling.
 248          *
 249          * It means that in order to get full max MBps, at least 5 IBs per
 250          * second must be submitted and not more than 200ms apart from each
 251          * other.
 252          */
 253         const s64 us_upper_bound = 200000;
 254
 255         if (!adev->mm_stats.log2_max_MBps) {
 256                 *max_bytes = 0;
 257                 *max_vis_bytes = 0;
 258                 return;
 259         }
 260
 261         total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
 262         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 263         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 264
 265         spin_lock(&adev->mm_stats.lock);
 266
 267         /* Increase the amount of accumulated us. */
 268         time_us = ktime_to_us(ktime_get());
 269         increment_us = time_us - adev->mm_stats.last_update_us;
 270         adev->mm_stats.last_update_us = time_us;
 271         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 272                                       us_upper_bound);
 273
 274         /* This prevents the short period of low performance when the VRAM
 275          * usage is low and the driver is in debt or doesn't have enough
 276          * accumulated us to fill VRAM quickly.
 277          *
 278          * The situation can occur in these cases:
 279          * - a lot of VRAM is freed by userspace
 280          * - the presence of a big buffer causes a lot of evictions
 281          *   (solution: split buffers into smaller ones)
 282          *
 283          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 284          * accum_us to a positive number.
 285          */
 286         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 287                 s64 min_us;
 288
 289                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 290                  * VRAM now.
 291                  */
 292                 if (!(adev->flags & AMD_IS_APU))
 293                         min_us = bytes_to_us(adev, free_vram / 4);
 294                 else
 295                         min_us = 0; /* Reset accum_us on APUs. */
 296
 297                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 298         }
 299
 300         /* This is set to 0 if the driver is in debt to disallow (optional)
 301          * buffer moves.
 302          */
 303         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 304
 305         /* Do the same for visible VRAM if half of it is free */
 306         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 307                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 308                 u64 used_vis_vram =
 309                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 310
 311                 if (used_vis_vram < total_vis_vram) {
 312                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 313                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 314                                                           increment_us, us_upper_bound);
 315
 316                         if (free_vis_vram >= total_vis_vram / 2)
 317                                 adev->mm_stats.accum_us_vis =
 318                                         max(bytes_to_us(adev, free_vis_vram / 2),
 319                                             adev->mm_stats.accum_us_vis);
 320                 }
 321
 322                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 323         } else {
 324                 *max_vis_bytes = 0;
 325         }
 326
 327         spin_unlock(&adev->mm_stats.lock);
 328 }
 329
 330 /* Report how many bytes have really been moved for the last command
 331  * submission. This can result in a debt that can stop buffer migrations
 332  * temporarily.
 333  */
 334 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 335                                   u64 num_vis_bytes)
 336 {
 337         spin_lock(&adev->mm_stats.lock);
 338         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 339         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 340         spin_unlock(&adev->mm_stats.lock);
 341 }
 342
 343 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 344                                  struct amdgpu_bo *bo)
 345 {
 346         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 347         struct ttm_operation_ctx ctx = {
 348                 .interruptible = true,
 349                 .no_wait_gpu = false,
 350                 .resv = bo->tbo.resv,
 351                 .flags = 0
 352         };
 353         uint32_t domain;
 354         int r;
 355
 356         if (bo->pin_count)
 357                 return 0;
 358
 359         /* Don't move this buffer if we have depleted our allowance
 360          * to move it. Don't move anything if the threshold is zero.
 361          */
 362         if (p->bytes_moved < p->bytes_moved_threshold) {
 363                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 364                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 365                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 366                          * visible VRAM if we've depleted our allowance to do
 367                          * that.
 368                          */
 369                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 370                                 domain = bo->preferred_domains;
 371                         else
 372                                 domain = bo->allowed_domains;
 373                 } else {
 374                         domain = bo->preferred_domains;
 375                 }
 376         } else {
 377                 domain = bo->allowed_domains;
 378         }
 379
 380 retry:
 381         amdgpu_ttm_placement_from_domain(bo, domain);
 382         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 383
 384         p->bytes_moved += ctx.bytes_moved;
 385         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 386             amdgpu_bo_in_cpu_visible_vram(bo))
 387                 p->bytes_moved_vis += ctx.bytes_moved;
 388
 389         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 390                 domain = bo->allowed_domains;
 391                 goto retry;
 392         }
 393
 394         return r;
 395 }
 396
 397 /* Last resort, try to evict something from the current working set */
 398 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 399                                 struct amdgpu_bo *validated)
 400 {
 401         uint32_t domain = validated->allowed_domains;
 402         struct ttm_operation_ctx ctx = { true, false };
 403         int r;
 404
 405         if (!p->evictable)
 406                 return false;
 407
 408         for (;&p->evictable->tv.head != &p->validated;
 409              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 410
 411                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 412                 struct amdgpu_bo *bo = candidate->robj;
 413                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 414                 bool update_bytes_moved_vis;
 415                 uint32_t other;
 416
 417                 /* If we reached our current BO we can forget it */
 418                 if (candidate->robj == validated)
 419                         break;
 420
 421                 /* We can't move pinned BOs here */
 422                 if (bo->pin_count)
 423                         continue;
 424
 425                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 426
 427                 /* Check if this BO is in one of the domains we need space for */
 428                 if (!(other & domain))
 429                         continue;
 430
 431                 /* Check if we can move this BO somewhere else */
 432                 other = bo->allowed_domains & ~domain;
 433                 if (!other)
 434                         continue;
 435
 436                 /* Good we can try to move this BO somewhere else */
 437                 update_bytes_moved_vis =
 438                                 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 439                                 amdgpu_bo_in_cpu_visible_vram(bo);
 440                 amdgpu_ttm_placement_from_domain(bo, other);
 441                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 442                 p->bytes_moved += ctx.bytes_moved;
 443                 if (update_bytes_moved_vis)
 444                         p->bytes_moved_vis += ctx.bytes_moved;
 445
 446                 if (unlikely(r))
 447                         break;
 448
 449                 p->evictable = list_prev_entry(p->evictable, tv.head);
 450                 list_move(&candidate->tv.head, &p->validated);
 451
 452                 return true;
 453         }
 454
 455         return false;
 456 }
 457
 458 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 459 {
 460         struct amdgpu_cs_parser *p = param;
 461         int r;
 462
 463         do {
 464                 r = amdgpu_cs_bo_validate(p, bo);
 465         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 466         if (r)
 467                 return r;
 468
 469         if (bo->shadow)
 470                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 471
 472         return r;
 473 }
 474
 475 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 476                             struct list_head *validated)
 477 {
 478         struct ttm_operation_ctx ctx = { true, false };
 479         struct amdgpu_bo_list_entry *lobj;
 480         int r;
 481
 482         list_for_each_entry(lobj, validated, tv.head) {
 483                 struct amdgpu_bo *bo = lobj->robj;
 484                 bool binding_userptr = false;
 485                 struct mm_struct *usermm;
 486
 487                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 488                 if (usermm && usermm != current->mm)
 489                         return -EPERM;
 490
 491                 /* Check if we have user pages and nobody bound the BO already */
 492                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 493                     lobj->user_pages) {
 494                         amdgpu_ttm_placement_from_domain(bo,
 495                                                          AMDGPU_GEM_DOMAIN_CPU);
 496                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 497                         if (r)
 498                                 return r;
 499                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 500                                                      lobj->user_pages);
 501                         binding_userptr = true;
 502                 }
 503
 504                 if (p->evictable == lobj)
 505                         p->evictable = NULL;
 506
 507                 r = amdgpu_cs_validate(p, bo);
 508                 if (r)
 509                         return r;
 510
 511                 if (binding_userptr) {
 512                         kvfree(lobj->user_pages);
 513                         lobj->user_pages = NULL;
 514                 }
 515         }
 516         return 0;
 517 }
 518
 519 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 520                                 union drm_amdgpu_cs *cs)
 521 {
 522         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 523         struct amdgpu_bo_list_entry *e;
 524         struct list_head duplicates;
 525         unsigned i, tries = 10;
 526         struct amdgpu_bo *gds;
 527         struct amdgpu_bo *gws;
 528         struct amdgpu_bo *oa;
 529         int r;
 530
 531         INIT_LIST_HEAD(&p->validated);
 532
 533         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 534         if (p->bo_list) {
 535                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 536                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 537                         p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 538         }
 539
 540         INIT_LIST_HEAD(&duplicates);
 541         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 542
 543         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 544                 list_add(&p->uf_entry.tv.head, &p->validated);
 545
 546         while (1) {
 547                 struct list_head need_pages;
 548                 unsigned i;
 549
 550                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 551                                            &duplicates);
 552                 if (unlikely(r != 0)) {
 553                         if (r != -ERESTARTSYS)
 554                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 555                         goto error_free_pages;
 556                 }
 557
 558                 /* Without a BO list we don't have userptr BOs */
 559                 if (!p->bo_list)
 560                         break;
 561
 562                 INIT_LIST_HEAD(&need_pages);
 563                 for (i = p->bo_list->first_userptr;
 564                      i < p->bo_list->num_entries; ++i) {
 565                         struct amdgpu_bo *bo;
 566
 567                         e = &p->bo_list->array[i];
 568                         bo = e->robj;
 569
 570                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 571                                  &e->user_invalidated) && e->user_pages) {
 572
 573                                 /* We acquired a page array, but somebody
 574                                  * invalidated it. Free it and try again
 575                                  */
 576                                 release_pages(e->user_pages,
 577                                               bo->tbo.ttm->num_pages);
 578                                 kvfree(e->user_pages);
 579                                 e->user_pages = NULL;
 580                         }
 581
 582                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 583                             !e->user_pages) {
 584                                 list_del(&e->tv.head);
 585                                 list_add(&e->tv.head, &need_pages);
 586
 587                                 amdgpu_bo_unreserve(e->robj);
 588                         }
 589                 }
 590
 591                 if (list_empty(&need_pages))
 592                         break;
 593
 594                 /* Unreserve everything again. */
 595                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 596
 597                 /* We tried too many times, just abort */
 598                 if (!--tries) {
 599                         r = -EDEADLK;
 600                         DRM_ERROR("deadlock in %s\n", __func__);
 601                         goto error_free_pages;
 602                 }
 603
 604                 /* Fill the page arrays for all userptrs. */
 605                 list_for_each_entry(e, &need_pages, tv.head) {
 606                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 607
 608                         e->user_pages = kvmalloc_array(ttm->num_pages,
 609                                                          sizeof(struct page*),
 610                                                          GFP_KERNEL | __GFP_ZERO);
 611                         if (!e->user_pages) {
 612                                 r = -ENOMEM;
 613                                 DRM_ERROR("calloc failure in %s\n", __func__);
 614                                 goto error_free_pages;
 615                         }
 616
 617                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 618                         if (r) {
 619                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 620                                 kvfree(e->user_pages);
 621                                 e->user_pages = NULL;
 622                                 goto error_free_pages;
 623                         }
 624                 }
 625
 626                 /* And try again. */
 627                 list_splice(&need_pages, &p->validated);
 628         }
 629
 630         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 631                                           &p->bytes_moved_vis_threshold);
 632         p->bytes_moved = 0;
 633         p->bytes_moved_vis = 0;
 634         p->evictable = list_last_entry(&p->validated,
 635                                        struct amdgpu_bo_list_entry,
 636                                        tv.head);
 637
 638         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 639                                       amdgpu_cs_validate, p);
 640         if (r) {
 641                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 642                 goto error_validate;
 643         }
 644
 645         r = amdgpu_cs_list_validate(p, &duplicates);
 646         if (r) {
 647                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 648                 goto error_validate;
 649         }
 650
 651         r = amdgpu_cs_list_validate(p, &p->validated);
 652         if (r) {
 653                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 654                 goto error_validate;
 655         }
 656
 657         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 658                                      p->bytes_moved_vis);
 659
 660         if (p->bo_list) {
 661                 struct amdgpu_vm *vm = &fpriv->vm;
 662                 unsigned i;
 663
 664                 gds = p->bo_list->gds_obj;
 665                 gws = p->bo_list->gws_obj;
 666                 oa = p->bo_list->oa_obj;
 667                 for (i = 0; i < p->bo_list->num_entries; i++) {
 668                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 669
 670                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 671                 }
 672         } else {
 673                 gds = p->adev->gds.gds_gfx_bo;
 674                 gws = p->adev->gds.gws_gfx_bo;
 675                 oa = p->adev->gds.oa_gfx_bo;
 676         }
 677
 678         if (gds) {
 679                 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 680                 p->job->gds_size = amdgpu_bo_size(gds);
 681         }
 682         if (gws) {
 683                 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 684                 p->job->gws_size = amdgpu_bo_size(gws);
 685         }
 686         if (oa) {
 687                 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 688                 p->job->oa_size = amdgpu_bo_size(oa);
 689         }
 690
 691         if (!r && p->uf_entry.robj) {
 692                 struct amdgpu_bo *uf = p->uf_entry.robj;
 693
 694                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 695                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 696         }
 697
 698 error_validate:
 699         if (r)
 700                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 701
 702 error_free_pages:
 703
 704         if (p->bo_list) {
 705                 for (i = p->bo_list->first_userptr;
 706                      i < p->bo_list->num_entries; ++i) {
 707                         e = &p->bo_list->array[i];
 708
 709                         if (!e->user_pages)
 710                                 continue;
 711
 712                         release_pages(e->user_pages,
 713                                       e->robj->tbo.ttm->num_pages);
 714                         kvfree(e->user_pages);
 715                 }
 716         }
 717
 718         return r;
 719 }
 720
 721 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 722 {
 723         struct amdgpu_bo_list_entry *e;
 724         int r;
 725
 726         list_for_each_entry(e, &p->validated, tv.head) {
 727                 struct reservation_object *resv = e->robj->tbo.resv;
 728                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 729                                      amdgpu_bo_explicit_sync(e->robj));
 730
 731                 if (r)
 732                         return r;
 733         }
 734         return 0;
 735 }
 736
 737 /**
 738  * cs_parser_fini() - clean parser states
 739  * @parser:     parser structure holding parsing context.
 740  * @error:      error number
 741  *
 742  * If error is set than unvalidate buffer, otherwise just free memory
 743  * used by parsing context.
 744  **/
 745 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 746                                   bool backoff)
 747 {
 748         unsigned i;
 749
 750         if (error && backoff)
 751                 ttm_eu_backoff_reservation(&parser->ticket,
 752                                            &parser->validated);
 753
 754         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 755                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 756         kfree(parser->post_dep_syncobjs);
 757
 758         dma_fence_put(parser->fence);
 759
 760         if (parser->ctx) {
 761                 mutex_unlock(&parser->ctx->lock);
 762                 amdgpu_ctx_put(parser->ctx);
 763         }
 764         if (parser->bo_list)
 765                 amdgpu_bo_list_put(parser->bo_list);
 766
 767         for (i = 0; i < parser->nchunks; i++)
 768                 kvfree(parser->chunks[i].kdata);
 769         kfree(parser->chunks);
 770         if (parser->job)
 771                 amdgpu_job_free(parser->job);
 772         amdgpu_bo_unref(&parser->uf_entry.robj);
 773 }
 774
 775 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 776 {
 777         struct amdgpu_device *adev = p->adev;
 778         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 779         struct amdgpu_vm *vm = &fpriv->vm;
 780         struct amdgpu_bo_va *bo_va;
 781         struct amdgpu_bo *bo;
 782         int i, r;
 783
 784         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 785         if (r)
 786                 return r;
 787
 788         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 789         if (r)
 790                 return r;
 791
 792         r = amdgpu_sync_fence(adev, &p->job->sync,
 793                               fpriv->prt_va->last_pt_update, false);
 794         if (r)
 795                 return r;
 796
 797         if (amdgpu_sriov_vf(adev)) {
 798                 struct dma_fence *f;
 799
 800                 bo_va = fpriv->csa_va;
 801                 BUG_ON(!bo_va);
 802                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 803                 if (r)
 804                         return r;
 805
 806                 f = bo_va->last_pt_update;
 807                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 808                 if (r)
 809                         return r;
 810         }
 811
 812         if (p->bo_list) {
 813                 for (i = 0; i < p->bo_list->num_entries; i++) {
 814                         struct dma_fence *f;
 815
 816                         /* ignore duplicates */
 817                         bo = p->bo_list->array[i].robj;
 818                         if (!bo)
 819                                 continue;
 820
 821                         bo_va = p->bo_list->array[i].bo_va;
 822                         if (bo_va == NULL)
 823                                 continue;
 824
 825                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 826                         if (r)
 827                                 return r;
 828
 829                         f = bo_va->last_pt_update;
 830                         r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 831                         if (r)
 832                                 return r;
 833                 }
 834
 835         }
 836
 837         r = amdgpu_vm_handle_moved(adev, vm);
 838         if (r)
 839                 return r;
 840
 841         r = amdgpu_vm_update_directories(adev, vm);
 842         if (r)
 843                 return r;
 844
 845         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 846         if (r)
 847                 return r;
 848
 849         if (amdgpu_vm_debug && p->bo_list) {
 850                 /* Invalidate all BOs to test for userspace bugs */
 851                 for (i = 0; i < p->bo_list->num_entries; i++) {
 852                         /* ignore duplicates */
 853                         bo = p->bo_list->array[i].robj;
 854                         if (!bo)
 855                                 continue;
 856
 857                         amdgpu_vm_bo_invalidate(adev, bo, false);
 858                 }
 859         }
 860
 861         return r;
 862 }
 863
 864 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 865                                  struct amdgpu_cs_parser *p)
 866 {
 867         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 868         struct amdgpu_vm *vm = &fpriv->vm;
 869         struct amdgpu_ring *ring = p->job->ring;
 870         int r;
 871
 872         /* Only for UVD/VCE VM emulation */
 873         if (p->job->ring->funcs->parse_cs) {
 874                 unsigned i, j;
 875
 876                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 877                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 878                         struct amdgpu_bo_va_mapping *m;
 879                         struct amdgpu_bo *aobj = NULL;
 880                         struct amdgpu_cs_chunk *chunk;
 881                         uint64_t offset, va_start;
 882                         struct amdgpu_ib *ib;
 883                         uint8_t *kptr;
 884
 885                         chunk = &p->chunks[i];
 886                         ib = &p->job->ibs[j];
 887                         chunk_ib = chunk->kdata;
 888
 889                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 890                                 continue;
 891
 892                         va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
 893                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 894                         if (r) {
 895                                 DRM_ERROR("IB va_start is invalid\n");
 896                                 return r;
 897                         }
 898
 899                         if ((va_start + chunk_ib->ib_bytes) >
 900                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 901                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 902                                 return -EINVAL;
 903                         }
 904
 905                         /* the IB should be reserved at this point */
 906                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 907                         if (r) {
 908                                 return r;
 909                         }
 910
 911                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 912                         kptr += va_start - offset;
 913
 914                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 915                         amdgpu_bo_kunmap(aobj);
 916
 917                         r = amdgpu_ring_parse_cs(ring, p, j);
 918                         if (r)
 919                                 return r;
 920
 921                         j++;
 922                 }
 923         }
 924
 925         if (p->job->vm) {
 926                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 927
 928                 r = amdgpu_bo_vm_update_pte(p);
 929                 if (r)
 930                         return r;
 931         }
 932
 933         return amdgpu_cs_sync_rings(p);
 934 }
 935
 936 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 937                              struct amdgpu_cs_parser *parser)
 938 {
 939         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 940         struct amdgpu_vm *vm = &fpriv->vm;
 941         int i, j;
 942         int r, ce_preempt = 0, de_preempt = 0;
 943
 944         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 945                 struct amdgpu_cs_chunk *chunk;
 946                 struct amdgpu_ib *ib;
 947                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 948                 struct amdgpu_ring *ring;
 949
 950                 chunk = &parser->chunks[i];
 951                 ib = &parser->job->ibs[j];
 952                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 953
 954                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 955                         continue;
 956
 957                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 958                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 959                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 960                                         ce_preempt++;
 961                                 else
 962                                         de_preempt++;
 963                         }
 964
 965                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 966                         if (ce_preempt > 1 || de_preempt > 1)
 967                                 return -EINVAL;
 968                 }
 969
 970                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 971                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 972                 if (r)
 973                         return r;
 974
 975                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 976                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 977                         if (!parser->ctx->preamble_presented) {
 978                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 979                                 parser->ctx->preamble_presented = true;
 980                         }
 981                 }
 982
 983                 if (parser->job->ring && parser->job->ring != ring)
 984                         return -EINVAL;
 985
 986                 parser->job->ring = ring;
 987
 988                 r =  amdgpu_ib_get(adev, vm,
 989                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
 990                                         ib);
 991                 if (r) {
 992                         DRM_ERROR("Failed to get ib !\n");
 993                         return r;
 994                 }
 995
 996                 ib->gpu_addr = chunk_ib->va_start;
 997                 ib->length_dw = chunk_ib->ib_bytes / 4;
 998                 ib->flags = chunk_ib->flags;
 999
1000                 j++;
1001         }
1002
1003         /* UVD & VCE fw doesn't support user fences */
1004         if (parser->job->uf_addr && (
1005             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1006             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1007                 return -EINVAL;
1008
1009         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
1010 }
1011
1012 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1013                                        struct amdgpu_cs_chunk *chunk)
1014 {
1015         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1016         unsigned num_deps;
1017         int i, r;
1018         struct drm_amdgpu_cs_chunk_dep *deps;
1019
1020         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1021         num_deps = chunk->length_dw * 4 /
1022                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1023
1024         for (i = 0; i < num_deps; ++i) {
1025                 struct amdgpu_ring *ring;
1026                 struct amdgpu_ctx *ctx;
1027                 struct dma_fence *fence;
1028
1029                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1030                 if (ctx == NULL)
1031                         return -EINVAL;
1032
1033                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1034                                          deps[i].ip_type,
1035                                          deps[i].ip_instance,
1036                                          deps[i].ring, &ring);
1037                 if (r) {
1038                         amdgpu_ctx_put(ctx);
1039                         return r;
1040                 }
1041
1042                 fence = amdgpu_ctx_get_fence(ctx, ring,
1043                                              deps[i].handle);
1044                 if (IS_ERR(fence)) {
1045                         r = PTR_ERR(fence);
1046                         amdgpu_ctx_put(ctx);
1047                         return r;
1048                 } else if (fence) {
1049                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1050                                         true);
1051                         dma_fence_put(fence);
1052                         amdgpu_ctx_put(ctx);
1053                         if (r)
1054                                 return r;
1055                 }
1056         }
1057         return 0;
1058 }
1059
1060 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1061                                                  uint32_t handle)
1062 {
1063         int r;
1064         struct dma_fence *fence;
1065         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1066         if (r)
1067                 return r;
1068
1069         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1070         dma_fence_put(fence);
1071
1072         return r;
1073 }
1074
1075 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1076                                             struct amdgpu_cs_chunk *chunk)
1077 {
1078         unsigned num_deps;
1079         int i, r;
1080         struct drm_amdgpu_cs_chunk_sem *deps;
1081
1082         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1083         num_deps = chunk->length_dw * 4 /
1084                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1085
1086         for (i = 0; i < num_deps; ++i) {
1087                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1088                 if (r)
1089                         return r;
1090         }
1091         return 0;
1092 }
1093
1094 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1095                                              struct amdgpu_cs_chunk *chunk)
1096 {
1097         unsigned num_deps;
1098         int i;
1099         struct drm_amdgpu_cs_chunk_sem *deps;
1100         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1101         num_deps = chunk->length_dw * 4 /
1102                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1103
1104         p->post_dep_syncobjs = kmalloc_array(num_deps,
1105                                              sizeof(struct drm_syncobj *),
1106                                              GFP_KERNEL);
1107         p->num_post_dep_syncobjs = 0;
1108
1109         if (!p->post_dep_syncobjs)
1110                 return -ENOMEM;
1111
1112         for (i = 0; i < num_deps; ++i) {
1113                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1114                 if (!p->post_dep_syncobjs[i])
1115                         return -EINVAL;
1116                 p->num_post_dep_syncobjs++;
1117         }
1118         return 0;
1119 }
1120
1121 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1122                                   struct amdgpu_cs_parser *p)
1123 {
1124         int i, r;
1125
1126         for (i = 0; i < p->nchunks; ++i) {
1127                 struct amdgpu_cs_chunk *chunk;
1128
1129                 chunk = &p->chunks[i];
1130
1131                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1132                         r = amdgpu_cs_process_fence_dep(p, chunk);
1133                         if (r)
1134                                 return r;
1135                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1136                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1137                         if (r)
1138                                 return r;
1139                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1140                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1141                         if (r)
1142                                 return r;
1143                 }
1144         }
1145
1146         return 0;
1147 }
1148
1149 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1150 {
1151         int i;
1152
1153         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1154                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1155 }
1156
1157 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1158                             union drm_amdgpu_cs *cs)
1159 {
1160         struct amdgpu_ring *ring = p->job->ring;
1161         struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1162         struct amdgpu_job *job;
1163         unsigned i;
1164         uint64_t seq;
1165
1166         int r;
1167
1168         amdgpu_mn_lock(p->mn);
1169         if (p->bo_list) {
1170                 for (i = p->bo_list->first_userptr;
1171                      i < p->bo_list->num_entries; ++i) {
1172                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1173
1174                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1175                                 amdgpu_mn_unlock(p->mn);
1176                                 return -ERESTARTSYS;
1177                         }
1178                 }
1179         }
1180
1181         job = p->job;
1182         p->job = NULL;
1183
1184         r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1185         if (r) {
1186                 amdgpu_job_free(job);
1187                 amdgpu_mn_unlock(p->mn);
1188                 return r;
1189         }
1190
1191         job->owner = p->filp;
1192         job->fence_ctx = entity->fence_context;
1193         p->fence = dma_fence_get(&job->base.s_fence->finished);
1194
1195         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1196         if (r) {
1197                 dma_fence_put(p->fence);
1198                 dma_fence_put(&job->base.s_fence->finished);
1199                 amdgpu_job_free(job);
1200                 amdgpu_mn_unlock(p->mn);
1201                 return r;
1202         }
1203
1204         amdgpu_cs_post_dependencies(p);
1205
1206         cs->out.handle = seq;
1207         job->uf_sequence = seq;
1208
1209         amdgpu_job_free_resources(job);
1210         amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1211
1212         trace_amdgpu_cs_ioctl(job);
1213         drm_sched_entity_push_job(&job->base, entity);
1214
1215         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1216         amdgpu_mn_unlock(p->mn);
1217
1218         return 0;
1219 }
1220
1221 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1222 {
1223         struct amdgpu_device *adev = dev->dev_private;
1224         union drm_amdgpu_cs *cs = data;
1225         struct amdgpu_cs_parser parser = {};
1226         bool reserved_buffers = false;
1227         int i, r;
1228
1229         if (!adev->accel_working)
1230                 return -EBUSY;
1231
1232         parser.adev = adev;
1233         parser.filp = filp;
1234
1235         r = amdgpu_cs_parser_init(&parser, data);
1236         if (r) {
1237                 DRM_ERROR("Failed to initialize parser !\n");
1238                 goto out;
1239         }
1240
1241         r = amdgpu_cs_ib_fill(adev, &parser);
1242         if (r)
1243                 goto out;
1244
1245         r = amdgpu_cs_parser_bos(&parser, data);
1246         if (r) {
1247                 if (r == -ENOMEM)
1248                         DRM_ERROR("Not enough memory for command submission!\n");
1249                 else if (r != -ERESTARTSYS)
1250                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1251                 goto out;
1252         }
1253
1254         reserved_buffers = true;
1255
1256         r = amdgpu_cs_dependencies(adev, &parser);
1257         if (r) {
1258                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1259                 goto out;
1260         }
1261
1262         for (i = 0; i < parser.job->num_ibs; i++)
1263                 trace_amdgpu_cs(&parser, i);
1264
1265         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1266         if (r)
1267                 goto out;
1268
1269         r = amdgpu_cs_submit(&parser, cs);
1270
1271 out:
1272         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1273         return r;
1274 }
1275
1276 /**
1277  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1278  *
1279  * @dev: drm device
1280  * @data: data from userspace
1281  * @filp: file private
1282  *
1283  * Wait for the command submission identified by handle to finish.
1284  */
1285 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1286                          struct drm_file *filp)
1287 {
1288         union drm_amdgpu_wait_cs *wait = data;
1289         struct amdgpu_device *adev = dev->dev_private;
1290         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1291         struct amdgpu_ring *ring = NULL;
1292         struct amdgpu_ctx *ctx;
1293         struct dma_fence *fence;
1294         long r;
1295
1296         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1297         if (ctx == NULL)
1298                 return -EINVAL;
1299
1300         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1301                                  wait->in.ip_type, wait->in.ip_instance,
1302                                  wait->in.ring, &ring);
1303         if (r) {
1304                 amdgpu_ctx_put(ctx);
1305                 return r;
1306         }
1307
1308         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1309         if (IS_ERR(fence))
1310                 r = PTR_ERR(fence);
1311         else if (fence) {
1312                 r = dma_fence_wait_timeout(fence, true, timeout);
1313                 if (r > 0 && fence->error)
1314                         r = fence->error;
1315                 dma_fence_put(fence);
1316         } else
1317                 r = 1;
1318
1319         amdgpu_ctx_put(ctx);
1320         if (r < 0)
1321                 return r;
1322
1323         memset(wait, 0, sizeof(*wait));
1324         wait->out.status = (r == 0);
1325
1326         return 0;
1327 }
1328
1329 /**
1330  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1331  *
1332  * @adev: amdgpu device
1333  * @filp: file private
1334  * @user: drm_amdgpu_fence copied from user space
1335  */
1336 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1337                                              struct drm_file *filp,
1338                                              struct drm_amdgpu_fence *user)
1339 {
1340         struct amdgpu_ring *ring;
1341         struct amdgpu_ctx *ctx;
1342         struct dma_fence *fence;
1343         int r;
1344
1345         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1346         if (ctx == NULL)
1347                 return ERR_PTR(-EINVAL);
1348
1349         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1350                                  user->ip_instance, user->ring, &ring);
1351         if (r) {
1352                 amdgpu_ctx_put(ctx);
1353                 return ERR_PTR(r);
1354         }
1355
1356         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1357         amdgpu_ctx_put(ctx);
1358
1359         return fence;
1360 }
1361
1362 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1363                                     struct drm_file *filp)
1364 {
1365         struct amdgpu_device *adev = dev->dev_private;
1366         union drm_amdgpu_fence_to_handle *info = data;
1367         struct dma_fence *fence;
1368         struct drm_syncobj *syncobj;
1369         struct sync_file *sync_file;
1370         int fd, r;
1371
1372         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1373         if (IS_ERR(fence))
1374                 return PTR_ERR(fence);
1375
1376         switch (info->in.what) {
1377         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1378                 r = drm_syncobj_create(&syncobj, 0, fence);
1379                 dma_fence_put(fence);
1380                 if (r)
1381                         return r;
1382                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1383                 drm_syncobj_put(syncobj);
1384                 return r;
1385
1386         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1387                 r = drm_syncobj_create(&syncobj, 0, fence);
1388                 dma_fence_put(fence);
1389                 if (r)
1390                         return r;
1391                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1392                 drm_syncobj_put(syncobj);
1393                 return r;
1394
1395         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1396                 fd = get_unused_fd_flags(O_CLOEXEC);
1397                 if (fd < 0) {
1398                         dma_fence_put(fence);
1399                         return fd;
1400                 }
1401
1402                 sync_file = sync_file_create(fence);
1403                 dma_fence_put(fence);
1404                 if (!sync_file) {
1405                         put_unused_fd(fd);
1406                         return -ENOMEM;
1407                 }
1408
1409                 fd_install(fd, sync_file->file);
1410                 info->out.handle = fd;
1411                 return 0;
1412
1413         default:
1414                 return -EINVAL;
1415         }
1416 }
1417
1418 /**
1419  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1420  *
1421  * @adev: amdgpu device
1422  * @filp: file private
1423  * @wait: wait parameters
1424  * @fences: array of drm_amdgpu_fence
1425  */
1426 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1427                                      struct drm_file *filp,
1428                                      union drm_amdgpu_wait_fences *wait,
1429                                      struct drm_amdgpu_fence *fences)
1430 {
1431         uint32_t fence_count = wait->in.fence_count;
1432         unsigned int i;
1433         long r = 1;
1434
1435         for (i = 0; i < fence_count; i++) {
1436                 struct dma_fence *fence;
1437                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1438
1439                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1440                 if (IS_ERR(fence))
1441                         return PTR_ERR(fence);
1442                 else if (!fence)
1443                         continue;
1444
1445                 r = dma_fence_wait_timeout(fence, true, timeout);
1446                 dma_fence_put(fence);
1447                 if (r < 0)
1448                         return r;
1449
1450                 if (r == 0)
1451                         break;
1452
1453                 if (fence->error)
1454                         return fence->error;
1455         }
1456
1457         memset(wait, 0, sizeof(*wait));
1458         wait->out.status = (r > 0);
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1465  *
1466  * @adev: amdgpu device
1467  * @filp: file private
1468  * @wait: wait parameters
1469  * @fences: array of drm_amdgpu_fence
1470  */
1471 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1472                                     struct drm_file *filp,
1473                                     union drm_amdgpu_wait_fences *wait,
1474                                     struct drm_amdgpu_fence *fences)
1475 {
1476         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1477         uint32_t fence_count = wait->in.fence_count;
1478         uint32_t first = ~0;
1479         struct dma_fence **array;
1480         unsigned int i;
1481         long r;
1482
1483         /* Prepare the fence array */
1484         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1485
1486         if (array == NULL)
1487                 return -ENOMEM;
1488
1489         for (i = 0; i < fence_count; i++) {
1490                 struct dma_fence *fence;
1491
1492                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1493                 if (IS_ERR(fence)) {
1494                         r = PTR_ERR(fence);
1495                         goto err_free_fence_array;
1496                 } else if (fence) {
1497                         array[i] = fence;
1498                 } else { /* NULL, the fence has been already signaled */
1499                         r = 1;
1500                         first = i;
1501                         goto out;
1502                 }
1503         }
1504
1505         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1506                                        &first);
1507         if (r < 0)
1508                 goto err_free_fence_array;
1509
1510 out:
1511         memset(wait, 0, sizeof(*wait));
1512         wait->out.status = (r > 0);
1513         wait->out.first_signaled = first;
1514
1515         if (first < fence_count && array[first])
1516                 r = array[first]->error;
1517         else
1518                 r = 0;
1519
1520 err_free_fence_array:
1521         for (i = 0; i < fence_count; i++)
1522                 dma_fence_put(array[i]);
1523         kfree(array);
1524
1525         return r;
1526 }
1527
1528 /**
1529  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1530  *
1531  * @dev: drm device
1532  * @data: data from userspace
1533  * @filp: file private
1534  */
1535 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1536                                 struct drm_file *filp)
1537 {
1538         struct amdgpu_device *adev = dev->dev_private;
1539         union drm_amdgpu_wait_fences *wait = data;
1540         uint32_t fence_count = wait->in.fence_count;
1541         struct drm_amdgpu_fence *fences_user;
1542         struct drm_amdgpu_fence *fences;
1543         int r;
1544
1545         /* Get the fences from userspace */
1546         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1547                         GFP_KERNEL);
1548         if (fences == NULL)
1549                 return -ENOMEM;
1550
1551         fences_user = u64_to_user_ptr(wait->in.fences);
1552         if (copy_from_user(fences, fences_user,
1553                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1554                 r = -EFAULT;
1555                 goto err_free_fences;
1556         }
1557
1558         if (wait->in.wait_all)
1559                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1560         else
1561                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1562
1563 err_free_fences:
1564         kfree(fences);
1565
1566         return r;
1567 }
1568
1569 /**
1570  * amdgpu_cs_find_bo_va - find bo_va for VM address
1571  *
1572  * @parser: command submission parser context
1573  * @addr: VM address
1574  * @bo: resulting BO of the mapping found
1575  *
1576  * Search the buffer objects in the command submission context for a certain
1577  * virtual memory address. Returns allocation structure when found, NULL
1578  * otherwise.
1579  */
1580 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1581                            uint64_t addr, struct amdgpu_bo **bo,
1582                            struct amdgpu_bo_va_mapping **map)
1583 {
1584         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1585         struct ttm_operation_ctx ctx = { false, false };
1586         struct amdgpu_vm *vm = &fpriv->vm;
1587         struct amdgpu_bo_va_mapping *mapping;
1588         int r;
1589
1590         addr /= AMDGPU_GPU_PAGE_SIZE;
1591
1592         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1593         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1594                 return -EINVAL;
1595
1596         *bo = mapping->bo_va->base.bo;
1597         *map = mapping;
1598
1599         /* Double check that the BO is reserved by this CS */
1600         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1601                 return -EINVAL;
1602
1603         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1604                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1605                 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1606                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1607                 if (r)
1608                         return r;
1609         }
1610
1611         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1612 }