drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 116 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 117 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 118 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 119 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 120 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 121
 122 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 123 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 124 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 125 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 126 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 127 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 128 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 129 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 130 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 131 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 132 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 133
 134 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 142 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 143 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 144 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 145 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 146 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 147
 148 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 149 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 150 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 151 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 152 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 153 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 154
 155 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 197 };
 198
 199 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 200 {
 201         /* Pending on emulation bring up */
 202 };
 203
 204 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 205 {
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1258 };
1259
1260 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1261 {
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1300 };
1301
1302 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1303 {
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1344 };
1345
1346 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1347 {
1348         static void *scratch_reg0;
1349         static void *scratch_reg1;
1350         static void *scratch_reg2;
1351         static void *scratch_reg3;
1352         static void *spare_int;
1353         static uint32_t grbm_cntl;
1354         static uint32_t grbm_idx;
1355         uint32_t i = 0;
1356         uint32_t retries = 50000;
1357
1358         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1359         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1360         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1361         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1362         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1363
1364         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1365         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1366
1367         if (amdgpu_sriov_runtime(adev)) {
1368                 pr_err("shouldn't call rlcg write register during runtime\n");
1369                 return;
1370         }
1371
1372         writel(v, scratch_reg0);
1373         writel(offset | 0x80000000, scratch_reg1);
1374         writel(1, spare_int);
1375         for (i = 0; i < retries; i++) {
1376                 u32 tmp;
1377
1378                 tmp = readl(scratch_reg1);
1379                 if (!(tmp & 0x80000000))
1380                         break;
1381
1382                 udelay(10);
1383         }
1384
1385         if (i >= retries)
1386                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1387 }
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1390 {
1391         /* Pending on emulation bring up */
1392 };
1393
1394 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1395 {
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2016 };
2017
2018 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2019 {
2020         /* Pending on emulation bring up */
2021 };
2022
2023 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2024 {
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3077 };
3078
3079 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3080 {
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3117 };
3118
3119 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3120 {
3121         /* Pending on emulation bring up */
3122 };
3123
3124 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3125 {
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3164 };
3165
3166 #define DEFAULT_SH_MEM_CONFIG \
3167         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3168          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3169          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3170          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3171
3172
3173 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3174 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3175 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3176 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3177 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3178                                  struct amdgpu_cu_info *cu_info);
3179 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3180 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3181                                    u32 sh_num, u32 instance);
3182 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3183
3184 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3185 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3186 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3187 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3188 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3189 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3190 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3191
3192 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3193 {
3194         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3195         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3196                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3197         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3198         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3199         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3200         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3201         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3202         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3203 }
3204
3205 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3206                                  struct amdgpu_ring *ring)
3207 {
3208         struct amdgpu_device *adev = kiq_ring->adev;
3209         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3210         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3211         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3212
3213         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3214         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3215         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3216                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3217                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3218                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3219                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3220                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3221                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3222                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3223                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3224                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3225         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3226         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3227         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3228         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3229         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3230 }
3231
3232 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3233                                    struct amdgpu_ring *ring,
3234                                    enum amdgpu_unmap_queues_action action,
3235                                    u64 gpu_addr, u64 seq)
3236 {
3237         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3238
3239         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3240         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3241                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3242                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3243                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3244                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3245         amdgpu_ring_write(kiq_ring,
3246                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3247
3248         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3249                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3250                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3251                 amdgpu_ring_write(kiq_ring, seq);
3252         } else {
3253                 amdgpu_ring_write(kiq_ring, 0);
3254                 amdgpu_ring_write(kiq_ring, 0);
3255                 amdgpu_ring_write(kiq_ring, 0);
3256         }
3257 }
3258
3259 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3260                                    struct amdgpu_ring *ring,
3261                                    u64 addr,
3262                                    u64 seq)
3263 {
3264         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3265
3266         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3267         amdgpu_ring_write(kiq_ring,
3268                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3269                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3270                           PACKET3_QUERY_STATUS_COMMAND(2));
3271         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3272                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3273                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3274         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3275         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3276         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3277         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3278 }
3279
3280 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3281                                 uint16_t pasid, uint32_t flush_type,
3282                                 bool all_hub)
3283 {
3284         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3285         amdgpu_ring_write(kiq_ring,
3286                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3287                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3288                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3289                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3290 }
3291
3292 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3293         .kiq_set_resources = gfx10_kiq_set_resources,
3294         .kiq_map_queues = gfx10_kiq_map_queues,
3295         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3296         .kiq_query_status = gfx10_kiq_query_status,
3297         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3298         .set_resources_size = 8,
3299         .map_queues_size = 7,
3300         .unmap_queues_size = 6,
3301         .query_status_size = 7,
3302         .invalidate_tlbs_size = 2,
3303 };
3304
3305 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3306 {
3307         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3308 }
3309
3310 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3311 {
3312         switch (adev->asic_type) {
3313         case CHIP_NAVI10:
3314                 soc15_program_register_sequence(adev,
3315                                                 golden_settings_gc_10_1,
3316                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3317                 soc15_program_register_sequence(adev,
3318                                                 golden_settings_gc_10_0_nv10,
3319                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3320                 soc15_program_register_sequence(adev,
3321                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3322                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3323                 break;
3324         case CHIP_NAVI14:
3325                 soc15_program_register_sequence(adev,
3326                                                 golden_settings_gc_10_1_1,
3327                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3328                 soc15_program_register_sequence(adev,
3329                                                 golden_settings_gc_10_1_nv14,
3330                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3331                 soc15_program_register_sequence(adev,
3332                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3333                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3334                 break;
3335         case CHIP_NAVI12:
3336                 soc15_program_register_sequence(adev,
3337                                                 golden_settings_gc_10_1_2,
3338                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3339                 soc15_program_register_sequence(adev,
3340                                                 golden_settings_gc_10_1_2_nv12,
3341                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3342                 soc15_program_register_sequence(adev,
3343                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3344                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3345                 break;
3346         case CHIP_SIENNA_CICHLID:
3347                 soc15_program_register_sequence(adev,
3348                                                 golden_settings_gc_10_3,
3349                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3350                 soc15_program_register_sequence(adev,
3351                                                 golden_settings_gc_10_3_sienna_cichlid,
3352                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3353                 break;
3354         case CHIP_NAVY_FLOUNDER:
3355                 soc15_program_register_sequence(adev,
3356                                                 golden_settings_gc_10_3_2,
3357                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3358                 break;
3359
3360         default:
3361                 break;
3362         }
3363 }
3364
3365 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3366 {
3367         adev->gfx.scratch.num_reg = 8;
3368         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3369         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3370 }
3371
3372 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3373                                        bool wc, uint32_t reg, uint32_t val)
3374 {
3375         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3376         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3377                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3378         amdgpu_ring_write(ring, reg);
3379         amdgpu_ring_write(ring, 0);
3380         amdgpu_ring_write(ring, val);
3381 }
3382
3383 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3384                                   int mem_space, int opt, uint32_t addr0,
3385                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3386                                   uint32_t inv)
3387 {
3388         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3389         amdgpu_ring_write(ring,
3390                           /* memory (1) or register (0) */
3391                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3392                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3393                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3394                            WAIT_REG_MEM_ENGINE(eng_sel)));
3395
3396         if (mem_space)
3397                 BUG_ON(addr0 & 0x3); /* Dword align */
3398         amdgpu_ring_write(ring, addr0);
3399         amdgpu_ring_write(ring, addr1);
3400         amdgpu_ring_write(ring, ref);
3401         amdgpu_ring_write(ring, mask);
3402         amdgpu_ring_write(ring, inv); /* poll interval */
3403 }
3404
3405 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3406 {
3407         struct amdgpu_device *adev = ring->adev;
3408         uint32_t scratch;
3409         uint32_t tmp = 0;
3410         unsigned i;
3411         int r;
3412
3413         r = amdgpu_gfx_scratch_get(adev, &scratch);
3414         if (r) {
3415                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3416                 return r;
3417         }
3418
3419         WREG32(scratch, 0xCAFEDEAD);
3420
3421         r = amdgpu_ring_alloc(ring, 3);
3422         if (r) {
3423                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3424                           ring->idx, r);
3425                 amdgpu_gfx_scratch_free(adev, scratch);
3426                 return r;
3427         }
3428
3429         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3430         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3431         amdgpu_ring_write(ring, 0xDEADBEEF);
3432         amdgpu_ring_commit(ring);
3433
3434         for (i = 0; i < adev->usec_timeout; i++) {
3435                 tmp = RREG32(scratch);
3436                 if (tmp == 0xDEADBEEF)
3437                         break;
3438                 if (amdgpu_emu_mode == 1)
3439                         msleep(1);
3440                 else
3441                         udelay(1);
3442         }
3443
3444         if (i >= adev->usec_timeout)
3445                 r = -ETIMEDOUT;
3446
3447         amdgpu_gfx_scratch_free(adev, scratch);
3448
3449         return r;
3450 }
3451
3452 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3453 {
3454         struct amdgpu_device *adev = ring->adev;
3455         struct amdgpu_ib ib;
3456         struct dma_fence *f = NULL;
3457         unsigned index;
3458         uint64_t gpu_addr;
3459         uint32_t tmp;
3460         long r;
3461
3462         r = amdgpu_device_wb_get(adev, &index);
3463         if (r)
3464                 return r;
3465
3466         gpu_addr = adev->wb.gpu_addr + (index * 4);
3467         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3468         memset(&ib, 0, sizeof(ib));
3469         r = amdgpu_ib_get(adev, NULL, 16,
3470                                         AMDGPU_IB_POOL_DIRECT, &ib);
3471         if (r)
3472                 goto err1;
3473
3474         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3475         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3476         ib.ptr[2] = lower_32_bits(gpu_addr);
3477         ib.ptr[3] = upper_32_bits(gpu_addr);
3478         ib.ptr[4] = 0xDEADBEEF;
3479         ib.length_dw = 5;
3480
3481         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3482         if (r)
3483                 goto err2;
3484
3485         r = dma_fence_wait_timeout(f, false, timeout);
3486         if (r == 0) {
3487                 r = -ETIMEDOUT;
3488                 goto err2;
3489         } else if (r < 0) {
3490                 goto err2;
3491         }
3492
3493         tmp = adev->wb.wb[index];
3494         if (tmp == 0xDEADBEEF)
3495                 r = 0;
3496         else
3497                 r = -EINVAL;
3498 err2:
3499         amdgpu_ib_free(adev, &ib, NULL);
3500         dma_fence_put(f);
3501 err1:
3502         amdgpu_device_wb_free(adev, index);
3503         return r;
3504 }
3505
3506 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3507 {
3508         release_firmware(adev->gfx.pfp_fw);
3509         adev->gfx.pfp_fw = NULL;
3510         release_firmware(adev->gfx.me_fw);
3511         adev->gfx.me_fw = NULL;
3512         release_firmware(adev->gfx.ce_fw);
3513         adev->gfx.ce_fw = NULL;
3514         release_firmware(adev->gfx.rlc_fw);
3515         adev->gfx.rlc_fw = NULL;
3516         release_firmware(adev->gfx.mec_fw);
3517         adev->gfx.mec_fw = NULL;
3518         release_firmware(adev->gfx.mec2_fw);
3519         adev->gfx.mec2_fw = NULL;
3520
3521         kfree(adev->gfx.rlc.register_list_format);
3522 }
3523
3524 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3525 {
3526         adev->gfx.cp_fw_write_wait = false;
3527
3528         switch (adev->asic_type) {
3529         case CHIP_NAVI10:
3530         case CHIP_NAVI12:
3531         case CHIP_NAVI14:
3532                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3533                     (adev->gfx.me_feature_version >= 27) &&
3534                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3535                     (adev->gfx.pfp_feature_version >= 27) &&
3536                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3537                     (adev->gfx.mec_feature_version >= 27))
3538                         adev->gfx.cp_fw_write_wait = true;
3539                 break;
3540         case CHIP_SIENNA_CICHLID:
3541         case CHIP_NAVY_FLOUNDER:
3542                 adev->gfx.cp_fw_write_wait = true;
3543                 break;
3544         default:
3545                 break;
3546         }
3547
3548         if (adev->gfx.cp_fw_write_wait == false)
3549                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3550 }
3551
3552
3553 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3554 {
3555         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3556
3557         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3558         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3559         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3560         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3561         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3562         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3563         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3564         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3565         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3566         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3567         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3568         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3569         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3570         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3571                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3572 }
3573
3574 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3575 {
3576         bool ret = false;
3577
3578         switch (adev->pdev->revision) {
3579         case 0xc2:
3580         case 0xc3:
3581                 ret = true;
3582                 break;
3583         default:
3584                 ret = false;
3585                 break;
3586         }
3587
3588         return ret ;
3589 }
3590
3591 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3592 {
3593         switch (adev->asic_type) {
3594         case CHIP_NAVI10:
3595                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3596                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3597                 break;
3598         case CHIP_NAVY_FLOUNDER:
3599                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3600                 break;
3601         default:
3602                 break;
3603         }
3604 }
3605
3606 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3607 {
3608         const char *chip_name;
3609         char fw_name[40];
3610         char wks[10];
3611         int err;
3612         struct amdgpu_firmware_info *info = NULL;
3613         const struct common_firmware_header *header = NULL;
3614         const struct gfx_firmware_header_v1_0 *cp_hdr;
3615         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3616         unsigned int *tmp = NULL;
3617         unsigned int i = 0;
3618         uint16_t version_major;
3619         uint16_t version_minor;
3620
3621         DRM_DEBUG("\n");
3622
3623         memset(wks, 0, sizeof(wks));
3624         switch (adev->asic_type) {
3625         case CHIP_NAVI10:
3626                 chip_name = "navi10";
3627                 break;
3628         case CHIP_NAVI14:
3629                 chip_name = "navi14";
3630                 if (!(adev->pdev->device == 0x7340 &&
3631                       adev->pdev->revision != 0x00))
3632                         snprintf(wks, sizeof(wks), "_wks");
3633                 break;
3634         case CHIP_NAVI12:
3635                 chip_name = "navi12";
3636                 break;
3637         case CHIP_SIENNA_CICHLID:
3638                 chip_name = "sienna_cichlid";
3639                 break;
3640         case CHIP_NAVY_FLOUNDER:
3641                 chip_name = "navy_flounder";
3642                 break;
3643         default:
3644                 BUG();
3645         }
3646
3647         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3648         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3649         if (err)
3650                 goto out;
3651         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3652         if (err)
3653                 goto out;
3654         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3655         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3656         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3657
3658         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3659         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3660         if (err)
3661                 goto out;
3662         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3663         if (err)
3664                 goto out;
3665         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3666         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3667         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3668
3669         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3670         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3671         if (err)
3672                 goto out;
3673         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3674         if (err)
3675                 goto out;
3676         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3677         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3678         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3679
3680         if (!amdgpu_sriov_vf(adev)) {
3681                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3682                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3683                 if (err)
3684                         goto out;
3685                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3686                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3687                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3688                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3689                 if (version_major == 2 && version_minor == 1)
3690                         adev->gfx.rlc.is_rlc_v2_1 = true;
3691
3692                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3693                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3694                 adev->gfx.rlc.save_and_restore_offset =
3695                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3696                 adev->gfx.rlc.clear_state_descriptor_offset =
3697                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3698                 adev->gfx.rlc.avail_scratch_ram_locations =
3699                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3700                 adev->gfx.rlc.reg_restore_list_size =
3701                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3702                 adev->gfx.rlc.reg_list_format_start =
3703                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3704                 adev->gfx.rlc.reg_list_format_separate_start =
3705                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3706                 adev->gfx.rlc.starting_offsets_start =
3707                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3708                 adev->gfx.rlc.reg_list_format_size_bytes =
3709                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3710                 adev->gfx.rlc.reg_list_size_bytes =
3711                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3712                 adev->gfx.rlc.register_list_format =
3713                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3714                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3715                 if (!adev->gfx.rlc.register_list_format) {
3716                         err = -ENOMEM;
3717                         goto out;
3718                 }
3719
3720                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3721                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3722                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3723                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3724
3725                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3726
3727                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3728                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3729                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3730                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3731
3732                 if (adev->gfx.rlc.is_rlc_v2_1)
3733                         gfx_v10_0_init_rlc_ext_microcode(adev);
3734         }
3735
3736         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3737         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3738         if (err)
3739                 goto out;
3740         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3741         if (err)
3742                 goto out;
3743         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3744         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3745         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3746
3747         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3748         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3749         if (!err) {
3750                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3751                 if (err)
3752                         goto out;
3753                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3754                 adev->gfx.mec2_fw->data;
3755                 adev->gfx.mec2_fw_version =
3756                 le32_to_cpu(cp_hdr->header.ucode_version);
3757                 adev->gfx.mec2_feature_version =
3758                 le32_to_cpu(cp_hdr->ucode_feature_version);
3759         } else {
3760                 err = 0;
3761                 adev->gfx.mec2_fw = NULL;
3762         }
3763
3764         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3765                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3766                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3767                 info->fw = adev->gfx.pfp_fw;
3768                 header = (const struct common_firmware_header *)info->fw->data;
3769                 adev->firmware.fw_size +=
3770                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3771
3772                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3773                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3774                 info->fw = adev->gfx.me_fw;
3775                 header = (const struct common_firmware_header *)info->fw->data;
3776                 adev->firmware.fw_size +=
3777                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3778
3779                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3780                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3781                 info->fw = adev->gfx.ce_fw;
3782                 header = (const struct common_firmware_header *)info->fw->data;
3783                 adev->firmware.fw_size +=
3784                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3785
3786                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3787                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3788                 info->fw = adev->gfx.rlc_fw;
3789                 if (info->fw) {
3790                         header = (const struct common_firmware_header *)info->fw->data;
3791                         adev->firmware.fw_size +=
3792                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3793                 }
3794                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3795                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3796                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3797                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3798                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3799                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3800                         info->fw = adev->gfx.rlc_fw;
3801                         adev->firmware.fw_size +=
3802                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3803
3804                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3805                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3806                         info->fw = adev->gfx.rlc_fw;
3807                         adev->firmware.fw_size +=
3808                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3809
3810                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3811                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3812                         info->fw = adev->gfx.rlc_fw;
3813                         adev->firmware.fw_size +=
3814                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3815                 }
3816
3817                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3818                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3819                 info->fw = adev->gfx.mec_fw;
3820                 header = (const struct common_firmware_header *)info->fw->data;
3821                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3822                 adev->firmware.fw_size +=
3823                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3824                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3825
3826                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3827                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3828                 info->fw = adev->gfx.mec_fw;
3829                 adev->firmware.fw_size +=
3830                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3831
3832                 if (adev->gfx.mec2_fw) {
3833                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3834                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3835                         info->fw = adev->gfx.mec2_fw;
3836                         header = (const struct common_firmware_header *)info->fw->data;
3837                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3838                         adev->firmware.fw_size +=
3839                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3840                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3841                                       PAGE_SIZE);
3842                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3843                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3844                         info->fw = adev->gfx.mec2_fw;
3845                         adev->firmware.fw_size +=
3846                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3847                                       PAGE_SIZE);
3848                 }
3849         }
3850
3851         gfx_v10_0_check_fw_write_wait(adev);
3852 out:
3853         if (err) {
3854                 dev_err(adev->dev,
3855                         "gfx10: Failed to load firmware \"%s\"\n",
3856                         fw_name);
3857                 release_firmware(adev->gfx.pfp_fw);
3858                 adev->gfx.pfp_fw = NULL;
3859                 release_firmware(adev->gfx.me_fw);
3860                 adev->gfx.me_fw = NULL;
3861                 release_firmware(adev->gfx.ce_fw);
3862                 adev->gfx.ce_fw = NULL;
3863                 release_firmware(adev->gfx.rlc_fw);
3864                 adev->gfx.rlc_fw = NULL;
3865                 release_firmware(adev->gfx.mec_fw);
3866                 adev->gfx.mec_fw = NULL;
3867                 release_firmware(adev->gfx.mec2_fw);
3868                 adev->gfx.mec2_fw = NULL;
3869         }
3870
3871         gfx_v10_0_check_gfxoff_flag(adev);
3872
3873         return err;
3874 }
3875
3876 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3877 {
3878         u32 count = 0;
3879         const struct cs_section_def *sect = NULL;
3880         const struct cs_extent_def *ext = NULL;
3881
3882         /* begin clear state */
3883         count += 2;
3884         /* context control state */
3885         count += 3;
3886
3887         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3888                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3889                         if (sect->id == SECT_CONTEXT)
3890                                 count += 2 + ext->reg_count;
3891                         else
3892                                 return 0;
3893                 }
3894         }
3895
3896         /* set PA_SC_TILE_STEERING_OVERRIDE */
3897         count += 3;
3898         /* end clear state */
3899         count += 2;
3900         /* clear state */
3901         count += 2;
3902
3903         return count;
3904 }
3905
3906 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3907                                     volatile u32 *buffer)
3908 {
3909         u32 count = 0, i;
3910         const struct cs_section_def *sect = NULL;
3911         const struct cs_extent_def *ext = NULL;
3912         int ctx_reg_offset;
3913
3914         if (adev->gfx.rlc.cs_data == NULL)
3915                 return;
3916         if (buffer == NULL)
3917                 return;
3918
3919         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3920         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3921
3922         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3923         buffer[count++] = cpu_to_le32(0x80000000);
3924         buffer[count++] = cpu_to_le32(0x80000000);
3925
3926         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3927                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3928                         if (sect->id == SECT_CONTEXT) {
3929                                 buffer[count++] =
3930                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3931                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3932                                                 PACKET3_SET_CONTEXT_REG_START);
3933                                 for (i = 0; i < ext->reg_count; i++)
3934                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3935                         } else {
3936                                 return;
3937                         }
3938                 }
3939         }
3940
3941         ctx_reg_offset =
3942                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3943         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3944         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3945         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3946
3947         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3948         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3949
3950         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3951         buffer[count++] = cpu_to_le32(0);
3952 }
3953
3954 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3955 {
3956         /* clear state block */
3957         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3958                         &adev->gfx.rlc.clear_state_gpu_addr,
3959                         (void **)&adev->gfx.rlc.cs_ptr);
3960
3961         /* jump table block */
3962         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3963                         &adev->gfx.rlc.cp_table_gpu_addr,
3964                         (void **)&adev->gfx.rlc.cp_table_ptr);
3965 }
3966
3967 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3968 {
3969         const struct cs_section_def *cs_data;
3970         int r;
3971
3972         adev->gfx.rlc.cs_data = gfx10_cs_data;
3973
3974         cs_data = adev->gfx.rlc.cs_data;
3975
3976         if (cs_data) {
3977                 /* init clear state block */
3978                 r = amdgpu_gfx_rlc_init_csb(adev);
3979                 if (r)
3980                         return r;
3981         }
3982
3983         /* init spm vmid with 0xf */
3984         if (adev->gfx.rlc.funcs->update_spm_vmid)
3985                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3986
3987         return 0;
3988 }
3989
3990 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
3991 {
3992         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
3993         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
3994 }
3995
3996 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
3997 {
3998         int r;
3999
4000         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4001
4002         amdgpu_gfx_graphics_queue_acquire(adev);
4003
4004         r = gfx_v10_0_init_microcode(adev);
4005         if (r)
4006                 DRM_ERROR("Failed to load gfx firmware!\n");
4007
4008         return r;
4009 }
4010
4011 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4012 {
4013         int r;
4014         u32 *hpd;
4015         const __le32 *fw_data = NULL;
4016         unsigned fw_size;
4017         u32 *fw = NULL;
4018         size_t mec_hpd_size;
4019
4020         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4021
4022         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4023
4024         /* take ownership of the relevant compute queues */
4025         amdgpu_gfx_compute_queue_acquire(adev);
4026         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4027
4028         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4029                                       AMDGPU_GEM_DOMAIN_GTT,
4030                                       &adev->gfx.mec.hpd_eop_obj,
4031                                       &adev->gfx.mec.hpd_eop_gpu_addr,
4032                                       (void **)&hpd);
4033         if (r) {
4034                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4035                 gfx_v10_0_mec_fini(adev);
4036                 return r;
4037         }
4038
4039         memset(hpd, 0, mec_hpd_size);
4040
4041         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4042         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4043
4044         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4045                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4046
4047                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4048                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4049                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4050
4051                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4052                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4053                                               &adev->gfx.mec.mec_fw_obj,
4054                                               &adev->gfx.mec.mec_fw_gpu_addr,
4055                                               (void **)&fw);
4056                 if (r) {
4057                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4058                         gfx_v10_0_mec_fini(adev);
4059                         return r;
4060                 }
4061
4062                 memcpy(fw, fw_data, fw_size);
4063
4064                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4065                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4066         }
4067
4068         return 0;
4069 }
4070
4071 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4072 {
4073         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4074                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4075                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4076         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4077 }
4078
4079 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4080                            uint32_t thread, uint32_t regno,
4081                            uint32_t num, uint32_t *out)
4082 {
4083         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4084                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4085                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4086                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4087                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4088         while (num--)
4089                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4090 }
4091
4092 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4093 {
4094         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4095          * field when performing a select_se_sh so it should be
4096          * zero here */
4097         WARN_ON(simd != 0);
4098
4099         /* type 2 wave data */
4100         dst[(*no_fields)++] = 2;
4101         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4102         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4103         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4104         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4105         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4106         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4107         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4108         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4109         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4110         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4111         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4112         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4113         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4114         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4115         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4116 }
4117
4118 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4119                                      uint32_t wave, uint32_t start,
4120                                      uint32_t size, uint32_t *dst)
4121 {
4122         WARN_ON(simd != 0);
4123
4124         wave_read_regs(
4125                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4126                 dst);
4127 }
4128
4129 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4130                                       uint32_t wave, uint32_t thread,
4131                                       uint32_t start, uint32_t size,
4132                                       uint32_t *dst)
4133 {
4134         wave_read_regs(
4135                 adev, wave, thread,
4136                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4137 }
4138
4139 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4140                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4141  {
4142        nv_grbm_select(adev, me, pipe, q, vm);
4143  }
4144
4145
4146 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4147         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4148         .select_se_sh = &gfx_v10_0_select_se_sh,
4149         .read_wave_data = &gfx_v10_0_read_wave_data,
4150         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4151         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4152         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4153 };
4154
4155 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4156 {
4157         u32 gb_addr_config;
4158
4159         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4160
4161         switch (adev->asic_type) {
4162         case CHIP_NAVI10:
4163         case CHIP_NAVI14:
4164         case CHIP_NAVI12:
4165                 adev->gfx.config.max_hw_contexts = 8;
4166                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4167                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4168                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4169                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4170                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4171                 break;
4172         case CHIP_SIENNA_CICHLID:
4173         case CHIP_NAVY_FLOUNDER:
4174                 adev->gfx.config.max_hw_contexts = 8;
4175                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4176                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4177                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4178                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4179                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4180                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4181                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4182                 break;
4183         default:
4184                 BUG();
4185                 break;
4186         }
4187
4188         adev->gfx.config.gb_addr_config = gb_addr_config;
4189
4190         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4191                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4192                                       GB_ADDR_CONFIG, NUM_PIPES);
4193
4194         adev->gfx.config.max_tile_pipes =
4195                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4196
4197         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4198                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4199                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4200         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4201                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4202                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4203         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4204                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4205                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4206         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4207                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4208                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4209 }
4210
4211 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4212                                    int me, int pipe, int queue)
4213 {
4214         int r;
4215         struct amdgpu_ring *ring;
4216         unsigned int irq_type;
4217
4218         ring = &adev->gfx.gfx_ring[ring_id];
4219
4220         ring->me = me;
4221         ring->pipe = pipe;
4222         ring->queue = queue;
4223
4224         ring->ring_obj = NULL;
4225         ring->use_doorbell = true;
4226
4227         if (!ring_id)
4228                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4229         else
4230                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4231         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4232
4233         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4234         r = amdgpu_ring_init(adev, ring, 1024,
4235                              &adev->gfx.eop_irq, irq_type,
4236                              AMDGPU_RING_PRIO_DEFAULT);
4237         if (r)
4238                 return r;
4239         return 0;
4240 }
4241
4242 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4243                                        int mec, int pipe, int queue)
4244 {
4245         int r;
4246         unsigned irq_type;
4247         struct amdgpu_ring *ring;
4248         unsigned int hw_prio;
4249
4250         ring = &adev->gfx.compute_ring[ring_id];
4251
4252         /* mec0 is me1 */
4253         ring->me = mec + 1;
4254         ring->pipe = pipe;
4255         ring->queue = queue;
4256
4257         ring->ring_obj = NULL;
4258         ring->use_doorbell = true;
4259         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4260         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4261                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4262         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4263
4264         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4265                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4266                 + ring->pipe;
4267         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4268                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4269         /* type-2 packets are deprecated on MEC, use type-3 instead */
4270         r = amdgpu_ring_init(adev, ring, 1024,
4271                              &adev->gfx.eop_irq, irq_type, hw_prio);
4272         if (r)
4273                 return r;
4274
4275         return 0;
4276 }
4277
4278 static int gfx_v10_0_sw_init(void *handle)
4279 {
4280         int i, j, k, r, ring_id = 0;
4281         struct amdgpu_kiq *kiq;
4282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4283
4284         switch (adev->asic_type) {
4285         case CHIP_NAVI10:
4286         case CHIP_NAVI14:
4287         case CHIP_NAVI12:
4288                 adev->gfx.me.num_me = 1;
4289                 adev->gfx.me.num_pipe_per_me = 1;
4290                 adev->gfx.me.num_queue_per_pipe = 1;
4291                 adev->gfx.mec.num_mec = 2;
4292                 adev->gfx.mec.num_pipe_per_mec = 4;
4293                 adev->gfx.mec.num_queue_per_pipe = 8;
4294                 break;
4295         case CHIP_SIENNA_CICHLID:
4296         case CHIP_NAVY_FLOUNDER:
4297                 adev->gfx.me.num_me = 1;
4298                 adev->gfx.me.num_pipe_per_me = 1;
4299                 adev->gfx.me.num_queue_per_pipe = 1;
4300                 adev->gfx.mec.num_mec = 2;
4301                 adev->gfx.mec.num_pipe_per_mec = 4;
4302                 adev->gfx.mec.num_queue_per_pipe = 4;
4303                 break;
4304         default:
4305                 adev->gfx.me.num_me = 1;
4306                 adev->gfx.me.num_pipe_per_me = 1;
4307                 adev->gfx.me.num_queue_per_pipe = 1;
4308                 adev->gfx.mec.num_mec = 1;
4309                 adev->gfx.mec.num_pipe_per_mec = 4;
4310                 adev->gfx.mec.num_queue_per_pipe = 8;
4311                 break;
4312         }
4313
4314         /* KIQ event */
4315         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4316                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4317                               &adev->gfx.kiq.irq);
4318         if (r)
4319                 return r;
4320
4321         /* EOP Event */
4322         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4323                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4324                               &adev->gfx.eop_irq);
4325         if (r)
4326                 return r;
4327
4328         /* Privileged reg */
4329         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4330                               &adev->gfx.priv_reg_irq);
4331         if (r)
4332                 return r;
4333
4334         /* Privileged inst */
4335         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4336                               &adev->gfx.priv_inst_irq);
4337         if (r)
4338                 return r;
4339
4340         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4341
4342         gfx_v10_0_scratch_init(adev);
4343
4344         r = gfx_v10_0_me_init(adev);
4345         if (r)
4346                 return r;
4347
4348         r = gfx_v10_0_rlc_init(adev);
4349         if (r) {
4350                 DRM_ERROR("Failed to init rlc BOs!\n");
4351                 return r;
4352         }
4353
4354         r = gfx_v10_0_mec_init(adev);
4355         if (r) {
4356                 DRM_ERROR("Failed to init MEC BOs!\n");
4357                 return r;
4358         }
4359
4360         /* set up the gfx ring */
4361         for (i = 0; i < adev->gfx.me.num_me; i++) {
4362                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4363                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4364                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4365                                         continue;
4366
4367                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4368                                                             i, k, j);
4369                                 if (r)
4370                                         return r;
4371                                 ring_id++;
4372                         }
4373                 }
4374         }
4375
4376         ring_id = 0;
4377         /* set up the compute queues - allocate horizontally across pipes */
4378         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4379                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4380                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4381                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4382                                                                      j))
4383                                         continue;
4384
4385                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4386                                                                 i, k, j);
4387                                 if (r)
4388                                         return r;
4389
4390                                 ring_id++;
4391                         }
4392                 }
4393         }
4394
4395         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4396         if (r) {
4397                 DRM_ERROR("Failed to init KIQ BOs!\n");
4398                 return r;
4399         }
4400
4401         kiq = &adev->gfx.kiq;
4402         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4403         if (r)
4404                 return r;
4405
4406         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4407         if (r)
4408                 return r;
4409
4410         /* allocate visible FB for rlc auto-loading fw */
4411         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4412                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4413                 if (r)
4414                         return r;
4415         }
4416
4417         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4418
4419         gfx_v10_0_gpu_early_init(adev);
4420
4421         return 0;
4422 }
4423
4424 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4425 {
4426         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4427                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4428                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4429 }
4430
4431 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4432 {
4433         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4434                               &adev->gfx.ce.ce_fw_gpu_addr,
4435                               (void **)&adev->gfx.ce.ce_fw_ptr);
4436 }
4437
4438 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4439 {
4440         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4441                               &adev->gfx.me.me_fw_gpu_addr,
4442                               (void **)&adev->gfx.me.me_fw_ptr);
4443 }
4444
4445 static int gfx_v10_0_sw_fini(void *handle)
4446 {
4447         int i;
4448         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4449
4450         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4451                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4452         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4453                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4454
4455         amdgpu_gfx_mqd_sw_fini(adev);
4456         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4457         amdgpu_gfx_kiq_fini(adev);
4458
4459         gfx_v10_0_pfp_fini(adev);
4460         gfx_v10_0_ce_fini(adev);
4461         gfx_v10_0_me_fini(adev);
4462         gfx_v10_0_rlc_fini(adev);
4463         gfx_v10_0_mec_fini(adev);
4464
4465         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4466                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4467
4468         gfx_v10_0_free_microcode(adev);
4469
4470         return 0;
4471 }
4472
4473 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4474                                    u32 sh_num, u32 instance)
4475 {
4476         u32 data;
4477
4478         if (instance == 0xffffffff)
4479                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4480                                      INSTANCE_BROADCAST_WRITES, 1);
4481         else
4482                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4483                                      instance);
4484
4485         if (se_num == 0xffffffff)
4486                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4487                                      1);
4488         else
4489                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4490
4491         if (sh_num == 0xffffffff)
4492                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4493                                      1);
4494         else
4495                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4496
4497         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4498 }
4499
4500 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4501 {
4502         u32 data, mask;
4503
4504         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4505         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4506
4507         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4508         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4509
4510         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4511                                          adev->gfx.config.max_sh_per_se);
4512
4513         return (~data) & mask;
4514 }
4515
4516 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4517 {
4518         int i, j;
4519         u32 data;
4520         u32 active_rbs = 0;
4521         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4522                                         adev->gfx.config.max_sh_per_se;
4523
4524         mutex_lock(&adev->grbm_idx_mutex);
4525         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4526                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4527                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4528                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4529                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4530                                                rb_bitmap_width_per_sh);
4531                 }
4532         }
4533         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4534         mutex_unlock(&adev->grbm_idx_mutex);
4535
4536         adev->gfx.config.backend_enable_mask = active_rbs;
4537         adev->gfx.config.num_rbs = hweight32(active_rbs);
4538 }
4539
4540 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4541 {
4542         uint32_t num_sc;
4543         uint32_t enabled_rb_per_sh;
4544         uint32_t active_rb_bitmap;
4545         uint32_t num_rb_per_sc;
4546         uint32_t num_packer_per_sc;
4547         uint32_t pa_sc_tile_steering_override;
4548
4549         /* for ASICs that integrates GFX v10.3
4550          * pa_sc_tile_steering_override should be set to 0 */
4551         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4552             adev->asic_type == CHIP_NAVY_FLOUNDER)
4553                 return 0;
4554
4555         /* init num_sc */
4556         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4557                         adev->gfx.config.num_sc_per_sh;
4558         /* init num_rb_per_sc */
4559         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4560         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4561         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4562         /* init num_packer_per_sc */
4563         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4564
4565         pa_sc_tile_steering_override = 0;
4566         pa_sc_tile_steering_override |=
4567                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4568                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4569         pa_sc_tile_steering_override |=
4570                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4571                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4572         pa_sc_tile_steering_override |=
4573                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4574                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4575
4576         return pa_sc_tile_steering_override;
4577 }
4578
4579 #define DEFAULT_SH_MEM_BASES    (0x6000)
4580
4581 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4582 {
4583         int i;
4584         uint32_t sh_mem_bases;
4585
4586         /*
4587          * Configure apertures:
4588          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4589          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4590          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4591          */
4592         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4593
4594         mutex_lock(&adev->srbm_mutex);
4595         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4596                 nv_grbm_select(adev, 0, 0, 0, i);
4597                 /* CP and shaders */
4598                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4599                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4600         }
4601         nv_grbm_select(adev, 0, 0, 0, 0);
4602         mutex_unlock(&adev->srbm_mutex);
4603
4604         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4605            acccess. These should be enabled by FW for target VMIDs. */
4606         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4607                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4608                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4609                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4610                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4611         }
4612 }
4613
4614 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4615 {
4616         int vmid;
4617
4618         /*
4619          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4620          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4621          * the driver can enable them for graphics. VMID0 should maintain
4622          * access so that HWS firmware can save/restore entries.
4623          */
4624         for (vmid = 1; vmid < 16; vmid++) {
4625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4626                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4627                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4628                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4629         }
4630 }
4631
4632
4633 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4634 {
4635         int i, j, k;
4636         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4637         u32 tmp, wgp_active_bitmap = 0;
4638         u32 gcrd_targets_disable_tcp = 0;
4639         u32 utcl_invreq_disable = 0;
4640         /*
4641          * GCRD_TARGETS_DISABLE field contains
4642          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4643          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4644          */
4645         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4646                 2 * max_wgp_per_sh + /* TCP */
4647                 max_wgp_per_sh + /* SQC */
4648                 4); /* GL1C */
4649         /*
4650          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4651          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4652          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4653          */
4654         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4655                 2 * max_wgp_per_sh + /* TCP */
4656                 2 * max_wgp_per_sh + /* SQC */
4657                 4 + /* RMI */
4658                 1); /* SQG */
4659
4660         if (adev->asic_type == CHIP_NAVI10 ||
4661             adev->asic_type == CHIP_NAVI14 ||
4662             adev->asic_type == CHIP_NAVI12) {
4663                 mutex_lock(&adev->grbm_idx_mutex);
4664                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4665                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4666                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4667                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4668                                 /*
4669                                  * Set corresponding TCP bits for the inactive WGPs in
4670                                  * GCRD_SA_TARGETS_DISABLE
4671                                  */
4672                                 gcrd_targets_disable_tcp = 0;
4673                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4674                                 utcl_invreq_disable = 0;
4675
4676                                 for (k = 0; k < max_wgp_per_sh; k++) {
4677                                         if (!(wgp_active_bitmap & (1 << k))) {
4678                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4679                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4680                                                         (3 << (2 * (max_wgp_per_sh + k)));
4681                                         }
4682                                 }
4683
4684                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4685                                 /* only override TCP & SQC bits */
4686                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4687                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4688                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4689
4690                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4691                                 /* only override TCP bits */
4692                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4693                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4694                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4695                         }
4696                 }
4697
4698                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4699                 mutex_unlock(&adev->grbm_idx_mutex);
4700         }
4701 }
4702
4703 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4704 {
4705         /* TCCs are global (not instanced). */
4706         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4707                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4708
4709         adev->gfx.config.tcc_disabled_mask =
4710                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4711                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4712 }
4713
4714 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4715 {
4716         u32 tmp;
4717         int i;
4718
4719         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4720
4721         gfx_v10_0_setup_rb(adev);
4722         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4723         gfx_v10_0_get_tcc_info(adev);
4724         adev->gfx.config.pa_sc_tile_steering_override =
4725                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4726
4727         /* XXX SH_MEM regs */
4728         /* where to put LDS, scratch, GPUVM in FSA64 space */
4729         mutex_lock(&adev->srbm_mutex);
4730         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4731                 nv_grbm_select(adev, 0, 0, 0, i);
4732                 /* CP and shaders */
4733                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4734                 if (i != 0) {
4735                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4736                                 (adev->gmc.private_aperture_start >> 48));
4737                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4738                                 (adev->gmc.shared_aperture_start >> 48));
4739                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4740                 }
4741         }
4742         nv_grbm_select(adev, 0, 0, 0, 0);
4743
4744         mutex_unlock(&adev->srbm_mutex);
4745
4746         gfx_v10_0_init_compute_vmid(adev);
4747         gfx_v10_0_init_gds_vmid(adev);
4748
4749 }
4750
4751 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4752                                                bool enable)
4753 {
4754         u32 tmp;
4755
4756         if (amdgpu_sriov_vf(adev))
4757                 return;
4758
4759         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4760
4761         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4762                             enable ? 1 : 0);
4763         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4764                             enable ? 1 : 0);
4765         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4766                             enable ? 1 : 0);
4767         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4768                             enable ? 1 : 0);
4769
4770         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4771 }
4772
4773 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4774 {
4775         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4776
4777         /* csib */
4778         if (adev->asic_type == CHIP_NAVI12) {
4779                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4780                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4781                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4782                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4783                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4784         } else {
4785                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4786                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4787                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4788                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4789                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4790         }
4791         return 0;
4792 }
4793
4794 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4795 {
4796         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4797
4798         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4799         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4800 }
4801
4802 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4803 {
4804         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4805         udelay(50);
4806         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4807         udelay(50);
4808 }
4809
4810 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4811                                              bool enable)
4812 {
4813         uint32_t rlc_pg_cntl;
4814
4815         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4816
4817         if (!enable) {
4818                 /* RLC_PG_CNTL[23] = 0 (default)
4819                  * RLC will wait for handshake acks with SMU
4820                  * GFXOFF will be enabled
4821                  * RLC_PG_CNTL[23] = 1
4822                  * RLC will not issue any message to SMU
4823                  * hence no handshake between SMU & RLC
4824                  * GFXOFF will be disabled
4825                  */
4826                 rlc_pg_cntl |= 0x800000;
4827         } else
4828                 rlc_pg_cntl &= ~0x800000;
4829         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4830 }
4831
4832 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4833 {
4834         /* TODO: enable rlc & smu handshake until smu
4835          * and gfxoff feature works as expected */
4836         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4837                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4838
4839         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4840         udelay(50);
4841 }
4842
4843 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4844 {
4845         uint32_t tmp;
4846
4847         /* enable Save Restore Machine */
4848         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4849         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4850         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4851         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4852 }
4853
4854 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4855 {
4856         const struct rlc_firmware_header_v2_0 *hdr;
4857         const __le32 *fw_data;
4858         unsigned i, fw_size;
4859
4860         if (!adev->gfx.rlc_fw)
4861                 return -EINVAL;
4862
4863         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4864         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4865
4866         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4867                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4868         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4869
4870         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4871                      RLCG_UCODE_LOADING_START_ADDRESS);
4872
4873         for (i = 0; i < fw_size; i++)
4874                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4875                              le32_to_cpup(fw_data++));
4876
4877         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4878
4879         return 0;
4880 }
4881
4882 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4883 {
4884         int r;
4885
4886         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4887
4888                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4889                 if (r)
4890                         return r;
4891
4892                 gfx_v10_0_init_csb(adev);
4893
4894                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4895                         gfx_v10_0_rlc_enable_srm(adev);
4896         } else {
4897                 if (amdgpu_sriov_vf(adev)) {
4898                         gfx_v10_0_init_csb(adev);
4899                         return 0;
4900                 }
4901
4902                 adev->gfx.rlc.funcs->stop(adev);
4903
4904                 /* disable CG */
4905                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4906
4907                 /* disable PG */
4908                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4909
4910                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4911                         /* legacy rlc firmware loading */
4912                         r = gfx_v10_0_rlc_load_microcode(adev);
4913                         if (r)
4914                                 return r;
4915                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4916                         /* rlc backdoor autoload firmware */
4917                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4918                         if (r)
4919                                 return r;
4920                 }
4921
4922                 gfx_v10_0_init_csb(adev);
4923
4924                 adev->gfx.rlc.funcs->start(adev);
4925
4926                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4927                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4928                         if (r)
4929                                 return r;
4930                 }
4931         }
4932         return 0;
4933 }
4934
4935 static struct {
4936         FIRMWARE_ID     id;
4937         unsigned int    offset;
4938         unsigned int    size;
4939 } rlc_autoload_info[FIRMWARE_ID_MAX];
4940
4941 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4942 {
4943         int ret;
4944         RLC_TABLE_OF_CONTENT *rlc_toc;
4945
4946         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4947                                         AMDGPU_GEM_DOMAIN_GTT,
4948                                         &adev->gfx.rlc.rlc_toc_bo,
4949                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4950                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4951         if (ret) {
4952                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4953                 return ret;
4954         }
4955
4956         /* Copy toc from psp sos fw to rlc toc buffer */
4957         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4958
4959         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4960         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4961                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4962                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4963                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4964                         /* Offset needs 4KB alignment */
4965                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4966                 }
4967
4968                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4969                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4970                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4971
4972                 rlc_toc++;
4973         }
4974
4975         return 0;
4976 }
4977
4978 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4979 {
4980         uint32_t total_size = 0;
4981         FIRMWARE_ID id;
4982         int ret;
4983
4984         ret = gfx_v10_0_parse_rlc_toc(adev);
4985         if (ret) {
4986                 dev_err(adev->dev, "failed to parse rlc toc\n");
4987                 return 0;
4988         }
4989
4990         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
4991                 total_size += rlc_autoload_info[id].size;
4992
4993         /* In case the offset in rlc toc ucode is aligned */
4994         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
4995                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
4996                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
4997
4998         return total_size;
4999 }
5000
5001 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5002 {
5003         int r;
5004         uint32_t total_size;
5005
5006         total_size = gfx_v10_0_calc_toc_total_size(adev);
5007
5008         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5009                                       AMDGPU_GEM_DOMAIN_GTT,
5010                                       &adev->gfx.rlc.rlc_autoload_bo,
5011                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5012                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5013         if (r) {
5014                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5015                 return r;
5016         }
5017
5018         return 0;
5019 }
5020
5021 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5022 {
5023         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5024                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5025                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5026         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5027                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5028                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5029 }
5030
5031 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5032                                                        FIRMWARE_ID id,
5033                                                        const void *fw_data,
5034                                                        uint32_t fw_size)
5035 {
5036         uint32_t toc_offset;
5037         uint32_t toc_fw_size;
5038         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5039
5040         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5041                 return;
5042
5043         toc_offset = rlc_autoload_info[id].offset;
5044         toc_fw_size = rlc_autoload_info[id].size;
5045
5046         if (fw_size == 0)
5047                 fw_size = toc_fw_size;
5048
5049         if (fw_size > toc_fw_size)
5050                 fw_size = toc_fw_size;
5051
5052         memcpy(ptr + toc_offset, fw_data, fw_size);
5053
5054         if (fw_size < toc_fw_size)
5055                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5056 }
5057
5058 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5059 {
5060         void *data;
5061         uint32_t size;
5062
5063         data = adev->gfx.rlc.rlc_toc_buf;
5064         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5065
5066         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5067                                                    FIRMWARE_ID_RLC_TOC,
5068                                                    data, size);
5069 }
5070
5071 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5072 {
5073         const __le32 *fw_data;
5074         uint32_t fw_size;
5075         const struct gfx_firmware_header_v1_0 *cp_hdr;
5076         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5077
5078         /* pfp ucode */
5079         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5080                 adev->gfx.pfp_fw->data;
5081         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5082                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5083         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5084         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5085                                                    FIRMWARE_ID_CP_PFP,
5086                                                    fw_data, fw_size);
5087
5088         /* ce ucode */
5089         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5090                 adev->gfx.ce_fw->data;
5091         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5092                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5093         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5094         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5095                                                    FIRMWARE_ID_CP_CE,
5096                                                    fw_data, fw_size);
5097
5098         /* me ucode */
5099         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5100                 adev->gfx.me_fw->data;
5101         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5102                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5103         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5104         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5105                                                    FIRMWARE_ID_CP_ME,
5106                                                    fw_data, fw_size);
5107
5108         /* rlc ucode */
5109         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5110                 adev->gfx.rlc_fw->data;
5111         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5112                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5113         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5114         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5115                                                    FIRMWARE_ID_RLC_G_UCODE,
5116                                                    fw_data, fw_size);
5117
5118         /* mec1 ucode */
5119         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5120                 adev->gfx.mec_fw->data;
5121         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5122                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5123         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5124                 cp_hdr->jt_size * 4;
5125         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5126                                                    FIRMWARE_ID_CP_MEC,
5127                                                    fw_data, fw_size);
5128         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5129 }
5130
5131 /* Temporarily put sdma part here */
5132 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5133 {
5134         const __le32 *fw_data;
5135         uint32_t fw_size;
5136         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5137         int i;
5138
5139         for (i = 0; i < adev->sdma.num_instances; i++) {
5140                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5141                         adev->sdma.instance[i].fw->data;
5142                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5143                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5144                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5145
5146                 if (i == 0) {
5147                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5148                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5149                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5150                                 FIRMWARE_ID_SDMA0_JT,
5151                                 (uint32_t *)fw_data +
5152                                 sdma_hdr->jt_offset,
5153                                 sdma_hdr->jt_size * 4);
5154                 } else if (i == 1) {
5155                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5156                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5157                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5158                                 FIRMWARE_ID_SDMA1_JT,
5159                                 (uint32_t *)fw_data +
5160                                 sdma_hdr->jt_offset,
5161                                 sdma_hdr->jt_size * 4);
5162                 }
5163         }
5164 }
5165
5166 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5167 {
5168         uint32_t rlc_g_offset, rlc_g_size, tmp;
5169         uint64_t gpu_addr;
5170
5171         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5172         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5173         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5174
5175         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5176         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5177         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5178
5179         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5180         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5181         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5182
5183         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5184         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5185                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5186                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5187                 return -EINVAL;
5188         }
5189
5190         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5191         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5192                 DRM_ERROR("RLC ROM should halt itself\n");
5193                 return -EINVAL;
5194         }
5195
5196         return 0;
5197 }
5198
5199 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5200 {
5201         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5202         uint32_t tmp;
5203         int i;
5204         uint64_t addr;
5205
5206         /* Trigger an invalidation of the L1 instruction caches */
5207         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5208         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5209         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5210
5211         /* Wait for invalidation complete */
5212         for (i = 0; i < usec_timeout; i++) {
5213                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5214                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5215                         INVALIDATE_CACHE_COMPLETE))
5216                         break;
5217                 udelay(1);
5218         }
5219
5220         if (i >= usec_timeout) {
5221                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5222                 return -EINVAL;
5223         }
5224
5225         /* Program me ucode address into intruction cache address register */
5226         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5227                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5228         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5229                         lower_32_bits(addr) & 0xFFFFF000);
5230         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5231                         upper_32_bits(addr));
5232
5233         return 0;
5234 }
5235
5236 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5237 {
5238         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5239         uint32_t tmp;
5240         int i;
5241         uint64_t addr;
5242
5243         /* Trigger an invalidation of the L1 instruction caches */
5244         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5245         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5246         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5247
5248         /* Wait for invalidation complete */
5249         for (i = 0; i < usec_timeout; i++) {
5250                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5251                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5252                         INVALIDATE_CACHE_COMPLETE))
5253                         break;
5254                 udelay(1);
5255         }
5256
5257         if (i >= usec_timeout) {
5258                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5259                 return -EINVAL;
5260         }
5261
5262         /* Program ce ucode address into intruction cache address register */
5263         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5264                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5265         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5266                         lower_32_bits(addr) & 0xFFFFF000);
5267         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5268                         upper_32_bits(addr));
5269
5270         return 0;
5271 }
5272
5273 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5274 {
5275         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5276         uint32_t tmp;
5277         int i;
5278         uint64_t addr;
5279
5280         /* Trigger an invalidation of the L1 instruction caches */
5281         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5282         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5283         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5284
5285         /* Wait for invalidation complete */
5286         for (i = 0; i < usec_timeout; i++) {
5287                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5288                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5289                         INVALIDATE_CACHE_COMPLETE))
5290                         break;
5291                 udelay(1);
5292         }
5293
5294         if (i >= usec_timeout) {
5295                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5296                 return -EINVAL;
5297         }
5298
5299         /* Program pfp ucode address into intruction cache address register */
5300         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5301                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5302         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5303                         lower_32_bits(addr) & 0xFFFFF000);
5304         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5305                         upper_32_bits(addr));
5306
5307         return 0;
5308 }
5309
5310 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5311 {
5312         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5313         uint32_t tmp;
5314         int i;
5315         uint64_t addr;
5316
5317         /* Trigger an invalidation of the L1 instruction caches */
5318         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5319         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5320         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5321
5322         /* Wait for invalidation complete */
5323         for (i = 0; i < usec_timeout; i++) {
5324                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5325                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5326                         INVALIDATE_CACHE_COMPLETE))
5327                         break;
5328                 udelay(1);
5329         }
5330
5331         if (i >= usec_timeout) {
5332                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5333                 return -EINVAL;
5334         }
5335
5336         /* Program mec1 ucode address into intruction cache address register */
5337         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5338                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5339         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5340                         lower_32_bits(addr) & 0xFFFFF000);
5341         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5342                         upper_32_bits(addr));
5343
5344         return 0;
5345 }
5346
5347 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5348 {
5349         uint32_t cp_status;
5350         uint32_t bootload_status;
5351         int i, r;
5352
5353         for (i = 0; i < adev->usec_timeout; i++) {
5354                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5355                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5356                 if ((cp_status == 0) &&
5357                     (REG_GET_FIELD(bootload_status,
5358                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5359                         break;
5360                 }
5361                 udelay(1);
5362         }
5363
5364         if (i >= adev->usec_timeout) {
5365                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5366                 return -ETIMEDOUT;
5367         }
5368
5369         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5370                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5371                 if (r)
5372                         return r;
5373
5374                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5375                 if (r)
5376                         return r;
5377
5378                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5379                 if (r)
5380                         return r;
5381
5382                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5383                 if (r)
5384                         return r;
5385         }
5386
5387         return 0;
5388 }
5389
5390 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5391 {
5392         int i;
5393         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5394
5395         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5396         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5397         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5398
5399         if (adev->asic_type == CHIP_NAVI12) {
5400                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5401         } else {
5402                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5403         }
5404
5405         for (i = 0; i < adev->usec_timeout; i++) {
5406                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5407                         break;
5408                 udelay(1);
5409         }
5410
5411         if (i >= adev->usec_timeout)
5412                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5413
5414         return 0;
5415 }
5416
5417 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5418 {
5419         int r;
5420         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5421         const __le32 *fw_data;
5422         unsigned i, fw_size;
5423         uint32_t tmp;
5424         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5425
5426         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5427                 adev->gfx.pfp_fw->data;
5428
5429         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5430
5431         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5432                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5433         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5434
5435         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5436                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5437                                       &adev->gfx.pfp.pfp_fw_obj,
5438                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5439                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5440         if (r) {
5441                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5442                 gfx_v10_0_pfp_fini(adev);
5443                 return r;
5444         }
5445
5446         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5447
5448         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5449         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5450
5451         /* Trigger an invalidation of the L1 instruction caches */
5452         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5453         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5454         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5455
5456         /* Wait for invalidation complete */
5457         for (i = 0; i < usec_timeout; i++) {
5458                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5459                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5460                         INVALIDATE_CACHE_COMPLETE))
5461                         break;
5462                 udelay(1);
5463         }
5464
5465         if (i >= usec_timeout) {
5466                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5467                 return -EINVAL;
5468         }
5469
5470         if (amdgpu_emu_mode == 1)
5471                 adev->nbio.funcs->hdp_flush(adev, NULL);
5472
5473         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5474         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5475         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5476         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5477         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5478         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5479         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5480                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5481         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5482                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5483
5484         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5485
5486         for (i = 0; i < pfp_hdr->jt_size; i++)
5487                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5488                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5489
5490         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5491
5492         return 0;
5493 }
5494
5495 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5496 {
5497         int r;
5498         const struct gfx_firmware_header_v1_0 *ce_hdr;
5499         const __le32 *fw_data;
5500         unsigned i, fw_size;
5501         uint32_t tmp;
5502         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5503
5504         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5505                 adev->gfx.ce_fw->data;
5506
5507         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5508
5509         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5510                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5511         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5512
5513         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5514                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5515                                       &adev->gfx.ce.ce_fw_obj,
5516                                       &adev->gfx.ce.ce_fw_gpu_addr,
5517                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5518         if (r) {
5519                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5520                 gfx_v10_0_ce_fini(adev);
5521                 return r;
5522         }
5523
5524         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5525
5526         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5527         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5528
5529         /* Trigger an invalidation of the L1 instruction caches */
5530         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5531         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5532         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5533
5534         /* Wait for invalidation complete */
5535         for (i = 0; i < usec_timeout; i++) {
5536                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5537                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5538                         INVALIDATE_CACHE_COMPLETE))
5539                         break;
5540                 udelay(1);
5541         }
5542
5543         if (i >= usec_timeout) {
5544                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5545                 return -EINVAL;
5546         }
5547
5548         if (amdgpu_emu_mode == 1)
5549                 adev->nbio.funcs->hdp_flush(adev, NULL);
5550
5551         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5552         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5553         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5554         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5555         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5556         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5557                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5558         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5559                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5560
5561         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5562
5563         for (i = 0; i < ce_hdr->jt_size; i++)
5564                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5565                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5566
5567         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5568
5569         return 0;
5570 }
5571
5572 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5573 {
5574         int r;
5575         const struct gfx_firmware_header_v1_0 *me_hdr;
5576         const __le32 *fw_data;
5577         unsigned i, fw_size;
5578         uint32_t tmp;
5579         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5580
5581         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5582                 adev->gfx.me_fw->data;
5583
5584         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5585
5586         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5587                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5588         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5589
5590         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5591                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5592                                       &adev->gfx.me.me_fw_obj,
5593                                       &adev->gfx.me.me_fw_gpu_addr,
5594                                       (void **)&adev->gfx.me.me_fw_ptr);
5595         if (r) {
5596                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5597                 gfx_v10_0_me_fini(adev);
5598                 return r;
5599         }
5600
5601         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5602
5603         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5604         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5605
5606         /* Trigger an invalidation of the L1 instruction caches */
5607         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5608         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5609         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5610
5611         /* Wait for invalidation complete */
5612         for (i = 0; i < usec_timeout; i++) {
5613                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5614                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5615                         INVALIDATE_CACHE_COMPLETE))
5616                         break;
5617                 udelay(1);
5618         }
5619
5620         if (i >= usec_timeout) {
5621                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5622                 return -EINVAL;
5623         }
5624
5625         if (amdgpu_emu_mode == 1)
5626                 adev->nbio.funcs->hdp_flush(adev, NULL);
5627
5628         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5629         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5630         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5631         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5632         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5633         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5634                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5635         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5636                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5637
5638         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5639
5640         for (i = 0; i < me_hdr->jt_size; i++)
5641                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5642                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5643
5644         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5645
5646         return 0;
5647 }
5648
5649 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5650 {
5651         int r;
5652
5653         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5654                 return -EINVAL;
5655
5656         gfx_v10_0_cp_gfx_enable(adev, false);
5657
5658         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5659         if (r) {
5660                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5661                 return r;
5662         }
5663
5664         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5665         if (r) {
5666                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5667                 return r;
5668         }
5669
5670         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5671         if (r) {
5672                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5673                 return r;
5674         }
5675
5676         return 0;
5677 }
5678
5679 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5680 {
5681         struct amdgpu_ring *ring;
5682         const struct cs_section_def *sect = NULL;
5683         const struct cs_extent_def *ext = NULL;
5684         int r, i;
5685         int ctx_reg_offset;
5686
5687         /* init the CP */
5688         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5689                      adev->gfx.config.max_hw_contexts - 1);
5690         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5691
5692         gfx_v10_0_cp_gfx_enable(adev, true);
5693
5694         ring = &adev->gfx.gfx_ring[0];
5695         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5696         if (r) {
5697                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5698                 return r;
5699         }
5700
5701         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5702         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5703
5704         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5705         amdgpu_ring_write(ring, 0x80000000);
5706         amdgpu_ring_write(ring, 0x80000000);
5707
5708         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5709                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5710                         if (sect->id == SECT_CONTEXT) {
5711                                 amdgpu_ring_write(ring,
5712                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5713                                                           ext->reg_count));
5714                                 amdgpu_ring_write(ring, ext->reg_index -
5715                                                   PACKET3_SET_CONTEXT_REG_START);
5716                                 for (i = 0; i < ext->reg_count; i++)
5717                                         amdgpu_ring_write(ring, ext->extent[i]);
5718                         }
5719                 }
5720         }
5721
5722         ctx_reg_offset =
5723                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5724         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5725         amdgpu_ring_write(ring, ctx_reg_offset);
5726         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5727
5728         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5729         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5730
5731         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5732         amdgpu_ring_write(ring, 0);
5733
5734         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5735         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5736         amdgpu_ring_write(ring, 0x8000);
5737         amdgpu_ring_write(ring, 0x8000);
5738
5739         amdgpu_ring_commit(ring);
5740
5741         /* submit cs packet to copy state 0 to next available state */
5742         if (adev->gfx.num_gfx_rings > 1) {
5743                 /* maximum supported gfx ring is 2 */
5744                 ring = &adev->gfx.gfx_ring[1];
5745                 r = amdgpu_ring_alloc(ring, 2);
5746                 if (r) {
5747                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5748                         return r;
5749                 }
5750
5751                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5752                 amdgpu_ring_write(ring, 0);
5753
5754                 amdgpu_ring_commit(ring);
5755         }
5756         return 0;
5757 }
5758
5759 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5760                                          CP_PIPE_ID pipe)
5761 {
5762         u32 tmp;
5763
5764         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5765         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5766
5767         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5768 }
5769
5770 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5771                                           struct amdgpu_ring *ring)
5772 {
5773         u32 tmp;
5774
5775         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5776         if (ring->use_doorbell) {
5777                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5778                                     DOORBELL_OFFSET, ring->doorbell_index);
5779                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5780                                     DOORBELL_EN, 1);
5781         } else {
5782                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5783                                     DOORBELL_EN, 0);
5784         }
5785         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5786         switch (adev->asic_type) {
5787         case CHIP_SIENNA_CICHLID:
5788         case CHIP_NAVY_FLOUNDER:
5789                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5790                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5791                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5792
5793                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5794                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5795                 break;
5796         default:
5797                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5798                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5799                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5800
5801                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5802                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5803                 break;
5804         }
5805 }
5806
5807 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5808 {
5809         struct amdgpu_ring *ring;
5810         u32 tmp;
5811         u32 rb_bufsz;
5812         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5813         u32 i;
5814
5815         /* Set the write pointer delay */
5816         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5817
5818         /* set the RB to use vmid 0 */
5819         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5820
5821         /* Init gfx ring 0 for pipe 0 */
5822         mutex_lock(&adev->srbm_mutex);
5823         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5824
5825         /* Set ring buffer size */
5826         ring = &adev->gfx.gfx_ring[0];
5827         rb_bufsz = order_base_2(ring->ring_size / 8);
5828         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5829         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5830 #ifdef __BIG_ENDIAN
5831         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5832 #endif
5833         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5834
5835         /* Initialize the ring buffer's write pointers */
5836         ring->wptr = 0;
5837         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5838         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5839
5840         /* set the wb address wether it's enabled or not */
5841         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5842         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5843         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5844                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5845
5846         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5847         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5848                      lower_32_bits(wptr_gpu_addr));
5849         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5850                      upper_32_bits(wptr_gpu_addr));
5851
5852         mdelay(1);
5853         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5854
5855         rb_addr = ring->gpu_addr >> 8;
5856         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5857         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5858
5859         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5860
5861         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5862         mutex_unlock(&adev->srbm_mutex);
5863
5864         /* Init gfx ring 1 for pipe 1 */
5865         if (adev->gfx.num_gfx_rings > 1) {
5866                 mutex_lock(&adev->srbm_mutex);
5867                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5868                 /* maximum supported gfx ring is 2 */
5869                 ring = &adev->gfx.gfx_ring[1];
5870                 rb_bufsz = order_base_2(ring->ring_size / 8);
5871                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5872                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5873                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5874                 /* Initialize the ring buffer's write pointers */
5875                 ring->wptr = 0;
5876                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5877                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5878                 /* Set the wb address wether it's enabled or not */
5879                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5880                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5881                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5882                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5883                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5884                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5885                              lower_32_bits(wptr_gpu_addr));
5886                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5887                              upper_32_bits(wptr_gpu_addr));
5888
5889                 mdelay(1);
5890                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5891
5892                 rb_addr = ring->gpu_addr >> 8;
5893                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5894                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5895                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5896
5897                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5898                 mutex_unlock(&adev->srbm_mutex);
5899         }
5900         /* Switch to pipe 0 */
5901         mutex_lock(&adev->srbm_mutex);
5902         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5903         mutex_unlock(&adev->srbm_mutex);
5904
5905         /* start the ring */
5906         gfx_v10_0_cp_gfx_start(adev);
5907
5908         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5909                 ring = &adev->gfx.gfx_ring[i];
5910                 ring->sched.ready = true;
5911         }
5912
5913         return 0;
5914 }
5915
5916 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5917 {
5918         if (enable) {
5919                 switch (adev->asic_type) {
5920                 case CHIP_SIENNA_CICHLID:
5921                 case CHIP_NAVY_FLOUNDER:
5922                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5923                         break;
5924                 default:
5925                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5926                         break;
5927                 }
5928         } else {
5929                 switch (adev->asic_type) {
5930                 case CHIP_SIENNA_CICHLID:
5931                 case CHIP_NAVY_FLOUNDER:
5932                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
5933                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5934                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5935                         break;
5936                 default:
5937                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5938                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5939                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5940                         break;
5941                 }
5942                 adev->gfx.kiq.ring.sched.ready = false;
5943         }
5944         udelay(50);
5945 }
5946
5947 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5948 {
5949         const struct gfx_firmware_header_v1_0 *mec_hdr;
5950         const __le32 *fw_data;
5951         unsigned i;
5952         u32 tmp;
5953         u32 usec_timeout = 50000; /* Wait for 50 ms */
5954
5955         if (!adev->gfx.mec_fw)
5956                 return -EINVAL;
5957
5958         gfx_v10_0_cp_compute_enable(adev, false);
5959
5960         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5961         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5962
5963         fw_data = (const __le32 *)
5964                 (adev->gfx.mec_fw->data +
5965                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5966
5967         /* Trigger an invalidation of the L1 instruction caches */
5968         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5969         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5970         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5971
5972         /* Wait for invalidation complete */
5973         for (i = 0; i < usec_timeout; i++) {
5974                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5975                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5976                                        INVALIDATE_CACHE_COMPLETE))
5977                         break;
5978                 udelay(1);
5979         }
5980
5981         if (i >= usec_timeout) {
5982                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5983                 return -EINVAL;
5984         }
5985
5986         if (amdgpu_emu_mode == 1)
5987                 adev->nbio.funcs->hdp_flush(adev, NULL);
5988
5989         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
5990         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5991         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
5992         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5993         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
5994
5995         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
5996                      0xFFFFF000);
5997         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5998                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
5999
6000         /* MEC1 */
6001         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6002
6003         for (i = 0; i < mec_hdr->jt_size; i++)
6004                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6005                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6006
6007         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6008
6009         /*
6010          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6011          * different microcode than MEC1.
6012          */
6013
6014         return 0;
6015 }
6016
6017 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6018 {
6019         uint32_t tmp;
6020         struct amdgpu_device *adev = ring->adev;
6021
6022         /* tell RLC which is KIQ queue */
6023         switch (adev->asic_type) {
6024         case CHIP_SIENNA_CICHLID:
6025         case CHIP_NAVY_FLOUNDER:
6026                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6027                 tmp &= 0xffffff00;
6028                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6029                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6030                 tmp |= 0x80;
6031                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6032                 break;
6033         default:
6034                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6035                 tmp &= 0xffffff00;
6036                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6037                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6038                 tmp |= 0x80;
6039                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6040                 break;
6041         }
6042 }
6043
6044 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6045 {
6046         struct amdgpu_device *adev = ring->adev;
6047         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6048         uint64_t hqd_gpu_addr, wb_gpu_addr;
6049         uint32_t tmp;
6050         uint32_t rb_bufsz;
6051
6052         /* set up gfx hqd wptr */
6053         mqd->cp_gfx_hqd_wptr = 0;
6054         mqd->cp_gfx_hqd_wptr_hi = 0;
6055
6056         /* set the pointer to the MQD */
6057         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6058         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6059
6060         /* set up mqd control */
6061         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6062         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6063         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6064         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6065         mqd->cp_gfx_mqd_control = tmp;
6066
6067         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6068         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6069         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6070         mqd->cp_gfx_hqd_vmid = 0;
6071
6072         /* set up default queue priority level
6073          * 0x0 = low priority, 0x1 = high priority */
6074         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6075         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6076         mqd->cp_gfx_hqd_queue_priority = tmp;
6077
6078         /* set up time quantum */
6079         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6080         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6081         mqd->cp_gfx_hqd_quantum = tmp;
6082
6083         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6084         hqd_gpu_addr = ring->gpu_addr >> 8;
6085         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6086         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6087
6088         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6089         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6090         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6091         mqd->cp_gfx_hqd_rptr_addr_hi =
6092                 upper_32_bits(wb_gpu_addr) & 0xffff;
6093
6094         /* set up rb_wptr_poll addr */
6095         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6096         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6097         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6098
6099         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6100         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6101         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6102         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6103         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6104 #ifdef __BIG_ENDIAN
6105         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6106 #endif
6107         mqd->cp_gfx_hqd_cntl = tmp;
6108
6109         /* set up cp_doorbell_control */
6110         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6111         if (ring->use_doorbell) {
6112                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6113                                     DOORBELL_OFFSET, ring->doorbell_index);
6114                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6115                                     DOORBELL_EN, 1);
6116         } else
6117                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6118                                     DOORBELL_EN, 0);
6119         mqd->cp_rb_doorbell_control = tmp;
6120
6121         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6122         ring->wptr = 0;
6123         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6124
6125         /* active the queue */
6126         mqd->cp_gfx_hqd_active = 1;
6127
6128         return 0;
6129 }
6130
6131 #ifdef BRING_UP_DEBUG
6132 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6133 {
6134         struct amdgpu_device *adev = ring->adev;
6135         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6136
6137         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6138         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6139         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6140
6141         /* set GFX_MQD_BASE */
6142         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6143         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6144
6145         /* set GFX_MQD_CONTROL */
6146         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6147
6148         /* set GFX_HQD_VMID to 0 */
6149         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6150
6151         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6152                         mqd->cp_gfx_hqd_queue_priority);
6153         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6154
6155         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6156         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6157         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6158
6159         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6160         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6161         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6162
6163         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6164         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6165
6166         /* set RB_WPTR_POLL_ADDR */
6167         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6168         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6169
6170         /* set RB_DOORBELL_CONTROL */
6171         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6172
6173         /* active the queue */
6174         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6175
6176         return 0;
6177 }
6178 #endif
6179
6180 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6181 {
6182         struct amdgpu_device *adev = ring->adev;
6183         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6184         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6185
6186         if (!adev->in_gpu_reset && !adev->in_suspend) {
6187                 memset((void *)mqd, 0, sizeof(*mqd));
6188                 mutex_lock(&adev->srbm_mutex);
6189                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6190                 gfx_v10_0_gfx_mqd_init(ring);
6191 #ifdef BRING_UP_DEBUG
6192                 gfx_v10_0_gfx_queue_init_register(ring);
6193 #endif
6194                 nv_grbm_select(adev, 0, 0, 0, 0);
6195                 mutex_unlock(&adev->srbm_mutex);
6196                 if (adev->gfx.me.mqd_backup[mqd_idx])
6197                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6198         } else if (adev->in_gpu_reset) {
6199                 /* reset mqd with the backup copy */
6200                 if (adev->gfx.me.mqd_backup[mqd_idx])
6201                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6202                 /* reset the ring */
6203                 ring->wptr = 0;
6204                 adev->wb.wb[ring->wptr_offs] = 0;
6205                 amdgpu_ring_clear_ring(ring);
6206 #ifdef BRING_UP_DEBUG
6207                 mutex_lock(&adev->srbm_mutex);
6208                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6209                 gfx_v10_0_gfx_queue_init_register(ring);
6210                 nv_grbm_select(adev, 0, 0, 0, 0);
6211                 mutex_unlock(&adev->srbm_mutex);
6212 #endif
6213         } else {
6214                 amdgpu_ring_clear_ring(ring);
6215         }
6216
6217         return 0;
6218 }
6219
6220 #ifndef BRING_UP_DEBUG
6221 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6222 {
6223         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6224         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6225         int r, i;
6226
6227         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6228                 return -EINVAL;
6229
6230         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6231                                         adev->gfx.num_gfx_rings);
6232         if (r) {
6233                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6234                 return r;
6235         }
6236
6237         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6238                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6239
6240         return amdgpu_ring_test_helper(kiq_ring);
6241 }
6242 #endif
6243
6244 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6245 {
6246         int r, i;
6247         struct amdgpu_ring *ring;
6248
6249         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6250                 ring = &adev->gfx.gfx_ring[i];
6251
6252                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6253                 if (unlikely(r != 0))
6254                         goto done;
6255
6256                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6257                 if (!r) {
6258                         r = gfx_v10_0_gfx_init_queue(ring);
6259                         amdgpu_bo_kunmap(ring->mqd_obj);
6260                         ring->mqd_ptr = NULL;
6261                 }
6262                 amdgpu_bo_unreserve(ring->mqd_obj);
6263                 if (r)
6264                         goto done;
6265         }
6266 #ifndef BRING_UP_DEBUG
6267         r = gfx_v10_0_kiq_enable_kgq(adev);
6268         if (r)
6269                 goto done;
6270 #endif
6271         r = gfx_v10_0_cp_gfx_start(adev);
6272         if (r)
6273                 goto done;
6274
6275         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6276                 ring = &adev->gfx.gfx_ring[i];
6277                 ring->sched.ready = true;
6278         }
6279 done:
6280         return r;
6281 }
6282
6283 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6284 {
6285         struct amdgpu_device *adev = ring->adev;
6286
6287         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6288                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6289                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6290                         mqd->cp_hqd_queue_priority =
6291                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6292                 }
6293         }
6294 }
6295
6296 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6297 {
6298         struct amdgpu_device *adev = ring->adev;
6299         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6300         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6301         uint32_t tmp;
6302
6303         mqd->header = 0xC0310800;
6304         mqd->compute_pipelinestat_enable = 0x00000001;
6305         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6306         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6307         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6308         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6309         mqd->compute_misc_reserved = 0x00000003;
6310
6311         eop_base_addr = ring->eop_gpu_addr >> 8;
6312         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6313         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6314
6315         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6316         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6317         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6318                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6319
6320         mqd->cp_hqd_eop_control = tmp;
6321
6322         /* enable doorbell? */
6323         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6324
6325         if (ring->use_doorbell) {
6326                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6327                                     DOORBELL_OFFSET, ring->doorbell_index);
6328                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6329                                     DOORBELL_EN, 1);
6330                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6331                                     DOORBELL_SOURCE, 0);
6332                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6333                                     DOORBELL_HIT, 0);
6334         } else {
6335                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6336                                     DOORBELL_EN, 0);
6337         }
6338
6339         mqd->cp_hqd_pq_doorbell_control = tmp;
6340
6341         /* disable the queue if it's active */
6342         ring->wptr = 0;
6343         mqd->cp_hqd_dequeue_request = 0;
6344         mqd->cp_hqd_pq_rptr = 0;
6345         mqd->cp_hqd_pq_wptr_lo = 0;
6346         mqd->cp_hqd_pq_wptr_hi = 0;
6347
6348         /* set the pointer to the MQD */
6349         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6350         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6351
6352         /* set MQD vmid to 0 */
6353         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6354         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6355         mqd->cp_mqd_control = tmp;
6356
6357         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6358         hqd_gpu_addr = ring->gpu_addr >> 8;
6359         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6360         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6361
6362         /* set up the HQD, this is similar to CP_RB0_CNTL */
6363         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6364         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6365                             (order_base_2(ring->ring_size / 4) - 1));
6366         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6367                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6368 #ifdef __BIG_ENDIAN
6369         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6370 #endif
6371         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6372         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6373         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6374         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6375         mqd->cp_hqd_pq_control = tmp;
6376
6377         /* set the wb address whether it's enabled or not */
6378         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6379         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6380         mqd->cp_hqd_pq_rptr_report_addr_hi =
6381                 upper_32_bits(wb_gpu_addr) & 0xffff;
6382
6383         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6384         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6385         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6386         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6387
6388         tmp = 0;
6389         /* enable the doorbell if requested */
6390         if (ring->use_doorbell) {
6391                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6392                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6393                                 DOORBELL_OFFSET, ring->doorbell_index);
6394
6395                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6396                                     DOORBELL_EN, 1);
6397                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6398                                     DOORBELL_SOURCE, 0);
6399                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6400                                     DOORBELL_HIT, 0);
6401         }
6402
6403         mqd->cp_hqd_pq_doorbell_control = tmp;
6404
6405         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6406         ring->wptr = 0;
6407         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6408
6409         /* set the vmid for the queue */
6410         mqd->cp_hqd_vmid = 0;
6411
6412         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6413         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6414         mqd->cp_hqd_persistent_state = tmp;
6415
6416         /* set MIN_IB_AVAIL_SIZE */
6417         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6418         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6419         mqd->cp_hqd_ib_control = tmp;
6420
6421         /* set static priority for a compute queue/ring */
6422         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6423
6424         /* map_queues packet doesn't need activate the queue,
6425          * so only kiq need set this field.
6426          */
6427         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6428                 mqd->cp_hqd_active = 1;
6429
6430         return 0;
6431 }
6432
6433 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6434 {
6435         struct amdgpu_device *adev = ring->adev;
6436         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6437         int j;
6438
6439         /* disable wptr polling */
6440         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6441
6442         /* write the EOP addr */
6443         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6444                mqd->cp_hqd_eop_base_addr_lo);
6445         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6446                mqd->cp_hqd_eop_base_addr_hi);
6447
6448         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6449         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6450                mqd->cp_hqd_eop_control);
6451
6452         /* enable doorbell? */
6453         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6454                mqd->cp_hqd_pq_doorbell_control);
6455
6456         /* disable the queue if it's active */
6457         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6458                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6459                 for (j = 0; j < adev->usec_timeout; j++) {
6460                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6461                                 break;
6462                         udelay(1);
6463                 }
6464                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6465                        mqd->cp_hqd_dequeue_request);
6466                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6467                        mqd->cp_hqd_pq_rptr);
6468                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6469                        mqd->cp_hqd_pq_wptr_lo);
6470                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6471                        mqd->cp_hqd_pq_wptr_hi);
6472         }
6473
6474         /* set the pointer to the MQD */
6475         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6476                mqd->cp_mqd_base_addr_lo);
6477         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6478                mqd->cp_mqd_base_addr_hi);
6479
6480         /* set MQD vmid to 0 */
6481         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6482                mqd->cp_mqd_control);
6483
6484         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6485         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6486                mqd->cp_hqd_pq_base_lo);
6487         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6488                mqd->cp_hqd_pq_base_hi);
6489
6490         /* set up the HQD, this is similar to CP_RB0_CNTL */
6491         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6492                mqd->cp_hqd_pq_control);
6493
6494         /* set the wb address whether it's enabled or not */
6495         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6496                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6497         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6498                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6499
6500         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6501         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6502                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6503         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6504                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6505
6506         /* enable the doorbell if requested */
6507         if (ring->use_doorbell) {
6508                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6509                         (adev->doorbell_index.kiq * 2) << 2);
6510                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6511                         (adev->doorbell_index.userqueue_end * 2) << 2);
6512         }
6513
6514         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6515                mqd->cp_hqd_pq_doorbell_control);
6516
6517         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6518         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6519                mqd->cp_hqd_pq_wptr_lo);
6520         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6521                mqd->cp_hqd_pq_wptr_hi);
6522
6523         /* set the vmid for the queue */
6524         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6525
6526         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6527                mqd->cp_hqd_persistent_state);
6528
6529         /* activate the queue */
6530         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6531                mqd->cp_hqd_active);
6532
6533         if (ring->use_doorbell)
6534                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6535
6536         return 0;
6537 }
6538
6539 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6540 {
6541         struct amdgpu_device *adev = ring->adev;
6542         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6543         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6544
6545         gfx_v10_0_kiq_setting(ring);
6546
6547         if (adev->in_gpu_reset) { /* for GPU_RESET case */
6548                 /* reset MQD to a clean status */
6549                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6550                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6551
6552                 /* reset ring buffer */
6553                 ring->wptr = 0;
6554                 amdgpu_ring_clear_ring(ring);
6555
6556                 mutex_lock(&adev->srbm_mutex);
6557                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6558                 gfx_v10_0_kiq_init_register(ring);
6559                 nv_grbm_select(adev, 0, 0, 0, 0);
6560                 mutex_unlock(&adev->srbm_mutex);
6561         } else {
6562                 memset((void *)mqd, 0, sizeof(*mqd));
6563                 mutex_lock(&adev->srbm_mutex);
6564                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6565                 gfx_v10_0_compute_mqd_init(ring);
6566                 gfx_v10_0_kiq_init_register(ring);
6567                 nv_grbm_select(adev, 0, 0, 0, 0);
6568                 mutex_unlock(&adev->srbm_mutex);
6569
6570                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6571                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6572         }
6573
6574         return 0;
6575 }
6576
6577 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6578 {
6579         struct amdgpu_device *adev = ring->adev;
6580         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6581         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6582
6583         if (!adev->in_gpu_reset && !adev->in_suspend) {
6584                 memset((void *)mqd, 0, sizeof(*mqd));
6585                 mutex_lock(&adev->srbm_mutex);
6586                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6587                 gfx_v10_0_compute_mqd_init(ring);
6588                 nv_grbm_select(adev, 0, 0, 0, 0);
6589                 mutex_unlock(&adev->srbm_mutex);
6590
6591                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6592                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6593         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
6594                 /* reset MQD to a clean status */
6595                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6596                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6597
6598                 /* reset ring buffer */
6599                 ring->wptr = 0;
6600                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6601                 amdgpu_ring_clear_ring(ring);
6602         } else {
6603                 amdgpu_ring_clear_ring(ring);
6604         }
6605
6606         return 0;
6607 }
6608
6609 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6610 {
6611         struct amdgpu_ring *ring;
6612         int r;
6613
6614         ring = &adev->gfx.kiq.ring;
6615
6616         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6617         if (unlikely(r != 0))
6618                 return r;
6619
6620         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6621         if (unlikely(r != 0))
6622                 return r;
6623
6624         gfx_v10_0_kiq_init_queue(ring);
6625         amdgpu_bo_kunmap(ring->mqd_obj);
6626         ring->mqd_ptr = NULL;
6627         amdgpu_bo_unreserve(ring->mqd_obj);
6628         ring->sched.ready = true;
6629         return 0;
6630 }
6631
6632 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6633 {
6634         struct amdgpu_ring *ring = NULL;
6635         int r = 0, i;
6636
6637         gfx_v10_0_cp_compute_enable(adev, true);
6638
6639         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6640                 ring = &adev->gfx.compute_ring[i];
6641
6642                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6643                 if (unlikely(r != 0))
6644                         goto done;
6645                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6646                 if (!r) {
6647                         r = gfx_v10_0_kcq_init_queue(ring);
6648                         amdgpu_bo_kunmap(ring->mqd_obj);
6649                         ring->mqd_ptr = NULL;
6650                 }
6651                 amdgpu_bo_unreserve(ring->mqd_obj);
6652                 if (r)
6653                         goto done;
6654         }
6655
6656         r = amdgpu_gfx_enable_kcq(adev);
6657 done:
6658         return r;
6659 }
6660
6661 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6662 {
6663         int r, i;
6664         struct amdgpu_ring *ring;
6665
6666         if (!(adev->flags & AMD_IS_APU))
6667                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6668
6669         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6670                 /* legacy firmware loading */
6671                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6672                 if (r)
6673                         return r;
6674
6675                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6676                 if (r)
6677                         return r;
6678         }
6679
6680         r = gfx_v10_0_kiq_resume(adev);
6681         if (r)
6682                 return r;
6683
6684         r = gfx_v10_0_kcq_resume(adev);
6685         if (r)
6686                 return r;
6687
6688         if (!amdgpu_async_gfx_ring) {
6689                 r = gfx_v10_0_cp_gfx_resume(adev);
6690                 if (r)
6691                         return r;
6692         } else {
6693                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6694                 if (r)
6695                         return r;
6696         }
6697
6698         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6699                 ring = &adev->gfx.gfx_ring[i];
6700                 r = amdgpu_ring_test_helper(ring);
6701                 if (r)
6702                         return r;
6703         }
6704
6705         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6706                 ring = &adev->gfx.compute_ring[i];
6707                 r = amdgpu_ring_test_helper(ring);
6708                 if (r)
6709                         return r;
6710         }
6711
6712         return 0;
6713 }
6714
6715 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6716 {
6717         gfx_v10_0_cp_gfx_enable(adev, enable);
6718         gfx_v10_0_cp_compute_enable(adev, enable);
6719 }
6720
6721 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6722 {
6723         uint32_t data, pattern = 0xDEADBEEF;
6724
6725         /* check if mmVGT_ESGS_RING_SIZE_UMD
6726          * has been remapped to mmVGT_ESGS_RING_SIZE */
6727         switch (adev->asic_type) {
6728         case CHIP_SIENNA_CICHLID:
6729         case CHIP_NAVY_FLOUNDER:
6730                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6731                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6732                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6733
6734                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6735                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6736                         return true;
6737                 } else {
6738                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6739                         return false;
6740                 }
6741                 break;
6742         default:
6743                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6744                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6745                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6746
6747                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6748                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6749                         return true;
6750                 } else {
6751                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6752                         return false;
6753                 }
6754                 break;
6755         }
6756 }
6757
6758 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6759 {
6760         uint32_t data;
6761
6762         /* initialize cam_index to 0
6763          * index will auto-inc after each data writting */
6764         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6765
6766         switch (adev->asic_type) {
6767         case CHIP_SIENNA_CICHLID:
6768         case CHIP_NAVY_FLOUNDER:
6769                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6770                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6771                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6772                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6773                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6774                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6775                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6776
6777                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6778                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6779                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6780                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6781                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6782                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6783                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6784
6785                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6786                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6787                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6788                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6789                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6790                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6791                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6792
6793                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6794                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6795                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6796                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6797                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6798                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6799                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6800
6801                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6802                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6803                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6804                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6805                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6806                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6807                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6808
6809                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6810                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6811                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6812                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6813                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6814                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6815                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6816
6817                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6818                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6819                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6820                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6821                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6822                 break;
6823         default:
6824                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6825                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6826                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6827                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6828                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6829                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6830                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6831
6832                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6833                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6834                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6835                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6836                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6837                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6838                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6839
6840                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6841                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6842                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6843                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6844                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6845                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6846                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6847
6848                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6849                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6850                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6851                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6852                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6853                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6854                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6855
6856                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6857                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6858                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6859                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6860                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6861                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6862                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6863
6864                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6865                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6866                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6867                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6868                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6869                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6870                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6871
6872                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6873                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6874                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6875                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6876                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6877                 break;
6878         }
6879
6880         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6881         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6882 }
6883
6884 static int gfx_v10_0_hw_init(void *handle)
6885 {
6886         int r;
6887         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6888
6889         if (!amdgpu_emu_mode)
6890                 gfx_v10_0_init_golden_registers(adev);
6891
6892         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6893                 /**
6894                  * For gfx 10, rlc firmware loading relies on smu firmware is
6895                  * loaded firstly, so in direct type, it has to load smc ucode
6896                  * here before rlc.
6897                  */
6898                 if (adev->smu.ppt_funcs != NULL) {
6899                         r = smu_load_microcode(&adev->smu);
6900                         if (r)
6901                                 return r;
6902
6903                         r = smu_check_fw_status(&adev->smu);
6904                         if (r) {
6905                                 pr_err("SMC firmware status is not correct\n");
6906                                 return r;
6907                         }
6908                 }
6909         }
6910
6911         /* if GRBM CAM not remapped, set up the remapping */
6912         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6913                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6914
6915         gfx_v10_0_constants_init(adev);
6916
6917         r = gfx_v10_0_rlc_resume(adev);
6918         if (r)
6919                 return r;
6920
6921         /*
6922          * init golden registers and rlc resume may override some registers,
6923          * reconfig them here
6924          */
6925         gfx_v10_0_tcp_harvest(adev);
6926
6927         r = gfx_v10_0_cp_resume(adev);
6928         if (r)
6929                 return r;
6930
6931         return r;
6932 }
6933
6934 #ifndef BRING_UP_DEBUG
6935 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6936 {
6937         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6938         struct amdgpu_ring *kiq_ring = &kiq->ring;
6939         int i;
6940
6941         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6942                 return -EINVAL;
6943
6944         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6945                                         adev->gfx.num_gfx_rings))
6946                 return -ENOMEM;
6947
6948         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6949                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6950                                            PREEMPT_QUEUES, 0, 0);
6951
6952         return amdgpu_ring_test_helper(kiq_ring);
6953 }
6954 #endif
6955
6956 static int gfx_v10_0_hw_fini(void *handle)
6957 {
6958         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6959         int r;
6960         uint32_t tmp;
6961
6962         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6963         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6964 #ifndef BRING_UP_DEBUG
6965         if (amdgpu_async_gfx_ring) {
6966                 r = gfx_v10_0_kiq_disable_kgq(adev);
6967                 if (r)
6968                         DRM_ERROR("KGQ disable failed\n");
6969         }
6970 #endif
6971         if (amdgpu_gfx_disable_kcq(adev))
6972                 DRM_ERROR("KCQ disable failed\n");
6973         if (amdgpu_sriov_vf(adev)) {
6974                 gfx_v10_0_cp_gfx_enable(adev, false);
6975                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
6976                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6977                 tmp &= 0xffffff00;
6978                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6979
6980                 return 0;
6981         }
6982         gfx_v10_0_cp_enable(adev, false);
6983         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6984
6985         return 0;
6986 }
6987
6988 static int gfx_v10_0_suspend(void *handle)
6989 {
6990         return gfx_v10_0_hw_fini(handle);
6991 }
6992
6993 static int gfx_v10_0_resume(void *handle)
6994 {
6995         return gfx_v10_0_hw_init(handle);
6996 }
6997
6998 static bool gfx_v10_0_is_idle(void *handle)
6999 {
7000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7001
7002         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7003                                 GRBM_STATUS, GUI_ACTIVE))
7004                 return false;
7005         else
7006                 return true;
7007 }
7008
7009 static int gfx_v10_0_wait_for_idle(void *handle)
7010 {
7011         unsigned i;
7012         u32 tmp;
7013         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7014
7015         for (i = 0; i < adev->usec_timeout; i++) {
7016                 /* read MC_STATUS */
7017                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7018                         GRBM_STATUS__GUI_ACTIVE_MASK;
7019
7020                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7021                         return 0;
7022                 udelay(1);
7023         }
7024         return -ETIMEDOUT;
7025 }
7026
7027 static int gfx_v10_0_soft_reset(void *handle)
7028 {
7029         u32 grbm_soft_reset = 0;
7030         u32 tmp;
7031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7032
7033         /* GRBM_STATUS */
7034         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7035         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7036                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7037                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7038                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7039                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
7040                    | GRBM_STATUS__BCI_BUSY_MASK)) {
7041                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7042                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7043                                                 1);
7044                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7045                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7046                                                 1);
7047         }
7048
7049         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7050                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7051                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7052                                                 1);
7053         }
7054
7055         /* GRBM_STATUS2 */
7056         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7057         switch (adev->asic_type) {
7058         case CHIP_SIENNA_CICHLID:
7059         case CHIP_NAVY_FLOUNDER:
7060                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7061                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7062                                                         GRBM_SOFT_RESET,
7063                                                         SOFT_RESET_RLC,
7064                                                         1);
7065                 break;
7066         default:
7067                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7068                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7069                                                         GRBM_SOFT_RESET,
7070                                                         SOFT_RESET_RLC,
7071                                                         1);
7072                 break;
7073         }
7074
7075         if (grbm_soft_reset) {
7076                 /* stop the rlc */
7077                 gfx_v10_0_rlc_stop(adev);
7078
7079                 /* Disable GFX parsing/prefetching */
7080                 gfx_v10_0_cp_gfx_enable(adev, false);
7081
7082                 /* Disable MEC parsing/prefetching */
7083                 gfx_v10_0_cp_compute_enable(adev, false);
7084
7085                 if (grbm_soft_reset) {
7086                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7087                         tmp |= grbm_soft_reset;
7088                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7089                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7090                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7091
7092                         udelay(50);
7093
7094                         tmp &= ~grbm_soft_reset;
7095                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7096                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7097                 }
7098
7099                 /* Wait a little for things to settle down */
7100                 udelay(50);
7101         }
7102         return 0;
7103 }
7104
7105 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7106 {
7107         uint64_t clock;
7108
7109         amdgpu_gfx_off_ctrl(adev, false);
7110         mutex_lock(&adev->gfx.gpu_clock_mutex);
7111         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7112                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7113         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7114         amdgpu_gfx_off_ctrl(adev, true);
7115         return clock;
7116 }
7117
7118 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7119                                            uint32_t vmid,
7120                                            uint32_t gds_base, uint32_t gds_size,
7121                                            uint32_t gws_base, uint32_t gws_size,
7122                                            uint32_t oa_base, uint32_t oa_size)
7123 {
7124         struct amdgpu_device *adev = ring->adev;
7125
7126         /* GDS Base */
7127         gfx_v10_0_write_data_to_reg(ring, 0, false,
7128                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7129                                     gds_base);
7130
7131         /* GDS Size */
7132         gfx_v10_0_write_data_to_reg(ring, 0, false,
7133                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7134                                     gds_size);
7135
7136         /* GWS */
7137         gfx_v10_0_write_data_to_reg(ring, 0, false,
7138                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7139                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7140
7141         /* OA */
7142         gfx_v10_0_write_data_to_reg(ring, 0, false,
7143                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7144                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7145 }
7146
7147 static int gfx_v10_0_early_init(void *handle)
7148 {
7149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7150
7151         switch (adev->asic_type) {
7152         case CHIP_NAVI10:
7153         case CHIP_NAVI14:
7154         case CHIP_NAVI12:
7155                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7156                 break;
7157         case CHIP_SIENNA_CICHLID:
7158         case CHIP_NAVY_FLOUNDER:
7159                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7160                 break;
7161         default:
7162                 break;
7163         }
7164
7165         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
7166
7167         gfx_v10_0_set_kiq_pm4_funcs(adev);
7168         gfx_v10_0_set_ring_funcs(adev);
7169         gfx_v10_0_set_irq_funcs(adev);
7170         gfx_v10_0_set_gds_init(adev);
7171         gfx_v10_0_set_rlc_funcs(adev);
7172
7173         return 0;
7174 }
7175
7176 static int gfx_v10_0_late_init(void *handle)
7177 {
7178         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7179         int r;
7180
7181         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7182         if (r)
7183                 return r;
7184
7185         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7186         if (r)
7187                 return r;
7188
7189         return 0;
7190 }
7191
7192 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7193 {
7194         uint32_t rlc_cntl;
7195
7196         /* if RLC is not enabled, do nothing */
7197         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7198         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7199 }
7200
7201 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7202 {
7203         uint32_t data;
7204         unsigned i;
7205
7206         data = RLC_SAFE_MODE__CMD_MASK;
7207         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7208
7209         switch (adev->asic_type) {
7210         case CHIP_SIENNA_CICHLID:
7211         case CHIP_NAVY_FLOUNDER:
7212                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7213
7214                 /* wait for RLC_SAFE_MODE */
7215                 for (i = 0; i < adev->usec_timeout; i++) {
7216                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7217                                            RLC_SAFE_MODE, CMD))
7218                                 break;
7219                         udelay(1);
7220                 }
7221                 break;
7222         default:
7223                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7224
7225                 /* wait for RLC_SAFE_MODE */
7226                 for (i = 0; i < adev->usec_timeout; i++) {
7227                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7228                                            RLC_SAFE_MODE, CMD))
7229                                 break;
7230                         udelay(1);
7231                 }
7232                 break;
7233         }
7234 }
7235
7236 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7237 {
7238         uint32_t data;
7239
7240         data = RLC_SAFE_MODE__CMD_MASK;
7241         switch (adev->asic_type) {
7242         case CHIP_SIENNA_CICHLID:
7243         case CHIP_NAVY_FLOUNDER:
7244                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7245                 break;
7246         default:
7247                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7248                 break;
7249         }
7250 }
7251
7252 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7253                                                       bool enable)
7254 {
7255         uint32_t data, def;
7256
7257         /* It is disabled by HW by default */
7258         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7259                 /* 0 - Disable some blocks' MGCG */
7260                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7261                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7262                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7263                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7264
7265                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7266                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7267                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7268                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7269                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7270                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7271
7272                 if (def != data)
7273                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7274
7275                 /* MGLS is a global flag to control all MGLS in GFX */
7276                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7277                         /* 2 - RLC memory Light sleep */
7278                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7279                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7280                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7281                                 if (def != data)
7282                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7283                         }
7284                         /* 3 - CP memory Light sleep */
7285                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7286                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7287                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7288                                 if (def != data)
7289                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7290                         }
7291                 }
7292         } else {
7293                 /* 1 - MGCG_OVERRIDE */
7294                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7295                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7296                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7297                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7298                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7299                 if (def != data)
7300                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7301
7302                 /* 2 - disable MGLS in CP */
7303                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7304                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7305                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7306                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7307                 }
7308
7309                 /* 3 - disable MGLS in RLC */
7310                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7311                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7312                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7313                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7314                 }
7315
7316         }
7317 }
7318
7319 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7320                                            bool enable)
7321 {
7322         uint32_t data, def;
7323
7324         /* Enable 3D CGCG/CGLS */
7325         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7326                 /* write cmd to clear cgcg/cgls ov */
7327                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7328                 /* unset CGCG override */
7329                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7330                 /* update CGCG and CGLS override bits */
7331                 if (def != data)
7332                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7333                 /* enable 3Dcgcg FSM(0x0000363f) */
7334                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7335                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7336                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7337                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7338                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7339                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7340                 if (def != data)
7341                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7342
7343                 /* set IDLE_POLL_COUNT(0x00900100) */
7344                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7345                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7346                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7347                 if (def != data)
7348                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7349         } else {
7350                 /* Disable CGCG/CGLS */
7351                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7352                 /* disable cgcg, cgls should be disabled */
7353                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7354                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7355                 /* disable cgcg and cgls in FSM */
7356                 if (def != data)
7357                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7358         }
7359 }
7360
7361 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7362                                                       bool enable)
7363 {
7364         uint32_t def, data;
7365
7366         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7367                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7368                 /* unset CGCG override */
7369                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7370                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7371                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7372                 else
7373                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7374                 /* update CGCG and CGLS override bits */
7375                 if (def != data)
7376                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7377
7378                 /* enable cgcg FSM(0x0000363F) */
7379                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7380                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7381                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7382                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7383                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7384                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7385                 if (def != data)
7386                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7387
7388                 /* set IDLE_POLL_COUNT(0x00900100) */
7389                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7390                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7391                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7392                 if (def != data)
7393                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7394         } else {
7395                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7396                 /* reset CGCG/CGLS bits */
7397                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7398                 /* disable cgcg and cgls in FSM */
7399                 if (def != data)
7400                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7401         }
7402 }
7403
7404 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7405                                             bool enable)
7406 {
7407         amdgpu_gfx_rlc_enter_safe_mode(adev);
7408
7409         if (enable) {
7410                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7411                  * ===  MGCG + MGLS ===
7412                  */
7413                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7414                 /* ===  CGCG /CGLS for GFX 3D Only === */
7415                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7416                 /* ===  CGCG + CGLS === */
7417                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7418         } else {
7419                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7420                  * ===  CGCG + CGLS ===
7421                  */
7422                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7423                 /* ===  CGCG /CGLS for GFX 3D Only === */
7424                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7425                 /* ===  MGCG + MGLS === */
7426                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7427         }
7428
7429         if (adev->cg_flags &
7430             (AMD_CG_SUPPORT_GFX_MGCG |
7431              AMD_CG_SUPPORT_GFX_CGLS |
7432              AMD_CG_SUPPORT_GFX_CGCG |
7433              AMD_CG_SUPPORT_GFX_CGLS |
7434              AMD_CG_SUPPORT_GFX_3D_CGCG |
7435              AMD_CG_SUPPORT_GFX_3D_CGLS))
7436                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7437
7438         amdgpu_gfx_rlc_exit_safe_mode(adev);
7439
7440         return 0;
7441 }
7442
7443 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7444 {
7445         u32 reg, data;
7446
7447         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7448         if (amdgpu_sriov_is_pp_one_vf(adev))
7449                 data = RREG32_NO_KIQ(reg);
7450         else
7451                 data = RREG32(reg);
7452
7453         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7454         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7455
7456         if (amdgpu_sriov_is_pp_one_vf(adev))
7457                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7458         else
7459                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7460 }
7461
7462 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7463                                         uint32_t offset,
7464                                         struct soc15_reg_rlcg *entries, int arr_size)
7465 {
7466         int i;
7467         uint32_t reg;
7468
7469         if (!entries)
7470                 return false;
7471
7472         for (i = 0; i < arr_size; i++) {
7473                 const struct soc15_reg_rlcg *entry;
7474
7475                 entry = &entries[i];
7476                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7477                 if (offset == reg)
7478                         return true;
7479         }
7480
7481         return false;
7482 }
7483
7484 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7485 {
7486         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7487 }
7488
7489 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7490         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7491         .set_safe_mode = gfx_v10_0_set_safe_mode,
7492         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7493         .init = gfx_v10_0_rlc_init,
7494         .get_csb_size = gfx_v10_0_get_csb_size,
7495         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7496         .resume = gfx_v10_0_rlc_resume,
7497         .stop = gfx_v10_0_rlc_stop,
7498         .reset = gfx_v10_0_rlc_reset,
7499         .start = gfx_v10_0_rlc_start,
7500         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7501 };
7502
7503 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7504         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7505         .set_safe_mode = gfx_v10_0_set_safe_mode,
7506         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7507         .init = gfx_v10_0_rlc_init,
7508         .get_csb_size = gfx_v10_0_get_csb_size,
7509         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7510         .resume = gfx_v10_0_rlc_resume,
7511         .stop = gfx_v10_0_rlc_stop,
7512         .reset = gfx_v10_0_rlc_reset,
7513         .start = gfx_v10_0_rlc_start,
7514         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7515         .rlcg_wreg = gfx_v10_rlcg_wreg,
7516         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7517 };
7518
7519 static int gfx_v10_0_set_powergating_state(void *handle,
7520                                           enum amd_powergating_state state)
7521 {
7522         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7523         bool enable = (state == AMD_PG_STATE_GATE);
7524
7525         if (amdgpu_sriov_vf(adev))
7526                 return 0;
7527
7528         switch (adev->asic_type) {
7529         case CHIP_NAVI10:
7530         case CHIP_NAVI14:
7531         case CHIP_NAVI12:
7532         case CHIP_SIENNA_CICHLID:
7533         case CHIP_NAVY_FLOUNDER:
7534                 amdgpu_gfx_off_ctrl(adev, enable);
7535                 break;
7536         default:
7537                 break;
7538         }
7539         return 0;
7540 }
7541
7542 static int gfx_v10_0_set_clockgating_state(void *handle,
7543                                           enum amd_clockgating_state state)
7544 {
7545         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7546
7547         if (amdgpu_sriov_vf(adev))
7548                 return 0;
7549
7550         switch (adev->asic_type) {
7551         case CHIP_NAVI10:
7552         case CHIP_NAVI14:
7553         case CHIP_NAVI12:
7554         case CHIP_SIENNA_CICHLID:
7555         case CHIP_NAVY_FLOUNDER:
7556                 gfx_v10_0_update_gfx_clock_gating(adev,
7557                                                  state == AMD_CG_STATE_GATE);
7558                 break;
7559         default:
7560                 break;
7561         }
7562         return 0;
7563 }
7564
7565 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7566 {
7567         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7568         int data;
7569
7570         /* AMD_CG_SUPPORT_GFX_MGCG */
7571         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7572         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7573                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7574
7575         /* AMD_CG_SUPPORT_GFX_CGCG */
7576         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7577         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7578                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7579
7580         /* AMD_CG_SUPPORT_GFX_CGLS */
7581         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7582                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7583
7584         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7585         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7586         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7587                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7588
7589         /* AMD_CG_SUPPORT_GFX_CP_LS */
7590         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7591         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7592                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7593
7594         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7595         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7596         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7597                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7598
7599         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7600         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7601                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7602 }
7603
7604 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7605 {
7606         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7607 }
7608
7609 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7610 {
7611         struct amdgpu_device *adev = ring->adev;
7612         u64 wptr;
7613
7614         /* XXX check if swapping is necessary on BE */
7615         if (ring->use_doorbell) {
7616                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7617         } else {
7618                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7619                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7620         }
7621
7622         return wptr;
7623 }
7624
7625 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7626 {
7627         struct amdgpu_device *adev = ring->adev;
7628
7629         if (ring->use_doorbell) {
7630                 /* XXX check if swapping is necessary on BE */
7631                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7632                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7633         } else {
7634                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7635                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7636         }
7637 }
7638
7639 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7640 {
7641         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7642 }
7643
7644 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7645 {
7646         u64 wptr;
7647
7648         /* XXX check if swapping is necessary on BE */
7649         if (ring->use_doorbell)
7650                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7651         else
7652                 BUG();
7653         return wptr;
7654 }
7655
7656 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7657 {
7658         struct amdgpu_device *adev = ring->adev;
7659
7660         /* XXX check if swapping is necessary on BE */
7661         if (ring->use_doorbell) {
7662                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7663                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7664         } else {
7665                 BUG(); /* only DOORBELL method supported on gfx10 now */
7666         }
7667 }
7668
7669 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7670 {
7671         struct amdgpu_device *adev = ring->adev;
7672         u32 ref_and_mask, reg_mem_engine;
7673         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7674
7675         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7676                 switch (ring->me) {
7677                 case 1:
7678                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7679                         break;
7680                 case 2:
7681                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7682                         break;
7683                 default:
7684                         return;
7685                 }
7686                 reg_mem_engine = 0;
7687         } else {
7688                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7689                 reg_mem_engine = 1; /* pfp */
7690         }
7691
7692         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7693                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7694                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7695                                ref_and_mask, ref_and_mask, 0x20);
7696 }
7697
7698 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7699                                        struct amdgpu_job *job,
7700                                        struct amdgpu_ib *ib,
7701                                        uint32_t flags)
7702 {
7703         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7704         u32 header, control = 0;
7705
7706         if (ib->flags & AMDGPU_IB_FLAG_CE)
7707                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7708         else
7709                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7710
7711         control |= ib->length_dw | (vmid << 24);
7712
7713         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7714                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7715
7716                 if (flags & AMDGPU_IB_PREEMPTED)
7717                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7718
7719                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7720                         gfx_v10_0_ring_emit_de_meta(ring,
7721                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7722         }
7723
7724         amdgpu_ring_write(ring, header);
7725         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7726         amdgpu_ring_write(ring,
7727 #ifdef __BIG_ENDIAN
7728                 (2 << 0) |
7729 #endif
7730                 lower_32_bits(ib->gpu_addr));
7731         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7732         amdgpu_ring_write(ring, control);
7733 }
7734
7735 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7736                                            struct amdgpu_job *job,
7737                                            struct amdgpu_ib *ib,
7738                                            uint32_t flags)
7739 {
7740         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7741         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7742
7743         /* Currently, there is a high possibility to get wave ID mismatch
7744          * between ME and GDS, leading to a hw deadlock, because ME generates
7745          * different wave IDs than the GDS expects. This situation happens
7746          * randomly when at least 5 compute pipes use GDS ordered append.
7747          * The wave IDs generated by ME are also wrong after suspend/resume.
7748          * Those are probably bugs somewhere else in the kernel driver.
7749          *
7750          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7751          * GDS to 0 for this ring (me/pipe).
7752          */
7753         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7754                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7755                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7756                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7757         }
7758
7759         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7760         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7761         amdgpu_ring_write(ring,
7762 #ifdef __BIG_ENDIAN
7763                                 (2 << 0) |
7764 #endif
7765                                 lower_32_bits(ib->gpu_addr));
7766         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7767         amdgpu_ring_write(ring, control);
7768 }
7769
7770 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7771                                      u64 seq, unsigned flags)
7772 {
7773         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7774         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7775
7776         /* RELEASE_MEM - flush caches, send int */
7777         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7778         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7779                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7780                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7781                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7782                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7783                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7784                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7785         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7786                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7787
7788         /*
7789          * the address should be Qword aligned if 64bit write, Dword
7790          * aligned if only send 32bit data low (discard data high)
7791          */
7792         if (write64bit)
7793                 BUG_ON(addr & 0x7);
7794         else
7795                 BUG_ON(addr & 0x3);
7796         amdgpu_ring_write(ring, lower_32_bits(addr));
7797         amdgpu_ring_write(ring, upper_32_bits(addr));
7798         amdgpu_ring_write(ring, lower_32_bits(seq));
7799         amdgpu_ring_write(ring, upper_32_bits(seq));
7800         amdgpu_ring_write(ring, 0);
7801 }
7802
7803 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7804 {
7805         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7806         uint32_t seq = ring->fence_drv.sync_seq;
7807         uint64_t addr = ring->fence_drv.gpu_addr;
7808
7809         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7810                                upper_32_bits(addr), seq, 0xffffffff, 4);
7811 }
7812
7813 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7814                                          unsigned vmid, uint64_t pd_addr)
7815 {
7816         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7817
7818         /* compute doesn't have PFP */
7819         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7820                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7821                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7822                 amdgpu_ring_write(ring, 0x0);
7823         }
7824 }
7825
7826 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7827                                           u64 seq, unsigned int flags)
7828 {
7829         struct amdgpu_device *adev = ring->adev;
7830
7831         /* we only allocate 32bit for each seq wb address */
7832         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7833
7834         /* write fence seq to the "addr" */
7835         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7836         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7837                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7838         amdgpu_ring_write(ring, lower_32_bits(addr));
7839         amdgpu_ring_write(ring, upper_32_bits(addr));
7840         amdgpu_ring_write(ring, lower_32_bits(seq));
7841
7842         if (flags & AMDGPU_FENCE_FLAG_INT) {
7843                 /* set register to trigger INT */
7844                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7845                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7846                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7847                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7848                 amdgpu_ring_write(ring, 0);
7849                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7850         }
7851 }
7852
7853 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7854 {
7855         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7856         amdgpu_ring_write(ring, 0);
7857 }
7858
7859 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7860                                          uint32_t flags)
7861 {
7862         uint32_t dw2 = 0;
7863
7864         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7865                 gfx_v10_0_ring_emit_ce_meta(ring,
7866                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7867
7868         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7869         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7870                 /* set load_global_config & load_global_uconfig */
7871                 dw2 |= 0x8001;
7872                 /* set load_cs_sh_regs */
7873                 dw2 |= 0x01000000;
7874                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7875                 dw2 |= 0x10002;
7876
7877                 /* set load_ce_ram if preamble presented */
7878                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7879                         dw2 |= 0x10000000;
7880         } else {
7881                 /* still load_ce_ram if this is the first time preamble presented
7882                  * although there is no context switch happens.
7883                  */
7884                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7885                         dw2 |= 0x10000000;
7886         }
7887
7888         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7889         amdgpu_ring_write(ring, dw2);
7890         amdgpu_ring_write(ring, 0);
7891 }
7892
7893 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7894 {
7895         unsigned ret;
7896
7897         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7898         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7899         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7900         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7901         ret = ring->wptr & ring->buf_mask;
7902         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7903
7904         return ret;
7905 }
7906
7907 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7908 {
7909         unsigned cur;
7910         BUG_ON(offset > ring->buf_mask);
7911         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7912
7913         cur = (ring->wptr - 1) & ring->buf_mask;
7914         if (likely(cur > offset))
7915                 ring->ring[offset] = cur - offset;
7916         else
7917                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7918 }
7919
7920 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7921 {
7922         int i, r = 0;
7923         struct amdgpu_device *adev = ring->adev;
7924         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7925         struct amdgpu_ring *kiq_ring = &kiq->ring;
7926         unsigned long flags;
7927
7928         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7929                 return -EINVAL;
7930
7931         spin_lock_irqsave(&kiq->ring_lock, flags);
7932
7933         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
7934                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
7935                 return -ENOMEM;
7936         }
7937
7938         /* assert preemption condition */
7939         amdgpu_ring_set_preempt_cond_exec(ring, false);
7940
7941         /* assert IB preemption, emit the trailing fence */
7942         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7943                                    ring->trail_fence_gpu_addr,
7944                                    ++ring->trail_seq);
7945         amdgpu_ring_commit(kiq_ring);
7946
7947         spin_unlock_irqrestore(&kiq->ring_lock, flags);
7948
7949         /* poll the trailing fence */
7950         for (i = 0; i < adev->usec_timeout; i++) {
7951                 if (ring->trail_seq ==
7952                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7953                         break;
7954                 udelay(1);
7955         }
7956
7957         if (i >= adev->usec_timeout) {
7958                 r = -EINVAL;
7959                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7960         }
7961
7962         /* deassert preemption condition */
7963         amdgpu_ring_set_preempt_cond_exec(ring, true);
7964         return r;
7965 }
7966
7967 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7968 {
7969         struct amdgpu_device *adev = ring->adev;
7970         struct v10_ce_ib_state ce_payload = {0};
7971         uint64_t csa_addr;
7972         int cnt;
7973
7974         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7975         csa_addr = amdgpu_csa_vaddr(ring->adev);
7976
7977         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7978         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7979                                  WRITE_DATA_DST_SEL(8) |
7980                                  WR_CONFIRM) |
7981                                  WRITE_DATA_CACHE_POLICY(0));
7982         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7983                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7984         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7985                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7986
7987         if (resume)
7988                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7989                                            offsetof(struct v10_gfx_meta_data,
7990                                                     ce_payload),
7991                                            sizeof(ce_payload) >> 2);
7992         else
7993                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
7994                                            sizeof(ce_payload) >> 2);
7995 }
7996
7997 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
7998 {
7999         struct amdgpu_device *adev = ring->adev;
8000         struct v10_de_ib_state de_payload = {0};
8001         uint64_t csa_addr, gds_addr;
8002         int cnt;
8003
8004         csa_addr = amdgpu_csa_vaddr(ring->adev);
8005         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8006                          PAGE_SIZE);
8007         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8008         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8009
8010         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8011         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8012         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8013                                  WRITE_DATA_DST_SEL(8) |
8014                                  WR_CONFIRM) |
8015                                  WRITE_DATA_CACHE_POLICY(0));
8016         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8017                               offsetof(struct v10_gfx_meta_data, de_payload)));
8018         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8019                               offsetof(struct v10_gfx_meta_data, de_payload)));
8020
8021         if (resume)
8022                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8023                                            offsetof(struct v10_gfx_meta_data,
8024                                                     de_payload),
8025                                            sizeof(de_payload) >> 2);
8026         else
8027                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8028                                            sizeof(de_payload) >> 2);
8029 }
8030
8031 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8032                                     bool secure)
8033 {
8034         uint32_t v = secure ? FRAME_TMZ : 0;
8035
8036         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8037         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8038 }
8039
8040 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8041                                      uint32_t reg_val_offs)
8042 {
8043         struct amdgpu_device *adev = ring->adev;
8044
8045         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8046         amdgpu_ring_write(ring, 0 |     /* src: register*/
8047                                 (5 << 8) |      /* dst: memory */
8048                                 (1 << 20));     /* write confirm */
8049         amdgpu_ring_write(ring, reg);
8050         amdgpu_ring_write(ring, 0);
8051         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8052                                 reg_val_offs * 4));
8053         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8054                                 reg_val_offs * 4));
8055 }
8056
8057 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8058                                    uint32_t val)
8059 {
8060         uint32_t cmd = 0;
8061
8062         switch (ring->funcs->type) {
8063         case AMDGPU_RING_TYPE_GFX:
8064                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8065                 break;
8066         case AMDGPU_RING_TYPE_KIQ:
8067                 cmd = (1 << 16); /* no inc addr */
8068                 break;
8069         default:
8070                 cmd = WR_CONFIRM;
8071                 break;
8072         }
8073         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8074         amdgpu_ring_write(ring, cmd);
8075         amdgpu_ring_write(ring, reg);
8076         amdgpu_ring_write(ring, 0);
8077         amdgpu_ring_write(ring, val);
8078 }
8079
8080 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8081                                         uint32_t val, uint32_t mask)
8082 {
8083         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8084 }
8085
8086 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8087                                                    uint32_t reg0, uint32_t reg1,
8088                                                    uint32_t ref, uint32_t mask)
8089 {
8090         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8091         struct amdgpu_device *adev = ring->adev;
8092         bool fw_version_ok = false;
8093
8094         fw_version_ok = adev->gfx.cp_fw_write_wait;
8095
8096         if (fw_version_ok)
8097                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8098                                        ref, mask, 0x20);
8099         else
8100                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8101                                                            ref, mask);
8102 }
8103
8104 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8105                                          unsigned vmid)
8106 {
8107         struct amdgpu_device *adev = ring->adev;
8108         uint32_t value = 0;
8109
8110         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8111         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8112         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8113         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8114         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8115 }
8116
8117 static void
8118 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8119                                       uint32_t me, uint32_t pipe,
8120                                       enum amdgpu_interrupt_state state)
8121 {
8122         uint32_t cp_int_cntl, cp_int_cntl_reg;
8123
8124         if (!me) {
8125                 switch (pipe) {
8126                 case 0:
8127                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8128                         break;
8129                 case 1:
8130                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8131                         break;
8132                 default:
8133                         DRM_DEBUG("invalid pipe %d\n", pipe);
8134                         return;
8135                 }
8136         } else {
8137                 DRM_DEBUG("invalid me %d\n", me);
8138                 return;
8139         }
8140
8141         switch (state) {
8142         case AMDGPU_IRQ_STATE_DISABLE:
8143                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8144                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8145                                             TIME_STAMP_INT_ENABLE, 0);
8146                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8147                 break;
8148         case AMDGPU_IRQ_STATE_ENABLE:
8149                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8150                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8151                                             TIME_STAMP_INT_ENABLE, 1);
8152                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8153                 break;
8154         default:
8155                 break;
8156         }
8157 }
8158
8159 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8160                                                      int me, int pipe,
8161                                                      enum amdgpu_interrupt_state state)
8162 {
8163         u32 mec_int_cntl, mec_int_cntl_reg;
8164
8165         /*
8166          * amdgpu controls only the first MEC. That's why this function only
8167          * handles the setting of interrupts for this specific MEC. All other
8168          * pipes' interrupts are set by amdkfd.
8169          */
8170
8171         if (me == 1) {
8172                 switch (pipe) {
8173                 case 0:
8174                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8175                         break;
8176                 case 1:
8177                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8178                         break;
8179                 case 2:
8180                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8181                         break;
8182                 case 3:
8183                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8184                         break;
8185                 default:
8186                         DRM_DEBUG("invalid pipe %d\n", pipe);
8187                         return;
8188                 }
8189         } else {
8190                 DRM_DEBUG("invalid me %d\n", me);
8191                 return;
8192         }
8193
8194         switch (state) {
8195         case AMDGPU_IRQ_STATE_DISABLE:
8196                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8197                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8198                                              TIME_STAMP_INT_ENABLE, 0);
8199                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8200                 break;
8201         case AMDGPU_IRQ_STATE_ENABLE:
8202                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8203                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8204                                              TIME_STAMP_INT_ENABLE, 1);
8205                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8206                 break;
8207         default:
8208                 break;
8209         }
8210 }
8211
8212 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8213                                             struct amdgpu_irq_src *src,
8214                                             unsigned type,
8215                                             enum amdgpu_interrupt_state state)
8216 {
8217         switch (type) {
8218         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8219                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8220                 break;
8221         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8222                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8223                 break;
8224         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8225                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8226                 break;
8227         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8228                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8229                 break;
8230         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8231                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8232                 break;
8233         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8234                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8235                 break;
8236         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8237                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8238                 break;
8239         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8240                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8241                 break;
8242         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8243                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8244                 break;
8245         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8246                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8247                 break;
8248         default:
8249                 break;
8250         }
8251         return 0;
8252 }
8253
8254 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8255                              struct amdgpu_irq_src *source,
8256                              struct amdgpu_iv_entry *entry)
8257 {
8258         int i;
8259         u8 me_id, pipe_id, queue_id;
8260         struct amdgpu_ring *ring;
8261
8262         DRM_DEBUG("IH: CP EOP\n");
8263         me_id = (entry->ring_id & 0x0c) >> 2;
8264         pipe_id = (entry->ring_id & 0x03) >> 0;
8265         queue_id = (entry->ring_id & 0x70) >> 4;
8266
8267         switch (me_id) {
8268         case 0:
8269                 if (pipe_id == 0)
8270                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8271                 else
8272                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8273                 break;
8274         case 1:
8275         case 2:
8276                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8277                         ring = &adev->gfx.compute_ring[i];
8278                         /* Per-queue interrupt is supported for MEC starting from VI.
8279                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8280                           */
8281                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8282                                 amdgpu_fence_process(ring);
8283                 }
8284                 break;
8285         }
8286         return 0;
8287 }
8288
8289 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8290                                               struct amdgpu_irq_src *source,
8291                                               unsigned type,
8292                                               enum amdgpu_interrupt_state state)
8293 {
8294         switch (state) {
8295         case AMDGPU_IRQ_STATE_DISABLE:
8296         case AMDGPU_IRQ_STATE_ENABLE:
8297                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8298                                PRIV_REG_INT_ENABLE,
8299                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8300                 break;
8301         default:
8302                 break;
8303         }
8304
8305         return 0;
8306 }
8307
8308 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8309                                                struct amdgpu_irq_src *source,
8310                                                unsigned type,
8311                                                enum amdgpu_interrupt_state state)
8312 {
8313         switch (state) {
8314         case AMDGPU_IRQ_STATE_DISABLE:
8315         case AMDGPU_IRQ_STATE_ENABLE:
8316                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8317                                PRIV_INSTR_INT_ENABLE,
8318                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8319         default:
8320                 break;
8321         }
8322
8323         return 0;
8324 }
8325
8326 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8327                                         struct amdgpu_iv_entry *entry)
8328 {
8329         u8 me_id, pipe_id, queue_id;
8330         struct amdgpu_ring *ring;
8331         int i;
8332
8333         me_id = (entry->ring_id & 0x0c) >> 2;
8334         pipe_id = (entry->ring_id & 0x03) >> 0;
8335         queue_id = (entry->ring_id & 0x70) >> 4;
8336
8337         switch (me_id) {
8338         case 0:
8339                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8340                         ring = &adev->gfx.gfx_ring[i];
8341                         /* we only enabled 1 gfx queue per pipe for now */
8342                         if (ring->me == me_id && ring->pipe == pipe_id)
8343                                 drm_sched_fault(&ring->sched);
8344                 }
8345                 break;
8346         case 1:
8347         case 2:
8348                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8349                         ring = &adev->gfx.compute_ring[i];
8350                         if (ring->me == me_id && ring->pipe == pipe_id &&
8351                             ring->queue == queue_id)
8352                                 drm_sched_fault(&ring->sched);
8353                 }
8354                 break;
8355         default:
8356                 BUG();
8357         }
8358 }
8359
8360 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8361                                   struct amdgpu_irq_src *source,
8362                                   struct amdgpu_iv_entry *entry)
8363 {
8364         DRM_ERROR("Illegal register access in command stream\n");
8365         gfx_v10_0_handle_priv_fault(adev, entry);
8366         return 0;
8367 }
8368
8369 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8370                                    struct amdgpu_irq_src *source,
8371                                    struct amdgpu_iv_entry *entry)
8372 {
8373         DRM_ERROR("Illegal instruction in command stream\n");
8374         gfx_v10_0_handle_priv_fault(adev, entry);
8375         return 0;
8376 }
8377
8378 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8379                                              struct amdgpu_irq_src *src,
8380                                              unsigned int type,
8381                                              enum amdgpu_interrupt_state state)
8382 {
8383         uint32_t tmp, target;
8384         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8385
8386         if (ring->me == 1)
8387                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8388         else
8389                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8390         target += ring->pipe;
8391
8392         switch (type) {
8393         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8394                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8395                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8396                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8397                                             GENERIC2_INT_ENABLE, 0);
8398                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8399
8400                         tmp = RREG32(target);
8401                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8402                                             GENERIC2_INT_ENABLE, 0);
8403                         WREG32(target, tmp);
8404                 } else {
8405                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8406                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8407                                             GENERIC2_INT_ENABLE, 1);
8408                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8409
8410                         tmp = RREG32(target);
8411                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8412                                             GENERIC2_INT_ENABLE, 1);
8413                         WREG32(target, tmp);
8414                 }
8415                 break;
8416         default:
8417                 BUG(); /* kiq only support GENERIC2_INT now */
8418                 break;
8419         }
8420         return 0;
8421 }
8422
8423 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8424                              struct amdgpu_irq_src *source,
8425                              struct amdgpu_iv_entry *entry)
8426 {
8427         u8 me_id, pipe_id, queue_id;
8428         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8429
8430         me_id = (entry->ring_id & 0x0c) >> 2;
8431         pipe_id = (entry->ring_id & 0x03) >> 0;
8432         queue_id = (entry->ring_id & 0x70) >> 4;
8433         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8434                    me_id, pipe_id, queue_id);
8435
8436         amdgpu_fence_process(ring);
8437         return 0;
8438 }
8439
8440 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8441 {
8442         const unsigned int gcr_cntl =
8443                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8444                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8445                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8446                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8447                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8448                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8449                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8450                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8451
8452         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8453         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8454         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8455         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8456         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8457         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8458         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8459         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8460         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8461 }
8462
8463 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8464         .name = "gfx_v10_0",
8465         .early_init = gfx_v10_0_early_init,
8466         .late_init = gfx_v10_0_late_init,
8467         .sw_init = gfx_v10_0_sw_init,
8468         .sw_fini = gfx_v10_0_sw_fini,
8469         .hw_init = gfx_v10_0_hw_init,
8470         .hw_fini = gfx_v10_0_hw_fini,
8471         .suspend = gfx_v10_0_suspend,
8472         .resume = gfx_v10_0_resume,
8473         .is_idle = gfx_v10_0_is_idle,
8474         .wait_for_idle = gfx_v10_0_wait_for_idle,
8475         .soft_reset = gfx_v10_0_soft_reset,
8476         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8477         .set_powergating_state = gfx_v10_0_set_powergating_state,
8478         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8479 };
8480
8481 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8482         .type = AMDGPU_RING_TYPE_GFX,
8483         .align_mask = 0xff,
8484         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8485         .support_64bit_ptrs = true,
8486         .vmhub = AMDGPU_GFXHUB_0,
8487         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8488         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8489         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8490         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8491                 5 + /* COND_EXEC */
8492                 7 + /* PIPELINE_SYNC */
8493                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8494                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8495                 2 + /* VM_FLUSH */
8496                 8 + /* FENCE for VM_FLUSH */
8497                 20 + /* GDS switch */
8498                 4 + /* double SWITCH_BUFFER,
8499                      * the first COND_EXEC jump to the place
8500                      * just prior to this double SWITCH_BUFFER
8501                      */
8502                 5 + /* COND_EXEC */
8503                 7 + /* HDP_flush */
8504                 4 + /* VGT_flush */
8505                 14 + /* CE_META */
8506                 31 + /* DE_META */
8507                 3 + /* CNTX_CTRL */
8508                 5 + /* HDP_INVL */
8509                 8 + 8 + /* FENCE x2 */
8510                 2 + /* SWITCH_BUFFER */
8511                 8, /* gfx_v10_0_emit_mem_sync */
8512         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8513         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8514         .emit_fence = gfx_v10_0_ring_emit_fence,
8515         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8516         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8517         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8518         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8519         .test_ring = gfx_v10_0_ring_test_ring,
8520         .test_ib = gfx_v10_0_ring_test_ib,
8521         .insert_nop = amdgpu_ring_insert_nop,
8522         .pad_ib = amdgpu_ring_generic_pad_ib,
8523         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8524         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8525         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8526         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8527         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8528         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8529         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8530         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8531         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8532         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8533         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8534 };
8535
8536 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8537         .type = AMDGPU_RING_TYPE_COMPUTE,
8538         .align_mask = 0xff,
8539         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8540         .support_64bit_ptrs = true,
8541         .vmhub = AMDGPU_GFXHUB_0,
8542         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8543         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8544         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8545         .emit_frame_size =
8546                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8547                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8548                 5 + /* hdp invalidate */
8549                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8550                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8551                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8552                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8553                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8554                 8, /* gfx_v10_0_emit_mem_sync */
8555         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8556         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8557         .emit_fence = gfx_v10_0_ring_emit_fence,
8558         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8559         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8560         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8561         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8562         .test_ring = gfx_v10_0_ring_test_ring,
8563         .test_ib = gfx_v10_0_ring_test_ib,
8564         .insert_nop = amdgpu_ring_insert_nop,
8565         .pad_ib = amdgpu_ring_generic_pad_ib,
8566         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8567         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8568         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8569         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8570 };
8571
8572 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8573         .type = AMDGPU_RING_TYPE_KIQ,
8574         .align_mask = 0xff,
8575         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8576         .support_64bit_ptrs = true,
8577         .vmhub = AMDGPU_GFXHUB_0,
8578         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8579         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8580         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8581         .emit_frame_size =
8582                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8583                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8584                 5 + /*hdp invalidate */
8585                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8586                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8587                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8588                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8589                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8590         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8591         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8592         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8593         .test_ring = gfx_v10_0_ring_test_ring,
8594         .test_ib = gfx_v10_0_ring_test_ib,
8595         .insert_nop = amdgpu_ring_insert_nop,
8596         .pad_ib = amdgpu_ring_generic_pad_ib,
8597         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8598         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8599         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8600         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8601 };
8602
8603 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8604 {
8605         int i;
8606
8607         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8608
8609         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8610                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8611
8612         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8613                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8614 }
8615
8616 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8617         .set = gfx_v10_0_set_eop_interrupt_state,
8618         .process = gfx_v10_0_eop_irq,
8619 };
8620
8621 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8622         .set = gfx_v10_0_set_priv_reg_fault_state,
8623         .process = gfx_v10_0_priv_reg_irq,
8624 };
8625
8626 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8627         .set = gfx_v10_0_set_priv_inst_fault_state,
8628         .process = gfx_v10_0_priv_inst_irq,
8629 };
8630
8631 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8632         .set = gfx_v10_0_kiq_set_interrupt_state,
8633         .process = gfx_v10_0_kiq_irq,
8634 };
8635
8636 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8637 {
8638         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8639         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8640
8641         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8642         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8643
8644         adev->gfx.priv_reg_irq.num_types = 1;
8645         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8646
8647         adev->gfx.priv_inst_irq.num_types = 1;
8648         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8649 }
8650
8651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8652 {
8653         switch (adev->asic_type) {
8654         case CHIP_NAVI10:
8655         case CHIP_NAVI14:
8656         case CHIP_SIENNA_CICHLID:
8657         case CHIP_NAVY_FLOUNDER:
8658                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8659                 break;
8660         case CHIP_NAVI12:
8661                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8662                 break;
8663         default:
8664                 break;
8665         }
8666 }
8667
8668 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8669 {
8670         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8671                             adev->gfx.config.max_sh_per_se *
8672                             adev->gfx.config.max_shader_engines;
8673
8674         adev->gds.gds_size = 0x10000;
8675         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8676         adev->gds.gws_size = 64;
8677         adev->gds.oa_size = 16;
8678 }
8679
8680 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8681                                                           u32 bitmap)
8682 {
8683         u32 data;
8684
8685         if (!bitmap)
8686                 return;
8687
8688         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8689         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8690
8691         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8692 }
8693
8694 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8695 {
8696         u32 data, wgp_bitmask;
8697         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8698         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8699
8700         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8701         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8702
8703         wgp_bitmask =
8704                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8705
8706         return (~data) & wgp_bitmask;
8707 }
8708
8709 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8710 {
8711         u32 wgp_idx, wgp_active_bitmap;
8712         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8713
8714         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8715         cu_active_bitmap = 0;
8716
8717         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8718                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8719                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8720                 if (wgp_active_bitmap & (1 << wgp_idx))
8721                         cu_active_bitmap |= cu_bitmap_per_wgp;
8722         }
8723
8724         return cu_active_bitmap;
8725 }
8726
8727 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8728                                  struct amdgpu_cu_info *cu_info)
8729 {
8730         int i, j, k, counter, active_cu_number = 0;
8731         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8732         unsigned disable_masks[4 * 2];
8733
8734         if (!adev || !cu_info)
8735                 return -EINVAL;
8736
8737         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8738
8739         mutex_lock(&adev->grbm_idx_mutex);
8740         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8741                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8742                         mask = 1;
8743                         ao_bitmap = 0;
8744                         counter = 0;
8745                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8746                         if (i < 4 && j < 2)
8747                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8748                                         adev, disable_masks[i * 2 + j]);
8749                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8750                         cu_info->bitmap[i][j] = bitmap;
8751
8752                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8753                                 if (bitmap & mask) {
8754                                         if (counter < adev->gfx.config.max_cu_per_sh)
8755                                                 ao_bitmap |= mask;
8756                                         counter++;
8757                                 }
8758                                 mask <<= 1;
8759                         }
8760                         active_cu_number += counter;
8761                         if (i < 2 && j < 2)
8762                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8763                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8764                 }
8765         }
8766         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8767         mutex_unlock(&adev->grbm_idx_mutex);
8768
8769         cu_info->number = active_cu_number;
8770         cu_info->ao_cu_mask = ao_cu_mask;
8771         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8772
8773         return 0;
8774 }
8775
8776 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8777 {
8778         .type = AMD_IP_BLOCK_TYPE_GFX,
8779         .major = 10,
8780         .minor = 0,
8781         .rev = 0,
8782         .funcs = &gfx_v10_0_ip_funcs,
8783 };