drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_syncobj.h>
  34 #include "amdgpu.h"
  35 #include "amdgpu_trace.h"
  36 #include "amdgpu_gmc.h"
  37 #include "amdgpu_gem.h"
  38 #include "amdgpu_ras.h"
  39
  40 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  41                                       struct drm_amdgpu_cs_chunk_fence *data,
  42                                       uint32_t *offset)
  43 {
  44         struct drm_gem_object *gobj;
  45         struct amdgpu_bo *bo;
  46         unsigned long size;
  47         int r;
  48
  49         gobj = drm_gem_object_lookup(p->filp, data->handle);
  50         if (gobj == NULL)
  51                 return -EINVAL;
  52
  53         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  54         p->uf_entry.priority = 0;
  55         p->uf_entry.tv.bo = &bo->tbo;
  56         /* One for TTM and one for the CS job */
  57         p->uf_entry.tv.num_shared = 2;
  58
  59         drm_gem_object_put_unlocked(gobj);
  60
  61         size = amdgpu_bo_size(bo);
  62         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  63                 r = -EINVAL;
  64                 goto error_unref;
  65         }
  66
  67         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  68                 r = -EINVAL;
  69                 goto error_unref;
  70         }
  71
  72         *offset = data->offset;
  73
  74         return 0;
  75
  76 error_unref:
  77         amdgpu_bo_unref(&bo);
  78         return r;
  79 }
  80
  81 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  82                                       struct drm_amdgpu_bo_list_in *data)
  83 {
  84         int r;
  85         struct drm_amdgpu_bo_list_entry *info = NULL;
  86
  87         r = amdgpu_bo_create_list_entry_array(data, &info);
  88         if (r)
  89                 return r;
  90
  91         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  92                                   &p->bo_list);
  93         if (r)
  94                 goto error_free;
  95
  96         kvfree(info);
  97         return 0;
  98
  99 error_free:
 100         if (info)
 101                 kvfree(info);
 102
 103         return r;
 104 }
 105
 106 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 107 {
 108         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 109         struct amdgpu_vm *vm = &fpriv->vm;
 110         uint64_t *chunk_array_user;
 111         uint64_t *chunk_array;
 112         unsigned size, num_ibs = 0;
 113         uint32_t uf_offset = 0;
 114         int i;
 115         int ret;
 116
 117         if (cs->in.num_chunks == 0)
 118                 return 0;
 119
 120         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 121         if (!chunk_array)
 122                 return -ENOMEM;
 123
 124         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 125         if (!p->ctx) {
 126                 ret = -EINVAL;
 127                 goto free_chunk;
 128         }
 129
 130         mutex_lock(&p->ctx->lock);
 131
 132         /* skip guilty context job */
 133         if (atomic_read(&p->ctx->guilty) == 1) {
 134                 ret = -ECANCELED;
 135                 goto free_chunk;
 136         }
 137
 138         /* get chunks */
 139         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 140         if (copy_from_user(chunk_array, chunk_array_user,
 141                            sizeof(uint64_t)*cs->in.num_chunks)) {
 142                 ret = -EFAULT;
 143                 goto free_chunk;
 144         }
 145
 146         p->nchunks = cs->in.num_chunks;
 147         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 148                             GFP_KERNEL);
 149         if (!p->chunks) {
 150                 ret = -ENOMEM;
 151                 goto free_chunk;
 152         }
 153
 154         for (i = 0; i < p->nchunks; i++) {
 155                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 156                 struct drm_amdgpu_cs_chunk user_chunk;
 157                 uint32_t __user *cdata;
 158
 159                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 160                 if (copy_from_user(&user_chunk, chunk_ptr,
 161                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 162                         ret = -EFAULT;
 163                         i--;
 164                         goto free_partial_kdata;
 165                 }
 166                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 167                 p->chunks[i].length_dw = user_chunk.length_dw;
 168
 169                 size = p->chunks[i].length_dw;
 170                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 171
 172                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 173                 if (p->chunks[i].kdata == NULL) {
 174                         ret = -ENOMEM;
 175                         i--;
 176                         goto free_partial_kdata;
 177                 }
 178                 size *= sizeof(uint32_t);
 179                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 180                         ret = -EFAULT;
 181                         goto free_partial_kdata;
 182                 }
 183
 184                 switch (p->chunks[i].chunk_id) {
 185                 case AMDGPU_CHUNK_ID_IB:
 186                         ++num_ibs;
 187                         break;
 188
 189                 case AMDGPU_CHUNK_ID_FENCE:
 190                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 191                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 192                                 ret = -EINVAL;
 193                                 goto free_partial_kdata;
 194                         }
 195
 196                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 197                                                          &uf_offset);
 198                         if (ret)
 199                                 goto free_partial_kdata;
 200
 201                         break;
 202
 203                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 204                         size = sizeof(struct drm_amdgpu_bo_list_in);
 205                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 206                                 ret = -EINVAL;
 207                                 goto free_partial_kdata;
 208                         }
 209
 210                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 211                         if (ret)
 212                                 goto free_partial_kdata;
 213
 214                         break;
 215
 216                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 218                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 219                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 221                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 222                         break;
 223
 224                 default:
 225                         ret = -EINVAL;
 226                         goto free_partial_kdata;
 227                 }
 228         }
 229
 230         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 231         if (ret)
 232                 goto free_all_kdata;
 233
 234         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 235                 ret = -ECANCELED;
 236                 goto free_all_kdata;
 237         }
 238
 239         if (p->uf_entry.tv.bo)
 240                 p->job->uf_addr = uf_offset;
 241         kfree(chunk_array);
 242
 243         /* Use this opportunity to fill in task info for the vm */
 244         amdgpu_vm_set_task_info(vm);
 245
 246         return 0;
 247
 248 free_all_kdata:
 249         i = p->nchunks - 1;
 250 free_partial_kdata:
 251         for (; i >= 0; i--)
 252                 kvfree(p->chunks[i].kdata);
 253         kfree(p->chunks);
 254         p->chunks = NULL;
 255         p->nchunks = 0;
 256 free_chunk:
 257         kfree(chunk_array);
 258
 259         return ret;
 260 }
 261
 262 /* Convert microseconds to bytes. */
 263 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 264 {
 265         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 266                 return 0;
 267
 268         /* Since accum_us is incremented by a million per second, just
 269          * multiply it by the number of MB/s to get the number of bytes.
 270          */
 271         return us << adev->mm_stats.log2_max_MBps;
 272 }
 273
 274 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 275 {
 276         if (!adev->mm_stats.log2_max_MBps)
 277                 return 0;
 278
 279         return bytes >> adev->mm_stats.log2_max_MBps;
 280 }
 281
 282 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 283  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 284  * which means it can go over the threshold once. If that happens, the driver
 285  * will be in debt and no other buffer migrations can be done until that debt
 286  * is repaid.
 287  *
 288  * This approach allows moving a buffer of any size (it's important to allow
 289  * that).
 290  *
 291  * The currency is simply time in microseconds and it increases as the clock
 292  * ticks. The accumulated microseconds (us) are converted to bytes and
 293  * returned.
 294  */
 295 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 296                                               u64 *max_bytes,
 297                                               u64 *max_vis_bytes)
 298 {
 299         s64 time_us, increment_us;
 300         u64 free_vram, total_vram, used_vram;
 301
 302         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 303          * throttling.
 304          *
 305          * It means that in order to get full max MBps, at least 5 IBs per
 306          * second must be submitted and not more than 200ms apart from each
 307          * other.
 308          */
 309         const s64 us_upper_bound = 200000;
 310
 311         if (!adev->mm_stats.log2_max_MBps) {
 312                 *max_bytes = 0;
 313                 *max_vis_bytes = 0;
 314                 return;
 315         }
 316
 317         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 318         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 319         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 320
 321         spin_lock(&adev->mm_stats.lock);
 322
 323         /* Increase the amount of accumulated us. */
 324         time_us = ktime_to_us(ktime_get());
 325         increment_us = time_us - adev->mm_stats.last_update_us;
 326         adev->mm_stats.last_update_us = time_us;
 327         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 328                                       us_upper_bound);
 329
 330         /* This prevents the short period of low performance when the VRAM
 331          * usage is low and the driver is in debt or doesn't have enough
 332          * accumulated us to fill VRAM quickly.
 333          *
 334          * The situation can occur in these cases:
 335          * - a lot of VRAM is freed by userspace
 336          * - the presence of a big buffer causes a lot of evictions
 337          *   (solution: split buffers into smaller ones)
 338          *
 339          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 340          * accum_us to a positive number.
 341          */
 342         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 343                 s64 min_us;
 344
 345                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 346                  * VRAM now.
 347                  */
 348                 if (!(adev->flags & AMD_IS_APU))
 349                         min_us = bytes_to_us(adev, free_vram / 4);
 350                 else
 351                         min_us = 0; /* Reset accum_us on APUs. */
 352
 353                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 354         }
 355
 356         /* This is set to 0 if the driver is in debt to disallow (optional)
 357          * buffer moves.
 358          */
 359         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 360
 361         /* Do the same for visible VRAM if half of it is free */
 362         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 363                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 364                 u64 used_vis_vram =
 365                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 366
 367                 if (used_vis_vram < total_vis_vram) {
 368                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 369                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 370                                                           increment_us, us_upper_bound);
 371
 372                         if (free_vis_vram >= total_vis_vram / 2)
 373                                 adev->mm_stats.accum_us_vis =
 374                                         max(bytes_to_us(adev, free_vis_vram / 2),
 375                                             adev->mm_stats.accum_us_vis);
 376                 }
 377
 378                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 379         } else {
 380                 *max_vis_bytes = 0;
 381         }
 382
 383         spin_unlock(&adev->mm_stats.lock);
 384 }
 385
 386 /* Report how many bytes have really been moved for the last command
 387  * submission. This can result in a debt that can stop buffer migrations
 388  * temporarily.
 389  */
 390 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 391                                   u64 num_vis_bytes)
 392 {
 393         spin_lock(&adev->mm_stats.lock);
 394         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 395         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 396         spin_unlock(&adev->mm_stats.lock);
 397 }
 398
 399 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 400                                  struct amdgpu_bo *bo)
 401 {
 402         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 403         struct ttm_operation_ctx ctx = {
 404                 .interruptible = true,
 405                 .no_wait_gpu = false,
 406                 .resv = bo->tbo.base.resv,
 407                 .flags = 0
 408         };
 409         uint32_t domain;
 410         int r;
 411
 412         if (bo->pin_count)
 413                 return 0;
 414
 415         /* Don't move this buffer if we have depleted our allowance
 416          * to move it. Don't move anything if the threshold is zero.
 417          */
 418         if (p->bytes_moved < p->bytes_moved_threshold) {
 419                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 420                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 421                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 422                          * visible VRAM if we've depleted our allowance to do
 423                          * that.
 424                          */
 425                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 426                                 domain = bo->preferred_domains;
 427                         else
 428                                 domain = bo->allowed_domains;
 429                 } else {
 430                         domain = bo->preferred_domains;
 431                 }
 432         } else {
 433                 domain = bo->allowed_domains;
 434         }
 435
 436 retry:
 437         amdgpu_bo_placement_from_domain(bo, domain);
 438         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 439
 440         p->bytes_moved += ctx.bytes_moved;
 441         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 442             amdgpu_bo_in_cpu_visible_vram(bo))
 443                 p->bytes_moved_vis += ctx.bytes_moved;
 444
 445         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 446                 domain = bo->allowed_domains;
 447                 goto retry;
 448         }
 449
 450         return r;
 451 }
 452
 453 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 454 {
 455         struct amdgpu_cs_parser *p = param;
 456         int r;
 457
 458         r = amdgpu_cs_bo_validate(p, bo);
 459         if (r)
 460                 return r;
 461
 462         if (bo->shadow)
 463                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 464
 465         return r;
 466 }
 467
 468 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 469                             struct list_head *validated)
 470 {
 471         struct ttm_operation_ctx ctx = { true, false };
 472         struct amdgpu_bo_list_entry *lobj;
 473         int r;
 474
 475         list_for_each_entry(lobj, validated, tv.head) {
 476                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 477                 struct mm_struct *usermm;
 478
 479                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 480                 if (usermm && usermm != current->mm)
 481                         return -EPERM;
 482
 483                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 484                     lobj->user_invalidated && lobj->user_pages) {
 485                         amdgpu_bo_placement_from_domain(bo,
 486                                                         AMDGPU_GEM_DOMAIN_CPU);
 487                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 488                         if (r)
 489                                 return r;
 490
 491                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 492                                                      lobj->user_pages);
 493                 }
 494
 495                 r = amdgpu_cs_validate(p, bo);
 496                 if (r)
 497                         return r;
 498
 499                 kvfree(lobj->user_pages);
 500                 lobj->user_pages = NULL;
 501         }
 502         return 0;
 503 }
 504
 505 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 506                                 union drm_amdgpu_cs *cs)
 507 {
 508         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 509         struct amdgpu_vm *vm = &fpriv->vm;
 510         struct amdgpu_bo_list_entry *e;
 511         struct list_head duplicates;
 512         struct amdgpu_bo *gds;
 513         struct amdgpu_bo *gws;
 514         struct amdgpu_bo *oa;
 515         int r;
 516
 517         INIT_LIST_HEAD(&p->validated);
 518
 519         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 520         if (cs->in.bo_list_handle) {
 521                 if (p->bo_list)
 522                         return -EINVAL;
 523
 524                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 525                                        &p->bo_list);
 526                 if (r)
 527                         return r;
 528         } else if (!p->bo_list) {
 529                 /* Create a empty bo_list when no handle is provided */
 530                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 531                                           &p->bo_list);
 532                 if (r)
 533                         return r;
 534         }
 535
 536         /* One for TTM and one for the CS job */
 537         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 538                 e->tv.num_shared = 2;
 539
 540         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 541         if (p->bo_list->first_userptr != p->bo_list->num_entries)
 542                 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 543
 544         INIT_LIST_HEAD(&duplicates);
 545         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 546
 547         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 548                 list_add(&p->uf_entry.tv.head, &p->validated);
 549
 550         /* Get userptr backing pages. If pages are updated after registered
 551          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 552          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 553          */
 554         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 555                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 556                 bool userpage_invalidated = false;
 557                 int i;
 558
 559                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 560                                         sizeof(struct page *),
 561                                         GFP_KERNEL | __GFP_ZERO);
 562                 if (!e->user_pages) {
 563                         DRM_ERROR("calloc failure\n");
 564                         return -ENOMEM;
 565                 }
 566
 567                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 568                 if (r) {
 569                         kvfree(e->user_pages);
 570                         e->user_pages = NULL;
 571                         return r;
 572                 }
 573
 574                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 575                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 576                                 userpage_invalidated = true;
 577                                 break;
 578                         }
 579                 }
 580                 e->user_invalidated = userpage_invalidated;
 581         }
 582
 583         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 584                                    &duplicates);
 585         if (unlikely(r != 0)) {
 586                 if (r != -ERESTARTSYS)
 587                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 588                 goto out;
 589         }
 590
 591         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 592                                           &p->bytes_moved_vis_threshold);
 593         p->bytes_moved = 0;
 594         p->bytes_moved_vis = 0;
 595
 596         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 597                                       amdgpu_cs_validate, p);
 598         if (r) {
 599                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 600                 goto error_validate;
 601         }
 602
 603         r = amdgpu_cs_list_validate(p, &duplicates);
 604         if (r)
 605                 goto error_validate;
 606
 607         r = amdgpu_cs_list_validate(p, &p->validated);
 608         if (r)
 609                 goto error_validate;
 610
 611         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 612                                      p->bytes_moved_vis);
 613
 614         gds = p->bo_list->gds_obj;
 615         gws = p->bo_list->gws_obj;
 616         oa = p->bo_list->oa_obj;
 617
 618         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 619                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 620
 621                 /* Make sure we use the exclusive slot for shared BOs */
 622                 if (bo->prime_shared_count)
 623                         e->tv.num_shared = 0;
 624                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 625         }
 626
 627         if (gds) {
 628                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 629                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 630         }
 631         if (gws) {
 632                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 633                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 634         }
 635         if (oa) {
 636                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 637                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 638         }
 639
 640         if (!r && p->uf_entry.tv.bo) {
 641                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 642
 643                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 644                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 645         }
 646
 647 error_validate:
 648         if (r)
 649                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 650 out:
 651         return r;
 652 }
 653
 654 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 655 {
 656         struct amdgpu_bo_list_entry *e;
 657         int r;
 658
 659         list_for_each_entry(e, &p->validated, tv.head) {
 660                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 661                 struct dma_resv *resv = bo->tbo.base.resv;
 662
 663                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 664                                      amdgpu_bo_explicit_sync(bo));
 665
 666                 if (r)
 667                         return r;
 668         }
 669         return 0;
 670 }
 671
 672 /**
 673  * cs_parser_fini() - clean parser states
 674  * @parser:     parser structure holding parsing context.
 675  * @error:      error number
 676  *
 677  * If error is set than unvalidate buffer, otherwise just free memory
 678  * used by parsing context.
 679  **/
 680 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 681                                   bool backoff)
 682 {
 683         unsigned i;
 684
 685         if (error && backoff)
 686                 ttm_eu_backoff_reservation(&parser->ticket,
 687                                            &parser->validated);
 688
 689         for (i = 0; i < parser->num_post_deps; i++) {
 690                 drm_syncobj_put(parser->post_deps[i].syncobj);
 691                 kfree(parser->post_deps[i].chain);
 692         }
 693         kfree(parser->post_deps);
 694
 695         dma_fence_put(parser->fence);
 696
 697         if (parser->ctx) {
 698                 mutex_unlock(&parser->ctx->lock);
 699                 amdgpu_ctx_put(parser->ctx);
 700         }
 701         if (parser->bo_list)
 702                 amdgpu_bo_list_put(parser->bo_list);
 703
 704         for (i = 0; i < parser->nchunks; i++)
 705                 kvfree(parser->chunks[i].kdata);
 706         kfree(parser->chunks);
 707         if (parser->job)
 708                 amdgpu_job_free(parser->job);
 709         if (parser->uf_entry.tv.bo) {
 710                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 711
 712                 amdgpu_bo_unref(&uf);
 713         }
 714 }
 715
 716 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 717 {
 718         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 719         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 720         struct amdgpu_device *adev = p->adev;
 721         struct amdgpu_vm *vm = &fpriv->vm;
 722         struct amdgpu_bo_list_entry *e;
 723         struct amdgpu_bo_va *bo_va;
 724         struct amdgpu_bo *bo;
 725         int r;
 726
 727         /* Only for UVD/VCE VM emulation */
 728         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 729                 unsigned i, j;
 730
 731                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 732                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 733                         struct amdgpu_bo_va_mapping *m;
 734                         struct amdgpu_bo *aobj = NULL;
 735                         struct amdgpu_cs_chunk *chunk;
 736                         uint64_t offset, va_start;
 737                         struct amdgpu_ib *ib;
 738                         uint8_t *kptr;
 739
 740                         chunk = &p->chunks[i];
 741                         ib = &p->job->ibs[j];
 742                         chunk_ib = chunk->kdata;
 743
 744                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 745                                 continue;
 746
 747                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 748                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 749                         if (r) {
 750                                 DRM_ERROR("IB va_start is invalid\n");
 751                                 return r;
 752                         }
 753
 754                         if ((va_start + chunk_ib->ib_bytes) >
 755                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 756                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 757                                 return -EINVAL;
 758                         }
 759
 760                         /* the IB should be reserved at this point */
 761                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 762                         if (r) {
 763                                 return r;
 764                         }
 765
 766                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 767                         kptr += va_start - offset;
 768
 769                         if (ring->funcs->parse_cs) {
 770                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 771                                 amdgpu_bo_kunmap(aobj);
 772
 773                                 r = amdgpu_ring_parse_cs(ring, p, j);
 774                                 if (r)
 775                                         return r;
 776                         } else {
 777                                 ib->ptr = (uint32_t *)kptr;
 778                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 779                                 amdgpu_bo_kunmap(aobj);
 780                                 if (r)
 781                                         return r;
 782                         }
 783
 784                         j++;
 785                 }
 786         }
 787
 788         if (!p->job->vm)
 789                 return amdgpu_cs_sync_rings(p);
 790
 791
 792         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 793         if (r)
 794                 return r;
 795
 796         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 797         if (r)
 798                 return r;
 799
 800         r = amdgpu_sync_fence(adev, &p->job->sync,
 801                               fpriv->prt_va->last_pt_update, false);
 802         if (r)
 803                 return r;
 804
 805         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 806                 struct dma_fence *f;
 807
 808                 bo_va = fpriv->csa_va;
 809                 BUG_ON(!bo_va);
 810                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 811                 if (r)
 812                         return r;
 813
 814                 f = bo_va->last_pt_update;
 815                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 816                 if (r)
 817                         return r;
 818         }
 819
 820         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 821                 struct dma_fence *f;
 822
 823                 /* ignore duplicates */
 824                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 825                 if (!bo)
 826                         continue;
 827
 828                 bo_va = e->bo_va;
 829                 if (bo_va == NULL)
 830                         continue;
 831
 832                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 833                 if (r)
 834                         return r;
 835
 836                 f = bo_va->last_pt_update;
 837                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 838                 if (r)
 839                         return r;
 840         }
 841
 842         r = amdgpu_vm_handle_moved(adev, vm);
 843         if (r)
 844                 return r;
 845
 846         r = amdgpu_vm_update_pdes(adev, vm, false);
 847         if (r)
 848                 return r;
 849
 850         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 851         if (r)
 852                 return r;
 853
 854         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 855
 856         if (amdgpu_vm_debug) {
 857                 /* Invalidate all BOs to test for userspace bugs */
 858                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 859                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 860
 861                         /* ignore duplicates */
 862                         if (!bo)
 863                                 continue;
 864
 865                         amdgpu_vm_bo_invalidate(adev, bo, false);
 866                 }
 867         }
 868
 869         return amdgpu_cs_sync_rings(p);
 870 }
 871
 872 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 873                              struct amdgpu_cs_parser *parser)
 874 {
 875         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 876         struct amdgpu_vm *vm = &fpriv->vm;
 877         int r, ce_preempt = 0, de_preempt = 0;
 878         struct amdgpu_ring *ring;
 879         int i, j;
 880
 881         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 882                 struct amdgpu_cs_chunk *chunk;
 883                 struct amdgpu_ib *ib;
 884                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 885                 struct drm_sched_entity *entity;
 886
 887                 chunk = &parser->chunks[i];
 888                 ib = &parser->job->ibs[j];
 889                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 890
 891                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 892                         continue;
 893
 894                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 895                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 896                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 897                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 898                                         ce_preempt++;
 899                                 else
 900                                         de_preempt++;
 901                         }
 902
 903                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 904                         if (ce_preempt > 1 || de_preempt > 1)
 905                                 return -EINVAL;
 906                 }
 907
 908                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 909                                           chunk_ib->ip_instance, chunk_ib->ring,
 910                                           &entity);
 911                 if (r)
 912                         return r;
 913
 914                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 915                         parser->job->preamble_status |=
 916                                 AMDGPU_PREAMBLE_IB_PRESENT;
 917
 918                 if (parser->entity && parser->entity != entity)
 919                         return -EINVAL;
 920
 921                 parser->entity = entity;
 922
 923                 ring = to_amdgpu_ring(entity->rq->sched);
 924                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 925                                    chunk_ib->ib_bytes : 0, ib);
 926                 if (r) {
 927                         DRM_ERROR("Failed to get ib !\n");
 928                         return r;
 929                 }
 930
 931                 ib->gpu_addr = chunk_ib->va_start;
 932                 ib->length_dw = chunk_ib->ib_bytes / 4;
 933                 ib->flags = chunk_ib->flags;
 934
 935                 j++;
 936         }
 937
 938         /* MM engine doesn't support user fences */
 939         ring = to_amdgpu_ring(parser->entity->rq->sched);
 940         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 941                 return -EINVAL;
 942
 943         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
 944 }
 945
 946 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 947                                        struct amdgpu_cs_chunk *chunk)
 948 {
 949         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 950         unsigned num_deps;
 951         int i, r;
 952         struct drm_amdgpu_cs_chunk_dep *deps;
 953
 954         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 955         num_deps = chunk->length_dw * 4 /
 956                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 957
 958         for (i = 0; i < num_deps; ++i) {
 959                 struct amdgpu_ctx *ctx;
 960                 struct drm_sched_entity *entity;
 961                 struct dma_fence *fence;
 962
 963                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 964                 if (ctx == NULL)
 965                         return -EINVAL;
 966
 967                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 968                                           deps[i].ip_instance,
 969                                           deps[i].ring, &entity);
 970                 if (r) {
 971                         amdgpu_ctx_put(ctx);
 972                         return r;
 973                 }
 974
 975                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 976                 amdgpu_ctx_put(ctx);
 977
 978                 if (IS_ERR(fence))
 979                         return PTR_ERR(fence);
 980                 else if (!fence)
 981                         continue;
 982
 983                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 984                         struct drm_sched_fence *s_fence;
 985                         struct dma_fence *old = fence;
 986
 987                         s_fence = to_drm_sched_fence(fence);
 988                         fence = dma_fence_get(&s_fence->scheduled);
 989                         dma_fence_put(old);
 990                 }
 991
 992                 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
 993                 dma_fence_put(fence);
 994                 if (r)
 995                         return r;
 996         }
 997         return 0;
 998 }
 999
1000 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1001                                                  uint32_t handle, u64 point,
1002                                                  u64 flags)
1003 {
1004         struct dma_fence *fence;
1005         int r;
1006
1007         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1008         if (r) {
1009                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1010                           handle, point, r);
1011                 return r;
1012         }
1013
1014         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1015         dma_fence_put(fence);
1016
1017         return r;
1018 }
1019
1020 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1021                                             struct amdgpu_cs_chunk *chunk)
1022 {
1023         struct drm_amdgpu_cs_chunk_sem *deps;
1024         unsigned num_deps;
1025         int i, r;
1026
1027         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1028         num_deps = chunk->length_dw * 4 /
1029                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1030         for (i = 0; i < num_deps; ++i) {
1031                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1032                                                           0, 0);
1033                 if (r)
1034                         return r;
1035         }
1036
1037         return 0;
1038 }
1039
1040
1041 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1042                                                      struct amdgpu_cs_chunk *chunk)
1043 {
1044         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1045         unsigned num_deps;
1046         int i, r;
1047
1048         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1049         num_deps = chunk->length_dw * 4 /
1050                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1051         for (i = 0; i < num_deps; ++i) {
1052                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1053                                                           syncobj_deps[i].handle,
1054                                                           syncobj_deps[i].point,
1055                                                           syncobj_deps[i].flags);
1056                 if (r)
1057                         return r;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1064                                              struct amdgpu_cs_chunk *chunk)
1065 {
1066         struct drm_amdgpu_cs_chunk_sem *deps;
1067         unsigned num_deps;
1068         int i;
1069
1070         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1071         num_deps = chunk->length_dw * 4 /
1072                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1073
1074         if (p->post_deps)
1075                 return -EINVAL;
1076
1077         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1078                                      GFP_KERNEL);
1079         p->num_post_deps = 0;
1080
1081         if (!p->post_deps)
1082                 return -ENOMEM;
1083
1084
1085         for (i = 0; i < num_deps; ++i) {
1086                 p->post_deps[i].syncobj =
1087                         drm_syncobj_find(p->filp, deps[i].handle);
1088                 if (!p->post_deps[i].syncobj)
1089                         return -EINVAL;
1090                 p->post_deps[i].chain = NULL;
1091                 p->post_deps[i].point = 0;
1092                 p->num_post_deps++;
1093         }
1094
1095         return 0;
1096 }
1097
1098
1099 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1100                                                       struct amdgpu_cs_chunk *chunk)
1101 {
1102         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1103         unsigned num_deps;
1104         int i;
1105
1106         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1107         num_deps = chunk->length_dw * 4 /
1108                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1109
1110         if (p->post_deps)
1111                 return -EINVAL;
1112
1113         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1114                                      GFP_KERNEL);
1115         p->num_post_deps = 0;
1116
1117         if (!p->post_deps)
1118                 return -ENOMEM;
1119
1120         for (i = 0; i < num_deps; ++i) {
1121                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1122
1123                 dep->chain = NULL;
1124                 if (syncobj_deps[i].point) {
1125                         dep->chain = kmalloc(sizeof(*dep->chain), GFP_KERNEL);
1126                         if (!dep->chain)
1127                                 return -ENOMEM;
1128                 }
1129
1130                 dep->syncobj = drm_syncobj_find(p->filp,
1131                                                 syncobj_deps[i].handle);
1132                 if (!dep->syncobj) {
1133                         kfree(dep->chain);
1134                         return -EINVAL;
1135                 }
1136                 dep->point = syncobj_deps[i].point;
1137                 p->num_post_deps++;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1144                                   struct amdgpu_cs_parser *p)
1145 {
1146         int i, r;
1147
1148         for (i = 0; i < p->nchunks; ++i) {
1149                 struct amdgpu_cs_chunk *chunk;
1150
1151                 chunk = &p->chunks[i];
1152
1153                 switch (chunk->chunk_id) {
1154                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1155                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1156                         r = amdgpu_cs_process_fence_dep(p, chunk);
1157                         if (r)
1158                                 return r;
1159                         break;
1160                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1161                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1162                         if (r)
1163                                 return r;
1164                         break;
1165                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1166                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1167                         if (r)
1168                                 return r;
1169                         break;
1170                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1171                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1172                         if (r)
1173                                 return r;
1174                         break;
1175                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1176                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1177                         if (r)
1178                                 return r;
1179                         break;
1180                 }
1181         }
1182
1183         return 0;
1184 }
1185
1186 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1187 {
1188         int i;
1189
1190         for (i = 0; i < p->num_post_deps; ++i) {
1191                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1192                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1193                                               p->post_deps[i].chain,
1194                                               p->fence, p->post_deps[i].point);
1195                         p->post_deps[i].chain = NULL;
1196                 } else {
1197                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1198                                                   p->fence);
1199                 }
1200         }
1201 }
1202
1203 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1204                             union drm_amdgpu_cs *cs)
1205 {
1206         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1207         struct drm_sched_entity *entity = p->entity;
1208         enum drm_sched_priority priority;
1209         struct amdgpu_ring *ring;
1210         struct amdgpu_bo_list_entry *e;
1211         struct amdgpu_job *job;
1212         uint64_t seq;
1213         int r;
1214
1215         job = p->job;
1216         p->job = NULL;
1217
1218         r = drm_sched_job_init(&job->base, entity, p->filp);
1219         if (r)
1220                 goto error_unlock;
1221
1222         /* No memory allocation is allowed while holding the mn lock.
1223          * p->mn is hold until amdgpu_cs_submit is finished and fence is added
1224          * to BOs.
1225          */
1226         amdgpu_mn_lock(p->mn);
1227
1228         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1229          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1230          */
1231         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1232                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1233
1234                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1235         }
1236         if (r) {
1237                 r = -EAGAIN;
1238                 goto error_abort;
1239         }
1240
1241         job->owner = p->filp;
1242         p->fence = dma_fence_get(&job->base.s_fence->finished);
1243
1244         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1245         amdgpu_cs_post_dependencies(p);
1246
1247         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1248             !p->ctx->preamble_presented) {
1249                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1250                 p->ctx->preamble_presented = true;
1251         }
1252
1253         cs->out.handle = seq;
1254         job->uf_sequence = seq;
1255
1256         amdgpu_job_free_resources(job);
1257
1258         trace_amdgpu_cs_ioctl(job);
1259         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1260         priority = job->base.s_priority;
1261         drm_sched_entity_push_job(&job->base, entity);
1262
1263         ring = to_amdgpu_ring(entity->rq->sched);
1264         amdgpu_ring_priority_get(ring, priority);
1265
1266         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1267
1268         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1269         amdgpu_mn_unlock(p->mn);
1270
1271         return 0;
1272
1273 error_abort:
1274         drm_sched_job_cleanup(&job->base);
1275         amdgpu_mn_unlock(p->mn);
1276
1277 error_unlock:
1278         amdgpu_job_free(job);
1279         return r;
1280 }
1281
1282 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1283 {
1284         struct amdgpu_device *adev = dev->dev_private;
1285         union drm_amdgpu_cs *cs = data;
1286         struct amdgpu_cs_parser parser = {};
1287         bool reserved_buffers = false;
1288         int i, r;
1289
1290         if (amdgpu_ras_intr_triggered())
1291                 return -EHWPOISON;
1292
1293         if (!adev->accel_working)
1294                 return -EBUSY;
1295
1296         parser.adev = adev;
1297         parser.filp = filp;
1298
1299         r = amdgpu_cs_parser_init(&parser, data);
1300         if (r) {
1301                 DRM_ERROR("Failed to initialize parser %d!\n", r);
1302                 goto out;
1303         }
1304
1305         r = amdgpu_cs_ib_fill(adev, &parser);
1306         if (r)
1307                 goto out;
1308
1309         r = amdgpu_cs_dependencies(adev, &parser);
1310         if (r) {
1311                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1312                 goto out;
1313         }
1314
1315         r = amdgpu_cs_parser_bos(&parser, data);
1316         if (r) {
1317                 if (r == -ENOMEM)
1318                         DRM_ERROR("Not enough memory for command submission!\n");
1319                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1320                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1321                 goto out;
1322         }
1323
1324         reserved_buffers = true;
1325
1326         for (i = 0; i < parser.job->num_ibs; i++)
1327                 trace_amdgpu_cs(&parser, i);
1328
1329         r = amdgpu_cs_vm_handling(&parser);
1330         if (r)
1331                 goto out;
1332
1333         r = amdgpu_cs_submit(&parser, cs);
1334
1335 out:
1336         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1337
1338         return r;
1339 }
1340
1341 /**
1342  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1343  *
1344  * @dev: drm device
1345  * @data: data from userspace
1346  * @filp: file private
1347  *
1348  * Wait for the command submission identified by handle to finish.
1349  */
1350 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1351                          struct drm_file *filp)
1352 {
1353         union drm_amdgpu_wait_cs *wait = data;
1354         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1355         struct drm_sched_entity *entity;
1356         struct amdgpu_ctx *ctx;
1357         struct dma_fence *fence;
1358         long r;
1359
1360         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1361         if (ctx == NULL)
1362                 return -EINVAL;
1363
1364         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1365                                   wait->in.ring, &entity);
1366         if (r) {
1367                 amdgpu_ctx_put(ctx);
1368                 return r;
1369         }
1370
1371         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1372         if (IS_ERR(fence))
1373                 r = PTR_ERR(fence);
1374         else if (fence) {
1375                 r = dma_fence_wait_timeout(fence, true, timeout);
1376                 if (r > 0 && fence->error)
1377                         r = fence->error;
1378                 dma_fence_put(fence);
1379         } else
1380                 r = 1;
1381
1382         amdgpu_ctx_put(ctx);
1383         if (r < 0)
1384                 return r;
1385
1386         memset(wait, 0, sizeof(*wait));
1387         wait->out.status = (r == 0);
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1394  *
1395  * @adev: amdgpu device
1396  * @filp: file private
1397  * @user: drm_amdgpu_fence copied from user space
1398  */
1399 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1400                                              struct drm_file *filp,
1401                                              struct drm_amdgpu_fence *user)
1402 {
1403         struct drm_sched_entity *entity;
1404         struct amdgpu_ctx *ctx;
1405         struct dma_fence *fence;
1406         int r;
1407
1408         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1409         if (ctx == NULL)
1410                 return ERR_PTR(-EINVAL);
1411
1412         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1413                                   user->ring, &entity);
1414         if (r) {
1415                 amdgpu_ctx_put(ctx);
1416                 return ERR_PTR(r);
1417         }
1418
1419         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1420         amdgpu_ctx_put(ctx);
1421
1422         return fence;
1423 }
1424
1425 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1426                                     struct drm_file *filp)
1427 {
1428         struct amdgpu_device *adev = dev->dev_private;
1429         union drm_amdgpu_fence_to_handle *info = data;
1430         struct dma_fence *fence;
1431         struct drm_syncobj *syncobj;
1432         struct sync_file *sync_file;
1433         int fd, r;
1434
1435         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1436         if (IS_ERR(fence))
1437                 return PTR_ERR(fence);
1438
1439         if (!fence)
1440                 fence = dma_fence_get_stub();
1441
1442         switch (info->in.what) {
1443         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1444                 r = drm_syncobj_create(&syncobj, 0, fence);
1445                 dma_fence_put(fence);
1446                 if (r)
1447                         return r;
1448                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1449                 drm_syncobj_put(syncobj);
1450                 return r;
1451
1452         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1453                 r = drm_syncobj_create(&syncobj, 0, fence);
1454                 dma_fence_put(fence);
1455                 if (r)
1456                         return r;
1457                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1458                 drm_syncobj_put(syncobj);
1459                 return r;
1460
1461         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1462                 fd = get_unused_fd_flags(O_CLOEXEC);
1463                 if (fd < 0) {
1464                         dma_fence_put(fence);
1465                         return fd;
1466                 }
1467
1468                 sync_file = sync_file_create(fence);
1469                 dma_fence_put(fence);
1470                 if (!sync_file) {
1471                         put_unused_fd(fd);
1472                         return -ENOMEM;
1473                 }
1474
1475                 fd_install(fd, sync_file->file);
1476                 info->out.handle = fd;
1477                 return 0;
1478
1479         default:
1480                 return -EINVAL;
1481         }
1482 }
1483
1484 /**
1485  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1486  *
1487  * @adev: amdgpu device
1488  * @filp: file private
1489  * @wait: wait parameters
1490  * @fences: array of drm_amdgpu_fence
1491  */
1492 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1493                                      struct drm_file *filp,
1494                                      union drm_amdgpu_wait_fences *wait,
1495                                      struct drm_amdgpu_fence *fences)
1496 {
1497         uint32_t fence_count = wait->in.fence_count;
1498         unsigned int i;
1499         long r = 1;
1500
1501         for (i = 0; i < fence_count; i++) {
1502                 struct dma_fence *fence;
1503                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1504
1505                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1506                 if (IS_ERR(fence))
1507                         return PTR_ERR(fence);
1508                 else if (!fence)
1509                         continue;
1510
1511                 r = dma_fence_wait_timeout(fence, true, timeout);
1512                 dma_fence_put(fence);
1513                 if (r < 0)
1514                         return r;
1515
1516                 if (r == 0)
1517                         break;
1518
1519                 if (fence->error)
1520                         return fence->error;
1521         }
1522
1523         memset(wait, 0, sizeof(*wait));
1524         wait->out.status = (r > 0);
1525
1526         return 0;
1527 }
1528
1529 /**
1530  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1531  *
1532  * @adev: amdgpu device
1533  * @filp: file private
1534  * @wait: wait parameters
1535  * @fences: array of drm_amdgpu_fence
1536  */
1537 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1538                                     struct drm_file *filp,
1539                                     union drm_amdgpu_wait_fences *wait,
1540                                     struct drm_amdgpu_fence *fences)
1541 {
1542         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1543         uint32_t fence_count = wait->in.fence_count;
1544         uint32_t first = ~0;
1545         struct dma_fence **array;
1546         unsigned int i;
1547         long r;
1548
1549         /* Prepare the fence array */
1550         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1551
1552         if (array == NULL)
1553                 return -ENOMEM;
1554
1555         for (i = 0; i < fence_count; i++) {
1556                 struct dma_fence *fence;
1557
1558                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1559                 if (IS_ERR(fence)) {
1560                         r = PTR_ERR(fence);
1561                         goto err_free_fence_array;
1562                 } else if (fence) {
1563                         array[i] = fence;
1564                 } else { /* NULL, the fence has been already signaled */
1565                         r = 1;
1566                         first = i;
1567                         goto out;
1568                 }
1569         }
1570
1571         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1572                                        &first);
1573         if (r < 0)
1574                 goto err_free_fence_array;
1575
1576 out:
1577         memset(wait, 0, sizeof(*wait));
1578         wait->out.status = (r > 0);
1579         wait->out.first_signaled = first;
1580
1581         if (first < fence_count && array[first])
1582                 r = array[first]->error;
1583         else
1584                 r = 0;
1585
1586 err_free_fence_array:
1587         for (i = 0; i < fence_count; i++)
1588                 dma_fence_put(array[i]);
1589         kfree(array);
1590
1591         return r;
1592 }
1593
1594 /**
1595  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1596  *
1597  * @dev: drm device
1598  * @data: data from userspace
1599  * @filp: file private
1600  */
1601 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1602                                 struct drm_file *filp)
1603 {
1604         struct amdgpu_device *adev = dev->dev_private;
1605         union drm_amdgpu_wait_fences *wait = data;
1606         uint32_t fence_count = wait->in.fence_count;
1607         struct drm_amdgpu_fence *fences_user;
1608         struct drm_amdgpu_fence *fences;
1609         int r;
1610
1611         /* Get the fences from userspace */
1612         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1613                         GFP_KERNEL);
1614         if (fences == NULL)
1615                 return -ENOMEM;
1616
1617         fences_user = u64_to_user_ptr(wait->in.fences);
1618         if (copy_from_user(fences, fences_user,
1619                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1620                 r = -EFAULT;
1621                 goto err_free_fences;
1622         }
1623
1624         if (wait->in.wait_all)
1625                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1626         else
1627                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1628
1629 err_free_fences:
1630         kfree(fences);
1631
1632         return r;
1633 }
1634
1635 /**
1636  * amdgpu_cs_find_bo_va - find bo_va for VM address
1637  *
1638  * @parser: command submission parser context
1639  * @addr: VM address
1640  * @bo: resulting BO of the mapping found
1641  *
1642  * Search the buffer objects in the command submission context for a certain
1643  * virtual memory address. Returns allocation structure when found, NULL
1644  * otherwise.
1645  */
1646 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1647                            uint64_t addr, struct amdgpu_bo **bo,
1648                            struct amdgpu_bo_va_mapping **map)
1649 {
1650         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1651         struct ttm_operation_ctx ctx = { false, false };
1652         struct amdgpu_vm *vm = &fpriv->vm;
1653         struct amdgpu_bo_va_mapping *mapping;
1654         int r;
1655
1656         addr /= AMDGPU_GPU_PAGE_SIZE;
1657
1658         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1659         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1660                 return -EINVAL;
1661
1662         *bo = mapping->bo_va->base.bo;
1663         *map = mapping;
1664
1665         /* Double check that the BO is reserved by this CS */
1666         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1667                 return -EINVAL;
1668
1669         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1670                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1671                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1672                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1673                 if (r)
1674                         return r;
1675         }
1676
1677         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1678 }