2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
31 #include <linux/firmware.h>
32 #include <linux/module.h>
35 #include <drm/drm_drv.h>
38 #include "amdgpu_pm.h"
39 #include "amdgpu_uvd.h"
40 #include "amdgpu_cs.h"
42 #include "uvd/uvd_4_2_d.h"
44 #include "amdgpu_ras.h"
46 /* 1 second timeout */
47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
49 /* Firmware versions for VI */
50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
55 /* Polaris10/11 firmware version */
56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
59 #ifdef CONFIG_DRM_AMDGPU_SI
60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin"
61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin"
62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin"
63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin"
65 #ifdef CONFIG_DRM_AMDGPU_CIK
66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin"
67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin"
72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin"
81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin"
83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin"
85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */
86 #define UVD_GPCOM_VCPU_CMD 0x03c3
87 #define UVD_GPCOM_VCPU_DATA0 0x03c4
88 #define UVD_GPCOM_VCPU_DATA1 0x03c5
89 #define UVD_NO_OP 0x03ff
90 #define UVD_BASE_SI 0x3800
93 * amdgpu_uvd_cs_ctx - Command submission parser context
95 * Used for emulating virtual memory support on UVD 4.2.
97 struct amdgpu_uvd_cs_ctx {
98 struct amdgpu_cs_parser *parser;
100 unsigned data0, data1;
102 struct amdgpu_ib *ib;
104 /* does the IB has a msg command */
107 /* minimum buffer sizes */
111 #ifdef CONFIG_DRM_AMDGPU_SI
112 MODULE_FIRMWARE(FIRMWARE_TAHITI);
113 MODULE_FIRMWARE(FIRMWARE_VERDE);
114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
115 MODULE_FIRMWARE(FIRMWARE_OLAND);
117 #ifdef CONFIG_DRM_AMDGPU_CIK
118 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
119 MODULE_FIRMWARE(FIRMWARE_KABINI);
120 MODULE_FIRMWARE(FIRMWARE_KAVERI);
121 MODULE_FIRMWARE(FIRMWARE_HAWAII);
122 MODULE_FIRMWARE(FIRMWARE_MULLINS);
124 MODULE_FIRMWARE(FIRMWARE_TONGA);
125 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
126 MODULE_FIRMWARE(FIRMWARE_FIJI);
127 MODULE_FIRMWARE(FIRMWARE_STONEY);
128 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
129 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
130 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
131 MODULE_FIRMWARE(FIRMWARE_VEGAM);
133 MODULE_FIRMWARE(FIRMWARE_VEGA10);
134 MODULE_FIRMWARE(FIRMWARE_VEGA12);
135 MODULE_FIRMWARE(FIRMWARE_VEGA20);
137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
138 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
142 struct amdgpu_bo **bo_ptr)
144 struct ttm_operation_ctx ctx = { true, false };
145 struct amdgpu_bo *bo = NULL;
149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
150 AMDGPU_GEM_DOMAIN_GTT,
155 if (adev->uvd.address_64_bit)
158 amdgpu_bo_kunmap(bo);
160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
161 amdgpu_uvd_force_into_uvd_segment(bo);
162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
168 r = amdgpu_bo_kmap(bo, &addr);
172 amdgpu_bo_unreserve(bo);
179 amdgpu_bo_unreserve(bo);
180 amdgpu_bo_unref(&bo);
184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
186 unsigned long bo_size;
188 const struct common_firmware_header *hdr;
192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
194 switch (adev->asic_type) {
195 #ifdef CONFIG_DRM_AMDGPU_SI
197 fw_name = FIRMWARE_TAHITI;
200 fw_name = FIRMWARE_VERDE;
203 fw_name = FIRMWARE_PITCAIRN;
206 fw_name = FIRMWARE_OLAND;
209 #ifdef CONFIG_DRM_AMDGPU_CIK
211 fw_name = FIRMWARE_BONAIRE;
214 fw_name = FIRMWARE_KABINI;
217 fw_name = FIRMWARE_KAVERI;
220 fw_name = FIRMWARE_HAWAII;
223 fw_name = FIRMWARE_MULLINS;
227 fw_name = FIRMWARE_TONGA;
230 fw_name = FIRMWARE_FIJI;
233 fw_name = FIRMWARE_CARRIZO;
236 fw_name = FIRMWARE_STONEY;
239 fw_name = FIRMWARE_POLARIS10;
242 fw_name = FIRMWARE_POLARIS11;
245 fw_name = FIRMWARE_POLARIS12;
248 fw_name = FIRMWARE_VEGA10;
251 fw_name = FIRMWARE_VEGA12;
254 fw_name = FIRMWARE_VEGAM;
257 fw_name = FIRMWARE_VEGA20;
263 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
265 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
270 r = amdgpu_ucode_validate(adev->uvd.fw);
272 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
274 release_firmware(adev->uvd.fw);
279 /* Set the default UVD handles that the firmware can handle */
280 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
282 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
283 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
285 if (adev->asic_type < CHIP_VEGA20) {
286 unsigned version_major, version_minor;
288 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
289 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
290 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
291 version_major, version_minor, family_id);
294 * Limit the number of UVD handles depending on microcode major
295 * and minor versions. The firmware version which has 40 UVD
296 * instances support is 1.80. So all subsequent versions should
297 * also have the same support.
299 if ((version_major > 0x01) ||
300 ((version_major == 0x01) && (version_minor >= 0x50)))
301 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
303 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
306 if ((adev->asic_type == CHIP_POLARIS10 ||
307 adev->asic_type == CHIP_POLARIS11) &&
308 (adev->uvd.fw_version < FW_1_66_16))
309 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",
310 version_major, version_minor);
312 unsigned int enc_major, enc_minor, dec_minor;
314 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
315 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
316 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
317 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",
318 enc_major, enc_minor, dec_minor, family_id);
320 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
322 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
325 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
326 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
327 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
328 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
330 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
331 if (adev->uvd.harvest_config & (1 << j))
333 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
334 AMDGPU_GEM_DOMAIN_VRAM |
335 AMDGPU_GEM_DOMAIN_GTT,
336 &adev->uvd.inst[j].vcpu_bo,
337 &adev->uvd.inst[j].gpu_addr,
338 &adev->uvd.inst[j].cpu_addr);
340 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
345 for (i = 0; i < adev->uvd.max_handles; ++i) {
346 atomic_set(&adev->uvd.handles[i], 0);
347 adev->uvd.filp[i] = NULL;
350 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
351 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
352 adev->uvd.address_64_bit = true;
354 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
358 switch (adev->asic_type) {
360 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
363 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
366 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
369 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
372 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
378 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
380 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
383 drm_sched_entity_destroy(&adev->uvd.entity);
385 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
386 if (adev->uvd.harvest_config & (1 << j))
388 kvfree(adev->uvd.inst[j].saved_bo);
390 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
391 &adev->uvd.inst[j].gpu_addr,
392 (void **)&adev->uvd.inst[j].cpu_addr);
394 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
396 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
397 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
399 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
400 release_firmware(adev->uvd.fw);
406 * amdgpu_uvd_entity_init - init entity
408 * @adev: amdgpu_device pointer
411 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
413 struct amdgpu_ring *ring;
414 struct drm_gpu_scheduler *sched;
417 ring = &adev->uvd.inst[0].ring;
418 sched = &ring->sched;
419 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
422 DRM_ERROR("Failed setting up UVD kernel entity.\n");
429 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
434 bool in_ras_intr = amdgpu_ras_intr_triggered();
436 cancel_delayed_work_sync(&adev->uvd.idle_work);
438 /* only valid for physical mode */
439 if (adev->asic_type < CHIP_POLARIS10) {
440 for (i = 0; i < adev->uvd.max_handles; ++i)
441 if (atomic_read(&adev->uvd.handles[i]))
444 if (i == adev->uvd.max_handles)
448 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
449 if (adev->uvd.harvest_config & (1 << j))
451 if (adev->uvd.inst[j].vcpu_bo == NULL)
454 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
455 ptr = adev->uvd.inst[j].cpu_addr;
457 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
458 if (!adev->uvd.inst[j].saved_bo)
461 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
462 /* re-write 0 since err_event_athub will corrupt VCPU buffer */
464 memset(adev->uvd.inst[j].saved_bo, 0, size);
466 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
473 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
478 int amdgpu_uvd_resume(struct amdgpu_device *adev)
484 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
485 if (adev->uvd.harvest_config & (1 << i))
487 if (adev->uvd.inst[i].vcpu_bo == NULL)
490 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
491 ptr = adev->uvd.inst[i].cpu_addr;
493 if (adev->uvd.inst[i].saved_bo != NULL) {
494 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
495 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
498 kvfree(adev->uvd.inst[i].saved_bo);
499 adev->uvd.inst[i].saved_bo = NULL;
501 const struct common_firmware_header *hdr;
504 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
505 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
506 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
507 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
508 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
509 le32_to_cpu(hdr->ucode_size_bytes));
512 size -= le32_to_cpu(hdr->ucode_size_bytes);
513 ptr += le32_to_cpu(hdr->ucode_size_bytes);
515 memset_io(ptr, 0, size);
516 /* to restore uvd fence seq */
517 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
523 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
525 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
528 for (i = 0; i < adev->uvd.max_handles; ++i) {
529 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
531 if (handle != 0 && adev->uvd.filp[i] == filp) {
532 struct dma_fence *fence;
534 r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
537 DRM_ERROR("Error destroying UVD %d!\n", r);
541 dma_fence_wait(fence, false);
542 dma_fence_put(fence);
544 adev->uvd.filp[i] = NULL;
545 atomic_set(&adev->uvd.handles[i], 0);
550 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
553 for (i = 0; i < abo->placement.num_placement; ++i) {
554 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
555 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
559 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
564 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0);
565 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1);
566 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
572 * amdgpu_uvd_cs_pass1 - first parsing round
574 * @ctx: UVD parser context
576 * Make sure UVD message and feedback buffers are in VRAM and
577 * nobody is violating an 256MB boundary.
579 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
581 struct ttm_operation_ctx tctx = { false, false };
582 struct amdgpu_bo_va_mapping *mapping;
583 struct amdgpu_bo *bo;
585 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
588 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
590 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
594 if (!ctx->parser->adev->uvd.address_64_bit) {
595 /* check if it's a message or feedback command */
596 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
597 if (cmd == 0x0 || cmd == 0x3) {
598 /* yes, force it into VRAM */
599 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
600 amdgpu_bo_placement_from_domain(bo, domain);
602 amdgpu_uvd_force_into_uvd_segment(bo);
604 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
611 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
613 * @adev: amdgpu_device pointer
614 * @msg: pointer to message structure
615 * @buf_sizes: placeholder to put the different buffer lengths
617 * Peek into the decode message and calculate the necessary buffer sizes.
619 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
620 unsigned buf_sizes[])
622 unsigned stream_type = msg[4];
623 unsigned width = msg[6];
624 unsigned height = msg[7];
625 unsigned dpb_size = msg[9];
626 unsigned pitch = msg[28];
627 unsigned level = msg[57];
629 unsigned width_in_mb = width / 16;
630 unsigned height_in_mb = ALIGN(height / 16, 2);
631 unsigned fs_in_mb = width_in_mb * height_in_mb;
633 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
634 unsigned min_ctx_size = ~0;
636 image_size = width * height;
637 image_size += image_size / 2;
638 image_size = ALIGN(image_size, 1024);
640 switch (stream_type) {
644 num_dpb_buffer = 8100 / fs_in_mb;
647 num_dpb_buffer = 18000 / fs_in_mb;
650 num_dpb_buffer = 20480 / fs_in_mb;
653 num_dpb_buffer = 32768 / fs_in_mb;
656 num_dpb_buffer = 34816 / fs_in_mb;
659 num_dpb_buffer = 110400 / fs_in_mb;
662 num_dpb_buffer = 184320 / fs_in_mb;
665 num_dpb_buffer = 184320 / fs_in_mb;
669 if (num_dpb_buffer > 17)
672 /* reference picture buffer */
673 min_dpb_size = image_size * num_dpb_buffer;
675 /* macroblock context buffer */
676 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
678 /* IT surface buffer */
679 min_dpb_size += width_in_mb * height_in_mb * 32;
684 /* reference picture buffer */
685 min_dpb_size = image_size * 3;
688 min_dpb_size += width_in_mb * height_in_mb * 128;
690 /* IT surface buffer */
691 min_dpb_size += width_in_mb * 64;
693 /* DB surface buffer */
694 min_dpb_size += width_in_mb * 128;
697 tmp = max(width_in_mb, height_in_mb);
698 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
703 /* reference picture buffer */
704 min_dpb_size = image_size * 3;
709 /* reference picture buffer */
710 min_dpb_size = image_size * 3;
713 min_dpb_size += width_in_mb * height_in_mb * 64;
715 /* IT surface buffer */
716 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
719 case 7: /* H264 Perf */
722 num_dpb_buffer = 8100 / fs_in_mb;
725 num_dpb_buffer = 18000 / fs_in_mb;
728 num_dpb_buffer = 20480 / fs_in_mb;
731 num_dpb_buffer = 32768 / fs_in_mb;
734 num_dpb_buffer = 34816 / fs_in_mb;
737 num_dpb_buffer = 110400 / fs_in_mb;
740 num_dpb_buffer = 184320 / fs_in_mb;
743 num_dpb_buffer = 184320 / fs_in_mb;
747 if (num_dpb_buffer > 17)
750 /* reference picture buffer */
751 min_dpb_size = image_size * num_dpb_buffer;
753 if (!adev->uvd.use_ctx_buf){
754 /* macroblock context buffer */
756 width_in_mb * height_in_mb * num_dpb_buffer * 192;
758 /* IT surface buffer */
759 min_dpb_size += width_in_mb * height_in_mb * 32;
761 /* macroblock context buffer */
763 width_in_mb * height_in_mb * num_dpb_buffer * 192;
772 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
773 image_size = ALIGN(image_size, 256);
775 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
776 min_dpb_size = image_size * num_dpb_buffer;
777 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
778 * 16 * num_dpb_buffer + 52 * 1024;
782 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
787 DRM_ERROR("Invalid UVD decoding target pitch!\n");
791 if (dpb_size < min_dpb_size) {
792 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
793 dpb_size, min_dpb_size);
797 buf_sizes[0x1] = dpb_size;
798 buf_sizes[0x2] = image_size;
799 buf_sizes[0x4] = min_ctx_size;
800 /* store image width to adjust nb memory pstate */
801 adev->uvd.decode_image_width = width;
806 * amdgpu_uvd_cs_msg - handle UVD message
808 * @ctx: UVD parser context
809 * @bo: buffer object containing the message
810 * @offset: offset into the buffer object
812 * Peek into the UVD message and extract the session id.
813 * Make sure that we don't open up to many sessions.
815 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
816 struct amdgpu_bo *bo, unsigned offset)
818 struct amdgpu_device *adev = ctx->parser->adev;
819 int32_t *msg, msg_type, handle;
825 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
829 r = amdgpu_bo_kmap(bo, &ptr);
831 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
841 amdgpu_bo_kunmap(bo);
842 DRM_ERROR("Invalid UVD handle!\n");
848 /* it's a create msg, calc image size (width * height) */
849 amdgpu_bo_kunmap(bo);
851 /* try to alloc a new handle */
852 for (i = 0; i < adev->uvd.max_handles; ++i) {
853 if (atomic_read(&adev->uvd.handles[i]) == handle) {
854 DRM_ERROR(")Handle 0x%x already in use!\n",
859 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
860 adev->uvd.filp[i] = ctx->parser->filp;
865 DRM_ERROR("No more free UVD handles!\n");
869 /* it's a decode msg, calc buffer sizes */
870 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
871 amdgpu_bo_kunmap(bo);
875 /* validate the handle */
876 for (i = 0; i < adev->uvd.max_handles; ++i) {
877 if (atomic_read(&adev->uvd.handles[i]) == handle) {
878 if (adev->uvd.filp[i] != ctx->parser->filp) {
879 DRM_ERROR("UVD handle collision detected!\n");
886 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
890 /* it's a destroy msg, free the handle */
891 for (i = 0; i < adev->uvd.max_handles; ++i)
892 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
893 amdgpu_bo_kunmap(bo);
897 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
900 amdgpu_bo_kunmap(bo);
905 * amdgpu_uvd_cs_pass2 - second parsing round
907 * @ctx: UVD parser context
909 * Patch buffer addresses, make sure buffer sizes are correct.
911 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
913 struct amdgpu_bo_va_mapping *mapping;
914 struct amdgpu_bo *bo;
917 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
920 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
922 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
926 start = amdgpu_bo_gpu_offset(bo);
928 end = (mapping->last + 1 - mapping->start);
929 end = end * AMDGPU_GPU_PAGE_SIZE + start;
931 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
934 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start));
935 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start));
937 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
939 if ((end - start) < ctx->buf_sizes[cmd]) {
940 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
941 (unsigned)(end - start),
942 ctx->buf_sizes[cmd]);
946 } else if (cmd == 0x206) {
947 if ((end - start) < ctx->buf_sizes[4]) {
948 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
949 (unsigned)(end - start),
953 } else if ((cmd != 0x100) && (cmd != 0x204)) {
954 DRM_ERROR("invalid UVD command %X!\n", cmd);
958 if (!ctx->parser->adev->uvd.address_64_bit) {
959 if ((start >> 28) != ((end - 1) >> 28)) {
960 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
965 if ((cmd == 0 || cmd == 0x3) &&
966 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
967 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
974 ctx->has_msg_cmd = true;
975 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
978 } else if (!ctx->has_msg_cmd) {
979 DRM_ERROR("Message needed before other commands are send!\n");
987 * amdgpu_uvd_cs_reg - parse register writes
989 * @ctx: UVD parser context
990 * @cb: callback function
992 * Parse the register writes, call cb on each complete command.
994 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
995 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
1000 for (i = 0; i <= ctx->count; ++i) {
1001 unsigned reg = ctx->reg + i;
1003 if (ctx->idx >= ctx->ib->length_dw) {
1004 DRM_ERROR("Register command after end of CS!\n");
1009 case mmUVD_GPCOM_VCPU_DATA0:
1010 ctx->data0 = ctx->idx;
1012 case mmUVD_GPCOM_VCPU_DATA1:
1013 ctx->data1 = ctx->idx;
1015 case mmUVD_GPCOM_VCPU_CMD:
1020 case mmUVD_ENGINE_CNTL:
1024 DRM_ERROR("Invalid reg 0x%X!\n", reg);
1033 * amdgpu_uvd_cs_packets - parse UVD packets
1035 * @ctx: UVD parser context
1036 * @cb: callback function
1038 * Parse the command stream packets.
1040 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
1041 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
1045 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) {
1046 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);
1047 unsigned type = CP_PACKET_GET_TYPE(cmd);
1050 ctx->reg = CP_PACKET0_GET_REG(cmd);
1051 ctx->count = CP_PACKET_GET_COUNT(cmd);
1052 r = amdgpu_uvd_cs_reg(ctx, cb);
1060 DRM_ERROR("Unknown packet type %d !\n", type);
1068 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
1070 * @parser: Command submission parser context
1071 * @job: the job to parse
1072 * @ib: the IB to patch
1074 * Parse the command stream, patch in addresses as necessary.
1076 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
1077 struct amdgpu_job *job,
1078 struct amdgpu_ib *ib)
1080 struct amdgpu_uvd_cs_ctx ctx = {};
1081 unsigned buf_sizes[] = {
1082 [0x00000000] = 2048,
1083 [0x00000001] = 0xFFFFFFFF,
1084 [0x00000002] = 0xFFFFFFFF,
1085 [0x00000003] = 2048,
1086 [0x00000004] = 0xFFFFFFFF,
1091 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1093 if (ib->length_dw % 16) {
1094 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
1099 ctx.parser = parser;
1100 ctx.buf_sizes = buf_sizes;
1103 /* first round only required on chips without UVD 64 bit address support */
1104 if (!parser->adev->uvd.address_64_bit) {
1105 /* first round, make sure the buffers are actually in the UVD segment */
1106 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1111 /* second round, patch buffer addresses into the command stream */
1112 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1116 if (!ctx.has_msg_cmd) {
1117 DRM_ERROR("UVD-IBs need a msg command!\n");
1124 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1125 bool direct, struct dma_fence **fence)
1127 struct amdgpu_device *adev = ring->adev;
1128 struct dma_fence *f = NULL;
1129 struct amdgpu_job *job;
1130 struct amdgpu_ib *ib;
1135 unsigned offset_idx = 0;
1136 unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1138 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,
1139 AMDGPU_FENCE_OWNER_UNDEFINED,
1140 64, direct ? AMDGPU_IB_POOL_DIRECT :
1141 AMDGPU_IB_POOL_DELAYED, &job);
1145 if (adev->asic_type >= CHIP_VEGA10) {
1146 offset_idx = 1 + ring->me;
1147 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1148 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1151 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1152 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1153 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1154 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1157 addr = amdgpu_bo_gpu_offset(bo);
1158 ib->ptr[0] = data[0];
1160 ib->ptr[2] = data[1];
1161 ib->ptr[3] = addr >> 32;
1162 ib->ptr[4] = data[2];
1164 for (i = 6; i < 16; i += 2) {
1165 ib->ptr[i] = data[3];
1171 r = dma_resv_wait_timeout(bo->tbo.base.resv,
1172 DMA_RESV_USAGE_KERNEL, false,
1173 msecs_to_jiffies(10));
1179 r = amdgpu_job_submit_direct(job, ring, &f);
1183 r = drm_sched_job_add_resv_dependencies(&job->base,
1185 DMA_RESV_USAGE_KERNEL);
1189 f = amdgpu_job_submit(job);
1192 amdgpu_bo_reserve(bo, true);
1193 amdgpu_bo_fence(bo, f, false);
1194 amdgpu_bo_unreserve(bo);
1197 *fence = dma_fence_get(f);
1203 amdgpu_job_free(job);
1207 /* multiple fence commands without any stream commands in between can
1208 crash the vcpu so just try to emmit a dummy create/destroy msg to
1210 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1211 struct dma_fence **fence)
1213 struct amdgpu_device *adev = ring->adev;
1214 struct amdgpu_bo *bo = adev->uvd.ib_bo;
1218 msg = amdgpu_bo_kptr(bo);
1219 /* stitch together an UVD create msg */
1220 msg[0] = cpu_to_le32(0x00000de4);
1221 msg[1] = cpu_to_le32(0x00000000);
1222 msg[2] = cpu_to_le32(handle);
1223 msg[3] = cpu_to_le32(0x00000000);
1224 msg[4] = cpu_to_le32(0x00000000);
1225 msg[5] = cpu_to_le32(0x00000000);
1226 msg[6] = cpu_to_le32(0x00000000);
1227 msg[7] = cpu_to_le32(0x00000780);
1228 msg[8] = cpu_to_le32(0x00000440);
1229 msg[9] = cpu_to_le32(0x00000000);
1230 msg[10] = cpu_to_le32(0x01b37000);
1231 for (i = 11; i < 1024; ++i)
1232 msg[i] = cpu_to_le32(0x0);
1234 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1238 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1239 bool direct, struct dma_fence **fence)
1241 struct amdgpu_device *adev = ring->adev;
1242 struct amdgpu_bo *bo = NULL;
1247 bo = adev->uvd.ib_bo;
1249 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
1254 msg = amdgpu_bo_kptr(bo);
1255 /* stitch together an UVD destroy msg */
1256 msg[0] = cpu_to_le32(0x00000de4);
1257 msg[1] = cpu_to_le32(0x00000002);
1258 msg[2] = cpu_to_le32(handle);
1259 msg[3] = cpu_to_le32(0x00000000);
1260 for (i = 4; i < 1024; ++i)
1261 msg[i] = cpu_to_le32(0x0);
1263 r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
1266 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
1271 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1273 struct amdgpu_device *adev =
1274 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1275 unsigned fences = 0, i, j;
1277 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1278 if (adev->uvd.harvest_config & (1 << i))
1280 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1281 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1282 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1287 if (adev->pm.dpm_enabled) {
1288 amdgpu_dpm_enable_uvd(adev, false);
1290 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1291 /* shutdown the UVD block */
1292 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1294 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1298 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1302 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1304 struct amdgpu_device *adev = ring->adev;
1307 if (amdgpu_sriov_vf(adev))
1310 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1312 if (adev->pm.dpm_enabled) {
1313 amdgpu_dpm_enable_uvd(adev, true);
1315 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1316 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1317 AMD_CG_STATE_UNGATE);
1318 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1319 AMD_PG_STATE_UNGATE);
1324 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1326 if (!amdgpu_sriov_vf(ring->adev))
1327 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1331 * amdgpu_uvd_ring_test_ib - test ib execution
1333 * @ring: amdgpu_ring pointer
1334 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1336 * Test if we can successfully execute an IB
1338 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1340 struct dma_fence *fence;
1343 r = amdgpu_uvd_get_create_msg(ring, 1, &fence);
1347 r = dma_fence_wait_timeout(fence, false, timeout);
1348 dma_fence_put(fence);
1354 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1358 r = dma_fence_wait_timeout(fence, false, timeout);
1364 dma_fence_put(fence);
1371 * amdgpu_uvd_used_handles - returns used UVD handles
1373 * @adev: amdgpu_device pointer
1375 * Returns the number of UVD handles in use
1377 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1380 uint32_t used_handles = 0;
1382 for (i = 0; i < adev->uvd.max_handles; ++i) {
1384 * Handles can be freed in any order, and not
1385 * necessarily linear. So we need to count
1386 * all non-zero handles.
1388 if (atomic_read(&adev->uvd.handles[i]))
1392 return used_handles;