2 * Driver for IBM PowerNV 842 compression accelerator
4 * Copyright (C) 2015 Dan Streetman, IBM Corp
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/timer.h>
24 #include <asm/icswx.h>
27 #include <asm/opal-api.h>
30 MODULE_LICENSE("GPL");
32 MODULE_DESCRIPTION("842 H/W Compression driver for IBM PowerNV processors");
33 MODULE_ALIAS_CRYPTO("842");
34 MODULE_ALIAS_CRYPTO("842-nx");
36 #define WORKMEM_ALIGN (CRB_ALIGN)
37 #define CSB_WAIT_MAX (5000) /* ms */
38 #define VAS_RETRIES (10)
39 /* # of requests allowed per RxFIFO at a time. 0 for unlimited */
40 #define MAX_CREDITS_PER_RXFIFO (1024)
42 struct nx842_workmem {
43 /* Below fields must be properly aligned */
44 struct coprocessor_request_block crb; /* CRB_ALIGN align */
45 struct data_descriptor_entry ddl_in[DDL_LEN_MAX]; /* DDE_ALIGN align */
46 struct data_descriptor_entry ddl_out[DDL_LEN_MAX]; /* DDE_ALIGN align */
47 /* Above fields must be properly aligned */
51 char padding[WORKMEM_ALIGN]; /* unused, to allow alignment */
52 } __packed __aligned(WORKMEM_ALIGN);
57 unsigned int ci; /* Coprocessor instance, used with icswx */
59 struct vas_window *rxwin;
62 struct list_head list;
66 * Send the request to NX engine on the chip for the corresponding CPU
67 * where the process is executing. Use with VAS function.
69 static DEFINE_PER_CPU(struct vas_window *, cpu_txwin);
71 /* no cpu hotplug on powernv, so this list never changes after init */
72 static LIST_HEAD(nx842_coprocs);
73 static unsigned int nx842_ct; /* used in icswx function */
75 static int (*nx842_powernv_exec)(const unsigned char *in,
76 unsigned int inlen, unsigned char *out,
77 unsigned int *outlenp, void *workmem, int fc);
80 * setup_indirect_dde - Setup an indirect DDE
82 * The DDE is setup with the the DDE count, byte count, and address of
83 * first direct DDE in the list.
85 static void setup_indirect_dde(struct data_descriptor_entry *dde,
86 struct data_descriptor_entry *ddl,
87 unsigned int dde_count, unsigned int byte_count)
90 dde->count = dde_count;
92 dde->length = cpu_to_be32(byte_count);
93 dde->address = cpu_to_be64(nx842_get_pa(ddl));
97 * setup_direct_dde - Setup single DDE from buffer
99 * The DDE is setup with the buffer and length. The buffer must be properly
100 * aligned. The used length is returned.
102 * N Successfully set up DDE with N bytes
104 static unsigned int setup_direct_dde(struct data_descriptor_entry *dde,
105 unsigned long pa, unsigned int len)
107 unsigned int l = min_t(unsigned int, len, LEN_ON_PAGE(pa));
112 dde->length = cpu_to_be32(l);
113 dde->address = cpu_to_be64(pa);
119 * setup_ddl - Setup DDL from buffer
122 * 0 Successfully set up DDL
124 static int setup_ddl(struct data_descriptor_entry *dde,
125 struct data_descriptor_entry *ddl,
126 unsigned char *buf, unsigned int len,
129 unsigned long pa = nx842_get_pa(buf);
130 int i, ret, total_len = len;
132 if (!IS_ALIGNED(pa, DDE_BUFFER_ALIGN)) {
133 pr_debug("%s buffer pa 0x%lx not 0x%x-byte aligned\n",
134 in ? "input" : "output", pa, DDE_BUFFER_ALIGN);
138 /* only need to check last mult; since buffer must be
139 * DDE_BUFFER_ALIGN aligned, and that is a multiple of
140 * DDE_BUFFER_SIZE_MULT, and pre-last page DDE buffers
141 * are guaranteed a multiple of DDE_BUFFER_SIZE_MULT.
143 if (len % DDE_BUFFER_LAST_MULT) {
144 pr_debug("%s buffer len 0x%x not a multiple of 0x%x\n",
145 in ? "input" : "output", len, DDE_BUFFER_LAST_MULT);
148 len = round_down(len, DDE_BUFFER_LAST_MULT);
151 /* use a single direct DDE */
152 if (len <= LEN_ON_PAGE(pa)) {
153 ret = setup_direct_dde(dde, pa, len);
159 for (i = 0; i < DDL_LEN_MAX && len > 0; i++) {
160 ret = setup_direct_dde(&ddl[i], pa, len);
163 pa = nx842_get_pa(buf);
167 pr_debug("0x%x total %s bytes 0x%x too many for DDL.\n",
168 total_len, in ? "input" : "output", len);
173 setup_indirect_dde(dde, ddl, i, total_len);
178 #define CSB_ERR(csb, msg, ...) \
179 pr_err("ERROR: " msg " : %02x %02x %02x %02x %08x\n", \
180 ##__VA_ARGS__, (csb)->flags, \
181 (csb)->cs, (csb)->cc, (csb)->ce, \
182 be32_to_cpu((csb)->count))
184 #define CSB_ERR_ADDR(csb, msg, ...) \
185 CSB_ERR(csb, msg " at %lx", ##__VA_ARGS__, \
186 (unsigned long)be64_to_cpu((csb)->address))
191 static int wait_for_csb(struct nx842_workmem *wmem,
192 struct coprocessor_status_block *csb)
194 ktime_t start = wmem->start, now = ktime_get();
195 ktime_t timeout = ktime_add_ms(start, CSB_WAIT_MAX);
197 while (!(READ_ONCE(csb->flags) & CSB_V)) {
200 if (ktime_after(now, timeout))
204 /* hw has updated csb and output buffer */
207 /* check CSB flags */
208 if (!(csb->flags & CSB_V)) {
209 CSB_ERR(csb, "CSB still not valid after %ld us, giving up",
210 (long)ktime_us_delta(now, start));
213 if (csb->flags & CSB_F) {
214 CSB_ERR(csb, "Invalid CSB format");
217 if (csb->flags & CSB_CH) {
218 CSB_ERR(csb, "Invalid CSB chaining state");
222 /* verify CSB completion sequence is 0 */
224 CSB_ERR(csb, "Invalid CSB completion sequence");
228 /* check CSB Completion Code */
233 case CSB_CC_TPBC_GT_SPBC:
234 /* not an error, but the compressed data is
235 * larger than the uncompressed data :(
239 /* input data errors */
240 case CSB_CC_OPERAND_OVERLAP:
241 /* input and output buffers overlap */
242 CSB_ERR(csb, "Operand Overlap error");
244 case CSB_CC_INVALID_OPERAND:
245 CSB_ERR(csb, "Invalid operand");
248 /* output buffer too small */
251 CSB_ERR(csb, "Function aborted");
253 case CSB_CC_CRC_MISMATCH:
254 CSB_ERR(csb, "CRC mismatch");
256 case CSB_CC_TEMPL_INVALID:
257 CSB_ERR(csb, "Compressed data template invalid");
259 case CSB_CC_TEMPL_OVERFLOW:
260 CSB_ERR(csb, "Compressed data template shows data past end");
262 case CSB_CC_EXCEED_BYTE_COUNT: /* P9 or later */
264 * DDE byte count exceeds the limit specified in Maximum
265 * byte count register.
267 CSB_ERR(csb, "DDE byte count exceeds the limit");
270 /* these should not happen */
271 case CSB_CC_INVALID_ALIGN:
272 /* setup_ddl should have detected this */
273 CSB_ERR_ADDR(csb, "Invalid alignment");
275 case CSB_CC_DATA_LENGTH:
276 /* setup_ddl should have detected this */
277 CSB_ERR(csb, "Invalid data length");
279 case CSB_CC_WR_TRANSLATION:
280 case CSB_CC_TRANSLATION:
281 case CSB_CC_TRANSLATION_DUP1:
282 case CSB_CC_TRANSLATION_DUP2:
283 case CSB_CC_TRANSLATION_DUP3:
284 case CSB_CC_TRANSLATION_DUP4:
285 case CSB_CC_TRANSLATION_DUP5:
286 case CSB_CC_TRANSLATION_DUP6:
287 /* should not happen, we use physical addrs */
288 CSB_ERR_ADDR(csb, "Translation error");
290 case CSB_CC_WR_PROTECTION:
291 case CSB_CC_PROTECTION:
292 case CSB_CC_PROTECTION_DUP1:
293 case CSB_CC_PROTECTION_DUP2:
294 case CSB_CC_PROTECTION_DUP3:
295 case CSB_CC_PROTECTION_DUP4:
296 case CSB_CC_PROTECTION_DUP5:
297 case CSB_CC_PROTECTION_DUP6:
298 /* should not happen, we use physical addrs */
299 CSB_ERR_ADDR(csb, "Protection error");
301 case CSB_CC_PRIVILEGE:
302 /* shouldn't happen, we're in HYP mode */
303 CSB_ERR(csb, "Insufficient Privilege error");
305 case CSB_CC_EXCESSIVE_DDE:
306 /* shouldn't happen, setup_ddl doesn't use many dde's */
307 CSB_ERR(csb, "Too many DDEs in DDL");
309 case CSB_CC_TRANSPORT:
310 case CSB_CC_INVALID_CRB: /* P9 or later */
311 /* shouldn't happen, we setup CRB correctly */
312 CSB_ERR(csb, "Invalid CRB");
314 case CSB_CC_INVALID_DDE: /* P9 or later */
316 * shouldn't happen, setup_direct/indirect_dde creates
319 CSB_ERR(csb, "Invalid DDE");
321 case CSB_CC_SEGMENTED_DDL:
322 /* shouldn't happen, setup_ddl creates DDL right */
323 CSB_ERR(csb, "Segmented DDL error");
325 case CSB_CC_DDE_OVERFLOW:
326 /* shouldn't happen, setup_ddl creates DDL right */
327 CSB_ERR(csb, "DDE overflow error");
330 /* should not happen with ICSWX */
331 CSB_ERR(csb, "Session violation error");
334 /* should not happen, we don't use chained CRBs */
335 CSB_ERR(csb, "Chained CRB error");
337 case CSB_CC_SEQUENCE:
338 /* should not happen, we don't use chained CRBs */
339 CSB_ERR(csb, "CRB sequence number error");
341 case CSB_CC_UNKNOWN_CODE:
342 CSB_ERR(csb, "Unknown subfunction code");
345 /* hardware errors */
346 case CSB_CC_RD_EXTERNAL:
347 case CSB_CC_RD_EXTERNAL_DUP1:
348 case CSB_CC_RD_EXTERNAL_DUP2:
349 case CSB_CC_RD_EXTERNAL_DUP3:
350 CSB_ERR_ADDR(csb, "Read error outside coprocessor");
352 case CSB_CC_WR_EXTERNAL:
353 CSB_ERR_ADDR(csb, "Write error outside coprocessor");
355 case CSB_CC_INTERNAL:
356 CSB_ERR(csb, "Internal error in coprocessor");
358 case CSB_CC_PROVISION:
359 CSB_ERR(csb, "Storage provision error");
362 CSB_ERR(csb, "Correctable hardware error");
364 case CSB_CC_HW_EXPIRED_TIMER: /* P9 or later */
365 CSB_ERR(csb, "Job did not finish within allowed time");
369 CSB_ERR(csb, "Invalid CC %d", csb->cc);
373 /* check Completion Extension state */
374 if (csb->ce & CSB_CE_TERMINATION) {
375 CSB_ERR(csb, "CSB request was terminated");
378 if (csb->ce & CSB_CE_INCOMPLETE) {
379 CSB_ERR(csb, "CSB request not complete");
382 if (!(csb->ce & CSB_CE_TPBC)) {
383 CSB_ERR(csb, "TPBC not provided, unknown target length");
387 /* successful completion */
388 pr_debug_ratelimited("Processed %u bytes in %lu us\n",
389 be32_to_cpu(csb->count),
390 (unsigned long)ktime_us_delta(now, start));
395 static int nx842_config_crb(const unsigned char *in, unsigned int inlen,
396 unsigned char *out, unsigned int outlen,
397 struct nx842_workmem *wmem)
399 struct coprocessor_request_block *crb;
400 struct coprocessor_status_block *csb;
407 /* Clear any previous values */
408 memset(crb, 0, sizeof(*crb));
411 ret = setup_ddl(&crb->source, wmem->ddl_in,
412 (unsigned char *)in, inlen, true);
416 ret = setup_ddl(&crb->target, wmem->ddl_out,
421 /* set up CRB's CSB addr */
422 csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
423 csb_addr |= CRB_CSB_AT; /* Addrs are phys */
424 crb->csb_addr = cpu_to_be64(csb_addr);
430 * nx842_exec_icswx - compress/decompress data using the 842 algorithm
432 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
433 * This compresses or decompresses the provided input buffer into the provided
436 * Upon return from this function @outlen contains the length of the
437 * output data. If there is an error then @outlen will be 0 and an
438 * error will be specified by the return code from this function.
440 * The @workmem buffer should only be used by one function call at a time.
442 * @in: input buffer pointer
443 * @inlen: input buffer size
444 * @out: output buffer pointer
445 * @outlenp: output buffer size pointer
446 * @workmem: working memory buffer pointer, size determined by
447 * nx842_powernv_driver.workmem_size
448 * @fc: function code, see CCW Function Codes in nx-842.h
451 * 0 Success, output of length @outlenp stored in the buffer at @out
452 * -ENODEV Hardware unavailable
453 * -ENOSPC Output buffer is to small
454 * -EMSGSIZE Input buffer too large
455 * -EINVAL buffer constraints do not fix nx842_constraints
456 * -EPROTO hardware error during operation
457 * -ETIMEDOUT hardware did not complete operation in reasonable time
458 * -EINTR operation was aborted
460 static int nx842_exec_icswx(const unsigned char *in, unsigned int inlen,
461 unsigned char *out, unsigned int *outlenp,
462 void *workmem, int fc)
464 struct coprocessor_request_block *crb;
465 struct coprocessor_status_block *csb;
466 struct nx842_workmem *wmem;
469 unsigned int outlen = *outlenp;
471 wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
475 /* shoudn't happen, we don't load without a coproc */
477 pr_err_ratelimited("coprocessor CT is 0");
481 ret = nx842_config_crb(in, inlen, out, outlen, wmem);
490 ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
491 ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
492 ccw = SET_FIELD(CCW_FC_842, ccw, fc);
494 wmem->start = ktime_get();
497 ret = icswx(cpu_to_be32(ccw), crb);
499 pr_debug_ratelimited("icswx CR %x ccw %x crb->ccw %x\n", ret,
501 (unsigned int)be32_to_cpu(crb->ccw));
504 * NX842 coprocessor sets 3rd bit in CR register with XER[S0].
505 * XER[S0] is the integer summary overflow bit which is nothing
506 * to do NX. Since this bit can be set with other return values,
512 case ICSWX_INITIATED:
513 ret = wait_for_csb(wmem, csb);
516 pr_debug_ratelimited("842 Coprocessor busy\n");
520 pr_err_ratelimited("ICSWX rejected\n");
526 *outlenp = be32_to_cpu(csb->count);
532 * nx842_exec_vas - compress/decompress data using the 842 algorithm
534 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
535 * This compresses or decompresses the provided input buffer into the provided
538 * Upon return from this function @outlen contains the length of the
539 * output data. If there is an error then @outlen will be 0 and an
540 * error will be specified by the return code from this function.
542 * The @workmem buffer should only be used by one function call at a time.
544 * @in: input buffer pointer
545 * @inlen: input buffer size
546 * @out: output buffer pointer
547 * @outlenp: output buffer size pointer
548 * @workmem: working memory buffer pointer, size determined by
549 * nx842_powernv_driver.workmem_size
550 * @fc: function code, see CCW Function Codes in nx-842.h
553 * 0 Success, output of length @outlenp stored in the buffer
555 * -ENODEV Hardware unavailable
556 * -ENOSPC Output buffer is to small
557 * -EMSGSIZE Input buffer too large
558 * -EINVAL buffer constraints do not fix nx842_constraints
559 * -EPROTO hardware error during operation
560 * -ETIMEDOUT hardware did not complete operation in reasonable time
561 * -EINTR operation was aborted
563 static int nx842_exec_vas(const unsigned char *in, unsigned int inlen,
564 unsigned char *out, unsigned int *outlenp,
565 void *workmem, int fc)
567 struct coprocessor_request_block *crb;
568 struct coprocessor_status_block *csb;
569 struct nx842_workmem *wmem;
570 struct vas_window *txwin;
573 unsigned int outlen = *outlenp;
575 wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
582 ret = nx842_config_crb(in, inlen, out, outlen, wmem);
587 ccw = SET_FIELD(CCW_FC_842, ccw, fc);
588 crb->ccw = cpu_to_be32(ccw);
591 wmem->start = ktime_get();
593 txwin = this_cpu_read(cpu_txwin);
596 * VAS copy CRB into L2 cache. Refer <asm/vas.h>.
599 vas_copy_crb(crb, 0);
602 * VAS paste previously copied CRB to NX.
603 * @txwin, @offset and @last (must be true).
605 ret = vas_paste_crb(txwin, 0, 1);
608 * Retry copy/paste function for VAS failures.
610 } while (ret && (i++ < VAS_RETRIES));
613 pr_err_ratelimited("VAS copy/paste failed\n");
617 ret = wait_for_csb(wmem, csb);
619 *outlenp = be32_to_cpu(csb->count);
625 * nx842_powernv_compress - Compress data using the 842 algorithm
627 * Compression provided by the NX842 coprocessor on IBM PowerNV systems.
628 * The input buffer is compressed and the result is stored in the
629 * provided output buffer.
631 * Upon return from this function @outlen contains the length of the
632 * compressed data. If there is an error then @outlen will be 0 and an
633 * error will be specified by the return code from this function.
635 * @in: input buffer pointer
636 * @inlen: input buffer size
637 * @out: output buffer pointer
638 * @outlenp: output buffer size pointer
639 * @workmem: working memory buffer pointer, size determined by
640 * nx842_powernv_driver.workmem_size
642 * Returns: see @nx842_powernv_exec()
644 static int nx842_powernv_compress(const unsigned char *in, unsigned int inlen,
645 unsigned char *out, unsigned int *outlenp,
648 return nx842_powernv_exec(in, inlen, out, outlenp,
649 wmem, CCW_FC_842_COMP_CRC);
653 * nx842_powernv_decompress - Decompress data using the 842 algorithm
655 * Decompression provided by the NX842 coprocessor on IBM PowerNV systems.
656 * The input buffer is decompressed and the result is stored in the
657 * provided output buffer.
659 * Upon return from this function @outlen contains the length of the
660 * decompressed data. If there is an error then @outlen will be 0 and an
661 * error will be specified by the return code from this function.
663 * @in: input buffer pointer
664 * @inlen: input buffer size
665 * @out: output buffer pointer
666 * @outlenp: output buffer size pointer
667 * @workmem: working memory buffer pointer, size determined by
668 * nx842_powernv_driver.workmem_size
670 * Returns: see @nx842_powernv_exec()
672 static int nx842_powernv_decompress(const unsigned char *in, unsigned int inlen,
673 unsigned char *out, unsigned int *outlenp,
676 return nx842_powernv_exec(in, inlen, out, outlenp,
677 wmem, CCW_FC_842_DECOMP_CRC);
680 static inline void nx842_add_coprocs_list(struct nx842_coproc *coproc,
683 coproc->chip_id = chipid;
684 INIT_LIST_HEAD(&coproc->list);
685 list_add(&coproc->list, &nx842_coprocs);
688 static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)
690 struct vas_window *txwin = NULL;
691 struct vas_tx_win_attr txattr;
694 * Kernel requests will be high priority. So open send
695 * windows only for high priority RxFIFO entries.
697 vas_init_tx_win_attr(&txattr, coproc->ct);
698 txattr.lpid = 0; /* lpid is 0 for kernel requests */
699 txattr.pid = 0; /* pid is 0 for kernel requests */
702 * Open a VAS send window which is used to send request to NX.
704 txwin = vas_tx_win_open(coproc->vas.id, coproc->ct, &txattr);
706 pr_err("ibm,nx-842: Can not open TX window: %ld\n",
713 * Identify chip ID for each CPU, open send wndow for the corresponding NX
714 * engine and save txwin in percpu cpu_txwin.
715 * cpu_txwin is used in copy/paste operation for each compression /
716 * decompression request.
718 static int nx842_open_percpu_txwins(void)
720 struct nx842_coproc *coproc, *n;
721 unsigned int i, chip_id;
723 for_each_possible_cpu(i) {
724 struct vas_window *txwin = NULL;
726 chip_id = cpu_to_chip_id(i);
728 list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
730 * Kernel requests use only high priority FIFOs. So
731 * open send windows for these FIFOs.
734 if (coproc->ct != VAS_COP_TYPE_842_HIPRI)
737 if (coproc->chip_id == chip_id) {
738 txwin = nx842_alloc_txwin(coproc);
740 return PTR_ERR(txwin);
742 per_cpu(cpu_txwin, i) = txwin;
747 if (!per_cpu(cpu_txwin, i)) {
748 /* shouldn't happen, Each chip will have NX engine */
749 pr_err("NX engine is not available for CPU %d\n", i);
757 static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
760 struct vas_window *rxwin = NULL;
761 struct vas_rx_win_attr rxattr;
762 struct nx842_coproc *coproc;
763 u32 lpid, pid, tid, fifo_size;
765 const char *priority;
768 ret = of_property_read_u64(dn, "rx-fifo-address", &rx_fifo);
770 pr_err("Missing rx-fifo-address property\n");
774 ret = of_property_read_u32(dn, "rx-fifo-size", &fifo_size);
776 pr_err("Missing rx-fifo-size property\n");
780 ret = of_property_read_u32(dn, "lpid", &lpid);
782 pr_err("Missing lpid property\n");
786 ret = of_property_read_u32(dn, "pid", &pid);
788 pr_err("Missing pid property\n");
792 ret = of_property_read_u32(dn, "tid", &tid);
794 pr_err("Missing tid property\n");
798 ret = of_property_read_string(dn, "priority", &priority);
800 pr_err("Missing priority property\n");
804 coproc = kzalloc(sizeof(*coproc), GFP_KERNEL);
808 if (!strcmp(priority, "High"))
809 coproc->ct = VAS_COP_TYPE_842_HIPRI;
810 else if (!strcmp(priority, "Normal"))
811 coproc->ct = VAS_COP_TYPE_842;
813 pr_err("Invalid RxFIFO priority value\n");
818 vas_init_rx_win_attr(&rxattr, coproc->ct);
819 rxattr.rx_fifo = (void *)rx_fifo;
820 rxattr.rx_fifo_size = fifo_size;
821 rxattr.lnotify_lpid = lpid;
822 rxattr.lnotify_pid = pid;
823 rxattr.lnotify_tid = tid;
824 rxattr.wcreds_max = MAX_CREDITS_PER_RXFIFO;
827 * Open a VAS receice window which is used to configure RxFIFO
830 rxwin = vas_rx_win_open(vasid, coproc->ct, &rxattr);
832 ret = PTR_ERR(rxwin);
833 pr_err("setting RxFIFO with VAS failed: %d\n",
838 coproc->vas.rxwin = rxwin;
839 coproc->vas.id = vasid;
840 nx842_add_coprocs_list(coproc, chip_id);
843 * (lpid, pid, tid) combination has to be unique for each
844 * coprocessor instance in the system. So to make it
845 * unique, skiboot uses coprocessor type such as 842 or
846 * GZIP for pid and provides this value to kernel in pid
847 * device-tree property.
859 static int __init nx842_powernv_probe_vas(struct device_node *pn)
861 struct device_node *dn;
862 int chip_id, vasid, ret = 0;
863 int nx_fifo_found = 0;
864 int uninitialized_var(ct);
866 chip_id = of_get_ibm_chip_id(pn);
868 pr_err("ibm,chip-id missing\n");
872 vasid = chip_to_vas_id(chip_id);
874 pr_err("Unable to map chip_id %d to vasid\n", chip_id);
878 for_each_child_of_node(pn, dn) {
879 if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
880 ret = vas_cfg_coproc_info(dn, chip_id, vasid, &ct);
889 if (!nx_fifo_found) {
890 pr_err("NX842 FIFO nodes are missing\n");
895 * Initialize NX instance for both high and normal priority FIFOs.
897 if (opal_check_token(OPAL_NX_COPROC_INIT)) {
898 ret = opal_nx_coproc_init(chip_id, ct);
900 pr_err("Failed to initialize NX for chip(%d): %d\n",
902 ret = opal_error_code(ret);
905 pr_warn("Firmware doesn't support NX initialization\n");
910 static int __init nx842_powernv_probe(struct device_node *dn)
912 struct nx842_coproc *coproc;
916 chip_id = of_get_ibm_chip_id(dn);
918 pr_err("ibm,chip-id missing\n");
922 if (of_property_read_u32(dn, "ibm,842-coprocessor-type", &ct)) {
923 pr_err("ibm,842-coprocessor-type missing\n");
927 if (of_property_read_u32(dn, "ibm,842-coprocessor-instance", &ci)) {
928 pr_err("ibm,842-coprocessor-instance missing\n");
932 coproc = kmalloc(sizeof(*coproc), GFP_KERNEL);
938 nx842_add_coprocs_list(coproc, chip_id);
940 pr_info("coprocessor found on chip %d, CT %d CI %d\n", chip_id, ct, ci);
944 else if (nx842_ct != ct)
945 pr_err("NX842 chip %d, CT %d != first found CT %d\n",
946 chip_id, ct, nx842_ct);
951 static void nx842_delete_coprocs(void)
953 struct nx842_coproc *coproc, *n;
954 struct vas_window *txwin;
958 * close percpu txwins that are opened for the corresponding coproc.
960 for_each_possible_cpu(i) {
961 txwin = per_cpu(cpu_txwin, i);
963 vas_win_close(txwin);
965 per_cpu(cpu_txwin, i) = 0;
968 list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
969 if (coproc->vas.rxwin)
970 vas_win_close(coproc->vas.rxwin);
972 list_del(&coproc->list);
977 static struct nx842_constraints nx842_powernv_constraints = {
978 .alignment = DDE_BUFFER_ALIGN,
979 .multiple = DDE_BUFFER_LAST_MULT,
980 .minimum = DDE_BUFFER_LAST_MULT,
981 .maximum = (DDL_LEN_MAX - 1) * PAGE_SIZE,
984 static struct nx842_driver nx842_powernv_driver = {
985 .name = KBUILD_MODNAME,
986 .owner = THIS_MODULE,
987 .workmem_size = sizeof(struct nx842_workmem),
988 .constraints = &nx842_powernv_constraints,
989 .compress = nx842_powernv_compress,
990 .decompress = nx842_powernv_decompress,
993 static int nx842_powernv_crypto_init(struct crypto_tfm *tfm)
995 return nx842_crypto_init(tfm, &nx842_powernv_driver);
998 static struct crypto_alg nx842_powernv_alg = {
1000 .cra_driver_name = "842-nx",
1001 .cra_priority = 300,
1002 .cra_flags = CRYPTO_ALG_TYPE_COMPRESS,
1003 .cra_ctxsize = sizeof(struct nx842_crypto_ctx),
1004 .cra_module = THIS_MODULE,
1005 .cra_init = nx842_powernv_crypto_init,
1006 .cra_exit = nx842_crypto_exit,
1007 .cra_u = { .compress = {
1008 .coa_compress = nx842_crypto_compress,
1009 .coa_decompress = nx842_crypto_decompress } }
1012 static __init int nx842_powernv_init(void)
1014 struct device_node *dn;
1017 /* verify workmem size/align restrictions */
1018 BUILD_BUG_ON(WORKMEM_ALIGN % CRB_ALIGN);
1019 BUILD_BUG_ON(CRB_ALIGN % DDE_ALIGN);
1020 BUILD_BUG_ON(CRB_SIZE % DDE_ALIGN);
1021 /* verify buffer size/align restrictions */
1022 BUILD_BUG_ON(PAGE_SIZE % DDE_BUFFER_ALIGN);
1023 BUILD_BUG_ON(DDE_BUFFER_ALIGN % DDE_BUFFER_SIZE_MULT);
1024 BUILD_BUG_ON(DDE_BUFFER_SIZE_MULT % DDE_BUFFER_LAST_MULT);
1026 for_each_compatible_node(dn, NULL, "ibm,power9-nx") {
1027 ret = nx842_powernv_probe_vas(dn);
1029 nx842_delete_coprocs();
1034 if (list_empty(&nx842_coprocs)) {
1035 for_each_compatible_node(dn, NULL, "ibm,power-nx")
1036 nx842_powernv_probe(dn);
1041 nx842_powernv_exec = nx842_exec_icswx;
1043 ret = nx842_open_percpu_txwins();
1045 nx842_delete_coprocs();
1049 nx842_powernv_exec = nx842_exec_vas;
1052 ret = crypto_register_alg(&nx842_powernv_alg);
1054 nx842_delete_coprocs();
1060 module_init(nx842_powernv_init);
1062 static void __exit nx842_powernv_exit(void)
1064 crypto_unregister_alg(&nx842_powernv_alg);
1066 nx842_delete_coprocs();
1068 module_exit(nx842_powernv_exit);