drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amd_pcie.h"
  44 #ifdef CONFIG_DRM_AMDGPU_SI
  45 #include "si.h"
  46 #endif
  47 #ifdef CONFIG_DRM_AMDGPU_CIK
  48 #include "cik.h"
  49 #endif
  50 #include "vi.h"
  51 #include "bif/bif_4_1_d.h"
  52 #include <linux/pci.h>
  53 #include <linux/firmware.h>
  54
  55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  57
  58 static const char *amdgpu_asic_name[] = {
  59         "TAHITI",
  60         "PITCAIRN",
  61         "VERDE",
  62         "OLAND",
  63         "HAINAN",
  64         "BONAIRE",
  65         "KAVERI",
  66         "KABINI",
  67         "HAWAII",
  68         "MULLINS",
  69         "TOPAZ",
  70         "TONGA",
  71         "FIJI",
  72         "CARRIZO",
  73         "STONEY",
  74         "POLARIS10",
  75         "POLARIS11",
  76         "LAST",
  77 };
  78
  79 bool amdgpu_device_is_px(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev->flags & AMD_IS_PX)
  84                 return true;
  85         return false;
  86 }
  87
  88 /*
  89  * MMIO register access helper functions.
  90  */
  91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  92                         bool always_indirect)
  93 {
  94         uint32_t ret;
  95
  96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  97                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
  98         else {
  99                 unsigned long flags;
 100
 101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 103                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 105         }
 106         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 107         return ret;
 108 }
 109
 110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 111                     bool always_indirect)
 112 {
 113         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 114
 115         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 116                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 117         else {
 118                 unsigned long flags;
 119
 120                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 121                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 122                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 123                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 124         }
 125 }
 126
 127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 128 {
 129         if ((reg * 4) < adev->rio_mem_size)
 130                 return ioread32(adev->rio_mem + (reg * 4));
 131         else {
 132                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 133                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 134         }
 135 }
 136
 137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 138 {
 139
 140         if ((reg * 4) < adev->rio_mem_size)
 141                 iowrite32(v, adev->rio_mem + (reg * 4));
 142         else {
 143                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 144                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 145         }
 146 }
 147
 148 /**
 149  * amdgpu_mm_rdoorbell - read a doorbell dword
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @index: doorbell index
 153  *
 154  * Returns the value in the doorbell aperture at the
 155  * requested doorbell index (CIK).
 156  */
 157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 158 {
 159         if (index < adev->doorbell.num_doorbells) {
 160                 return readl(adev->doorbell.ptr + index);
 161         } else {
 162                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 163                 return 0;
 164         }
 165 }
 166
 167 /**
 168  * amdgpu_mm_wdoorbell - write a doorbell dword
 169  *
 170  * @adev: amdgpu_device pointer
 171  * @index: doorbell index
 172  * @v: value to write
 173  *
 174  * Writes @v to the doorbell aperture at the
 175  * requested doorbell index (CIK).
 176  */
 177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 178 {
 179         if (index < adev->doorbell.num_doorbells) {
 180                 writel(v, adev->doorbell.ptr + index);
 181         } else {
 182                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 183         }
 184 }
 185
 186 /**
 187  * amdgpu_invalid_rreg - dummy reg read function
 188  *
 189  * @adev: amdgpu device pointer
 190  * @reg: offset of register
 191  *
 192  * Dummy register read function.  Used for register blocks
 193  * that certain asics don't have (all asics).
 194  * Returns the value in the register.
 195  */
 196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 197 {
 198         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 199         BUG();
 200         return 0;
 201 }
 202
 203 /**
 204  * amdgpu_invalid_wreg - dummy reg write function
 205  *
 206  * @adev: amdgpu device pointer
 207  * @reg: offset of register
 208  * @v: value to write to the register
 209  *
 210  * Dummy register read function.  Used for register blocks
 211  * that certain asics don't have (all asics).
 212  */
 213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 214 {
 215         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 216                   reg, v);
 217         BUG();
 218 }
 219
 220 /**
 221  * amdgpu_block_invalid_rreg - dummy reg read function
 222  *
 223  * @adev: amdgpu device pointer
 224  * @block: offset of instance
 225  * @reg: offset of register
 226  *
 227  * Dummy register read function.  Used for register blocks
 228  * that certain asics don't have (all asics).
 229  * Returns the value in the register.
 230  */
 231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 232                                           uint32_t block, uint32_t reg)
 233 {
 234         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 235                   reg, block);
 236         BUG();
 237         return 0;
 238 }
 239
 240 /**
 241  * amdgpu_block_invalid_wreg - dummy reg write function
 242  *
 243  * @adev: amdgpu device pointer
 244  * @block: offset of instance
 245  * @reg: offset of register
 246  * @v: value to write to the register
 247  *
 248  * Dummy register read function.  Used for register blocks
 249  * that certain asics don't have (all asics).
 250  */
 251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 252                                       uint32_t block,
 253                                       uint32_t reg, uint32_t v)
 254 {
 255         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 256                   reg, block, v);
 257         BUG();
 258 }
 259
 260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 261 {
 262         int r;
 263
 264         if (adev->vram_scratch.robj == NULL) {
 265                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 266                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 267                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 268                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 269                                      NULL, NULL, &adev->vram_scratch.robj);
 270                 if (r) {
 271                         return r;
 272                 }
 273         }
 274
 275         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 276         if (unlikely(r != 0))
 277                 return r;
 278         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 279                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 280         if (r) {
 281                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 282                 return r;
 283         }
 284         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 285                                 (void **)&adev->vram_scratch.ptr);
 286         if (r)
 287                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 288         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 289
 290         return r;
 291 }
 292
 293 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 294 {
 295         int r;
 296
 297         if (adev->vram_scratch.robj == NULL) {
 298                 return;
 299         }
 300         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 301         if (likely(r == 0)) {
 302                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 303                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 304                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 305         }
 306         amdgpu_bo_unref(&adev->vram_scratch.robj);
 307 }
 308
 309 /**
 310  * amdgpu_program_register_sequence - program an array of registers.
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @registers: pointer to the register array
 314  * @array_size: size of the register array
 315  *
 316  * Programs an array or registers with and and or masks.
 317  * This is a helper for setting golden registers.
 318  */
 319 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 320                                       const u32 *registers,
 321                                       const u32 array_size)
 322 {
 323         u32 tmp, reg, and_mask, or_mask;
 324         int i;
 325
 326         if (array_size % 3)
 327                 return;
 328
 329         for (i = 0; i < array_size; i +=3) {
 330                 reg = registers[i + 0];
 331                 and_mask = registers[i + 1];
 332                 or_mask = registers[i + 2];
 333
 334                 if (and_mask == 0xffffffff) {
 335                         tmp = or_mask;
 336                 } else {
 337                         tmp = RREG32(reg);
 338                         tmp &= ~and_mask;
 339                         tmp |= or_mask;
 340                 }
 341                 WREG32(reg, tmp);
 342         }
 343 }
 344
 345 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 346 {
 347         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 348 }
 349
 350 /*
 351  * GPU doorbell aperture helpers function.
 352  */
 353 /**
 354  * amdgpu_doorbell_init - Init doorbell driver information.
 355  *
 356  * @adev: amdgpu_device pointer
 357  *
 358  * Init doorbell driver information (CIK)
 359  * Returns 0 on success, error on failure.
 360  */
 361 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 362 {
 363         /* doorbell bar mapping */
 364         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 365         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 366
 367         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 368                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 369         if (adev->doorbell.num_doorbells == 0)
 370                 return -EINVAL;
 371
 372         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 373         if (adev->doorbell.ptr == NULL) {
 374                 return -ENOMEM;
 375         }
 376         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 377         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 378
 379         return 0;
 380 }
 381
 382 /**
 383  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 384  *
 385  * @adev: amdgpu_device pointer
 386  *
 387  * Tear down doorbell driver information (CIK)
 388  */
 389 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 390 {
 391         iounmap(adev->doorbell.ptr);
 392         adev->doorbell.ptr = NULL;
 393 }
 394
 395 /**
 396  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 397  *                                setup amdkfd
 398  *
 399  * @adev: amdgpu_device pointer
 400  * @aperture_base: output returning doorbell aperture base physical address
 401  * @aperture_size: output returning doorbell aperture size in bytes
 402  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 403  *
 404  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 405  * takes doorbells required for its own rings and reports the setup to amdkfd.
 406  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 407  */
 408 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 409                                 phys_addr_t *aperture_base,
 410                                 size_t *aperture_size,
 411                                 size_t *start_offset)
 412 {
 413         /*
 414          * The first num_doorbells are used by amdgpu.
 415          * amdkfd takes whatever's left in the aperture.
 416          */
 417         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 418                 *aperture_base = adev->doorbell.base;
 419                 *aperture_size = adev->doorbell.size;
 420                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 421         } else {
 422                 *aperture_base = 0;
 423                 *aperture_size = 0;
 424                 *start_offset = 0;
 425         }
 426 }
 427
 428 /*
 429  * amdgpu_wb_*()
 430  * Writeback is the the method by which the the GPU updates special pages
 431  * in memory with the status of certain GPU events (fences, ring pointers,
 432  * etc.).
 433  */
 434
 435 /**
 436  * amdgpu_wb_fini - Disable Writeback and free memory
 437  *
 438  * @adev: amdgpu_device pointer
 439  *
 440  * Disables Writeback and frees the Writeback memory (all asics).
 441  * Used at driver shutdown.
 442  */
 443 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 444 {
 445         if (adev->wb.wb_obj) {
 446                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 447                                       &adev->wb.gpu_addr,
 448                                       (void **)&adev->wb.wb);
 449                 adev->wb.wb_obj = NULL;
 450         }
 451 }
 452
 453 /**
 454  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 455  *
 456  * @adev: amdgpu_device pointer
 457  *
 458  * Disables Writeback and frees the Writeback memory (all asics).
 459  * Used at driver startup.
 460  * Returns 0 on success or an -error on failure.
 461  */
 462 static int amdgpu_wb_init(struct amdgpu_device *adev)
 463 {
 464         int r;
 465
 466         if (adev->wb.wb_obj == NULL) {
 467                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4,
 468                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 469                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 470                                             (void **)&adev->wb.wb);
 471                 if (r) {
 472                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 473                         return r;
 474                 }
 475
 476                 adev->wb.num_wb = AMDGPU_MAX_WB;
 477                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 478
 479                 /* clear wb memory */
 480                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 481         }
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * amdgpu_wb_get - Allocate a wb entry
 488  *
 489  * @adev: amdgpu_device pointer
 490  * @wb: wb index
 491  *
 492  * Allocate a wb slot for use by the driver (all asics).
 493  * Returns 0 on success or -EINVAL on failure.
 494  */
 495 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 496 {
 497         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 498         if (offset < adev->wb.num_wb) {
 499                 __set_bit(offset, adev->wb.used);
 500                 *wb = offset;
 501                 return 0;
 502         } else {
 503                 return -EINVAL;
 504         }
 505 }
 506
 507 /**
 508  * amdgpu_wb_free - Free a wb entry
 509  *
 510  * @adev: amdgpu_device pointer
 511  * @wb: wb index
 512  *
 513  * Free a wb slot allocated for use by the driver (all asics)
 514  */
 515 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 516 {
 517         if (wb < adev->wb.num_wb)
 518                 __clear_bit(wb, adev->wb.used);
 519 }
 520
 521 /**
 522  * amdgpu_vram_location - try to find VRAM location
 523  * @adev: amdgpu device structure holding all necessary informations
 524  * @mc: memory controller structure holding memory informations
 525  * @base: base address at which to put VRAM
 526  *
 527  * Function will place try to place VRAM at base address provided
 528  * as parameter (which is so far either PCI aperture address or
 529  * for IGP TOM base address).
 530  *
 531  * If there is not enough space to fit the unvisible VRAM in the 32bits
 532  * address space then we limit the VRAM size to the aperture.
 533  *
 534  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 535  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 536  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 537  * not IGP.
 538  *
 539  * Note: we use mc_vram_size as on some board we need to program the mc to
 540  * cover the whole aperture even if VRAM size is inferior to aperture size
 541  * Novell bug 204882 + along with lots of ubuntu ones
 542  *
 543  * Note: when limiting vram it's safe to overwritte real_vram_size because
 544  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 545  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 546  * ones)
 547  *
 548  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 549  * explicitly check for that thought.
 550  *
 551  * FIXME: when reducing VRAM size align new size on power of 2.
 552  */
 553 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 554 {
 555         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 556
 557         mc->vram_start = base;
 558         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 559                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 560                 mc->real_vram_size = mc->aper_size;
 561                 mc->mc_vram_size = mc->aper_size;
 562         }
 563         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 564         if (limit && limit < mc->real_vram_size)
 565                 mc->real_vram_size = limit;
 566         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 567                         mc->mc_vram_size >> 20, mc->vram_start,
 568                         mc->vram_end, mc->real_vram_size >> 20);
 569 }
 570
 571 /**
 572  * amdgpu_gtt_location - try to find GTT location
 573  * @adev: amdgpu device structure holding all necessary informations
 574  * @mc: memory controller structure holding memory informations
 575  *
 576  * Function will place try to place GTT before or after VRAM.
 577  *
 578  * If GTT size is bigger than space left then we ajust GTT size.
 579  * Thus function will never fails.
 580  *
 581  * FIXME: when reducing GTT size align new size on power of 2.
 582  */
 583 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 584 {
 585         u64 size_af, size_bf;
 586
 587         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 588         size_bf = mc->vram_start & ~mc->gtt_base_align;
 589         if (size_bf > size_af) {
 590                 if (mc->gtt_size > size_bf) {
 591                         dev_warn(adev->dev, "limiting GTT\n");
 592                         mc->gtt_size = size_bf;
 593                 }
 594                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 595         } else {
 596                 if (mc->gtt_size > size_af) {
 597                         dev_warn(adev->dev, "limiting GTT\n");
 598                         mc->gtt_size = size_af;
 599                 }
 600                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 601         }
 602         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 603         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 604                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 605 }
 606
 607 /*
 608  * GPU helpers function.
 609  */
 610 /**
 611  * amdgpu_card_posted - check if the hw has already been initialized
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Check if the asic has been initialized (all asics).
 616  * Used at driver startup.
 617  * Returns true if initialized or false if not.
 618  */
 619 bool amdgpu_card_posted(struct amdgpu_device *adev)
 620 {
 621         uint32_t reg;
 622
 623         /* then check MEM_SIZE, in case the crtcs are off */
 624         reg = RREG32(mmCONFIG_MEMSIZE);
 625
 626         if (reg)
 627                 return true;
 628
 629         return false;
 630
 631 }
 632
 633 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
 634 {
 635         if (amdgpu_sriov_vf(adev))
 636                 return false;
 637
 638         if (amdgpu_passthrough(adev)) {
 639                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 640                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 641                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 642                  * vpost executed for smc version below 22.15
 643                  */
 644                 if (adev->asic_type == CHIP_FIJI) {
 645                         int err;
 646                         uint32_t fw_ver;
 647                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 648                         /* force vPost if error occured */
 649                         if (err)
 650                                 return true;
 651
 652                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 653                         if (fw_ver < 0x00160e00)
 654                                 return true;
 655                 }
 656         }
 657         return !amdgpu_card_posted(adev);
 658 }
 659
 660 /**
 661  * amdgpu_dummy_page_init - init dummy page used by the driver
 662  *
 663  * @adev: amdgpu_device pointer
 664  *
 665  * Allocate the dummy page used by the driver (all asics).
 666  * This dummy page is used by the driver as a filler for gart entries
 667  * when pages are taken out of the GART
 668  * Returns 0 on sucess, -ENOMEM on failure.
 669  */
 670 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 671 {
 672         if (adev->dummy_page.page)
 673                 return 0;
 674         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 675         if (adev->dummy_page.page == NULL)
 676                 return -ENOMEM;
 677         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 678                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 679         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 680                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 681                 __free_page(adev->dummy_page.page);
 682                 adev->dummy_page.page = NULL;
 683                 return -ENOMEM;
 684         }
 685         return 0;
 686 }
 687
 688 /**
 689  * amdgpu_dummy_page_fini - free dummy page used by the driver
 690  *
 691  * @adev: amdgpu_device pointer
 692  *
 693  * Frees the dummy page used by the driver (all asics).
 694  */
 695 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 696 {
 697         if (adev->dummy_page.page == NULL)
 698                 return;
 699         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 700                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 701         __free_page(adev->dummy_page.page);
 702         adev->dummy_page.page = NULL;
 703 }
 704
 705
 706 /* ATOM accessor methods */
 707 /*
 708  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 709  * driver registers callbacks to access registers and the interpreter
 710  * in the driver parses the tables and executes then to program specific
 711  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 712  * atombios.h, and atom.c
 713  */
 714
 715 /**
 716  * cail_pll_read - read PLL register
 717  *
 718  * @info: atom card_info pointer
 719  * @reg: PLL register offset
 720  *
 721  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 722  * Returns the value of the PLL register.
 723  */
 724 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 725 {
 726         return 0;
 727 }
 728
 729 /**
 730  * cail_pll_write - write PLL register
 731  *
 732  * @info: atom card_info pointer
 733  * @reg: PLL register offset
 734  * @val: value to write to the pll register
 735  *
 736  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 737  */
 738 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 739 {
 740
 741 }
 742
 743 /**
 744  * cail_mc_read - read MC (Memory Controller) register
 745  *
 746  * @info: atom card_info pointer
 747  * @reg: MC register offset
 748  *
 749  * Provides an MC register accessor for the atom interpreter (r4xx+).
 750  * Returns the value of the MC register.
 751  */
 752 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 753 {
 754         return 0;
 755 }
 756
 757 /**
 758  * cail_mc_write - write MC (Memory Controller) register
 759  *
 760  * @info: atom card_info pointer
 761  * @reg: MC register offset
 762  * @val: value to write to the pll register
 763  *
 764  * Provides a MC register accessor for the atom interpreter (r4xx+).
 765  */
 766 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 767 {
 768
 769 }
 770
 771 /**
 772  * cail_reg_write - write MMIO register
 773  *
 774  * @info: atom card_info pointer
 775  * @reg: MMIO register offset
 776  * @val: value to write to the pll register
 777  *
 778  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 779  */
 780 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 781 {
 782         struct amdgpu_device *adev = info->dev->dev_private;
 783
 784         WREG32(reg, val);
 785 }
 786
 787 /**
 788  * cail_reg_read - read MMIO register
 789  *
 790  * @info: atom card_info pointer
 791  * @reg: MMIO register offset
 792  *
 793  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 794  * Returns the value of the MMIO register.
 795  */
 796 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 797 {
 798         struct amdgpu_device *adev = info->dev->dev_private;
 799         uint32_t r;
 800
 801         r = RREG32(reg);
 802         return r;
 803 }
 804
 805 /**
 806  * cail_ioreg_write - write IO register
 807  *
 808  * @info: atom card_info pointer
 809  * @reg: IO register offset
 810  * @val: value to write to the pll register
 811  *
 812  * Provides a IO register accessor for the atom interpreter (r4xx+).
 813  */
 814 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 815 {
 816         struct amdgpu_device *adev = info->dev->dev_private;
 817
 818         WREG32_IO(reg, val);
 819 }
 820
 821 /**
 822  * cail_ioreg_read - read IO register
 823  *
 824  * @info: atom card_info pointer
 825  * @reg: IO register offset
 826  *
 827  * Provides an IO register accessor for the atom interpreter (r4xx+).
 828  * Returns the value of the IO register.
 829  */
 830 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 831 {
 832         struct amdgpu_device *adev = info->dev->dev_private;
 833         uint32_t r;
 834
 835         r = RREG32_IO(reg);
 836         return r;
 837 }
 838
 839 /**
 840  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 841  *
 842  * @adev: amdgpu_device pointer
 843  *
 844  * Frees the driver info and register access callbacks for the ATOM
 845  * interpreter (r4xx+).
 846  * Called at driver shutdown.
 847  */
 848 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 849 {
 850         if (adev->mode_info.atom_context) {
 851                 kfree(adev->mode_info.atom_context->scratch);
 852                 kfree(adev->mode_info.atom_context->iio);
 853         }
 854         kfree(adev->mode_info.atom_context);
 855         adev->mode_info.atom_context = NULL;
 856         kfree(adev->mode_info.atom_card_info);
 857         adev->mode_info.atom_card_info = NULL;
 858 }
 859
 860 /**
 861  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 862  *
 863  * @adev: amdgpu_device pointer
 864  *
 865  * Initializes the driver info and register access callbacks for the
 866  * ATOM interpreter (r4xx+).
 867  * Returns 0 on sucess, -ENOMEM on failure.
 868  * Called at driver startup.
 869  */
 870 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 871 {
 872         struct card_info *atom_card_info =
 873             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 874
 875         if (!atom_card_info)
 876                 return -ENOMEM;
 877
 878         adev->mode_info.atom_card_info = atom_card_info;
 879         atom_card_info->dev = adev->ddev;
 880         atom_card_info->reg_read = cail_reg_read;
 881         atom_card_info->reg_write = cail_reg_write;
 882         /* needed for iio ops */
 883         if (adev->rio_mem) {
 884                 atom_card_info->ioreg_read = cail_ioreg_read;
 885                 atom_card_info->ioreg_write = cail_ioreg_write;
 886         } else {
 887                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 888                 atom_card_info->ioreg_read = cail_reg_read;
 889                 atom_card_info->ioreg_write = cail_reg_write;
 890         }
 891         atom_card_info->mc_read = cail_mc_read;
 892         atom_card_info->mc_write = cail_mc_write;
 893         atom_card_info->pll_read = cail_pll_read;
 894         atom_card_info->pll_write = cail_pll_write;
 895
 896         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 897         if (!adev->mode_info.atom_context) {
 898                 amdgpu_atombios_fini(adev);
 899                 return -ENOMEM;
 900         }
 901
 902         mutex_init(&adev->mode_info.atom_context->mutex);
 903         amdgpu_atombios_scratch_regs_init(adev);
 904         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 905         return 0;
 906 }
 907
 908 /* if we get transitioned to only one device, take VGA back */
 909 /**
 910  * amdgpu_vga_set_decode - enable/disable vga decode
 911  *
 912  * @cookie: amdgpu_device pointer
 913  * @state: enable/disable vga decode
 914  *
 915  * Enable/disable vga decode (all asics).
 916  * Returns VGA resource flags.
 917  */
 918 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 919 {
 920         struct amdgpu_device *adev = cookie;
 921         amdgpu_asic_set_vga_state(adev, state);
 922         if (state)
 923                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 924                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 925         else
 926                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 927 }
 928
 929 /**
 930  * amdgpu_check_pot_argument - check that argument is a power of two
 931  *
 932  * @arg: value to check
 933  *
 934  * Validates that a certain argument is a power of two (all asics).
 935  * Returns true if argument is valid.
 936  */
 937 static bool amdgpu_check_pot_argument(int arg)
 938 {
 939         return (arg & (arg - 1)) == 0;
 940 }
 941
 942 /**
 943  * amdgpu_check_arguments - validate module params
 944  *
 945  * @adev: amdgpu_device pointer
 946  *
 947  * Validates certain module parameters and updates
 948  * the associated values used by the driver (all asics).
 949  */
 950 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 951 {
 952         if (amdgpu_sched_jobs < 4) {
 953                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 954                          amdgpu_sched_jobs);
 955                 amdgpu_sched_jobs = 4;
 956         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 957                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 958                          amdgpu_sched_jobs);
 959                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 960         }
 961
 962         if (amdgpu_gart_size != -1) {
 963                 /* gtt size must be greater or equal to 32M */
 964                 if (amdgpu_gart_size < 32) {
 965                         dev_warn(adev->dev, "gart size (%d) too small\n",
 966                                  amdgpu_gart_size);
 967                         amdgpu_gart_size = -1;
 968                 }
 969         }
 970
 971         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 972                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 973                          amdgpu_vm_size);
 974                 amdgpu_vm_size = 8;
 975         }
 976
 977         if (amdgpu_vm_size < 1) {
 978                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 979                          amdgpu_vm_size);
 980                 amdgpu_vm_size = 8;
 981         }
 982
 983         /*
 984          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 985          */
 986         if (amdgpu_vm_size > 1024) {
 987                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 988                          amdgpu_vm_size);
 989                 amdgpu_vm_size = 8;
 990         }
 991
 992         /* defines number of bits in page table versus page directory,
 993          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 994          * page table and the remaining bits are in the page directory */
 995         if (amdgpu_vm_block_size == -1) {
 996
 997                 /* Total bits covered by PD + PTs */
 998                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 999
1000                 /* Make sure the PD is 4K in size up to 8GB address space.
1001                    Above that split equal between PD and PTs */
1002                 if (amdgpu_vm_size <= 8)
1003                         amdgpu_vm_block_size = bits - 9;
1004                 else
1005                         amdgpu_vm_block_size = (bits + 3) / 2;
1006
1007         } else if (amdgpu_vm_block_size < 9) {
1008                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1009                          amdgpu_vm_block_size);
1010                 amdgpu_vm_block_size = 9;
1011         }
1012
1013         if (amdgpu_vm_block_size > 24 ||
1014             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1015                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1016                          amdgpu_vm_block_size);
1017                 amdgpu_vm_block_size = 9;
1018         }
1019
1020         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1021             !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1022                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1023                          amdgpu_vram_page_split);
1024                 amdgpu_vram_page_split = 1024;
1025         }
1026 }
1027
1028 /**
1029  * amdgpu_switcheroo_set_state - set switcheroo state
1030  *
1031  * @pdev: pci dev pointer
1032  * @state: vga_switcheroo state
1033  *
1034  * Callback for the switcheroo driver.  Suspends or resumes the
1035  * the asics before or after it is powered up using ACPI methods.
1036  */
1037 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1038 {
1039         struct drm_device *dev = pci_get_drvdata(pdev);
1040
1041         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1042                 return;
1043
1044         if (state == VGA_SWITCHEROO_ON) {
1045                 unsigned d3_delay = dev->pdev->d3_delay;
1046
1047                 printk(KERN_INFO "amdgpu: switched on\n");
1048                 /* don't suspend or resume card normally */
1049                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1050
1051                 amdgpu_device_resume(dev, true, true);
1052
1053                 dev->pdev->d3_delay = d3_delay;
1054
1055                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1056                 drm_kms_helper_poll_enable(dev);
1057         } else {
1058                 printk(KERN_INFO "amdgpu: switched off\n");
1059                 drm_kms_helper_poll_disable(dev);
1060                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1061                 amdgpu_device_suspend(dev, true, true);
1062                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1063         }
1064 }
1065
1066 /**
1067  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1068  *
1069  * @pdev: pci dev pointer
1070  *
1071  * Callback for the switcheroo driver.  Check of the switcheroo
1072  * state can be changed.
1073  * Returns true if the state can be changed, false if not.
1074  */
1075 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1076 {
1077         struct drm_device *dev = pci_get_drvdata(pdev);
1078
1079         /*
1080         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1081         * locking inversion with the driver load path. And the access here is
1082         * completely racy anyway. So don't bother with locking for now.
1083         */
1084         return dev->open_count == 0;
1085 }
1086
1087 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1088         .set_gpu_state = amdgpu_switcheroo_set_state,
1089         .reprobe = NULL,
1090         .can_switch = amdgpu_switcheroo_can_switch,
1091 };
1092
1093 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1094                                   enum amd_ip_block_type block_type,
1095                                   enum amd_clockgating_state state)
1096 {
1097         int i, r = 0;
1098
1099         for (i = 0; i < adev->num_ip_blocks; i++) {
1100                 if (!adev->ip_blocks[i].status.valid)
1101                         continue;
1102                 if (adev->ip_blocks[i].version->type == block_type) {
1103                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1104                                                                                      state);
1105                         if (r)
1106                                 return r;
1107                         break;
1108                 }
1109         }
1110         return r;
1111 }
1112
1113 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1114                                   enum amd_ip_block_type block_type,
1115                                   enum amd_powergating_state state)
1116 {
1117         int i, r = 0;
1118
1119         for (i = 0; i < adev->num_ip_blocks; i++) {
1120                 if (!adev->ip_blocks[i].status.valid)
1121                         continue;
1122                 if (adev->ip_blocks[i].version->type == block_type) {
1123                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1124                                                                                      state);
1125                         if (r)
1126                                 return r;
1127                         break;
1128                 }
1129         }
1130         return r;
1131 }
1132
1133 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1134                          enum amd_ip_block_type block_type)
1135 {
1136         int i, r;
1137
1138         for (i = 0; i < adev->num_ip_blocks; i++) {
1139                 if (!adev->ip_blocks[i].status.valid)
1140                         continue;
1141                 if (adev->ip_blocks[i].version->type == block_type) {
1142                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1143                         if (r)
1144                                 return r;
1145                         break;
1146                 }
1147         }
1148         return 0;
1149
1150 }
1151
1152 bool amdgpu_is_idle(struct amdgpu_device *adev,
1153                     enum amd_ip_block_type block_type)
1154 {
1155         int i;
1156
1157         for (i = 0; i < adev->num_ip_blocks; i++) {
1158                 if (!adev->ip_blocks[i].status.valid)
1159                         continue;
1160                 if (adev->ip_blocks[i].version->type == block_type)
1161                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1162         }
1163         return true;
1164
1165 }
1166
1167 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1168                                              enum amd_ip_block_type type)
1169 {
1170         int i;
1171
1172         for (i = 0; i < adev->num_ip_blocks; i++)
1173                 if (adev->ip_blocks[i].version->type == type)
1174                         return &adev->ip_blocks[i];
1175
1176         return NULL;
1177 }
1178
1179 /**
1180  * amdgpu_ip_block_version_cmp
1181  *
1182  * @adev: amdgpu_device pointer
1183  * @type: enum amd_ip_block_type
1184  * @major: major version
1185  * @minor: minor version
1186  *
1187  * return 0 if equal or greater
1188  * return 1 if smaller or the ip_block doesn't exist
1189  */
1190 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1191                                 enum amd_ip_block_type type,
1192                                 u32 major, u32 minor)
1193 {
1194         struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1195
1196         if (ip_block && ((ip_block->version->major > major) ||
1197                         ((ip_block->version->major == major) &&
1198                         (ip_block->version->minor >= minor))))
1199                 return 0;
1200
1201         return 1;
1202 }
1203
1204 /**
1205  * amdgpu_ip_block_add
1206  *
1207  * @adev: amdgpu_device pointer
1208  * @ip_block_version: pointer to the IP to add
1209  *
1210  * Adds the IP block driver information to the collection of IPs
1211  * on the asic.
1212  */
1213 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1214                         const struct amdgpu_ip_block_version *ip_block_version)
1215 {
1216         if (!ip_block_version)
1217                 return -EINVAL;
1218
1219         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1220
1221         return 0;
1222 }
1223
1224 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1225 {
1226         adev->enable_virtual_display = false;
1227
1228         if (amdgpu_virtual_display) {
1229                 struct drm_device *ddev = adev->ddev;
1230                 const char *pci_address_name = pci_name(ddev->pdev);
1231                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1232
1233                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1234                 pciaddstr_tmp = pciaddstr;
1235                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1236                         pciaddname = strsep(&pciaddname_tmp, ",");
1237                         if (!strcmp(pci_address_name, pciaddname)) {
1238                                 long num_crtc;
1239                                 int res = -1;
1240
1241                                 adev->enable_virtual_display = true;
1242
1243                                 if (pciaddname_tmp)
1244                                         res = kstrtol(pciaddname_tmp, 10,
1245                                                       &num_crtc);
1246
1247                                 if (!res) {
1248                                         if (num_crtc < 1)
1249                                                 num_crtc = 1;
1250                                         if (num_crtc > 6)
1251                                                 num_crtc = 6;
1252                                         adev->mode_info.num_crtc = num_crtc;
1253                                 } else {
1254                                         adev->mode_info.num_crtc = 1;
1255                                 }
1256                                 break;
1257                         }
1258                 }
1259
1260                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1261                          amdgpu_virtual_display, pci_address_name,
1262                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1263
1264                 kfree(pciaddstr);
1265         }
1266 }
1267
1268 static int amdgpu_early_init(struct amdgpu_device *adev)
1269 {
1270         int i, r;
1271
1272         amdgpu_device_enable_virtual_display(adev);
1273
1274         switch (adev->asic_type) {
1275         case CHIP_TOPAZ:
1276         case CHIP_TONGA:
1277         case CHIP_FIJI:
1278         case CHIP_POLARIS11:
1279         case CHIP_POLARIS10:
1280         case CHIP_CARRIZO:
1281         case CHIP_STONEY:
1282                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1283                         adev->family = AMDGPU_FAMILY_CZ;
1284                 else
1285                         adev->family = AMDGPU_FAMILY_VI;
1286
1287                 r = vi_set_ip_blocks(adev);
1288                 if (r)
1289                         return r;
1290                 break;
1291 #ifdef CONFIG_DRM_AMDGPU_SI
1292         case CHIP_VERDE:
1293         case CHIP_TAHITI:
1294         case CHIP_PITCAIRN:
1295         case CHIP_OLAND:
1296         case CHIP_HAINAN:
1297                 adev->family = AMDGPU_FAMILY_SI;
1298                 r = si_set_ip_blocks(adev);
1299                 if (r)
1300                         return r;
1301                 break;
1302 #endif
1303 #ifdef CONFIG_DRM_AMDGPU_CIK
1304         case CHIP_BONAIRE:
1305         case CHIP_HAWAII:
1306         case CHIP_KAVERI:
1307         case CHIP_KABINI:
1308         case CHIP_MULLINS:
1309                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1310                         adev->family = AMDGPU_FAMILY_CI;
1311                 else
1312                         adev->family = AMDGPU_FAMILY_KV;
1313
1314                 r = cik_set_ip_blocks(adev);
1315                 if (r)
1316                         return r;
1317                 break;
1318 #endif
1319         default:
1320                 /* FIXME: not supported yet */
1321                 return -EINVAL;
1322         }
1323
1324         for (i = 0; i < adev->num_ip_blocks; i++) {
1325                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1326                         DRM_ERROR("disabled ip block: %d\n", i);
1327                         adev->ip_blocks[i].status.valid = false;
1328                 } else {
1329                         if (adev->ip_blocks[i].version->funcs->early_init) {
1330                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1331                                 if (r == -ENOENT) {
1332                                         adev->ip_blocks[i].status.valid = false;
1333                                 } else if (r) {
1334                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1335                                                   adev->ip_blocks[i].version->funcs->name, r);
1336                                         return r;
1337                                 } else {
1338                                         adev->ip_blocks[i].status.valid = true;
1339                                 }
1340                         } else {
1341                                 adev->ip_blocks[i].status.valid = true;
1342                         }
1343                 }
1344         }
1345
1346         adev->cg_flags &= amdgpu_cg_mask;
1347         adev->pg_flags &= amdgpu_pg_mask;
1348
1349         return 0;
1350 }
1351
1352 static int amdgpu_init(struct amdgpu_device *adev)
1353 {
1354         int i, r;
1355
1356         for (i = 0; i < adev->num_ip_blocks; i++) {
1357                 if (!adev->ip_blocks[i].status.valid)
1358                         continue;
1359                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1360                 if (r) {
1361                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1362                                   adev->ip_blocks[i].version->funcs->name, r);
1363                         return r;
1364                 }
1365                 adev->ip_blocks[i].status.sw = true;
1366                 /* need to do gmc hw init early so we can allocate gpu mem */
1367                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1368                         r = amdgpu_vram_scratch_init(adev);
1369                         if (r) {
1370                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1371                                 return r;
1372                         }
1373                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1374                         if (r) {
1375                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1376                                 return r;
1377                         }
1378                         r = amdgpu_wb_init(adev);
1379                         if (r) {
1380                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1381                                 return r;
1382                         }
1383                         adev->ip_blocks[i].status.hw = true;
1384                 }
1385         }
1386
1387         for (i = 0; i < adev->num_ip_blocks; i++) {
1388                 if (!adev->ip_blocks[i].status.sw)
1389                         continue;
1390                 /* gmc hw init is done early */
1391                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1392                         continue;
1393                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1394                 if (r) {
1395                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1396                                   adev->ip_blocks[i].version->funcs->name, r);
1397                         return r;
1398                 }
1399                 adev->ip_blocks[i].status.hw = true;
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int amdgpu_late_init(struct amdgpu_device *adev)
1406 {
1407         int i = 0, r;
1408
1409         for (i = 0; i < adev->num_ip_blocks; i++) {
1410                 if (!adev->ip_blocks[i].status.valid)
1411                         continue;
1412                 if (adev->ip_blocks[i].version->funcs->late_init) {
1413                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1414                         if (r) {
1415                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1416                                           adev->ip_blocks[i].version->funcs->name, r);
1417                                 return r;
1418                         }
1419                         adev->ip_blocks[i].status.late_initialized = true;
1420                 }
1421                 /* skip CG for VCE/UVD, it's handled specially */
1422                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1423                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1424                         /* enable clockgating to save power */
1425                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1426                                                                                      AMD_CG_STATE_GATE);
1427                         if (r) {
1428                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1429                                           adev->ip_blocks[i].version->funcs->name, r);
1430                                 return r;
1431                         }
1432                 }
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int amdgpu_fini(struct amdgpu_device *adev)
1439 {
1440         int i, r;
1441
1442         /* need to disable SMC first */
1443         for (i = 0; i < adev->num_ip_blocks; i++) {
1444                 if (!adev->ip_blocks[i].status.hw)
1445                         continue;
1446                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1447                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1448                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1449                                                                                      AMD_CG_STATE_UNGATE);
1450                         if (r) {
1451                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1452                                           adev->ip_blocks[i].version->funcs->name, r);
1453                                 return r;
1454                         }
1455                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1456                         /* XXX handle errors */
1457                         if (r) {
1458                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1459                                           adev->ip_blocks[i].version->funcs->name, r);
1460                         }
1461                         adev->ip_blocks[i].status.hw = false;
1462                         break;
1463                 }
1464         }
1465
1466         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1467                 if (!adev->ip_blocks[i].status.hw)
1468                         continue;
1469                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1470                         amdgpu_wb_fini(adev);
1471                         amdgpu_vram_scratch_fini(adev);
1472                 }
1473
1474                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1475                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1476                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1477                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1478                                                                                      AMD_CG_STATE_UNGATE);
1479                         if (r) {
1480                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1481                                           adev->ip_blocks[i].version->funcs->name, r);
1482                                 return r;
1483                         }
1484                 }
1485
1486                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1487                 /* XXX handle errors */
1488                 if (r) {
1489                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1490                                   adev->ip_blocks[i].version->funcs->name, r);
1491                 }
1492
1493                 adev->ip_blocks[i].status.hw = false;
1494         }
1495
1496         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1497                 if (!adev->ip_blocks[i].status.sw)
1498                         continue;
1499                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1500                 /* XXX handle errors */
1501                 if (r) {
1502                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1503                                   adev->ip_blocks[i].version->funcs->name, r);
1504                 }
1505                 adev->ip_blocks[i].status.sw = false;
1506                 adev->ip_blocks[i].status.valid = false;
1507         }
1508
1509         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1510                 if (!adev->ip_blocks[i].status.late_initialized)
1511                         continue;
1512                 if (adev->ip_blocks[i].version->funcs->late_fini)
1513                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1514                 adev->ip_blocks[i].status.late_initialized = false;
1515         }
1516
1517         return 0;
1518 }
1519
1520 int amdgpu_suspend(struct amdgpu_device *adev)
1521 {
1522         int i, r;
1523
1524         /* ungate SMC block first */
1525         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1526                                          AMD_CG_STATE_UNGATE);
1527         if (r) {
1528                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1529         }
1530
1531         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1532                 if (!adev->ip_blocks[i].status.valid)
1533                         continue;
1534                 /* ungate blocks so that suspend can properly shut them down */
1535                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1536                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1537                                                                                      AMD_CG_STATE_UNGATE);
1538                         if (r) {
1539                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1540                                           adev->ip_blocks[i].version->funcs->name, r);
1541                         }
1542                 }
1543                 /* XXX handle errors */
1544                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1545                 /* XXX handle errors */
1546                 if (r) {
1547                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1548                                   adev->ip_blocks[i].version->funcs->name, r);
1549                 }
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int amdgpu_resume(struct amdgpu_device *adev)
1556 {
1557         int i, r;
1558
1559         for (i = 0; i < adev->num_ip_blocks; i++) {
1560                 if (!adev->ip_blocks[i].status.valid)
1561                         continue;
1562                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1563                 if (r) {
1564                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1565                                   adev->ip_blocks[i].version->funcs->name, r);
1566                         return r;
1567                 }
1568         }
1569
1570         return 0;
1571 }
1572
1573 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1574 {
1575         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1576                 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1577 }
1578
1579 /**
1580  * amdgpu_device_init - initialize the driver
1581  *
1582  * @adev: amdgpu_device pointer
1583  * @pdev: drm dev pointer
1584  * @pdev: pci dev pointer
1585  * @flags: driver flags
1586  *
1587  * Initializes the driver info and hw (all asics).
1588  * Returns 0 for success or an error on failure.
1589  * Called at driver startup.
1590  */
1591 int amdgpu_device_init(struct amdgpu_device *adev,
1592                        struct drm_device *ddev,
1593                        struct pci_dev *pdev,
1594                        uint32_t flags)
1595 {
1596         int r, i;
1597         bool runtime = false;
1598         u32 max_MBps;
1599
1600         adev->shutdown = false;
1601         adev->dev = &pdev->dev;
1602         adev->ddev = ddev;
1603         adev->pdev = pdev;
1604         adev->flags = flags;
1605         adev->asic_type = flags & AMD_ASIC_MASK;
1606         adev->is_atom_bios = false;
1607         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1608         adev->mc.gtt_size = 512 * 1024 * 1024;
1609         adev->accel_working = false;
1610         adev->num_rings = 0;
1611         adev->mman.buffer_funcs = NULL;
1612         adev->mman.buffer_funcs_ring = NULL;
1613         adev->vm_manager.vm_pte_funcs = NULL;
1614         adev->vm_manager.vm_pte_num_rings = 0;
1615         adev->gart.gart_funcs = NULL;
1616         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1617
1618         adev->smc_rreg = &amdgpu_invalid_rreg;
1619         adev->smc_wreg = &amdgpu_invalid_wreg;
1620         adev->pcie_rreg = &amdgpu_invalid_rreg;
1621         adev->pcie_wreg = &amdgpu_invalid_wreg;
1622         adev->pciep_rreg = &amdgpu_invalid_rreg;
1623         adev->pciep_wreg = &amdgpu_invalid_wreg;
1624         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1625         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1626         adev->didt_rreg = &amdgpu_invalid_rreg;
1627         adev->didt_wreg = &amdgpu_invalid_wreg;
1628         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1629         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1630         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1631         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1632
1633
1634         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1635                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1636                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1637
1638         /* mutex initialization are all done here so we
1639          * can recall function without having locking issues */
1640         mutex_init(&adev->vm_manager.lock);
1641         atomic_set(&adev->irq.ih.lock, 0);
1642         mutex_init(&adev->pm.mutex);
1643         mutex_init(&adev->gfx.gpu_clock_mutex);
1644         mutex_init(&adev->srbm_mutex);
1645         mutex_init(&adev->grbm_idx_mutex);
1646         mutex_init(&adev->mn_lock);
1647         hash_init(adev->mn_hash);
1648
1649         amdgpu_check_arguments(adev);
1650
1651         /* Registers mapping */
1652         /* TODO: block userspace mapping of io register */
1653         spin_lock_init(&adev->mmio_idx_lock);
1654         spin_lock_init(&adev->smc_idx_lock);
1655         spin_lock_init(&adev->pcie_idx_lock);
1656         spin_lock_init(&adev->uvd_ctx_idx_lock);
1657         spin_lock_init(&adev->didt_idx_lock);
1658         spin_lock_init(&adev->gc_cac_idx_lock);
1659         spin_lock_init(&adev->audio_endpt_idx_lock);
1660         spin_lock_init(&adev->mm_stats.lock);
1661
1662         INIT_LIST_HEAD(&adev->shadow_list);
1663         mutex_init(&adev->shadow_list_lock);
1664
1665         INIT_LIST_HEAD(&adev->gtt_list);
1666         spin_lock_init(&adev->gtt_list_lock);
1667
1668         if (adev->asic_type >= CHIP_BONAIRE) {
1669                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1670                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1671         } else {
1672                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1673                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1674         }
1675
1676         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1677         if (adev->rmmio == NULL) {
1678                 return -ENOMEM;
1679         }
1680         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1681         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1682
1683         if (adev->asic_type >= CHIP_BONAIRE)
1684                 /* doorbell bar mapping */
1685                 amdgpu_doorbell_init(adev);
1686
1687         /* io port mapping */
1688         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1689                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1690                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1691                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1692                         break;
1693                 }
1694         }
1695         if (adev->rio_mem == NULL)
1696                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1697
1698         /* early init functions */
1699         r = amdgpu_early_init(adev);
1700         if (r)
1701                 return r;
1702
1703         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1704         /* this will fail for cards that aren't VGA class devices, just
1705          * ignore it */
1706         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1707
1708         if (amdgpu_runtime_pm == 1)
1709                 runtime = true;
1710         if (amdgpu_device_is_px(ddev))
1711                 runtime = true;
1712         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1713         if (runtime)
1714                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1715
1716         /* Read BIOS */
1717         if (!amdgpu_get_bios(adev)) {
1718                 r = -EINVAL;
1719                 goto failed;
1720         }
1721         /* Must be an ATOMBIOS */
1722         if (!adev->is_atom_bios) {
1723                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1724                 r = -EINVAL;
1725                 goto failed;
1726         }
1727         r = amdgpu_atombios_init(adev);
1728         if (r) {
1729                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1730                 goto failed;
1731         }
1732
1733         /* detect if we are with an SRIOV vbios */
1734         amdgpu_device_detect_sriov_bios(adev);
1735
1736         /* Post card if necessary */
1737         if (amdgpu_vpost_needed(adev)) {
1738                 if (!adev->bios) {
1739                         dev_err(adev->dev, "no vBIOS found\n");
1740                         r = -EINVAL;
1741                         goto failed;
1742                 }
1743                 DRM_INFO("GPU posting now...\n");
1744                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1745                 if (r) {
1746                         dev_err(adev->dev, "gpu post error!\n");
1747                         goto failed;
1748                 }
1749         } else {
1750                 DRM_INFO("GPU post is not needed\n");
1751         }
1752
1753         /* Initialize clocks */
1754         r = amdgpu_atombios_get_clock_info(adev);
1755         if (r) {
1756                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1757                 goto failed;
1758         }
1759         /* init i2c buses */
1760         amdgpu_atombios_i2c_init(adev);
1761
1762         /* Fence driver */
1763         r = amdgpu_fence_driver_init(adev);
1764         if (r) {
1765                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1766                 goto failed;
1767         }
1768
1769         /* init the mode config */
1770         drm_mode_config_init(adev->ddev);
1771
1772         r = amdgpu_init(adev);
1773         if (r) {
1774                 dev_err(adev->dev, "amdgpu_init failed\n");
1775                 amdgpu_fini(adev);
1776                 goto failed;
1777         }
1778
1779         adev->accel_working = true;
1780
1781         /* Initialize the buffer migration limit. */
1782         if (amdgpu_moverate >= 0)
1783                 max_MBps = amdgpu_moverate;
1784         else
1785                 max_MBps = 8; /* Allow 8 MB/s. */
1786         /* Get a log2 for easy divisions. */
1787         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1788
1789         amdgpu_fbdev_init(adev);
1790
1791         r = amdgpu_ib_pool_init(adev);
1792         if (r) {
1793                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1794                 goto failed;
1795         }
1796
1797         r = amdgpu_ib_ring_tests(adev);
1798         if (r)
1799                 DRM_ERROR("ib ring test failed (%d).\n", r);
1800
1801         r = amdgpu_gem_debugfs_init(adev);
1802         if (r) {
1803                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1804         }
1805
1806         r = amdgpu_debugfs_regs_init(adev);
1807         if (r) {
1808                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1809         }
1810
1811         r = amdgpu_debugfs_firmware_init(adev);
1812         if (r) {
1813                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1814                 return r;
1815         }
1816
1817         if ((amdgpu_testing & 1)) {
1818                 if (adev->accel_working)
1819                         amdgpu_test_moves(adev);
1820                 else
1821                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1822         }
1823         if ((amdgpu_testing & 2)) {
1824                 if (adev->accel_working)
1825                         amdgpu_test_syncing(adev);
1826                 else
1827                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1828         }
1829         if (amdgpu_benchmarking) {
1830                 if (adev->accel_working)
1831                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1832                 else
1833                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1834         }
1835
1836         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1837          * explicit gating rather than handling it automatically.
1838          */
1839         r = amdgpu_late_init(adev);
1840         if (r) {
1841                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1842                 goto failed;
1843         }
1844
1845         return 0;
1846
1847 failed:
1848         if (runtime)
1849                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1850         return r;
1851 }
1852
1853 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1854
1855 /**
1856  * amdgpu_device_fini - tear down the driver
1857  *
1858  * @adev: amdgpu_device pointer
1859  *
1860  * Tear down the driver info (all asics).
1861  * Called at driver shutdown.
1862  */
1863 void amdgpu_device_fini(struct amdgpu_device *adev)
1864 {
1865         int r;
1866
1867         DRM_INFO("amdgpu: finishing device.\n");
1868         adev->shutdown = true;
1869         drm_crtc_force_disable_all(adev->ddev);
1870         /* evict vram memory */
1871         amdgpu_bo_evict_vram(adev);
1872         amdgpu_ib_pool_fini(adev);
1873         amdgpu_fence_driver_fini(adev);
1874         amdgpu_fbdev_fini(adev);
1875         r = amdgpu_fini(adev);
1876         adev->accel_working = false;
1877         /* free i2c buses */
1878         amdgpu_i2c_fini(adev);
1879         amdgpu_atombios_fini(adev);
1880         kfree(adev->bios);
1881         adev->bios = NULL;
1882         vga_switcheroo_unregister_client(adev->pdev);
1883         if (adev->flags & AMD_IS_PX)
1884                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1885         vga_client_register(adev->pdev, NULL, NULL, NULL);
1886         if (adev->rio_mem)
1887                 pci_iounmap(adev->pdev, adev->rio_mem);
1888         adev->rio_mem = NULL;
1889         iounmap(adev->rmmio);
1890         adev->rmmio = NULL;
1891         if (adev->asic_type >= CHIP_BONAIRE)
1892                 amdgpu_doorbell_fini(adev);
1893         amdgpu_debugfs_regs_cleanup(adev);
1894         amdgpu_debugfs_remove_files(adev);
1895 }
1896
1897
1898 /*
1899  * Suspend & resume.
1900  */
1901 /**
1902  * amdgpu_device_suspend - initiate device suspend
1903  *
1904  * @pdev: drm dev pointer
1905  * @state: suspend state
1906  *
1907  * Puts the hw in the suspend state (all asics).
1908  * Returns 0 for success or an error on failure.
1909  * Called at driver suspend.
1910  */
1911 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1912 {
1913         struct amdgpu_device *adev;
1914         struct drm_crtc *crtc;
1915         struct drm_connector *connector;
1916         int r;
1917
1918         if (dev == NULL || dev->dev_private == NULL) {
1919                 return -ENODEV;
1920         }
1921
1922         adev = dev->dev_private;
1923
1924         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1925                 return 0;
1926
1927         drm_kms_helper_poll_disable(dev);
1928
1929         /* turn off display hw */
1930         drm_modeset_lock_all(dev);
1931         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1932                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1933         }
1934         drm_modeset_unlock_all(dev);
1935
1936         /* unpin the front buffers and cursors */
1937         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1938                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1939                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1940                 struct amdgpu_bo *robj;
1941
1942                 if (amdgpu_crtc->cursor_bo) {
1943                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1944                         r = amdgpu_bo_reserve(aobj, false);
1945                         if (r == 0) {
1946                                 amdgpu_bo_unpin(aobj);
1947                                 amdgpu_bo_unreserve(aobj);
1948                         }
1949                 }
1950
1951                 if (rfb == NULL || rfb->obj == NULL) {
1952                         continue;
1953                 }
1954                 robj = gem_to_amdgpu_bo(rfb->obj);
1955                 /* don't unpin kernel fb objects */
1956                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1957                         r = amdgpu_bo_reserve(robj, false);
1958                         if (r == 0) {
1959                                 amdgpu_bo_unpin(robj);
1960                                 amdgpu_bo_unreserve(robj);
1961                         }
1962                 }
1963         }
1964         /* evict vram memory */
1965         amdgpu_bo_evict_vram(adev);
1966
1967         amdgpu_fence_driver_suspend(adev);
1968
1969         r = amdgpu_suspend(adev);
1970
1971         /* evict remaining vram memory
1972          * This second call to evict vram is to evict the gart page table
1973          * using the CPU.
1974          */
1975         amdgpu_bo_evict_vram(adev);
1976
1977         amdgpu_atombios_scratch_regs_save(adev);
1978         pci_save_state(dev->pdev);
1979         if (suspend) {
1980                 /* Shut down the device */
1981                 pci_disable_device(dev->pdev);
1982                 pci_set_power_state(dev->pdev, PCI_D3hot);
1983         } else {
1984                 r = amdgpu_asic_reset(adev);
1985                 if (r)
1986                         DRM_ERROR("amdgpu asic reset failed\n");
1987         }
1988
1989         if (fbcon) {
1990                 console_lock();
1991                 amdgpu_fbdev_set_suspend(adev, 1);
1992                 console_unlock();
1993         }
1994         return 0;
1995 }
1996
1997 /**
1998  * amdgpu_device_resume - initiate device resume
1999  *
2000  * @pdev: drm dev pointer
2001  *
2002  * Bring the hw back to operating state (all asics).
2003  * Returns 0 for success or an error on failure.
2004  * Called at driver resume.
2005  */
2006 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2007 {
2008         struct drm_connector *connector;
2009         struct amdgpu_device *adev = dev->dev_private;
2010         struct drm_crtc *crtc;
2011         int r;
2012
2013         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2014                 return 0;
2015
2016         if (fbcon)
2017                 console_lock();
2018
2019         if (resume) {
2020                 pci_set_power_state(dev->pdev, PCI_D0);
2021                 pci_restore_state(dev->pdev);
2022                 r = pci_enable_device(dev->pdev);
2023                 if (r) {
2024                         if (fbcon)
2025                                 console_unlock();
2026                         return r;
2027                 }
2028         }
2029         amdgpu_atombios_scratch_regs_restore(adev);
2030
2031         /* post card */
2032         if (!amdgpu_card_posted(adev) || !resume) {
2033                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2034                 if (r)
2035                         DRM_ERROR("amdgpu asic init failed\n");
2036         }
2037
2038         r = amdgpu_resume(adev);
2039         if (r)
2040                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2041
2042         amdgpu_fence_driver_resume(adev);
2043
2044         if (resume) {
2045                 r = amdgpu_ib_ring_tests(adev);
2046                 if (r)
2047                         DRM_ERROR("ib ring test failed (%d).\n", r);
2048         }
2049
2050         r = amdgpu_late_init(adev);
2051         if (r)
2052                 return r;
2053
2054         /* pin cursors */
2055         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2056                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2057
2058                 if (amdgpu_crtc->cursor_bo) {
2059                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2060                         r = amdgpu_bo_reserve(aobj, false);
2061                         if (r == 0) {
2062                                 r = amdgpu_bo_pin(aobj,
2063                                                   AMDGPU_GEM_DOMAIN_VRAM,
2064                                                   &amdgpu_crtc->cursor_addr);
2065                                 if (r != 0)
2066                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2067                                 amdgpu_bo_unreserve(aobj);
2068                         }
2069                 }
2070         }
2071
2072         /* blat the mode back in */
2073         if (fbcon) {
2074                 drm_helper_resume_force_mode(dev);
2075                 /* turn on display hw */
2076                 drm_modeset_lock_all(dev);
2077                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2078                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2079                 }
2080                 drm_modeset_unlock_all(dev);
2081         }
2082
2083         drm_kms_helper_poll_enable(dev);
2084
2085         /*
2086          * Most of the connector probing functions try to acquire runtime pm
2087          * refs to ensure that the GPU is powered on when connector polling is
2088          * performed. Since we're calling this from a runtime PM callback,
2089          * trying to acquire rpm refs will cause us to deadlock.
2090          *
2091          * Since we're guaranteed to be holding the rpm lock, it's safe to
2092          * temporarily disable the rpm helpers so this doesn't deadlock us.
2093          */
2094 #ifdef CONFIG_PM
2095         dev->dev->power.disable_depth++;
2096 #endif
2097         drm_helper_hpd_irq_event(dev);
2098 #ifdef CONFIG_PM
2099         dev->dev->power.disable_depth--;
2100 #endif
2101
2102         if (fbcon) {
2103                 amdgpu_fbdev_set_suspend(adev, 0);
2104                 console_unlock();
2105         }
2106
2107         return 0;
2108 }
2109
2110 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2111 {
2112         int i;
2113         bool asic_hang = false;
2114
2115         for (i = 0; i < adev->num_ip_blocks; i++) {
2116                 if (!adev->ip_blocks[i].status.valid)
2117                         continue;
2118                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2119                         adev->ip_blocks[i].status.hang =
2120                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2121                 if (adev->ip_blocks[i].status.hang) {
2122                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2123                         asic_hang = true;
2124                 }
2125         }
2126         return asic_hang;
2127 }
2128
2129 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2130 {
2131         int i, r = 0;
2132
2133         for (i = 0; i < adev->num_ip_blocks; i++) {
2134                 if (!adev->ip_blocks[i].status.valid)
2135                         continue;
2136                 if (adev->ip_blocks[i].status.hang &&
2137                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2138                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2139                         if (r)
2140                                 return r;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2148 {
2149         int i;
2150
2151         for (i = 0; i < adev->num_ip_blocks; i++) {
2152                 if (!adev->ip_blocks[i].status.valid)
2153                         continue;
2154                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2155                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2156                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2157                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2158                         if (adev->ip_blocks[i].status.hang) {
2159                                 DRM_INFO("Some block need full reset!\n");
2160                                 return true;
2161                         }
2162                 }
2163         }
2164         return false;
2165 }
2166
2167 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2168 {
2169         int i, r = 0;
2170
2171         for (i = 0; i < adev->num_ip_blocks; i++) {
2172                 if (!adev->ip_blocks[i].status.valid)
2173                         continue;
2174                 if (adev->ip_blocks[i].status.hang &&
2175                     adev->ip_blocks[i].version->funcs->soft_reset) {
2176                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2177                         if (r)
2178                                 return r;
2179                 }
2180         }
2181
2182         return 0;
2183 }
2184
2185 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2186 {
2187         int i, r = 0;
2188
2189         for (i = 0; i < adev->num_ip_blocks; i++) {
2190                 if (!adev->ip_blocks[i].status.valid)
2191                         continue;
2192                 if (adev->ip_blocks[i].status.hang &&
2193                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2194                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2195                 if (r)
2196                         return r;
2197         }
2198
2199         return 0;
2200 }
2201
2202 bool amdgpu_need_backup(struct amdgpu_device *adev)
2203 {
2204         if (adev->flags & AMD_IS_APU)
2205                 return false;
2206
2207         return amdgpu_lockup_timeout > 0 ? true : false;
2208 }
2209
2210 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2211                                            struct amdgpu_ring *ring,
2212                                            struct amdgpu_bo *bo,
2213                                            struct dma_fence **fence)
2214 {
2215         uint32_t domain;
2216         int r;
2217
2218        if (!bo->shadow)
2219                return 0;
2220
2221        r = amdgpu_bo_reserve(bo, false);
2222        if (r)
2223                return r;
2224        domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2225        /* if bo has been evicted, then no need to recover */
2226        if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2227                r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2228                                                  NULL, fence, true);
2229                if (r) {
2230                        DRM_ERROR("recover page table failed!\n");
2231                        goto err;
2232                }
2233        }
2234 err:
2235        amdgpu_bo_unreserve(bo);
2236        return r;
2237 }
2238
2239 /**
2240  * amdgpu_gpu_reset - reset the asic
2241  *
2242  * @adev: amdgpu device pointer
2243  *
2244  * Attempt the reset the GPU if it has hung (all asics).
2245  * Returns 0 for success or an error on failure.
2246  */
2247 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2248 {
2249         int i, r;
2250         int resched;
2251         bool need_full_reset;
2252
2253         if (!amdgpu_check_soft_reset(adev)) {
2254                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2255                 return 0;
2256         }
2257
2258         atomic_inc(&adev->gpu_reset_counter);
2259
2260         /* block TTM */
2261         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2262
2263         /* block scheduler */
2264         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2265                 struct amdgpu_ring *ring = adev->rings[i];
2266
2267                 if (!ring)
2268                         continue;
2269                 kthread_park(ring->sched.thread);
2270                 amd_sched_hw_job_reset(&ring->sched);
2271         }
2272         /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2273         amdgpu_fence_driver_force_completion(adev);
2274
2275         need_full_reset = amdgpu_need_full_reset(adev);
2276
2277         if (!need_full_reset) {
2278                 amdgpu_pre_soft_reset(adev);
2279                 r = amdgpu_soft_reset(adev);
2280                 amdgpu_post_soft_reset(adev);
2281                 if (r || amdgpu_check_soft_reset(adev)) {
2282                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2283                         need_full_reset = true;
2284                 }
2285         }
2286
2287         if (need_full_reset) {
2288                 r = amdgpu_suspend(adev);
2289
2290 retry:
2291                 /* Disable fb access */
2292                 if (adev->mode_info.num_crtc) {
2293                         struct amdgpu_mode_mc_save save;
2294                         amdgpu_display_stop_mc_access(adev, &save);
2295                         amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2296                 }
2297                 amdgpu_atombios_scratch_regs_save(adev);
2298                 r = amdgpu_asic_reset(adev);
2299                 amdgpu_atombios_scratch_regs_restore(adev);
2300                 /* post card */
2301                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2302
2303                 if (!r) {
2304                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2305                         r = amdgpu_resume(adev);
2306                 }
2307         }
2308         if (!r) {
2309                 amdgpu_irq_gpu_reset_resume_helper(adev);
2310                 if (need_full_reset && amdgpu_need_backup(adev)) {
2311                         r = amdgpu_ttm_recover_gart(adev);
2312                         if (r)
2313                                 DRM_ERROR("gart recovery failed!!!\n");
2314                 }
2315                 r = amdgpu_ib_ring_tests(adev);
2316                 if (r) {
2317                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2318                         r = amdgpu_suspend(adev);
2319                         need_full_reset = true;
2320                         goto retry;
2321                 }
2322                 /**
2323                  * recovery vm page tables, since we cannot depend on VRAM is
2324                  * consistent after gpu full reset.
2325                  */
2326                 if (need_full_reset && amdgpu_need_backup(adev)) {
2327                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2328                         struct amdgpu_bo *bo, *tmp;
2329                         struct dma_fence *fence = NULL, *next = NULL;
2330
2331                         DRM_INFO("recover vram bo from shadow\n");
2332                         mutex_lock(&adev->shadow_list_lock);
2333                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2334                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2335                                 if (fence) {
2336                                         r = dma_fence_wait(fence, false);
2337                                         if (r) {
2338                                                 WARN(r, "recovery from shadow isn't comleted\n");
2339                                                 break;
2340                                         }
2341                                 }
2342
2343                                 dma_fence_put(fence);
2344                                 fence = next;
2345                         }
2346                         mutex_unlock(&adev->shadow_list_lock);
2347                         if (fence) {
2348                                 r = dma_fence_wait(fence, false);
2349                                 if (r)
2350                                         WARN(r, "recovery from shadow isn't comleted\n");
2351                         }
2352                         dma_fence_put(fence);
2353                 }
2354                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2355                         struct amdgpu_ring *ring = adev->rings[i];
2356                         if (!ring)
2357                                 continue;
2358
2359                         amd_sched_job_recovery(&ring->sched);
2360                         kthread_unpark(ring->sched.thread);
2361                 }
2362         } else {
2363                 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2364                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2365                         if (adev->rings[i]) {
2366                                 kthread_unpark(adev->rings[i]->sched.thread);
2367                         }
2368                 }
2369         }
2370
2371         drm_helper_resume_force_mode(adev->ddev);
2372
2373         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2374         if (r) {
2375                 /* bad news, how to tell it to userspace ? */
2376                 dev_info(adev->dev, "GPU reset failed\n");
2377         }
2378
2379         return r;
2380 }
2381
2382 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2383 {
2384         u32 mask;
2385         int ret;
2386
2387         if (amdgpu_pcie_gen_cap)
2388                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2389
2390         if (amdgpu_pcie_lane_cap)
2391                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2392
2393         /* covers APUs as well */
2394         if (pci_is_root_bus(adev->pdev->bus)) {
2395                 if (adev->pm.pcie_gen_mask == 0)
2396                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2397                 if (adev->pm.pcie_mlw_mask == 0)
2398                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2399                 return;
2400         }
2401
2402         if (adev->pm.pcie_gen_mask == 0) {
2403                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2404                 if (!ret) {
2405                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2406                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2407                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2408
2409                         if (mask & DRM_PCIE_SPEED_25)
2410                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2411                         if (mask & DRM_PCIE_SPEED_50)
2412                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2413                         if (mask & DRM_PCIE_SPEED_80)
2414                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2415                 } else {
2416                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2417                 }
2418         }
2419         if (adev->pm.pcie_mlw_mask == 0) {
2420                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2421                 if (!ret) {
2422                         switch (mask) {
2423                         case 32:
2424                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2425                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2426                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2427                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2428                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2429                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2430                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2431                                 break;
2432                         case 16:
2433                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2434                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2435                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2436                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2437                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2438                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2439                                 break;
2440                         case 12:
2441                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2442                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2443                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2444                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2445                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2446                                 break;
2447                         case 8:
2448                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2449                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2450                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2451                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2452                                 break;
2453                         case 4:
2454                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2455                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2456                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2457                                 break;
2458                         case 2:
2459                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2460                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2461                                 break;
2462                         case 1:
2463                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2464                                 break;
2465                         default:
2466                                 break;
2467                         }
2468                 } else {
2469                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2470                 }
2471         }
2472 }
2473
2474 /*
2475  * Debugfs
2476  */
2477 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2478                              const struct drm_info_list *files,
2479                              unsigned nfiles)
2480 {
2481         unsigned i;
2482
2483         for (i = 0; i < adev->debugfs_count; i++) {
2484                 if (adev->debugfs[i].files == files) {
2485                         /* Already registered */
2486                         return 0;
2487                 }
2488         }
2489
2490         i = adev->debugfs_count + 1;
2491         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2492                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2493                 DRM_ERROR("Report so we increase "
2494                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2495                 return -EINVAL;
2496         }
2497         adev->debugfs[adev->debugfs_count].files = files;
2498         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2499         adev->debugfs_count = i;
2500 #if defined(CONFIG_DEBUG_FS)
2501         drm_debugfs_create_files(files, nfiles,
2502                                  adev->ddev->primary->debugfs_root,
2503                                  adev->ddev->primary);
2504 #endif
2505         return 0;
2506 }
2507
2508 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2509 {
2510 #if defined(CONFIG_DEBUG_FS)
2511         unsigned i;
2512
2513         for (i = 0; i < adev->debugfs_count; i++) {
2514                 drm_debugfs_remove_files(adev->debugfs[i].files,
2515                                          adev->debugfs[i].num_files,
2516                                          adev->ddev->primary);
2517         }
2518 #endif
2519 }
2520
2521 #if defined(CONFIG_DEBUG_FS)
2522
2523 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2524                                         size_t size, loff_t *pos)
2525 {
2526         struct amdgpu_device *adev = file_inode(f)->i_private;
2527         ssize_t result = 0;
2528         int r;
2529         bool pm_pg_lock, use_bank;
2530         unsigned instance_bank, sh_bank, se_bank;
2531
2532         if (size & 0x3 || *pos & 0x3)
2533                 return -EINVAL;
2534
2535         /* are we reading registers for which a PG lock is necessary? */
2536         pm_pg_lock = (*pos >> 23) & 1;
2537
2538         if (*pos & (1ULL << 62)) {
2539                 se_bank = (*pos >> 24) & 0x3FF;
2540                 sh_bank = (*pos >> 34) & 0x3FF;
2541                 instance_bank = (*pos >> 44) & 0x3FF;
2542
2543                 if (se_bank == 0x3FF)
2544                         se_bank = 0xFFFFFFFF;
2545                 if (sh_bank == 0x3FF)
2546                         sh_bank = 0xFFFFFFFF;
2547                 if (instance_bank == 0x3FF)
2548                         instance_bank = 0xFFFFFFFF;
2549                 use_bank = 1;
2550         } else {
2551                 use_bank = 0;
2552         }
2553
2554         *pos &= 0x3FFFF;
2555
2556         if (use_bank) {
2557                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2558                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2559                         return -EINVAL;
2560                 mutex_lock(&adev->grbm_idx_mutex);
2561                 amdgpu_gfx_select_se_sh(adev, se_bank,
2562                                         sh_bank, instance_bank);
2563         }
2564
2565         if (pm_pg_lock)
2566                 mutex_lock(&adev->pm.mutex);
2567
2568         while (size) {
2569                 uint32_t value;
2570
2571                 if (*pos > adev->rmmio_size)
2572                         goto end;
2573
2574                 value = RREG32(*pos >> 2);
2575                 r = put_user(value, (uint32_t *)buf);
2576                 if (r) {
2577                         result = r;
2578                         goto end;
2579                 }
2580
2581                 result += 4;
2582                 buf += 4;
2583                 *pos += 4;
2584                 size -= 4;
2585         }
2586
2587 end:
2588         if (use_bank) {
2589                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2590                 mutex_unlock(&adev->grbm_idx_mutex);
2591         }
2592
2593         if (pm_pg_lock)
2594                 mutex_unlock(&adev->pm.mutex);
2595
2596         return result;
2597 }
2598
2599 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2600                                          size_t size, loff_t *pos)
2601 {
2602         struct amdgpu_device *adev = file_inode(f)->i_private;
2603         ssize_t result = 0;
2604         int r;
2605         bool pm_pg_lock, use_bank;
2606         unsigned instance_bank, sh_bank, se_bank;
2607
2608         if (size & 0x3 || *pos & 0x3)
2609                 return -EINVAL;
2610
2611         /* are we reading registers for which a PG lock is necessary? */
2612         pm_pg_lock = (*pos >> 23) & 1;
2613
2614         if (*pos & (1ULL << 62)) {
2615                 se_bank = (*pos >> 24) & 0x3FF;
2616                 sh_bank = (*pos >> 34) & 0x3FF;
2617                 instance_bank = (*pos >> 44) & 0x3FF;
2618
2619                 if (se_bank == 0x3FF)
2620                         se_bank = 0xFFFFFFFF;
2621                 if (sh_bank == 0x3FF)
2622                         sh_bank = 0xFFFFFFFF;
2623                 if (instance_bank == 0x3FF)
2624                         instance_bank = 0xFFFFFFFF;
2625                 use_bank = 1;
2626         } else {
2627                 use_bank = 0;
2628         }
2629
2630         *pos &= 0x3FFFF;
2631
2632         if (use_bank) {
2633                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2634                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2635                         return -EINVAL;
2636                 mutex_lock(&adev->grbm_idx_mutex);
2637                 amdgpu_gfx_select_se_sh(adev, se_bank,
2638                                         sh_bank, instance_bank);
2639         }
2640
2641         if (pm_pg_lock)
2642                 mutex_lock(&adev->pm.mutex);
2643
2644         while (size) {
2645                 uint32_t value;
2646
2647                 if (*pos > adev->rmmio_size)
2648                         return result;
2649
2650                 r = get_user(value, (uint32_t *)buf);
2651                 if (r)
2652                         return r;
2653
2654                 WREG32(*pos >> 2, value);
2655
2656                 result += 4;
2657                 buf += 4;
2658                 *pos += 4;
2659                 size -= 4;
2660         }
2661
2662         if (use_bank) {
2663                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2664                 mutex_unlock(&adev->grbm_idx_mutex);
2665         }
2666
2667         if (pm_pg_lock)
2668                 mutex_unlock(&adev->pm.mutex);
2669
2670         return result;
2671 }
2672
2673 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2674                                         size_t size, loff_t *pos)
2675 {
2676         struct amdgpu_device *adev = file_inode(f)->i_private;
2677         ssize_t result = 0;
2678         int r;
2679
2680         if (size & 0x3 || *pos & 0x3)
2681                 return -EINVAL;
2682
2683         while (size) {
2684                 uint32_t value;
2685
2686                 value = RREG32_PCIE(*pos >> 2);
2687                 r = put_user(value, (uint32_t *)buf);
2688                 if (r)
2689                         return r;
2690
2691                 result += 4;
2692                 buf += 4;
2693                 *pos += 4;
2694                 size -= 4;
2695         }
2696
2697         return result;
2698 }
2699
2700 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2701                                          size_t size, loff_t *pos)
2702 {
2703         struct amdgpu_device *adev = file_inode(f)->i_private;
2704         ssize_t result = 0;
2705         int r;
2706
2707         if (size & 0x3 || *pos & 0x3)
2708                 return -EINVAL;
2709
2710         while (size) {
2711                 uint32_t value;
2712
2713                 r = get_user(value, (uint32_t *)buf);
2714                 if (r)
2715                         return r;
2716
2717                 WREG32_PCIE(*pos >> 2, value);
2718
2719                 result += 4;
2720                 buf += 4;
2721                 *pos += 4;
2722                 size -= 4;
2723         }
2724
2725         return result;
2726 }
2727
2728 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2729                                         size_t size, loff_t *pos)
2730 {
2731         struct amdgpu_device *adev = file_inode(f)->i_private;
2732         ssize_t result = 0;
2733         int r;
2734
2735         if (size & 0x3 || *pos & 0x3)
2736                 return -EINVAL;
2737
2738         while (size) {
2739                 uint32_t value;
2740
2741                 value = RREG32_DIDT(*pos >> 2);
2742                 r = put_user(value, (uint32_t *)buf);
2743                 if (r)
2744                         return r;
2745
2746                 result += 4;
2747                 buf += 4;
2748                 *pos += 4;
2749                 size -= 4;
2750         }
2751
2752         return result;
2753 }
2754
2755 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2756                                          size_t size, loff_t *pos)
2757 {
2758         struct amdgpu_device *adev = file_inode(f)->i_private;
2759         ssize_t result = 0;
2760         int r;
2761
2762         if (size & 0x3 || *pos & 0x3)
2763                 return -EINVAL;
2764
2765         while (size) {
2766                 uint32_t value;
2767
2768                 r = get_user(value, (uint32_t *)buf);
2769                 if (r)
2770                         return r;
2771
2772                 WREG32_DIDT(*pos >> 2, value);
2773
2774                 result += 4;
2775                 buf += 4;
2776                 *pos += 4;
2777                 size -= 4;
2778         }
2779
2780         return result;
2781 }
2782
2783 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2784                                         size_t size, loff_t *pos)
2785 {
2786         struct amdgpu_device *adev = file_inode(f)->i_private;
2787         ssize_t result = 0;
2788         int r;
2789
2790         if (size & 0x3 || *pos & 0x3)
2791                 return -EINVAL;
2792
2793         while (size) {
2794                 uint32_t value;
2795
2796                 value = RREG32_SMC(*pos);
2797                 r = put_user(value, (uint32_t *)buf);
2798                 if (r)
2799                         return r;
2800
2801                 result += 4;
2802                 buf += 4;
2803                 *pos += 4;
2804                 size -= 4;
2805         }
2806
2807         return result;
2808 }
2809
2810 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2811                                          size_t size, loff_t *pos)
2812 {
2813         struct amdgpu_device *adev = file_inode(f)->i_private;
2814         ssize_t result = 0;
2815         int r;
2816
2817         if (size & 0x3 || *pos & 0x3)
2818                 return -EINVAL;
2819
2820         while (size) {
2821                 uint32_t value;
2822
2823                 r = get_user(value, (uint32_t *)buf);
2824                 if (r)
2825                         return r;
2826
2827                 WREG32_SMC(*pos, value);
2828
2829                 result += 4;
2830                 buf += 4;
2831                 *pos += 4;
2832                 size -= 4;
2833         }
2834
2835         return result;
2836 }
2837
2838 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2839                                         size_t size, loff_t *pos)
2840 {
2841         struct amdgpu_device *adev = file_inode(f)->i_private;
2842         ssize_t result = 0;
2843         int r;
2844         uint32_t *config, no_regs = 0;
2845
2846         if (size & 0x3 || *pos & 0x3)
2847                 return -EINVAL;
2848
2849         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2850         if (!config)
2851                 return -ENOMEM;
2852
2853         /* version, increment each time something is added */
2854         config[no_regs++] = 2;
2855         config[no_regs++] = adev->gfx.config.max_shader_engines;
2856         config[no_regs++] = adev->gfx.config.max_tile_pipes;
2857         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2858         config[no_regs++] = adev->gfx.config.max_sh_per_se;
2859         config[no_regs++] = adev->gfx.config.max_backends_per_se;
2860         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2861         config[no_regs++] = adev->gfx.config.max_gprs;
2862         config[no_regs++] = adev->gfx.config.max_gs_threads;
2863         config[no_regs++] = adev->gfx.config.max_hw_contexts;
2864         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2865         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2866         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2867         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2868         config[no_regs++] = adev->gfx.config.num_tile_pipes;
2869         config[no_regs++] = adev->gfx.config.backend_enable_mask;
2870         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2871         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2872         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2873         config[no_regs++] = adev->gfx.config.num_gpus;
2874         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2875         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2876         config[no_regs++] = adev->gfx.config.gb_addr_config;
2877         config[no_regs++] = adev->gfx.config.num_rbs;
2878
2879         /* rev==1 */
2880         config[no_regs++] = adev->rev_id;
2881         config[no_regs++] = adev->pg_flags;
2882         config[no_regs++] = adev->cg_flags;
2883
2884         /* rev==2 */
2885         config[no_regs++] = adev->family;
2886         config[no_regs++] = adev->external_rev_id;
2887
2888         while (size && (*pos < no_regs * 4)) {
2889                 uint32_t value;
2890
2891                 value = config[*pos >> 2];
2892                 r = put_user(value, (uint32_t *)buf);
2893                 if (r) {
2894                         kfree(config);
2895                         return r;
2896                 }
2897
2898                 result += 4;
2899                 buf += 4;
2900                 *pos += 4;
2901                 size -= 4;
2902         }
2903
2904         kfree(config);
2905         return result;
2906 }
2907
2908 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2909                                         size_t size, loff_t *pos)
2910 {
2911         struct amdgpu_device *adev = file_inode(f)->i_private;
2912         int idx, r;
2913         int32_t value;
2914
2915         if (size != 4 || *pos & 0x3)
2916                 return -EINVAL;
2917
2918         /* convert offset to sensor number */
2919         idx = *pos >> 2;
2920
2921         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2922                 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2923         else
2924                 return -EINVAL;
2925
2926         if (!r)
2927                 r = put_user(value, (int32_t *)buf);
2928
2929         return !r ? 4 : r;
2930 }
2931
2932 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
2933                                         size_t size, loff_t *pos)
2934 {
2935         struct amdgpu_device *adev = f->f_inode->i_private;
2936         int r, x;
2937         ssize_t result=0;
2938         uint32_t offset, se, sh, cu, wave, simd, data[32];
2939
2940         if (size & 3 || *pos & 3)
2941                 return -EINVAL;
2942
2943         /* decode offset */
2944         offset = (*pos & 0x7F);
2945         se = ((*pos >> 7) & 0xFF);
2946         sh = ((*pos >> 15) & 0xFF);
2947         cu = ((*pos >> 23) & 0xFF);
2948         wave = ((*pos >> 31) & 0xFF);
2949         simd = ((*pos >> 37) & 0xFF);
2950
2951         /* switch to the specific se/sh/cu */
2952         mutex_lock(&adev->grbm_idx_mutex);
2953         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
2954
2955         x = 0;
2956         if (adev->gfx.funcs->read_wave_data)
2957                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
2958
2959         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
2960         mutex_unlock(&adev->grbm_idx_mutex);
2961
2962         if (!x)
2963                 return -EINVAL;
2964
2965         while (size && (offset < x * 4)) {
2966                 uint32_t value;
2967
2968                 value = data[offset >> 2];
2969                 r = put_user(value, (uint32_t *)buf);
2970                 if (r)
2971                         return r;
2972
2973                 result += 4;
2974                 buf += 4;
2975                 offset += 4;
2976                 size -= 4;
2977         }
2978
2979         return result;
2980 }
2981
2982 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
2983                                         size_t size, loff_t *pos)
2984 {
2985         struct amdgpu_device *adev = f->f_inode->i_private;
2986         int r;
2987         ssize_t result = 0;
2988         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
2989
2990         if (size & 3 || *pos & 3)
2991                 return -EINVAL;
2992
2993         /* decode offset */
2994         offset = (*pos & 0xFFF);       /* in dwords */
2995         se = ((*pos >> 12) & 0xFF);
2996         sh = ((*pos >> 20) & 0xFF);
2997         cu = ((*pos >> 28) & 0xFF);
2998         wave = ((*pos >> 36) & 0xFF);
2999         simd = ((*pos >> 44) & 0xFF);
3000         thread = ((*pos >> 52) & 0xFF);
3001         bank = ((*pos >> 60) & 1);
3002
3003         data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3004         if (!data)
3005                 return -ENOMEM;
3006
3007         /* switch to the specific se/sh/cu */
3008         mutex_lock(&adev->grbm_idx_mutex);
3009         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3010
3011         if (bank == 0) {
3012                 if (adev->gfx.funcs->read_wave_vgprs)
3013                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3014         } else {
3015                 if (adev->gfx.funcs->read_wave_sgprs)
3016                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3017         }
3018
3019         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3020         mutex_unlock(&adev->grbm_idx_mutex);
3021
3022         while (size) {
3023                 uint32_t value;
3024
3025                 value = data[offset++];
3026                 r = put_user(value, (uint32_t *)buf);
3027                 if (r) {
3028                         result = r;
3029                         goto err;
3030                 }
3031
3032                 result += 4;
3033                 buf += 4;
3034                 size -= 4;
3035         }
3036
3037 err:
3038         kfree(data);
3039         return result;
3040 }
3041
3042 static const struct file_operations amdgpu_debugfs_regs_fops = {
3043         .owner = THIS_MODULE,
3044         .read = amdgpu_debugfs_regs_read,
3045         .write = amdgpu_debugfs_regs_write,
3046         .llseek = default_llseek
3047 };
3048 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3049         .owner = THIS_MODULE,
3050         .read = amdgpu_debugfs_regs_didt_read,
3051         .write = amdgpu_debugfs_regs_didt_write,
3052         .llseek = default_llseek
3053 };
3054 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3055         .owner = THIS_MODULE,
3056         .read = amdgpu_debugfs_regs_pcie_read,
3057         .write = amdgpu_debugfs_regs_pcie_write,
3058         .llseek = default_llseek
3059 };
3060 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3061         .owner = THIS_MODULE,
3062         .read = amdgpu_debugfs_regs_smc_read,
3063         .write = amdgpu_debugfs_regs_smc_write,
3064         .llseek = default_llseek
3065 };
3066
3067 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3068         .owner = THIS_MODULE,
3069         .read = amdgpu_debugfs_gca_config_read,
3070         .llseek = default_llseek
3071 };
3072
3073 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3074         .owner = THIS_MODULE,
3075         .read = amdgpu_debugfs_sensor_read,
3076         .llseek = default_llseek
3077 };
3078
3079 static const struct file_operations amdgpu_debugfs_wave_fops = {
3080         .owner = THIS_MODULE,
3081         .read = amdgpu_debugfs_wave_read,
3082         .llseek = default_llseek
3083 };
3084 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3085         .owner = THIS_MODULE,
3086         .read = amdgpu_debugfs_gpr_read,
3087         .llseek = default_llseek
3088 };
3089
3090 static const struct file_operations *debugfs_regs[] = {
3091         &amdgpu_debugfs_regs_fops,
3092         &amdgpu_debugfs_regs_didt_fops,
3093         &amdgpu_debugfs_regs_pcie_fops,
3094         &amdgpu_debugfs_regs_smc_fops,
3095         &amdgpu_debugfs_gca_config_fops,
3096         &amdgpu_debugfs_sensors_fops,
3097         &amdgpu_debugfs_wave_fops,
3098         &amdgpu_debugfs_gpr_fops,
3099 };
3100
3101 static const char *debugfs_regs_names[] = {
3102         "amdgpu_regs",
3103         "amdgpu_regs_didt",
3104         "amdgpu_regs_pcie",
3105         "amdgpu_regs_smc",
3106         "amdgpu_gca_config",
3107         "amdgpu_sensors",
3108         "amdgpu_wave",
3109         "amdgpu_gpr",
3110 };
3111
3112 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3113 {
3114         struct drm_minor *minor = adev->ddev->primary;
3115         struct dentry *ent, *root = minor->debugfs_root;
3116         unsigned i, j;
3117
3118         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3119                 ent = debugfs_create_file(debugfs_regs_names[i],
3120                                           S_IFREG | S_IRUGO, root,
3121                                           adev, debugfs_regs[i]);
3122                 if (IS_ERR(ent)) {
3123                         for (j = 0; j < i; j++) {
3124                                 debugfs_remove(adev->debugfs_regs[i]);
3125                                 adev->debugfs_regs[i] = NULL;
3126                         }
3127                         return PTR_ERR(ent);
3128                 }
3129
3130                 if (!i)
3131                         i_size_write(ent->d_inode, adev->rmmio_size);
3132                 adev->debugfs_regs[i] = ent;
3133         }
3134
3135         return 0;
3136 }
3137
3138 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3139 {
3140         unsigned i;
3141
3142         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3143                 if (adev->debugfs_regs[i]) {
3144                         debugfs_remove(adev->debugfs_regs[i]);
3145                         adev->debugfs_regs[i] = NULL;
3146                 }
3147         }
3148 }
3149
3150 int amdgpu_debugfs_init(struct drm_minor *minor)
3151 {
3152         return 0;
3153 }
3154
3155 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
3156 {
3157 }
3158 #else
3159 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3160 {
3161         return 0;
3162 }
3163 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
3164 #endif