drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  33 {
  34         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  35                                                 firmwareinfo);
  36         uint16_t data_offset;
  37
  38         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  39                                           NULL, NULL, &data_offset)) {
  40                 struct atom_firmware_info_v3_1 *firmware_info =
  41                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  42                                                            data_offset);
  43
  44                 if (le32_to_cpu(firmware_info->firmware_capability) &
  45                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  46                         return true;
  47         }
  48         return false;
  49 }
  50
  51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  52 {
  53         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  54                                                 firmwareinfo);
  55         uint16_t data_offset;
  56
  57         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  58                                           NULL, NULL, &data_offset)) {
  59                 struct atom_firmware_info_v3_1 *firmware_info =
  60                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  61                                                            data_offset);
  62
  63                 adev->bios_scratch_reg_offset =
  64                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  65         }
  66 }
  67
  68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  69 {
  70         struct atom_context *ctx = adev->mode_info.atom_context;
  71         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  72                                                 vram_usagebyfirmware);
  73         struct vram_usagebyfirmware_v2_1 *firmware_usage;
  74         uint32_t start_addr, size;
  75         uint16_t data_offset;
  76         int usage_bytes = 0;
  77
  78         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  79                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  81                           le32_to_cpu(firmware_usage->start_address_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  84
  85                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  86                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  87
  88                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  89                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  90                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  91                         /* Firmware request VRAM reservation for SR-IOV */
  92                         adev->mman.fw_vram_usage_start_offset = (start_addr &
  93                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  94                         adev->mman.fw_vram_usage_size = size << 10;
  95                         /* Use the default scratch size */
  96                         usage_bytes = 0;
  97                 } else {
  98                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  99                 }
 100         }
 101         ctx->scratch_size_bytes = 0;
 102         if (usage_bytes == 0)
 103                 usage_bytes = 20 * 1024;
 104         /* allocate some scratch memory */
 105         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 106         if (!ctx->scratch)
 107                 return -ENOMEM;
 108         ctx->scratch_size_bytes = usage_bytes;
 109         return 0;
 110 }
 111
 112 union igp_info {
 113         struct atom_integrated_system_info_v1_11 v11;
 114         struct atom_integrated_system_info_v1_12 v12;
 115         struct atom_integrated_system_info_v2_1 v21;
 116 };
 117
 118 union umc_info {
 119         struct atom_umc_info_v3_1 v31;
 120         struct atom_umc_info_v3_2 v32;
 121         struct atom_umc_info_v3_3 v33;
 122 };
 123
 124 union vram_info {
 125         struct atom_vram_info_header_v2_3 v23;
 126         struct atom_vram_info_header_v2_4 v24;
 127         struct atom_vram_info_header_v2_5 v25;
 128         struct atom_vram_info_header_v2_6 v26;
 129 };
 130
 131 union vram_module {
 132         struct atom_vram_module_v9 v9;
 133         struct atom_vram_module_v10 v10;
 134         struct atom_vram_module_v11 v11;
 135 };
 136
 137 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 138                                               int atom_mem_type)
 139 {
 140         int vram_type;
 141
 142         if (adev->flags & AMD_IS_APU) {
 143                 switch (atom_mem_type) {
 144                 case Ddr2MemType:
 145                 case LpDdr2MemType:
 146                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 147                         break;
 148                 case Ddr3MemType:
 149                 case LpDdr3MemType:
 150                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 151                         break;
 152                 case Ddr4MemType:
 153                 case LpDdr4MemType:
 154                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 155                         break;
 156                 case Ddr5MemType:
 157                 case LpDdr5MemType:
 158                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 159                         break;
 160                 default:
 161                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 162                         break;
 163                 }
 164         } else {
 165                 switch (atom_mem_type) {
 166                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 167                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 168                         break;
 169                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 170                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 171                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 172                         break;
 173                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 174                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 175                         break;
 176                 default:
 177                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 178                         break;
 179                 }
 180         }
 181
 182         return vram_type;
 183 }
 184
 185
 186 int
 187 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 188                                   int *vram_width, int *vram_type,
 189                                   int *vram_vendor)
 190 {
 191         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 192         int index, i = 0;
 193         u16 data_offset, size;
 194         union igp_info *igp_info;
 195         union vram_info *vram_info;
 196         union vram_module *vram_module;
 197         u8 frev, crev;
 198         u8 mem_type;
 199         u8 mem_vendor;
 200         u32 mem_channel_number;
 201         u32 mem_channel_width;
 202         u32 module_id;
 203
 204         if (adev->flags & AMD_IS_APU)
 205                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 206                                                     integratedsysteminfo);
 207         else
 208                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 209                                                     vram_info);
 210
 211         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 212                                           index, &size,
 213                                           &frev, &crev, &data_offset)) {
 214                 if (adev->flags & AMD_IS_APU) {
 215                         igp_info = (union igp_info *)
 216                                 (mode_info->atom_context->bios + data_offset);
 217                         switch (frev) {
 218                         case 1:
 219                                 switch (crev) {
 220                                 case 11:
 221                                 case 12:
 222                                         mem_channel_number = igp_info->v11.umachannelnumber;
 223                                         if (!mem_channel_number)
 224                                                 mem_channel_number = 1;
 225                                         /* channel width is 64 */
 226                                         if (vram_width)
 227                                                 *vram_width = mem_channel_number * 64;
 228                                         mem_type = igp_info->v11.memorytype;
 229                                         if (vram_type)
 230                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 231                                         break;
 232                                 default:
 233                                         return -EINVAL;
 234                                 }
 235                                 break;
 236                         case 2:
 237                                 switch (crev) {
 238                                 case 1:
 239                                 case 2:
 240                                         mem_channel_number = igp_info->v21.umachannelnumber;
 241                                         if (!mem_channel_number)
 242                                                 mem_channel_number = 1;
 243                                         /* channel width is 64 */
 244                                         if (vram_width)
 245                                                 *vram_width = mem_channel_number * 64;
 246                                         mem_type = igp_info->v21.memorytype;
 247                                         if (vram_type)
 248                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 249                                         break;
 250                                 default:
 251                                         return -EINVAL;
 252                                 }
 253                                 break;
 254                         default:
 255                                 return -EINVAL;
 256                         }
 257                 } else {
 258                         vram_info = (union vram_info *)
 259                                 (mode_info->atom_context->bios + data_offset);
 260                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 261                         switch (crev) {
 262                         case 3:
 263                                 if (module_id > vram_info->v23.vram_module_num)
 264                                         module_id = 0;
 265                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 266                                 while (i < module_id) {
 267                                         vram_module = (union vram_module *)
 268                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 269                                         i++;
 270                                 }
 271                                 mem_type = vram_module->v9.memory_type;
 272                                 if (vram_type)
 273                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 274                                 mem_channel_number = vram_module->v9.channel_num;
 275                                 mem_channel_width = vram_module->v9.channel_width;
 276                                 if (vram_width)
 277                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 278                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 279                                 if (vram_vendor)
 280                                         *vram_vendor = mem_vendor;
 281                                 break;
 282                         case 4:
 283                                 if (module_id > vram_info->v24.vram_module_num)
 284                                         module_id = 0;
 285                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 286                                 while (i < module_id) {
 287                                         vram_module = (union vram_module *)
 288                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 289                                         i++;
 290                                 }
 291                                 mem_type = vram_module->v10.memory_type;
 292                                 if (vram_type)
 293                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 294                                 mem_channel_number = vram_module->v10.channel_num;
 295                                 mem_channel_width = vram_module->v10.channel_width;
 296                                 if (vram_width)
 297                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 298                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 299                                 if (vram_vendor)
 300                                         *vram_vendor = mem_vendor;
 301                                 break;
 302                         case 5:
 303                                 if (module_id > vram_info->v25.vram_module_num)
 304                                         module_id = 0;
 305                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 306                                 while (i < module_id) {
 307                                         vram_module = (union vram_module *)
 308                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 309                                         i++;
 310                                 }
 311                                 mem_type = vram_module->v11.memory_type;
 312                                 if (vram_type)
 313                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 314                                 mem_channel_number = vram_module->v11.channel_num;
 315                                 mem_channel_width = vram_module->v11.channel_width;
 316                                 if (vram_width)
 317                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 318                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 319                                 if (vram_vendor)
 320                                         *vram_vendor = mem_vendor;
 321                                 break;
 322                         case 6:
 323                                 if (module_id > vram_info->v26.vram_module_num)
 324                                         module_id = 0;
 325                                 vram_module = (union vram_module *)vram_info->v26.vram_module;
 326                                 while (i < module_id) {
 327                                         vram_module = (union vram_module *)
 328                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 329                                         i++;
 330                                 }
 331                                 mem_type = vram_module->v9.memory_type;
 332                                 if (vram_type)
 333                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 334                                 mem_channel_number = vram_module->v9.channel_num;
 335                                 mem_channel_width = vram_module->v9.channel_width;
 336                                 if (vram_width)
 337                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 338                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 339                                 if (vram_vendor)
 340                                         *vram_vendor = mem_vendor;
 341                                 break;
 342                         default:
 343                                 return -EINVAL;
 344                         }
 345                 }
 346
 347         }
 348
 349         return 0;
 350 }
 351
 352 /*
 353  * Return true if vbios enabled ecc by default, if umc info table is available
 354  * or false if ecc is not enabled or umc info table is not available
 355  */
 356 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 357 {
 358         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 359         int index;
 360         u16 data_offset, size;
 361         union umc_info *umc_info;
 362         u8 frev, crev;
 363         bool ecc_default_enabled = false;
 364
 365         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 366                         umc_info);
 367
 368         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 369                                 index, &size, &frev, &crev, &data_offset)) {
 370                 if (frev == 3) {
 371                         umc_info = (union umc_info *)
 372                                 (mode_info->atom_context->bios + data_offset);
 373                         switch (crev) {
 374                         case 1:
 375                                 ecc_default_enabled =
 376                                         (le32_to_cpu(umc_info->v31.umc_config) &
 377                                          UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 378                                 break;
 379                         case 2:
 380                                 ecc_default_enabled =
 381                                         (le32_to_cpu(umc_info->v32.umc_config) &
 382                                          UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 383                                 break;
 384                         case 3:
 385                                 ecc_default_enabled =
 386                                         (le32_to_cpu(umc_info->v33.umc_config1) &
 387                                          UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
 388                                 break;
 389                         default:
 390                                 /* unsupported crev */
 391                                 return false;
 392                         }
 393                 }
 394         }
 395
 396         return ecc_default_enabled;
 397 }
 398
 399 union firmware_info {
 400         struct atom_firmware_info_v3_1 v31;
 401         struct atom_firmware_info_v3_2 v32;
 402         struct atom_firmware_info_v3_3 v33;
 403         struct atom_firmware_info_v3_4 v34;
 404 };
 405
 406 /*
 407  * Return true if vbios supports sram ecc or false if not
 408  */
 409 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 410 {
 411         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 412         int index;
 413         u16 data_offset, size;
 414         union firmware_info *firmware_info;
 415         u8 frev, crev;
 416         bool sram_ecc_supported = false;
 417
 418         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 419                         firmwareinfo);
 420
 421         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 422                                 index, &size, &frev, &crev, &data_offset)) {
 423                 /* support firmware_info 3.1 + */
 424                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 425                         firmware_info = (union firmware_info *)
 426                                 (mode_info->atom_context->bios + data_offset);
 427                         sram_ecc_supported =
 428                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 429                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 430                 }
 431         }
 432
 433         return sram_ecc_supported;
 434 }
 435
 436 union smu_info {
 437         struct atom_smu_info_v3_1 v31;
 438 };
 439
 440 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 441 {
 442         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 443         struct amdgpu_pll *spll = &adev->clock.spll;
 444         struct amdgpu_pll *mpll = &adev->clock.mpll;
 445         uint8_t frev, crev;
 446         uint16_t data_offset;
 447         int ret = -EINVAL, index;
 448
 449         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 450                                             firmwareinfo);
 451         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 452                                    &frev, &crev, &data_offset)) {
 453                 union firmware_info *firmware_info =
 454                         (union firmware_info *)(mode_info->atom_context->bios +
 455                                                 data_offset);
 456
 457                 adev->clock.default_sclk =
 458                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 459                 adev->clock.default_mclk =
 460                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 461
 462                 adev->pm.current_sclk = adev->clock.default_sclk;
 463                 adev->pm.current_mclk = adev->clock.default_mclk;
 464
 465                 /* not technically a clock, but... */
 466                 adev->mode_info.firmware_flags =
 467                         le32_to_cpu(firmware_info->v31.firmware_capability);
 468
 469                 ret = 0;
 470         }
 471
 472         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 473                                             smu_info);
 474         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 475                                    &frev, &crev, &data_offset)) {
 476                 union smu_info *smu_info =
 477                         (union smu_info *)(mode_info->atom_context->bios +
 478                                            data_offset);
 479
 480                 /* system clock */
 481                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 482
 483                 spll->reference_div = 0;
 484                 spll->min_post_div = 1;
 485                 spll->max_post_div = 1;
 486                 spll->min_ref_div = 2;
 487                 spll->max_ref_div = 0xff;
 488                 spll->min_feedback_div = 4;
 489                 spll->max_feedback_div = 0xff;
 490                 spll->best_vco = 0;
 491
 492                 ret = 0;
 493         }
 494
 495         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 496                                             umc_info);
 497         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 498                                    &frev, &crev, &data_offset)) {
 499                 union umc_info *umc_info =
 500                         (union umc_info *)(mode_info->atom_context->bios +
 501                                            data_offset);
 502
 503                 /* memory clock */
 504                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 505
 506                 mpll->reference_div = 0;
 507                 mpll->min_post_div = 1;
 508                 mpll->max_post_div = 1;
 509                 mpll->min_ref_div = 2;
 510                 mpll->max_ref_div = 0xff;
 511                 mpll->min_feedback_div = 4;
 512                 mpll->max_feedback_div = 0xff;
 513                 mpll->best_vco = 0;
 514
 515                 ret = 0;
 516         }
 517
 518         return ret;
 519 }
 520
 521 union gfx_info {
 522         struct atom_gfx_info_v2_4 v24;
 523         struct atom_gfx_info_v2_7 v27;
 524 };
 525
 526 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 527 {
 528         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 529         int index;
 530         uint8_t frev, crev;
 531         uint16_t data_offset;
 532
 533         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 534                                             gfx_info);
 535         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 536                                    &frev, &crev, &data_offset)) {
 537                 union gfx_info *gfx_info = (union gfx_info *)
 538                         (mode_info->atom_context->bios + data_offset);
 539                 switch (crev) {
 540                 case 4:
 541                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 542                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 543                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 544                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 545                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 546                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 547                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 548                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 549                         adev->gfx.config.gs_prim_buffer_depth =
 550                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 551                         adev->gfx.config.double_offchip_lds_buf =
 552                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 553                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 554                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 555                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 556                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 557                         return 0;
 558                 case 7:
 559                         adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 560                         adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 561                         adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 562                         adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 563                         adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 564                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 565                         adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 566                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 567                         adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 568                         adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 569                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 570                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 571                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 572                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 573                         return 0;
 574                 default:
 575                         return -EINVAL;
 576                 }
 577
 578         }
 579         return -EINVAL;
 580 }
 581
 582 /*
 583  * Check if VBIOS supports GDDR6 training data save/restore
 584  */
 585 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 586 {
 587         uint16_t data_offset;
 588         int index;
 589
 590         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 591                                             firmwareinfo);
 592         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 593                                           NULL, NULL, &data_offset)) {
 594                 struct atom_firmware_info_v3_1 *firmware_info =
 595                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 596                                                            data_offset);
 597
 598                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 599                           le32_to_cpu(firmware_info->firmware_capability));
 600
 601                 if (le32_to_cpu(firmware_info->firmware_capability) &
 602                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 603                         return true;
 604         }
 605
 606         return false;
 607 }
 608
 609 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 610 {
 611         int ret;
 612         uint32_t major, minor, revision, hw_v;
 613
 614         if (gddr6_mem_train_vbios_support(adev)) {
 615                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 616                 hw_v = HW_REV(major, minor, revision);
 617                 /*
 618                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 619                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 620                  * none of the functions will be initialized, it should not cause any problems
 621                  */
 622                 switch (hw_v) {
 623                 case HW_REV(11, 0, 0):
 624                 case HW_REV(11, 0, 5):
 625                 case HW_REV(11, 0, 7):
 626                 case HW_REV(11, 0, 11):
 627                 case HW_REV(11, 0, 12):
 628                         ret = 1;
 629                         break;
 630                 default:
 631                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 632                                   " doesn't support!\n", hw_v);
 633                         ret = -1;
 634                         break;
 635                 }
 636         } else {
 637                 ret = 0;
 638                 hw_v = -1;
 639         }
 640
 641
 642         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 643         return ret;
 644 }
 645
 646 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 647 {
 648         struct atom_context *ctx = adev->mode_info.atom_context;
 649         union firmware_info *firmware_info;
 650         int index;
 651         u16 data_offset, size;
 652         u8 frev, crev;
 653         int fw_reserved_fb_size;
 654
 655         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 656                         firmwareinfo);
 657
 658         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 659                                 &frev, &crev, &data_offset))
 660                 /* fail to parse data_header */
 661                 return 0;
 662
 663         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 664
 665         if (frev !=3)
 666                 return -EINVAL;
 667
 668         switch (crev) {
 669         case 4:
 670                 fw_reserved_fb_size =
 671                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 672                 break;
 673         default:
 674                 fw_reserved_fb_size = 0;
 675                 break;
 676         }
 677
 678         return fw_reserved_fb_size;
 679 }