drivers/scsi/pm8001/pm8001_sas.h

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #ifndef _PM8001_SAS_H_
  42 #define _PM8001_SAS_H_
  43
  44 #include <linux/kernel.h>
  45 #include <linux/module.h>
  46 #include <linux/spinlock.h>
  47 #include <linux/delay.h>
  48 #include <linux/types.h>
  49 #include <linux/ctype.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/pci.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/workqueue.h>
  54 #include <scsi/libsas.h>
  55 #include <scsi/scsi_tcq.h>
  56 #include <scsi/sas_ata.h>
  57 #include <linux/atomic.h>
  58 #include "pm8001_defs.h"
  59
  60 #define DRV_NAME                "pm80xx"
  61 #define DRV_VERSION             "0.1.40"
  62 #define PM8001_FAIL_LOGGING     0x01 /* Error message logging */
  63 #define PM8001_INIT_LOGGING     0x02 /* driver init logging */
  64 #define PM8001_DISC_LOGGING     0x04 /* discovery layer logging */
  65 #define PM8001_IO_LOGGING       0x08 /* I/O path logging */
  66 #define PM8001_EH_LOGGING       0x10 /* libsas EH function logging*/
  67 #define PM8001_IOCTL_LOGGING    0x20 /* IOCTL message logging */
  68 #define PM8001_MSG_LOGGING      0x40 /* misc message logging */
  69 #define PM8001_DEV_LOGGING      0x80 /* development message logging */
  70 #define PM8001_DEVIO_LOGGING    0x100 /* development io message logging */
  71 #define PM8001_IOERR_LOGGING    0x200 /* development io err message logging */
  72 #define pm8001_printk(format, arg...)   pr_info("%s:: %s  %d:" \
  73                         format, pm8001_ha->name, __func__, __LINE__, ## arg)
  74 #define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD)   \
  75 do {                                            \
  76         if (unlikely(HBA->logging_level & LEVEL))       \
  77                 do {                                    \
  78                         CMD;                            \
  79                 } while (0);                            \
  80 } while (0);
  81
  82 #define PM8001_EH_DBG(HBA, CMD)                 \
  83         PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
  84
  85 #define PM8001_INIT_DBG(HBA, CMD)               \
  86         PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
  87
  88 #define PM8001_DISC_DBG(HBA, CMD)               \
  89         PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
  90
  91 #define PM8001_IO_DBG(HBA, CMD)         \
  92         PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
  93
  94 #define PM8001_FAIL_DBG(HBA, CMD)               \
  95         PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
  96
  97 #define PM8001_IOCTL_DBG(HBA, CMD)              \
  98         PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
  99
 100 #define PM8001_MSG_DBG(HBA, CMD)                \
 101         PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
 102
 103 #define PM8001_DEV_DBG(HBA, CMD)                \
 104         PM8001_CHECK_LOGGING(HBA, PM8001_DEV_LOGGING, CMD)
 105
 106 #define PM8001_DEVIO_DBG(HBA, CMD)              \
 107         PM8001_CHECK_LOGGING(HBA, PM8001_DEVIO_LOGGING, CMD)
 108
 109 #define PM8001_IOERR_DBG(HBA, CMD)              \
 110         PM8001_CHECK_LOGGING(HBA, PM8001_IOERR_LOGGING, CMD)
 111
 112 #define PM8001_USE_TASKLET
 113 #define PM8001_USE_MSIX
 114 #define PM8001_READ_VPD
 115
 116
 117 #define IS_SPCV_12G(dev)        ((dev->device == 0X8074)                \
 118                                 || (dev->device == 0X8076)              \
 119                                 || (dev->device == 0X8077)              \
 120                                 || (dev->device == 0X8070)              \
 121                                 || (dev->device == 0X8072))
 122
 123 #define PM8001_NAME_LENGTH              32/* generic length of strings */
 124 extern struct list_head hba_list;
 125 extern const struct pm8001_dispatch pm8001_8001_dispatch;
 126 extern const struct pm8001_dispatch pm8001_80xx_dispatch;
 127
 128 struct pm8001_hba_info;
 129 struct pm8001_ccb_info;
 130 struct pm8001_device;
 131 /* define task management IU */
 132 struct pm8001_tmf_task {
 133         u8      tmf;
 134         u32     tag_of_task_to_be_managed;
 135 };
 136 struct pm8001_ioctl_payload {
 137         u32     signature;
 138         u16     major_function;
 139         u16     minor_function;
 140         u16     status;
 141         u16     offset;
 142         u16     id;
 143         u32     wr_length;
 144         u32     rd_length;
 145         u8      *func_specific;
 146 };
 147
 148 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
 149 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
 150 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET            0x00     /* HNFBUFL */
 151 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET            0x04     /* HNFBUFH */
 152 #define MPI_FATAL_EDUMP_TABLE_LENGTH               0x08     /* HNFBLEN */
 153 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE            0x0C     /* FDDHSHK */
 154 #define MPI_FATAL_EDUMP_TABLE_STATUS               0x10     /* FDDTSTAT */
 155 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN            0x14     /* ACCDDLEN */
 156 #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN            0x18     /* TOTALLEN */
 157 #define MPI_FATAL_EDUMP_TABLE_SIGNATURE            0x1C     /* SIGNITURE */
 158 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY              0x1
 159 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY             0x0
 160 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD                 0x0
 161 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED           0x1
 162 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
 163 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE      0x3
 164 #define TYPE_GSM_SPACE        1
 165 #define TYPE_QUEUE            2
 166 #define TYPE_FATAL            3
 167 #define TYPE_NON_FATAL        4
 168 #define TYPE_INBOUND          1
 169 #define TYPE_OUTBOUND         2
 170 struct forensic_data {
 171         u32  data_type;
 172         union {
 173                 struct {
 174                         u32  direct_len;
 175                         u32  direct_offset;
 176                         void  *direct_data;
 177                 } gsm_buf;
 178                 struct {
 179                         u16  queue_type;
 180                         u16  queue_index;
 181                         u32  direct_len;
 182                         void  *direct_data;
 183                 } queue_buf;
 184                 struct {
 185                         u32  direct_len;
 186                         u32  direct_offset;
 187                         u32  read_len;
 188                         void  *direct_data;
 189                 } data_buf;
 190         };
 191 };
 192
 193 /* bit31-26 - mask bar */
 194 #define SCRATCH_PAD0_BAR_MASK                    0xFC000000
 195 /* bit25-0  - offset mask */
 196 #define SCRATCH_PAD0_OFFSET_MASK                 0x03FFFFFF
 197 /* if AAP error state */
 198 #define SCRATCH_PAD0_AAPERR_MASK                 0xFFFFFFFF
 199 /* Inbound doorbell bit7 */
 200 #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP        0x80
 201 /* Inbound doorbell bit7 SPCV */
 202 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO  0x80
 203 #define MAIN_MERRDCTO_MERRDCES                   0xA0/* DWORD 0x28) */
 204
 205 struct pm8001_dispatch {
 206         char *name;
 207         int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
 208         int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
 209         void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
 210         int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
 211         void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
 212         irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 213         u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
 214         int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 215         void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 216         void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 217         void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
 218         int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
 219                 struct pm8001_ccb_info *ccb);
 220         int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
 221                 struct pm8001_ccb_info *ccb);
 222         int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
 223                 struct pm8001_ccb_info *ccb);
 224         int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 225         int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 226         int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
 227                 struct pm8001_device *pm8001_dev, u32 flag);
 228         int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 229         int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
 230                 u32 phy_id, u32 phy_op);
 231         int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
 232                 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
 233                 u32 cmd_tag);
 234         int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
 235                 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
 236         int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 237         int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 238         int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
 239                 void *payload);
 240         int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
 241                 struct pm8001_device *pm8001_dev, u32 state);
 242         int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
 243                 u32 state);
 244         int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
 245                 u32 state);
 246         int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
 247 };
 248
 249 struct pm8001_chip_info {
 250         u32     encrypt;
 251         u32     n_phy;
 252         const struct pm8001_dispatch    *dispatch;
 253 };
 254 #define PM8001_CHIP_DISP        (pm8001_ha->chip->dispatch)
 255
 256 struct pm8001_port {
 257         struct asd_sas_port     sas_port;
 258         u8                      port_attached;
 259         u16                     wide_port_phymap;
 260         u8                      port_state;
 261         struct list_head        list;
 262 };
 263
 264 struct pm8001_phy {
 265         struct pm8001_hba_info  *pm8001_ha;
 266         struct pm8001_port      *port;
 267         struct asd_sas_phy      sas_phy;
 268         struct sas_identify     identify;
 269         struct scsi_device      *sdev;
 270         u64                     dev_sas_addr;
 271         u32                     phy_type;
 272         struct completion       *enable_completion;
 273         u32                     frame_rcvd_size;
 274         u8                      frame_rcvd[32];
 275         u8                      phy_attached;
 276         u8                      phy_state;
 277         enum sas_linkrate       minimum_linkrate;
 278         enum sas_linkrate       maximum_linkrate;
 279         struct completion       *reset_completion;
 280         bool                    port_reset_status;
 281         bool                    reset_success;
 282 };
 283
 284 /* port reset status */
 285 #define PORT_RESET_SUCCESS      0x00
 286 #define PORT_RESET_TMO          0x01
 287
 288 struct pm8001_device {
 289         enum sas_device_type    dev_type;
 290         struct domain_device    *sas_device;
 291         u32                     attached_phy;
 292         u32                     id;
 293         struct completion       *dcompletion;
 294         struct completion       *setds_completion;
 295         u32                     device_id;
 296         u32                     running_req;
 297 };
 298
 299 struct pm8001_prd_imt {
 300         __le32                  len;
 301         __le32                  e;
 302 };
 303
 304 struct pm8001_prd {
 305         __le64                  addr;           /* 64-bit buffer address */
 306         struct pm8001_prd_imt   im_len;         /* 64-bit length */
 307 } __attribute__ ((packed));
 308 /*
 309  * CCB(Command Control Block)
 310  */
 311 struct pm8001_ccb_info {
 312         struct list_head        entry;
 313         struct sas_task         *task;
 314         u32                     n_elem;
 315         u32                     ccb_tag;
 316         dma_addr_t              ccb_dma_handle;
 317         struct pm8001_device    *device;
 318         struct pm8001_prd       *buf_prd;
 319         struct fw_control_ex    *fw_control_context;
 320         u8                      open_retry;
 321 };
 322
 323 struct mpi_mem {
 324         void                    *virt_ptr;
 325         dma_addr_t              phys_addr;
 326         u32                     phys_addr_hi;
 327         u32                     phys_addr_lo;
 328         u32                     total_len;
 329         u32                     num_elements;
 330         u32                     element_size;
 331         u32                     alignment;
 332 };
 333
 334 struct mpi_mem_req {
 335         /* The number of element in the  mpiMemory array */
 336         u32                     count;
 337         /* The array of structures that define memroy regions*/
 338         struct mpi_mem          region[USI_MAX_MEMCNT];
 339 };
 340
 341 struct encrypt {
 342         u32     cipher_mode;
 343         u32     sec_mode;
 344         u32     status;
 345         u32     flag;
 346 };
 347
 348 struct sas_phy_attribute_table {
 349         u32     phystart1_16[16];
 350         u32     outbound_hw_event_pid1_16[16];
 351 };
 352
 353 union main_cfg_table {
 354         struct {
 355         u32                     signature;
 356         u32                     interface_rev;
 357         u32                     firmware_rev;
 358         u32                     max_out_io;
 359         u32                     max_sgl;
 360         u32                     ctrl_cap_flag;
 361         u32                     gst_offset;
 362         u32                     inbound_queue_offset;
 363         u32                     outbound_queue_offset;
 364         u32                     inbound_q_nppd_hppd;
 365         u32                     outbound_hw_event_pid0_3;
 366         u32                     outbound_hw_event_pid4_7;
 367         u32                     outbound_ncq_event_pid0_3;
 368         u32                     outbound_ncq_event_pid4_7;
 369         u32                     outbound_tgt_ITNexus_event_pid0_3;
 370         u32                     outbound_tgt_ITNexus_event_pid4_7;
 371         u32                     outbound_tgt_ssp_event_pid0_3;
 372         u32                     outbound_tgt_ssp_event_pid4_7;
 373         u32                     outbound_tgt_smp_event_pid0_3;
 374         u32                     outbound_tgt_smp_event_pid4_7;
 375         u32                     upper_event_log_addr;
 376         u32                     lower_event_log_addr;
 377         u32                     event_log_size;
 378         u32                     event_log_option;
 379         u32                     upper_iop_event_log_addr;
 380         u32                     lower_iop_event_log_addr;
 381         u32                     iop_event_log_size;
 382         u32                     iop_event_log_option;
 383         u32                     fatal_err_interrupt;
 384         u32                     fatal_err_dump_offset0;
 385         u32                     fatal_err_dump_length0;
 386         u32                     fatal_err_dump_offset1;
 387         u32                     fatal_err_dump_length1;
 388         u32                     hda_mode_flag;
 389         u32                     anolog_setup_table_offset;
 390         u32                     rsvd[4];
 391         } pm8001_tbl;
 392
 393         struct {
 394         u32                     signature;
 395         u32                     interface_rev;
 396         u32                     firmware_rev;
 397         u32                     max_out_io;
 398         u32                     max_sgl;
 399         u32                     ctrl_cap_flag;
 400         u32                     gst_offset;
 401         u32                     inbound_queue_offset;
 402         u32                     outbound_queue_offset;
 403         u32                     inbound_q_nppd_hppd;
 404         u32                     rsvd[8];
 405         u32                     crc_core_dump;
 406         u32                     rsvd1;
 407         u32                     upper_event_log_addr;
 408         u32                     lower_event_log_addr;
 409         u32                     event_log_size;
 410         u32                     event_log_severity;
 411         u32                     upper_pcs_event_log_addr;
 412         u32                     lower_pcs_event_log_addr;
 413         u32                     pcs_event_log_size;
 414         u32                     pcs_event_log_severity;
 415         u32                     fatal_err_interrupt;
 416         u32                     fatal_err_dump_offset0;
 417         u32                     fatal_err_dump_length0;
 418         u32                     fatal_err_dump_offset1;
 419         u32                     fatal_err_dump_length1;
 420         u32                     gpio_led_mapping;
 421         u32                     analog_setup_table_offset;
 422         u32                     int_vec_table_offset;
 423         u32                     phy_attr_table_offset;
 424         u32                     port_recovery_timer;
 425         u32                     interrupt_reassertion_delay;
 426         u32                     fatal_n_non_fatal_dump;         /* 0x28 */
 427         u32                     ila_version;
 428         u32                     inc_fw_version;
 429         } pm80xx_tbl;
 430 };
 431
 432 union general_status_table {
 433         struct {
 434         u32                     gst_len_mpistate;
 435         u32                     iq_freeze_state0;
 436         u32                     iq_freeze_state1;
 437         u32                     msgu_tcnt;
 438         u32                     iop_tcnt;
 439         u32                     rsvd;
 440         u32                     phy_state[8];
 441         u32                     gpio_input_val;
 442         u32                     rsvd1[2];
 443         u32                     recover_err_info[8];
 444         } pm8001_tbl;
 445         struct {
 446         u32                     gst_len_mpistate;
 447         u32                     iq_freeze_state0;
 448         u32                     iq_freeze_state1;
 449         u32                     msgu_tcnt;
 450         u32                     iop_tcnt;
 451         u32                     rsvd[9];
 452         u32                     gpio_input_val;
 453         u32                     rsvd1[2];
 454         u32                     recover_err_info[8];
 455         } pm80xx_tbl;
 456 };
 457 struct inbound_queue_table {
 458         u32                     element_pri_size_cnt;
 459         u32                     upper_base_addr;
 460         u32                     lower_base_addr;
 461         u32                     ci_upper_base_addr;
 462         u32                     ci_lower_base_addr;
 463         u32                     pi_pci_bar;
 464         u32                     pi_offset;
 465         u32                     total_length;
 466         void                    *base_virt;
 467         void                    *ci_virt;
 468         u32                     reserved;
 469         __le32                  consumer_index;
 470         u32                     producer_idx;
 471         spinlock_t              iq_lock;
 472 };
 473 struct outbound_queue_table {
 474         u32                     element_size_cnt;
 475         u32                     upper_base_addr;
 476         u32                     lower_base_addr;
 477         void                    *base_virt;
 478         u32                     pi_upper_base_addr;
 479         u32                     pi_lower_base_addr;
 480         u32                     ci_pci_bar;
 481         u32                     ci_offset;
 482         u32                     total_length;
 483         void                    *pi_virt;
 484         u32                     interrup_vec_cnt_delay;
 485         u32                     dinterrup_to_pci_offset;
 486         __le32                  producer_index;
 487         u32                     consumer_idx;
 488 };
 489 struct pm8001_hba_memspace {
 490         void __iomem            *memvirtaddr;
 491         u64                     membase;
 492         u32                     memsize;
 493 };
 494 struct isr_param {
 495         struct pm8001_hba_info *drv_inst;
 496         u32 irq_id;
 497 };
 498 struct pm8001_hba_info {
 499         char                    name[PM8001_NAME_LENGTH];
 500         struct list_head        list;
 501         unsigned long           flags;
 502         spinlock_t              lock;/* host-wide lock */
 503         spinlock_t              bitmap_lock;
 504         struct pci_dev          *pdev;/* our device */
 505         struct device           *dev;
 506         struct pm8001_hba_memspace io_mem[6];
 507         struct mpi_mem_req      memoryMap;
 508         struct encrypt          encrypt_info; /* support encryption */
 509         struct forensic_data    forensic_info;
 510         u32                     fatal_bar_loc;
 511         u32                     forensic_last_offset;
 512         u32                     fatal_forensic_shift_offset;
 513         u32                     forensic_fatal_step;
 514         u32                     forensic_preserved_accumulated_transfer;
 515         u32                     evtlog_ib_offset;
 516         u32                     evtlog_ob_offset;
 517         void __iomem    *msg_unit_tbl_addr;/*Message Unit Table Addr*/
 518         void __iomem    *main_cfg_tbl_addr;/*Main Config Table Addr*/
 519         void __iomem    *general_stat_tbl_addr;/*General Status Table Addr*/
 520         void __iomem    *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
 521         void __iomem    *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
 522         void __iomem    *pspa_q_tbl_addr;
 523                         /*MPI SAS PHY attributes Queue Config Table Addr*/
 524         void __iomem    *ivt_tbl_addr; /*MPI IVT Table Addr */
 525         void __iomem    *fatal_tbl_addr; /*MPI IVT Table Addr */
 526         union main_cfg_table    main_cfg_tbl;
 527         union general_status_table      gs_tbl;
 528         struct inbound_queue_table      inbnd_q_tbl[PM8001_MAX_INB_NUM];
 529         struct outbound_queue_table     outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
 530         struct sas_phy_attribute_table  phy_attr_table;
 531                                         /* MPI SAS PHY attributes */
 532         u8                      sas_addr[SAS_ADDR_SIZE];
 533         struct sas_ha_struct    *sas;/* SCSI/SAS glue */
 534         struct Scsi_Host        *shost;
 535         u32                     chip_id;
 536         const struct pm8001_chip_info   *chip;
 537         struct completion       *nvmd_completion;
 538         int                     tags_num;
 539         unsigned long           *tags;
 540         struct pm8001_phy       phy[PM8001_MAX_PHYS];
 541         struct pm8001_port      port[PM8001_MAX_PHYS];
 542         u32                     id;
 543         u32                     irq;
 544         u32                     iomb_size; /* SPC and SPCV IOMB size */
 545         struct pm8001_device    *devices;
 546         struct pm8001_ccb_info  *ccb_info;
 547 #ifdef PM8001_USE_MSIX
 548         int                     number_of_intr;/*will be used in remove()*/
 549         char                    intr_drvname[PM8001_MAX_MSIX_VEC]
 550                                 [PM8001_NAME_LENGTH+1+3+1];
 551 #endif
 552 #ifdef PM8001_USE_TASKLET
 553         struct tasklet_struct   tasklet[PM8001_MAX_MSIX_VEC];
 554 #endif
 555         u32                     logging_level;
 556         u32                     link_rate;
 557         u32                     fw_status;
 558         u32                     smp_exp_mode;
 559         bool                    controller_fatal_error;
 560         const struct firmware   *fw_image;
 561         struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
 562         u32                     reset_in_progress;
 563         u32                     non_fatal_count;
 564         u32                     non_fatal_read_length;
 565         u32 max_q_num;
 566         u32 ib_offset;
 567         u32 ob_offset;
 568         u32 ci_offset;
 569         u32 pi_offset;
 570         u32 max_memcnt;
 571 };
 572
 573 struct pm8001_work {
 574         struct work_struct work;
 575         struct pm8001_hba_info *pm8001_ha;
 576         void *data;
 577         int handler;
 578 };
 579
 580 struct pm8001_fw_image_header {
 581         u8 vender_id[8];
 582         u8 product_id;
 583         u8 hardware_rev;
 584         u8 dest_partition;
 585         u8 reserved;
 586         u8 fw_rev[4];
 587         __be32  image_length;
 588         __be32 image_crc;
 589         __be32 startup_entry;
 590 } __attribute__((packed, aligned(4)));
 591
 592
 593 /**
 594  * FW Flash Update status values
 595  */
 596 #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT    0x00
 597 #define FLASH_UPDATE_IN_PROGRESS                0x01
 598 #define FLASH_UPDATE_HDR_ERR                    0x02
 599 #define FLASH_UPDATE_OFFSET_ERR                 0x03
 600 #define FLASH_UPDATE_CRC_ERR                    0x04
 601 #define FLASH_UPDATE_LENGTH_ERR                 0x05
 602 #define FLASH_UPDATE_HW_ERR                     0x06
 603 #define FLASH_UPDATE_DNLD_NOT_SUPPORTED         0x10
 604 #define FLASH_UPDATE_DISABLED                   0x11
 605
 606 #define NCQ_READ_LOG_FLAG                       0x80000000
 607 #define NCQ_ABORT_ALL_FLAG                      0x40000000
 608 #define NCQ_2ND_RLE_FLAG                        0x20000000
 609
 610 /* Device states */
 611 #define DS_OPERATIONAL                          0x01
 612 #define DS_PORT_IN_RESET                        0x02
 613 #define DS_IN_RECOVERY                          0x03
 614 #define DS_IN_ERROR                             0x04
 615 #define DS_NON_OPERATIONAL                      0x07
 616
 617 /**
 618  * brief param structure for firmware flash update.
 619  */
 620 struct fw_flash_updata_info {
 621         u32                     cur_image_offset;
 622         u32                     cur_image_len;
 623         u32                     total_image_len;
 624         struct pm8001_prd       sgl;
 625 };
 626
 627 struct fw_control_info {
 628         u32                     retcode;/*ret code (status)*/
 629         u32                     phase;/*ret code phase*/
 630         u32                     phaseCmplt;/*percent complete for the current
 631         update phase */
 632         u32                     version;/*Hex encoded firmware version number*/
 633         u32                     offset;/*Used for downloading firmware  */
 634         u32                     len; /*len of buffer*/
 635         u32                     size;/* Used in OS VPD and Trace get size
 636         operations.*/
 637         u32                     reserved;/* padding required for 64 bit
 638         alignment */
 639         u8                      buffer[1];/* Start of buffer */
 640 };
 641 struct fw_control_ex {
 642         struct fw_control_info *fw_control;
 643         void                    *buffer;/* keep buffer pointer to be
 644         freed when the response comes*/
 645         void                    *virtAddr;/* keep virtual address of the data */
 646         void                    *usrAddr;/* keep virtual address of the
 647         user data */
 648         dma_addr_t              phys_addr;
 649         u32                     len; /* len of buffer  */
 650         void                    *payload; /* pointer to IOCTL Payload */
 651         u8                      inProgress;/*if 1 - the IOCTL request is in
 652         progress */
 653         void                    *param1;
 654         void                    *param2;
 655         void                    *param3;
 656 };
 657
 658 /* pm8001 workqueue */
 659 extern struct workqueue_struct *pm8001_wq;
 660
 661 /******************** function prototype *********************/
 662 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
 663 void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
 664 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
 665 void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
 666         struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
 667 int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
 668         void *funcdata);
 669 void pm8001_scan_start(struct Scsi_Host *shost);
 670 int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
 671 int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
 672 int pm8001_abort_task(struct sas_task *task);
 673 int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
 674 int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
 675 int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
 676 int pm8001_dev_found(struct domain_device *dev);
 677 void pm8001_dev_gone(struct domain_device *dev);
 678 int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
 679 int pm8001_I_T_nexus_reset(struct domain_device *dev);
 680 int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
 681 int pm8001_query_task(struct sas_task *task);
 682 void pm8001_open_reject_retry(
 683         struct pm8001_hba_info *pm8001_ha,
 684         struct sas_task *task_to_close,
 685         struct pm8001_device *device_to_close);
 686 int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
 687         dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
 688         u32 mem_size, u32 align);
 689
 690 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
 691 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
 692                         struct inbound_queue_table *circularQ,
 693                         u32 opCode, void *payload, size_t nb,
 694                         u32 responseQueue);
 695 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
 696                                 u16 messageSize, void **messagePtr);
 697 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
 698                         struct outbound_queue_table *circularQ, u8 bc);
 699 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
 700                         struct outbound_queue_table *circularQ,
 701                         void **messagePtr1, u8 *pBC);
 702 int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
 703                         struct pm8001_device *pm8001_dev, u32 state);
 704 int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
 705                                         void *payload);
 706 int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
 707                                         void *fw_flash_updata_info, u32 tag);
 708 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 709 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 710 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
 711                                 struct pm8001_ccb_info *ccb,
 712                                 struct pm8001_tmf_task *tmf);
 713 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
 714                                 struct pm8001_device *pm8001_dev,
 715                                 u8 flag, u32 task_tag, u32 cmd_tag);
 716 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 717 void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
 718 void pm8001_work_fn(struct work_struct *work);
 719 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
 720                                         void *data, int handler);
 721 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
 722                                                         void *piomb);
 723 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 724                                                         void *piomb);
 725 void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 726                                                         void *piomb);
 727 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
 728                                                         void *piomb);
 729 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
 730 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
 731 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
 732 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 733 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 734 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
 735                                                         void *piomb);
 736 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
 737 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 738 struct sas_task *pm8001_alloc_task(void);
 739 void pm8001_task_done(struct sas_task *task);
 740 void pm8001_free_task(struct sas_task *task);
 741 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
 742 struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
 743                                         u32 device_id);
 744 int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
 745
 746 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 747 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
 748         u32 length, u8 *buf);
 749 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
 750                 u32 phy, u32 length, u32 *buf);
 751 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 752 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
 753                 struct device_attribute *attr, char *buf);
 754 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 755                 struct device_attribute *attr, char *buf);
 756 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
 757 /* ctl shared API */
 758 extern struct device_attribute *pm8001_host_attrs[];
 759
 760 static inline void
 761 pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
 762                         struct sas_task *task, struct pm8001_ccb_info *ccb,
 763                         u32 ccb_idx)
 764 {
 765         pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
 766         smp_mb(); /*in order to force CPU ordering*/
 767         spin_unlock(&pm8001_ha->lock);
 768         task->task_done(task);
 769         spin_lock(&pm8001_ha->lock);
 770 }
 771
 772 #endif
 773