drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
  60
  61 /*
  62  * chip info structure to identify chip key functionality as
  63  * encryption available/not, no of ports, hw specific function ref
  64  */
  65 static const struct pm8001_chip_info pm8001_chips[] = {
  66         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  67         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  68         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  69         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  70         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  71         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  72         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  76         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  77 };
  78 static int pm8001_id;
  79
  80 LIST_HEAD(hba_list);
  81
  82 struct workqueue_struct *pm8001_wq;
  83
  84 /*
  85  * The main structure which LLDD must register for scsi core.
  86  */
  87 static struct scsi_host_template pm8001_sht = {
  88         .module                 = THIS_MODULE,
  89         .name                   = DRV_NAME,
  90         .queuecommand           = sas_queuecommand,
  91         .dma_need_drain         = ata_scsi_dma_need_drain,
  92         .target_alloc           = sas_target_alloc,
  93         .slave_configure        = sas_slave_configure,
  94         .scan_finished          = pm8001_scan_finished,
  95         .scan_start             = pm8001_scan_start,
  96         .change_queue_depth     = sas_change_queue_depth,
  97         .bios_param             = sas_bios_param,
  98         .can_queue              = 1,
  99         .this_id                = -1,
 100         .sg_tablesize           = PM8001_MAX_DMA_SG,
 101         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 102         .eh_device_reset_handler = sas_eh_device_reset_handler,
 103         .eh_target_reset_handler = sas_eh_target_reset_handler,
 104         .target_destroy         = sas_target_destroy,
 105         .ioctl                  = sas_ioctl,
 106 #ifdef CONFIG_COMPAT
 107         .compat_ioctl           = sas_ioctl,
 108 #endif
 109         .shost_attrs            = pm8001_host_attrs,
 110         .track_queue_depth      = 1,
 111 };
 112
 113 /*
 114  * Sas layer call this function to execute specific task.
 115  */
 116 static struct sas_domain_function_template pm8001_transport_ops = {
 117         .lldd_dev_found         = pm8001_dev_found,
 118         .lldd_dev_gone          = pm8001_dev_gone,
 119
 120         .lldd_execute_task      = pm8001_queue_command,
 121         .lldd_control_phy       = pm8001_phy_control,
 122
 123         .lldd_abort_task        = pm8001_abort_task,
 124         .lldd_abort_task_set    = pm8001_abort_task_set,
 125         .lldd_clear_aca         = pm8001_clear_aca,
 126         .lldd_clear_task_set    = pm8001_clear_task_set,
 127         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 128         .lldd_lu_reset          = pm8001_lu_reset,
 129         .lldd_query_task        = pm8001_query_task,
 130 };
 131
 132 /**
 133  * pm8001_phy_init - initiate our adapter phys
 134  * @pm8001_ha: our hba structure.
 135  * @phy_id: phy id.
 136  */
 137 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 138 {
 139         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 140         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 141         phy->phy_state = PHY_LINK_DISABLE;
 142         phy->pm8001_ha = pm8001_ha;
 143         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 144         sas_phy->class = SAS;
 145         sas_phy->iproto = SAS_PROTOCOL_ALL;
 146         sas_phy->tproto = 0;
 147         sas_phy->type = PHY_TYPE_PHYSICAL;
 148         sas_phy->role = PHY_ROLE_INITIATOR;
 149         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 150         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 151         sas_phy->id = phy_id;
 152         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 153         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 154         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 155         sas_phy->lldd_phy = phy;
 156 }
 157
 158 /**
 159  * pm8001_free - free hba
 160  * @pm8001_ha:  our hba structure.
 161  */
 162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 163 {
 164         int i;
 165
 166         if (!pm8001_ha)
 167                 return;
 168
 169         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 170                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 171                         dma_free_coherent(&pm8001_ha->pdev->dev,
 172                                 (pm8001_ha->memoryMap.region[i].total_len +
 173                                 pm8001_ha->memoryMap.region[i].alignment),
 174                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 175                                 pm8001_ha->memoryMap.region[i].phys_addr);
 176                         }
 177         }
 178         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 179         flush_workqueue(pm8001_wq);
 180         kfree(pm8001_ha->tags);
 181         kfree(pm8001_ha);
 182 }
 183
 184 #ifdef PM8001_USE_TASKLET
 185
 186 /**
 187  * tasklet for 64 msi-x interrupt handler
 188  * @opaque: the passed general host adapter struct
 189  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 190  */
 191 static void pm8001_tasklet(unsigned long opaque)
 192 {
 193         struct pm8001_hba_info *pm8001_ha;
 194         struct isr_param *irq_vector;
 195
 196         irq_vector = (struct isr_param *)opaque;
 197         pm8001_ha = irq_vector->drv_inst;
 198         if (unlikely(!pm8001_ha))
 199                 BUG_ON(1);
 200         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 201 }
 202 #endif
 203
 204 /**
 205  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 206  * It obtains the vector number and calls the equivalent bottom
 207  * half or services directly.
 208  * @irq: interrupt number
 209  * @opaque: the passed outbound queue/vector. Host structure is
 210  * retrieved from the same.
 211  */
 212 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 213 {
 214         struct isr_param *irq_vector;
 215         struct pm8001_hba_info *pm8001_ha;
 216         irqreturn_t ret = IRQ_HANDLED;
 217         irq_vector = (struct isr_param *)opaque;
 218         pm8001_ha = irq_vector->drv_inst;
 219
 220         if (unlikely(!pm8001_ha))
 221                 return IRQ_NONE;
 222         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 223                 return IRQ_NONE;
 224 #ifdef PM8001_USE_TASKLET
 225         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 226 #else
 227         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 228 #endif
 229         return ret;
 230 }
 231
 232 /**
 233  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 234  * @irq: interrupt number
 235  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 236  */
 237
 238 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 239 {
 240         struct pm8001_hba_info *pm8001_ha;
 241         irqreturn_t ret = IRQ_HANDLED;
 242         struct sas_ha_struct *sha = dev_id;
 243         pm8001_ha = sha->lldd_ha;
 244         if (unlikely(!pm8001_ha))
 245                 return IRQ_NONE;
 246         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 247                 return IRQ_NONE;
 248
 249 #ifdef PM8001_USE_TASKLET
 250         tasklet_schedule(&pm8001_ha->tasklet[0]);
 251 #else
 252         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 253 #endif
 254         return ret;
 255 }
 256
 257 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 258 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 259
 260 /**
 261  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 262  * @pm8001_ha: our hba structure.
 263  * @ent: PCI device ID structure to match on
 264  */
 265 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 266                         const struct pci_device_id *ent)
 267 {
 268         int i, count = 0, rc = 0;
 269         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 270         struct inbound_queue_table *circularQ;
 271
 272         spin_lock_init(&pm8001_ha->lock);
 273         spin_lock_init(&pm8001_ha->bitmap_lock);
 274         PM8001_INIT_DBG(pm8001_ha,
 275                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 276                                 pm8001_ha->chip->n_phy));
 277
 278         /* Setup Interrupt */
 279         rc = pm8001_setup_irq(pm8001_ha);
 280         if (rc) {
 281                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 282                                 "pm8001_setup_irq failed [ret: %d]\n", rc));
 283                 goto err_out_shost;
 284         }
 285         /* Request Interrupt */
 286         rc = pm8001_request_irq(pm8001_ha);
 287         if (rc)
 288                 goto err_out_shost;
 289
 290         count = pm8001_ha->max_q_num;
 291         /* Queues are chosen based on the number of cores/msix availability */
 292         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 293         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 294         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 295         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 296         pm8001_ha->max_memcnt = pi_offset + count;
 297
 298         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 299                 pm8001_phy_init(pm8001_ha, i);
 300                 pm8001_ha->port[i].wide_port_phymap = 0;
 301                 pm8001_ha->port[i].port_attached = 0;
 302                 pm8001_ha->port[i].port_state = 0;
 303                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 304         }
 305
 306         /* MPI Memory region 1 for AAP Event Log for fw */
 307         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 308         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 309         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 310         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 311
 312         /* MPI Memory region 2 for IOP Event Log for fw */
 313         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 314         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 315         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 316         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 317
 318         for (i = 0; i < count; i++) {
 319                 circularQ = &pm8001_ha->inbnd_q_tbl[i];
 320                 spin_lock_init(&circularQ->iq_lock);
 321                 /* MPI Memory region 3 for consumer Index of inbound queues */
 322                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 323                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 324                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 325                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 326
 327                 if ((ent->driver_data) != chip_8001) {
 328                         /* MPI Memory region 5 inbound queues */
 329                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 330                                                 PM8001_MPI_QUEUE;
 331                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 332                                                                 = 128;
 333                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 334                                                 PM8001_MPI_QUEUE * 128;
 335                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 336                                                                 = 128;
 337                 } else {
 338                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 339                                                 PM8001_MPI_QUEUE;
 340                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 341                                                                 = 64;
 342                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 343                                                 PM8001_MPI_QUEUE * 64;
 344                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 345                 }
 346         }
 347
 348         for (i = 0; i < count; i++) {
 349                 /* MPI Memory region 4 for producer Index of outbound queues */
 350                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 351                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 352                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 353                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 354
 355                 if (ent->driver_data != chip_8001) {
 356                         /* MPI Memory region 6 Outbound queues */
 357                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 358                                                 PM8001_MPI_QUEUE;
 359                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 360                                                                 = 128;
 361                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 362                                                 PM8001_MPI_QUEUE * 128;
 363                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 364                                                                 = 128;
 365                 } else {
 366                         /* MPI Memory region 6 Outbound queues */
 367                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 368                                                 PM8001_MPI_QUEUE;
 369                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 370                                                                 = 64;
 371                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 372                                                 PM8001_MPI_QUEUE * 64;
 373                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 374                 }
 375
 376         }
 377         /* Memory region write DMA*/
 378         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 379         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 380         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 381
 382         /* Memory region for fw flash */
 383         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 384
 385         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 386         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 387         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 388         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 389         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 390                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 391                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 392                         &pm8001_ha->memoryMap.region[i].phys_addr,
 393                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 394                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 395                         pm8001_ha->memoryMap.region[i].total_len,
 396                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 397                                 PM8001_FAIL_DBG(pm8001_ha,
 398                                         pm8001_printk("Mem%d alloc failed\n",
 399                                         i));
 400                                 goto err_out;
 401                 }
 402         }
 403
 404         /* Memory region for devices*/
 405         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 406                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 407         if (!pm8001_ha->devices) {
 408                 rc = -ENOMEM;
 409                 goto err_out_nodev;
 410         }
 411         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 412                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 413                 pm8001_ha->devices[i].id = i;
 414                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 415                 pm8001_ha->devices[i].running_req = 0;
 416         }
 417         pm8001_ha->flags = PM8001F_INIT_TIME;
 418         /* Initialize tags */
 419         pm8001_tag_init(pm8001_ha);
 420         return 0;
 421
 422 err_out_shost:
 423         scsi_remove_host(pm8001_ha->shost);
 424 err_out_nodev:
 425         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 426                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 427                         pci_free_consistent(pm8001_ha->pdev,
 428                                 (pm8001_ha->memoryMap.region[i].total_len +
 429                                 pm8001_ha->memoryMap.region[i].alignment),
 430                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 431                                 pm8001_ha->memoryMap.region[i].phys_addr);
 432                 }
 433         }
 434 err_out:
 435         return 1;
 436 }
 437
 438 /**
 439  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 440  * address so that we can access them.
 441  * @pm8001_ha:our hba structure.
 442  */
 443 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 444 {
 445         u32 bar;
 446         u32 logicalBar = 0;
 447         struct pci_dev *pdev;
 448
 449         pdev = pm8001_ha->pdev;
 450         /* map pci mem (PMC pci base 0-3)*/
 451         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 452                 /*
 453                 ** logical BARs for SPC:
 454                 ** bar 0 and 1 - logical BAR0
 455                 ** bar 2 and 3 - logical BAR1
 456                 ** bar4 - logical BAR2
 457                 ** bar5 - logical BAR3
 458                 ** Skip the appropriate assignments:
 459                 */
 460                 if ((bar == 1) || (bar == 3))
 461                         continue;
 462                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 463                         pm8001_ha->io_mem[logicalBar].membase =
 464                                 pci_resource_start(pdev, bar);
 465                         pm8001_ha->io_mem[logicalBar].memsize =
 466                                 pci_resource_len(pdev, bar);
 467                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 468                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 469                                 pm8001_ha->io_mem[logicalBar].memsize);
 470                         PM8001_INIT_DBG(pm8001_ha,
 471                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 472                                 bar, logicalBar));
 473                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 474                                 "base addr %llx virt_addr=%llx len=%d\n",
 475                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 476                                 (u64)(unsigned long)
 477                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 478                                 pm8001_ha->io_mem[logicalBar].memsize));
 479                 } else {
 480                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 481                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 482                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 483                 }
 484                 logicalBar++;
 485         }
 486         return 0;
 487 }
 488
 489 /**
 490  * pm8001_pci_alloc - initialize our ha card structure
 491  * @pdev: pci device.
 492  * @ent: ent
 493  * @shost: scsi host struct which has been initialized before.
 494  */
 495 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 496                                  const struct pci_device_id *ent,
 497                                 struct Scsi_Host *shost)
 498
 499 {
 500         struct pm8001_hba_info *pm8001_ha;
 501         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 502         int j;
 503
 504         pm8001_ha = sha->lldd_ha;
 505         if (!pm8001_ha)
 506                 return NULL;
 507
 508         pm8001_ha->pdev = pdev;
 509         pm8001_ha->dev = &pdev->dev;
 510         pm8001_ha->chip_id = ent->driver_data;
 511         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 512         pm8001_ha->irq = pdev->irq;
 513         pm8001_ha->sas = sha;
 514         pm8001_ha->shost = shost;
 515         pm8001_ha->id = pm8001_id++;
 516         pm8001_ha->logging_level = logging_level;
 517         pm8001_ha->non_fatal_count = 0;
 518         if (link_rate >= 1 && link_rate <= 15)
 519                 pm8001_ha->link_rate = (link_rate << 8);
 520         else {
 521                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 522                         LINKRATE_60 | LINKRATE_120;
 523                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 524                         "Setting link rate to default value\n"));
 525         }
 526         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 527         /* IOMB size is 128 for 8088/89 controllers */
 528         if (pm8001_ha->chip_id != chip_8001)
 529                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 530         else
 531                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 532
 533 #ifdef PM8001_USE_TASKLET
 534         /* Tasklet for non msi-x interrupt handler */
 535         if ((!pdev->msix_cap || !pci_msi_enabled())
 536             || (pm8001_ha->chip_id == chip_8001))
 537                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 538                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 539         else
 540                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 541                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 542                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 543 #endif
 544         pm8001_ioremap(pm8001_ha);
 545         if (!pm8001_alloc(pm8001_ha, ent))
 546                 return pm8001_ha;
 547         pm8001_free(pm8001_ha);
 548         return NULL;
 549 }
 550
 551 /**
 552  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 553  * @pdev: pci device.
 554  */
 555 static int pci_go_44(struct pci_dev *pdev)
 556 {
 557         int rc;
 558
 559         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 560         if (rc) {
 561                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 562                 if (rc)
 563                         dev_printk(KERN_ERR, &pdev->dev,
 564                                 "32-bit DMA enable failed\n");
 565         }
 566         return rc;
 567 }
 568
 569 /**
 570  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 571  * @shost: scsi host which has been allocated outside.
 572  * @chip_info: our ha struct.
 573  */
 574 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 575                                    const struct pm8001_chip_info *chip_info)
 576 {
 577         int phy_nr, port_nr;
 578         struct asd_sas_phy **arr_phy;
 579         struct asd_sas_port **arr_port;
 580         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 581
 582         phy_nr = chip_info->n_phy;
 583         port_nr = phy_nr;
 584         memset(sha, 0x00, sizeof(*sha));
 585         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 586         if (!arr_phy)
 587                 goto exit;
 588         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 589         if (!arr_port)
 590                 goto exit_free2;
 591
 592         sha->sas_phy = arr_phy;
 593         sha->sas_port = arr_port;
 594         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 595         if (!sha->lldd_ha)
 596                 goto exit_free1;
 597
 598         shost->transportt = pm8001_stt;
 599         shost->max_id = PM8001_MAX_DEVICES;
 600         shost->max_lun = 8;
 601         shost->max_channel = 0;
 602         shost->unique_id = pm8001_id;
 603         shost->max_cmd_len = 16;
 604         shost->can_queue = PM8001_CAN_QUEUE;
 605         shost->cmd_per_lun = 32;
 606         return 0;
 607 exit_free1:
 608         kfree(arr_port);
 609 exit_free2:
 610         kfree(arr_phy);
 611 exit:
 612         return -1;
 613 }
 614
 615 /**
 616  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 617  * @shost: scsi host which has been allocated outside
 618  * @chip_info: our ha struct.
 619  */
 620 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 621                                      const struct pm8001_chip_info *chip_info)
 622 {
 623         int i = 0;
 624         struct pm8001_hba_info *pm8001_ha;
 625         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 626
 627         pm8001_ha = sha->lldd_ha;
 628         for (i = 0; i < chip_info->n_phy; i++) {
 629                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 630                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 631                 sha->sas_phy[i]->sas_addr =
 632                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 633         }
 634         sha->sas_ha_name = DRV_NAME;
 635         sha->dev = pm8001_ha->dev;
 636         sha->strict_wide_ports = 1;
 637         sha->lldd_module = THIS_MODULE;
 638         sha->sas_addr = &pm8001_ha->sas_addr[0];
 639         sha->num_phys = chip_info->n_phy;
 640         sha->core.shost = shost;
 641 }
 642
 643 /**
 644  * pm8001_init_sas_add - initialize sas address
 645  * @pm8001_ha: our ha struct.
 646  *
 647  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 648  * it should read from the EEPROM
 649  */
 650 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 651 {
 652         u8 i, j;
 653         u8 sas_add[8];
 654 #ifdef PM8001_READ_VPD
 655         /* For new SPC controllers WWN is stored in flash vpd
 656         *  For SPC/SPCve controllers WWN is stored in EEPROM
 657         *  For Older SPC WWN is stored in NVMD
 658         */
 659         DECLARE_COMPLETION_ONSTACK(completion);
 660         struct pm8001_ioctl_payload payload;
 661         u16 deviceid;
 662         int rc;
 663
 664         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 665         pm8001_ha->nvmd_completion = &completion;
 666
 667         if (pm8001_ha->chip_id == chip_8001) {
 668                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 669                         payload.minor_function = 4;
 670                         payload.rd_length = 4096;
 671                 } else {
 672                         payload.minor_function = 0;
 673                         payload.rd_length = 128;
 674                 }
 675         } else if ((pm8001_ha->chip_id == chip_8070 ||
 676                         pm8001_ha->chip_id == chip_8072) &&
 677                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 678                 payload.minor_function = 4;
 679                 payload.rd_length = 4096;
 680         } else {
 681                 payload.minor_function = 1;
 682                 payload.rd_length = 4096;
 683         }
 684         payload.offset = 0;
 685         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 686         if (!payload.func_specific) {
 687                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 688                 return;
 689         }
 690         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 691         if (rc) {
 692                 kfree(payload.func_specific);
 693                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 694                 return;
 695         }
 696         wait_for_completion(&completion);
 697
 698         for (i = 0, j = 0; i <= 7; i++, j++) {
 699                 if (pm8001_ha->chip_id == chip_8001) {
 700                         if (deviceid == 0x8081)
 701                                 pm8001_ha->sas_addr[j] =
 702                                         payload.func_specific[0x704 + i];
 703                         else if (deviceid == 0x0042)
 704                                 pm8001_ha->sas_addr[j] =
 705                                         payload.func_specific[0x010 + i];
 706                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 707                                 pm8001_ha->chip_id == chip_8072) &&
 708                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 709                         pm8001_ha->sas_addr[j] =
 710                                         payload.func_specific[0x010 + i];
 711                 } else
 712                         pm8001_ha->sas_addr[j] =
 713                                         payload.func_specific[0x804 + i];
 714         }
 715         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 716         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 717                 if (i && ((i % 4) == 0))
 718                         sas_add[7] = sas_add[7] + 4;
 719                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 720                         sas_add, SAS_ADDR_SIZE);
 721                 PM8001_INIT_DBG(pm8001_ha,
 722                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 723                         pm8001_ha->phy[i].dev_sas_addr));
 724         }
 725         kfree(payload.func_specific);
 726 #else
 727         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 728                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 729                 pm8001_ha->phy[i].dev_sas_addr =
 730                         cpu_to_be64((u64)
 731                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 732         }
 733         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 734                 SAS_ADDR_SIZE);
 735 #endif
 736 }
 737
 738 /*
 739  * pm8001_get_phy_settings_info : Read phy setting values.
 740  * @pm8001_ha : our hba.
 741  */
 742 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 743 {
 744
 745 #ifdef PM8001_READ_VPD
 746         /*OPTION ROM FLASH read for the SPC cards */
 747         DECLARE_COMPLETION_ONSTACK(completion);
 748         struct pm8001_ioctl_payload payload;
 749         int rc;
 750
 751         pm8001_ha->nvmd_completion = &completion;
 752         /* SAS ADDRESS read from flash / EEPROM */
 753         payload.minor_function = 6;
 754         payload.offset = 0;
 755         payload.rd_length = 4096;
 756         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 757         if (!payload.func_specific)
 758                 return -ENOMEM;
 759         /* Read phy setting values from flash */
 760         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 761         if (rc) {
 762                 kfree(payload.func_specific);
 763                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 764                 return -ENOMEM;
 765         }
 766         wait_for_completion(&completion);
 767         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 768         kfree(payload.func_specific);
 769 #endif
 770         return 0;
 771 }
 772
 773 struct pm8001_mpi3_phy_pg_trx_config {
 774         u32 LaneLosCfg;
 775         u32 LanePgaCfg1;
 776         u32 LanePisoCfg1;
 777         u32 LanePisoCfg2;
 778         u32 LanePisoCfg3;
 779         u32 LanePisoCfg4;
 780         u32 LanePisoCfg5;
 781         u32 LanePisoCfg6;
 782         u32 LaneBctCtrl;
 783 };
 784
 785 /**
 786  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 787  * @pm8001_ha : our adapter
 788  * @phycfg : PHY config page to populate
 789  */
 790 static
 791 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 792                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 793 {
 794         phycfg->LaneLosCfg   = 0x00000132;
 795         phycfg->LanePgaCfg1  = 0x00203949;
 796         phycfg->LanePisoCfg1 = 0x000000FF;
 797         phycfg->LanePisoCfg2 = 0xFF000001;
 798         phycfg->LanePisoCfg3 = 0xE7011300;
 799         phycfg->LanePisoCfg4 = 0x631C40C0;
 800         phycfg->LanePisoCfg5 = 0xF8102036;
 801         phycfg->LanePisoCfg6 = 0xF74A1000;
 802         phycfg->LaneBctCtrl  = 0x00FB33F8;
 803 }
 804
 805 /**
 806  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 807  * @pm8001_ha : our adapter
 808  * @phycfg : PHY config page to populate
 809  */
 810 static
 811 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 812                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 813 {
 814         phycfg->LaneLosCfg   = 0x00000132;
 815         phycfg->LanePgaCfg1  = 0x00203949;
 816         phycfg->LanePisoCfg1 = 0x000000FF;
 817         phycfg->LanePisoCfg2 = 0xFF000001;
 818         phycfg->LanePisoCfg3 = 0xE7011300;
 819         phycfg->LanePisoCfg4 = 0x63349140;
 820         phycfg->LanePisoCfg5 = 0xF8102036;
 821         phycfg->LanePisoCfg6 = 0xF80D9300;
 822         phycfg->LaneBctCtrl  = 0x00FB33F8;
 823 }
 824
 825 /**
 826  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 827  * @pm8001_ha : our adapter
 828  * @phymask : The PHY mask
 829  */
 830 static
 831 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 832 {
 833         switch (pm8001_ha->pdev->subsystem_device) {
 834         case 0x0070: /* H1280 - 8 external 0 internal */
 835         case 0x0072: /* H12F0 - 16 external 0 internal */
 836                 *phymask = 0x0000;
 837                 break;
 838
 839         case 0x0071: /* H1208 - 0 external 8 internal */
 840         case 0x0073: /* H120F - 0 external 16 internal */
 841                 *phymask = 0xFFFF;
 842                 break;
 843
 844         case 0x0080: /* H1244 - 4 external 4 internal */
 845                 *phymask = 0x00F0;
 846                 break;
 847
 848         case 0x0081: /* H1248 - 4 external 8 internal */
 849                 *phymask = 0x0FF0;
 850                 break;
 851
 852         case 0x0082: /* H1288 - 8 external 8 internal */
 853                 *phymask = 0xFF00;
 854                 break;
 855
 856         default:
 857                 PM8001_INIT_DBG(pm8001_ha,
 858                         pm8001_printk("Unknown subsystem device=0x%.04x",
 859                                 pm8001_ha->pdev->subsystem_device));
 860         }
 861 }
 862
 863 /**
 864  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 865  * @pm8001_ha : our adapter
 866  */
 867 static
 868 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 869 {
 870         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 871         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 872         int phymask = 0;
 873         int i = 0;
 874
 875         memset(&phycfg_int, 0, sizeof(phycfg_int));
 876         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 877
 878         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 879         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 880         pm8001_get_phy_mask(pm8001_ha, &phymask);
 881
 882         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 883                 if (phymask & (1 << i)) {/* Internal PHY */
 884                         pm8001_set_phy_profile_single(pm8001_ha, i,
 885                                         sizeof(phycfg_int) / sizeof(u32),
 886                                         (u32 *)&phycfg_int);
 887
 888                 } else { /* External PHY */
 889                         pm8001_set_phy_profile_single(pm8001_ha, i,
 890                                         sizeof(phycfg_ext) / sizeof(u32),
 891                                         (u32 *)&phycfg_ext);
 892                 }
 893         }
 894
 895         return 0;
 896 }
 897
 898 /**
 899  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 900  * @pm8001_ha : our hba.
 901  */
 902 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 903 {
 904         switch (pm8001_ha->pdev->subsystem_vendor) {
 905         case PCI_VENDOR_ID_ATTO:
 906                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 907                         return 0;
 908                 else
 909                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 910
 911         case PCI_VENDOR_ID_ADAPTEC2:
 912         case 0:
 913                 return 0;
 914
 915         default:
 916                 return pm8001_get_phy_settings_info(pm8001_ha);
 917         }
 918 }
 919
 920 #ifdef PM8001_USE_MSIX
 921 /**
 922  * pm8001_setup_msix - enable MSI-X interrupt
 923  * @pm8001_ha: our ha struct.
 924  */
 925 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 926 {
 927         u32 number_of_intr;
 928         int rc, cpu_online_count;
 929         unsigned int allocated_irq_vectors;
 930
 931         /* SPCv controllers supports 64 msi-x */
 932         if (pm8001_ha->chip_id == chip_8001) {
 933                 number_of_intr = 1;
 934         } else {
 935                 number_of_intr = PM8001_MAX_MSIX_VEC;
 936         }
 937
 938         cpu_online_count = num_online_cpus();
 939         number_of_intr = min_t(int, cpu_online_count, number_of_intr);
 940         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 941                         number_of_intr, PCI_IRQ_MSIX);
 942         allocated_irq_vectors = rc;
 943         if (rc < 0)
 944                 return rc;
 945
 946         /* Assigns the number of interrupts */
 947         number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
 948         pm8001_ha->number_of_intr = number_of_intr;
 949
 950         /* Maximum queue number updating in HBA structure */
 951         pm8001_ha->max_q_num = number_of_intr;
 952
 953         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 954                 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 955                                 rc, pm8001_ha->number_of_intr));
 956         return 0;
 957 }
 958
 959 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 960 {
 961         u32 i = 0, j = 0;
 962         int flag = 0, rc = 0;
 963
 964         if (pm8001_ha->chip_id != chip_8001)
 965                 flag &= ~IRQF_SHARED;
 966
 967         PM8001_INIT_DBG(pm8001_ha,
 968                 pm8001_printk("pci_enable_msix request number of intr %d\n",
 969                 pm8001_ha->number_of_intr));
 970
 971         for (i = 0; i < pm8001_ha->number_of_intr; i++) {
 972                 snprintf(pm8001_ha->intr_drvname[i],
 973                         sizeof(pm8001_ha->intr_drvname[0]),
 974                         "%s-%d", pm8001_ha->name, i);
 975                 pm8001_ha->irq_vector[i].irq_id = i;
 976                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 977
 978                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 979                         pm8001_interrupt_handler_msix, flag,
 980                         pm8001_ha->intr_drvname[i],
 981                         &(pm8001_ha->irq_vector[i]));
 982                 if (rc) {
 983                         for (j = 0; j < i; j++) {
 984                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 985                                         &(pm8001_ha->irq_vector[i]));
 986                         }
 987                         pci_free_irq_vectors(pm8001_ha->pdev);
 988                         break;
 989                 }
 990         }
 991
 992         return rc;
 993 }
 994 #endif
 995
 996 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
 997 {
 998         struct pci_dev *pdev;
 999
1000         pdev = pm8001_ha->pdev;
1001
1002 #ifdef PM8001_USE_MSIX
1003         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1004                 return pm8001_setup_msix(pm8001_ha);
1005         PM8001_INIT_DBG(pm8001_ha,
1006                 pm8001_printk("MSIX not supported!!!\n"));
1007 #endif
1008         return 0;
1009 }
1010
1011 /**
1012  * pm8001_request_irq - register interrupt
1013  * @pm8001_ha: our ha struct.
1014  */
1015 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1016 {
1017         struct pci_dev *pdev;
1018         int rc;
1019
1020         pdev = pm8001_ha->pdev;
1021
1022 #ifdef PM8001_USE_MSIX
1023         if (pdev->msix_cap && pci_msi_enabled())
1024                 return pm8001_request_msix(pm8001_ha);
1025         else {
1026                 PM8001_INIT_DBG(pm8001_ha,
1027                         pm8001_printk("MSIX not supported!!!\n"));
1028                 goto intx;
1029         }
1030 #endif
1031
1032 intx:
1033         /* initialize the INT-X interrupt */
1034         pm8001_ha->irq_vector[0].irq_id = 0;
1035         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1036         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1037                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1038         return rc;
1039 }
1040
1041 /**
1042  * pm8001_pci_probe - probe supported device
1043  * @pdev: pci device which kernel has been prepared for.
1044  * @ent: pci device id
1045  *
1046  * This function is the main initialization function, when register a new
1047  * pci driver it is invoked, all struct an hardware initilization should be done
1048  * here, also, register interrupt
1049  */
1050 static int pm8001_pci_probe(struct pci_dev *pdev,
1051                             const struct pci_device_id *ent)
1052 {
1053         unsigned int rc;
1054         u32     pci_reg;
1055         u8      i = 0;
1056         struct pm8001_hba_info *pm8001_ha;
1057         struct Scsi_Host *shost = NULL;
1058         const struct pm8001_chip_info *chip;
1059         struct sas_ha_struct *sha;
1060
1061         dev_printk(KERN_INFO, &pdev->dev,
1062                 "pm80xx: driver version %s\n", DRV_VERSION);
1063         rc = pci_enable_device(pdev);
1064         if (rc)
1065                 goto err_out_enable;
1066         pci_set_master(pdev);
1067         /*
1068          * Enable pci slot busmaster by setting pci command register.
1069          * This is required by FW for Cyclone card.
1070          */
1071
1072         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1073         pci_reg |= 0x157;
1074         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1075         rc = pci_request_regions(pdev, DRV_NAME);
1076         if (rc)
1077                 goto err_out_disable;
1078         rc = pci_go_44(pdev);
1079         if (rc)
1080                 goto err_out_regions;
1081
1082         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1083         if (!shost) {
1084                 rc = -ENOMEM;
1085                 goto err_out_regions;
1086         }
1087         chip = &pm8001_chips[ent->driver_data];
1088         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1089         if (!sha) {
1090                 rc = -ENOMEM;
1091                 goto err_out_free_host;
1092         }
1093         SHOST_TO_SAS_HA(shost) = sha;
1094
1095         rc = pm8001_prep_sas_ha_init(shost, chip);
1096         if (rc) {
1097                 rc = -ENOMEM;
1098                 goto err_out_free;
1099         }
1100         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1101         /* ent->driver variable is used to differentiate between controllers */
1102         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1103         if (!pm8001_ha) {
1104                 rc = -ENOMEM;
1105                 goto err_out_free;
1106         }
1107
1108         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1109         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1110         if (rc) {
1111                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1112                         "chip_init failed [ret: %d]\n", rc));
1113                 goto err_out_ha_free;
1114         }
1115
1116         rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1117         if (rc)
1118                 goto err_out_enable;
1119
1120         rc = scsi_add_host(shost, &pdev->dev);
1121         if (rc)
1122                 goto err_out_ha_free;
1123
1124         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1125         if (pm8001_ha->chip_id != chip_8001) {
1126                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1127                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1128                 /* setup thermal configuration. */
1129                 pm80xx_set_thermal_config(pm8001_ha);
1130         }
1131
1132         pm8001_init_sas_add(pm8001_ha);
1133         /* phy setting support for motherboard controller */
1134         if (pm8001_configure_phy_settings(pm8001_ha))
1135                 goto err_out_shost;
1136
1137         pm8001_post_sas_ha_init(shost, chip);
1138         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1139         if (rc) {
1140                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1141                         "sas_register_ha failed [ret: %d]\n", rc));
1142                 goto err_out_shost;
1143         }
1144         list_add_tail(&pm8001_ha->list, &hba_list);
1145         scsi_scan_host(pm8001_ha->shost);
1146         pm8001_ha->flags = PM8001F_RUN_TIME;
1147         return 0;
1148
1149 err_out_shost:
1150         scsi_remove_host(pm8001_ha->shost);
1151 err_out_ha_free:
1152         pm8001_free(pm8001_ha);
1153 err_out_free:
1154         kfree(sha);
1155 err_out_free_host:
1156         scsi_host_put(shost);
1157 err_out_regions:
1158         pci_release_regions(pdev);
1159 err_out_disable:
1160         pci_disable_device(pdev);
1161 err_out_enable:
1162         return rc;
1163 }
1164
1165 /*
1166  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1167  * @pm8001_ha: our hba card information.
1168  * @shost: scsi host which has been allocated outside.
1169  */
1170 static int
1171 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1172                         struct pci_dev *pdev)
1173 {
1174         int i = 0;
1175         u32 max_out_io, ccb_count;
1176         u32 can_queue;
1177
1178         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1179         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1180
1181         /* Update to the scsi host*/
1182         can_queue = ccb_count - PM8001_RESERVE_SLOT;
1183         shost->can_queue = can_queue;
1184
1185         pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1186         if (!pm8001_ha->tags)
1187                 goto err_out;
1188
1189         /* Memory region for ccb_info*/
1190         pm8001_ha->ccb_info = (struct pm8001_ccb_info *)
1191                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1192         if (!pm8001_ha->ccb_info) {
1193                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk
1194                         ("Unable to allocate memory for ccb\n"));
1195                 goto err_out_noccb;
1196         }
1197         for (i = 0; i < ccb_count; i++) {
1198                 pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev,
1199                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1200                                 &pm8001_ha->ccb_info[i].ccb_dma_handle);
1201                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1202                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk
1203                                         ("pm80xx: ccb prd memory allocation error\n"));
1204                         goto err_out;
1205                 }
1206                 pm8001_ha->ccb_info[i].task = NULL;
1207                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1208                 pm8001_ha->ccb_info[i].device = NULL;
1209                 ++pm8001_ha->tags_num;
1210         }
1211         return 0;
1212
1213 err_out_noccb:
1214         kfree(pm8001_ha->devices);
1215 err_out:
1216         return -ENOMEM;
1217 }
1218
1219 static void pm8001_pci_remove(struct pci_dev *pdev)
1220 {
1221         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1222         struct pm8001_hba_info *pm8001_ha;
1223         int i, j;
1224         pm8001_ha = sha->lldd_ha;
1225         sas_unregister_ha(sha);
1226         sas_remove_host(pm8001_ha->shost);
1227         list_del(&pm8001_ha->list);
1228         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1229         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1230
1231 #ifdef PM8001_USE_MSIX
1232         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1233                 synchronize_irq(pci_irq_vector(pdev, i));
1234         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1235                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1236         pci_free_irq_vectors(pdev);
1237 #else
1238         free_irq(pm8001_ha->irq, sha);
1239 #endif
1240 #ifdef PM8001_USE_TASKLET
1241         /* For non-msix and msix interrupts */
1242         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1243             (pm8001_ha->chip_id == chip_8001))
1244                 tasklet_kill(&pm8001_ha->tasklet[0]);
1245         else
1246                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1247                         tasklet_kill(&pm8001_ha->tasklet[j]);
1248 #endif
1249         scsi_host_put(pm8001_ha->shost);
1250         pm8001_free(pm8001_ha);
1251         kfree(sha->sas_phy);
1252         kfree(sha->sas_port);
1253         kfree(sha);
1254         pci_release_regions(pdev);
1255         pci_disable_device(pdev);
1256 }
1257
1258 /**
1259  * pm8001_pci_suspend - power management suspend main entry point
1260  * @pdev: PCI device struct
1261  * @state: PM state change to (usually PCI_D3)
1262  *
1263  * Returns 0 success, anything else error.
1264  */
1265 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1266 {
1267         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1268         struct pm8001_hba_info *pm8001_ha;
1269         int  i, j;
1270         u32 device_state;
1271         pm8001_ha = sha->lldd_ha;
1272         sas_suspend_ha(sha);
1273         flush_workqueue(pm8001_wq);
1274         scsi_block_requests(pm8001_ha->shost);
1275         if (!pdev->pm_cap) {
1276                 dev_err(&pdev->dev, " PCI PM not supported\n");
1277                 return -ENODEV;
1278         }
1279         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1280         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1281 #ifdef PM8001_USE_MSIX
1282         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1283                 synchronize_irq(pci_irq_vector(pdev, i));
1284         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1285                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1286         pci_free_irq_vectors(pdev);
1287 #else
1288         free_irq(pm8001_ha->irq, sha);
1289 #endif
1290 #ifdef PM8001_USE_TASKLET
1291         /* For non-msix and msix interrupts */
1292         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1293             (pm8001_ha->chip_id == chip_8001))
1294                 tasklet_kill(&pm8001_ha->tasklet[0]);
1295         else
1296                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1297                         tasklet_kill(&pm8001_ha->tasklet[j]);
1298 #endif
1299         device_state = pci_choose_state(pdev, state);
1300         pm8001_printk("pdev=0x%p, slot=%s, entering "
1301                       "operating state [D%d]\n", pdev,
1302                       pm8001_ha->name, device_state);
1303         pci_save_state(pdev);
1304         pci_disable_device(pdev);
1305         pci_set_power_state(pdev, device_state);
1306         return 0;
1307 }
1308
1309 /**
1310  * pm8001_pci_resume - power management resume main entry point
1311  * @pdev: PCI device struct
1312  *
1313  * Returns 0 success, anything else error.
1314  */
1315 static int pm8001_pci_resume(struct pci_dev *pdev)
1316 {
1317         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1318         struct pm8001_hba_info *pm8001_ha;
1319         int rc;
1320         u8 i = 0, j;
1321         u32 device_state;
1322         DECLARE_COMPLETION_ONSTACK(completion);
1323         pm8001_ha = sha->lldd_ha;
1324         device_state = pdev->current_state;
1325
1326         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1327                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1328
1329         pci_set_power_state(pdev, PCI_D0);
1330         pci_enable_wake(pdev, PCI_D0, 0);
1331         pci_restore_state(pdev);
1332         rc = pci_enable_device(pdev);
1333         if (rc) {
1334                 pm8001_printk("slot=%s Enable device failed during resume\n",
1335                               pm8001_ha->name);
1336                 goto err_out_enable;
1337         }
1338
1339         pci_set_master(pdev);
1340         rc = pci_go_44(pdev);
1341         if (rc)
1342                 goto err_out_disable;
1343         sas_prep_resume_ha(sha);
1344         /* chip soft rst only for spc */
1345         if (pm8001_ha->chip_id == chip_8001) {
1346                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1347                 PM8001_INIT_DBG(pm8001_ha,
1348                         pm8001_printk("chip soft reset successful\n"));
1349         }
1350         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1351         if (rc)
1352                 goto err_out_disable;
1353
1354         /* disable all the interrupt bits */
1355         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1356
1357         rc = pm8001_request_irq(pm8001_ha);
1358         if (rc)
1359                 goto err_out_disable;
1360 #ifdef PM8001_USE_TASKLET
1361         /*  Tasklet for non msi-x interrupt handler */
1362         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1363             (pm8001_ha->chip_id == chip_8001))
1364                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1365                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1366         else
1367                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1368                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1369                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1370 #endif
1371         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1372         if (pm8001_ha->chip_id != chip_8001) {
1373                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1374                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1375         }
1376
1377         /* Chip documentation for the 8070 and 8072 SPCv    */
1378         /* states that a 500ms minimum delay is required    */
1379         /* before issuing commands. Otherwise, the firmware */
1380         /* will enter an unrecoverable state.               */
1381
1382         if (pm8001_ha->chip_id == chip_8070 ||
1383                 pm8001_ha->chip_id == chip_8072) {
1384                 mdelay(500);
1385         }
1386
1387         /* Spin up the PHYs */
1388
1389         pm8001_ha->flags = PM8001F_RUN_TIME;
1390         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1391                 pm8001_ha->phy[i].enable_completion = &completion;
1392                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1393                 wait_for_completion(&completion);
1394         }
1395         sas_resume_ha(sha);
1396         return 0;
1397
1398 err_out_disable:
1399         scsi_remove_host(pm8001_ha->shost);
1400         pci_disable_device(pdev);
1401 err_out_enable:
1402         return rc;
1403 }
1404
1405 /* update of pci device, vendor id and driver data with
1406  * unique value for each of the controller
1407  */
1408 static struct pci_device_id pm8001_pci_table[] = {
1409         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1410         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1411         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1412         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1413         /* Support for SPC/SPCv/SPCve controllers */
1414         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1415         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1416         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1417         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1418         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1419         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1420         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1421         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1422         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1423         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1424         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1425         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1426         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1427         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1428         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1429         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1430                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1431         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1432                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1433         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1434                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1435         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1436                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1437         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1438                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1439         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1440                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1441         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1442                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1443         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1444                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1445         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1446                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1447         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1448                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1449         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1450                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1451         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1452                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1453         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1454                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1455         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1456                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1457         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1458                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1459         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1460                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1461         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1462                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1463         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1464                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1465         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1466                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1467         { PCI_VENDOR_ID_ATTO, 0x8070,
1468                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1469         { PCI_VENDOR_ID_ATTO, 0x8070,
1470                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1471         { PCI_VENDOR_ID_ATTO, 0x8072,
1472                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1473         { PCI_VENDOR_ID_ATTO, 0x8072,
1474                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1475         { PCI_VENDOR_ID_ATTO, 0x8070,
1476                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1477         { PCI_VENDOR_ID_ATTO, 0x8072,
1478                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1479         { PCI_VENDOR_ID_ATTO, 0x8072,
1480                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1481         {} /* terminate list */
1482 };
1483
1484 static struct pci_driver pm8001_pci_driver = {
1485         .name           = DRV_NAME,
1486         .id_table       = pm8001_pci_table,
1487         .probe          = pm8001_pci_probe,
1488         .remove         = pm8001_pci_remove,
1489         .suspend        = pm8001_pci_suspend,
1490         .resume         = pm8001_pci_resume,
1491 };
1492
1493 /**
1494  *      pm8001_init - initialize scsi transport template
1495  */
1496 static int __init pm8001_init(void)
1497 {
1498         int rc = -ENOMEM;
1499
1500         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1501         if (!pm8001_wq)
1502                 goto err;
1503
1504         pm8001_id = 0;
1505         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1506         if (!pm8001_stt)
1507                 goto err_wq;
1508         rc = pci_register_driver(&pm8001_pci_driver);
1509         if (rc)
1510                 goto err_tp;
1511         return 0;
1512
1513 err_tp:
1514         sas_release_transport(pm8001_stt);
1515 err_wq:
1516         destroy_workqueue(pm8001_wq);
1517 err:
1518         return rc;
1519 }
1520
1521 static void __exit pm8001_exit(void)
1522 {
1523         pci_unregister_driver(&pm8001_pci_driver);
1524         sas_release_transport(pm8001_stt);
1525         destroy_workqueue(pm8001_wq);
1526 }
1527
1528 module_init(pm8001_init);
1529 module_exit(pm8001_exit);
1530
1531 MODULE_AUTHOR("Jack Wang <[email protected]>");
1532 MODULE_AUTHOR("Anand Kumar Santhanam <[email protected]>");
1533 MODULE_AUTHOR("Sangeetha Gnanasekaran <[email protected]>");
1534 MODULE_AUTHOR("Nikith Ganigarakoppal <[email protected]>");
1535 MODULE_DESCRIPTION(
1536                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1537                 "SAS/SATA controller driver");
1538 MODULE_VERSION(DRV_VERSION);
1539 MODULE_LICENSE("GPL");
1540 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1541