drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "bios/bios_parser_helper.h"
  45 #include "include/irq_service_interface.h"
  46 #include "transform.h"
  47 #include "dmcu.h"
  48 #include "dpp.h"
  49 #include "timing_generator.h"
  50 #include "abm.h"
  51 #include "virtual/virtual_link_encoder.h"
  52 #include "hubp.h"
  53
  54 #include "link_hwss.h"
  55 #include "link_encoder.h"
  56 #include "link_enc_cfg.h"
  57
  58 #include "dc_link.h"
  59 #include "dc_link_ddc.h"
  60 #include "dm_helpers.h"
  61 #include "mem_input.h"
  62
  63 #include "dc_link_dp.h"
  64 #include "dc_dmub_srv.h"
  65
  66 #include "dsc.h"
  67
  68 #include "vm_helper.h"
  69
  70 #include "dce/dce_i2c.h"
  71
  72 #include "dmub/dmub_srv.h"
  73
  74 #include "i2caux_interface.h"
  75 #include "dce/dmub_hw_lock_mgr.h"
  76
  77 #include "dc_trace.h"
  78
  79 #include "dce/dmub_outbox.h"
  80
  81 #define CTX \
  82         dc->ctx
  83
  84 #define DC_LOGGER \
  85         dc->ctx->logger
  86
  87 static const char DC_BUILD_ID[] = "production-build";
  88
  89 /**
  90  * DOC: Overview
  91  *
  92  * DC is the OS-agnostic component of the amdgpu DC driver.
  93  *
  94  * DC maintains and validates a set of structs representing the state of the
  95  * driver and writes that state to AMD hardware
  96  *
  97  * Main DC HW structs:
  98  *
  99  * struct dc - The central struct.  One per driver.  Created on driver load,
 100  * destroyed on driver unload.
 101  *
 102  * struct dc_context - One per driver.
 103  * Used as a backpointer by most other structs in dc.
 104  *
 105  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 106  * plugpoints).  Created on driver load, destroyed on driver unload.
 107  *
 108  * struct dc_sink - One per display.  Created on boot or hotplug.
 109  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 110  * (the display directly attached).  It may also have one or more remote
 111  * sinks (in the Multi-Stream Transport case)
 112  *
 113  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 114  * main pipeline.  Not directly accessible by dm.
 115  *
 116  * Main dc state structs:
 117  *
 118  * These structs can be created and destroyed as needed.  There is a full set of
 119  * these structs in dc->current_state representing the currently programmed state.
 120  *
 121  * struct dc_state - The global DC state to track global state information,
 122  * such as bandwidth values.
 123  *
 124  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 125  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 126  *
 127  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 128  * and may have more in the Multi-Plane Overlay case.
 129  *
 130  * struct resource_context - Represents the programmable state of everything in
 131  * the resource_pool.  Not directly accessible by dm.
 132  *
 133  * struct pipe_ctx - A member of struct resource_context.  Represents the
 134  * internal hardware pipeline components.  Each dc_plane_state has either
 135  * one or two (in the pipe-split case).
 136  */
 137
 138 /*******************************************************************************
 139  * Private functions
 140  ******************************************************************************/
 141
 142 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 143 {
 144         if (new > *original)
 145                 *original = new;
 146 }
 147
 148 static void destroy_links(struct dc *dc)
 149 {
 150         uint32_t i;
 151
 152         for (i = 0; i < dc->link_count; i++) {
 153                 if (NULL != dc->links[i])
 154                         link_destroy(&dc->links[i]);
 155         }
 156 }
 157
 158 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 159 {
 160         int i;
 161         uint32_t count = 0;
 162
 163         for (i = 0; i < num_links; i++) {
 164                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 165                                 links[i]->is_internal_display)
 166                         count++;
 167         }
 168
 169         return count;
 170 }
 171
 172 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 173 {
 174         uint8_t i;
 175         uint8_t seamless_boot_stream_count = 0;
 176
 177         for (i = 0; i < ctx->stream_count; i++)
 178                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 179                         seamless_boot_stream_count++;
 180
 181         return seamless_boot_stream_count;
 182 }
 183
 184 static bool create_links(
 185                 struct dc *dc,
 186                 uint32_t num_virtual_links)
 187 {
 188         int i;
 189         int connectors_num;
 190         struct dc_bios *bios = dc->ctx->dc_bios;
 191
 192         dc->link_count = 0;
 193
 194         connectors_num = bios->funcs->get_connectors_number(bios);
 195
 196         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 197
 198         if (connectors_num > ENUM_ID_COUNT) {
 199                 dm_error(
 200                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 201                         connectors_num,
 202                         ENUM_ID_COUNT);
 203                 return false;
 204         }
 205
 206         dm_output_to_console(
 207                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 208                 __func__,
 209                 connectors_num,
 210                 num_virtual_links);
 211
 212         for (i = 0; i < connectors_num; i++) {
 213                 struct link_init_data link_init_params = {0};
 214                 struct dc_link *link;
 215
 216                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 217
 218                 link_init_params.ctx = dc->ctx;
 219                 /* next BIOS object table connector */
 220                 link_init_params.connector_index = i;
 221                 link_init_params.link_index = dc->link_count;
 222                 link_init_params.dc = dc;
 223                 link = link_create(&link_init_params);
 224
 225                 if (link) {
 226                         dc->links[dc->link_count] = link;
 227                         link->dc = dc;
 228                         ++dc->link_count;
 229                 }
 230         }
 231
 232         DC_LOG_DC("BIOS object table - end");
 233
 234         /* Create a link for each usb4 dpia port */
 235         for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
 236                 struct link_init_data link_init_params = {0};
 237                 struct dc_link *link;
 238
 239                 link_init_params.ctx = dc->ctx;
 240                 link_init_params.connector_index = i;
 241                 link_init_params.link_index = dc->link_count;
 242                 link_init_params.dc = dc;
 243                 link_init_params.is_dpia_link = true;
 244
 245                 link = link_create(&link_init_params);
 246                 if (link) {
 247                         dc->links[dc->link_count] = link;
 248                         link->dc = dc;
 249                         ++dc->link_count;
 250                 }
 251         }
 252
 253         for (i = 0; i < num_virtual_links; i++) {
 254                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 255                 struct encoder_init_data enc_init = {0};
 256
 257                 if (link == NULL) {
 258                         BREAK_TO_DEBUGGER();
 259                         goto failed_alloc;
 260                 }
 261
 262                 link->link_index = dc->link_count;
 263                 dc->links[dc->link_count] = link;
 264                 dc->link_count++;
 265
 266                 link->ctx = dc->ctx;
 267                 link->dc = dc;
 268                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 269                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 270                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 271                 link->link_id.enum_id = ENUM_ID_1;
 272                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 273
 274                 if (!link->link_enc) {
 275                         BREAK_TO_DEBUGGER();
 276                         goto failed_alloc;
 277                 }
 278
 279                 link->link_status.dpcd_caps = &link->dpcd_caps;
 280
 281                 enc_init.ctx = dc->ctx;
 282                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 283                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 284                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 285                 enc_init.connector = link->link_id;
 286                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 287                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 288                 enc_init.encoder.enum_id = ENUM_ID_1;
 289                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 290         }
 291
 292         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 293
 294         return true;
 295
 296 failed_alloc:
 297         return false;
 298 }
 299
 300 /* Create additional DIG link encoder objects if fewer than the platform
 301  * supports were created during link construction. This can happen if the
 302  * number of physical connectors is less than the number of DIGs.
 303  */
 304 static bool create_link_encoders(struct dc *dc)
 305 {
 306         bool res = true;
 307         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 308         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 309         int i;
 310
 311         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 312          * link encoders and physical display endpoints and does not require
 313          * additional link encoder objects.
 314          */
 315         if (num_usb4_dpia == 0)
 316                 return res;
 317
 318         /* Create as many link encoder objects as the platform supports. DPIA
 319          * endpoints can be programmably mapped to any DIG.
 320          */
 321         if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
 322                 for (i = 0; i < num_dig_link_enc; i++) {
 323                         struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 324
 325                         if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
 326                                 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
 327                                                 (enum engine_id)(ENGINE_ID_DIGA + i));
 328                                 if (link_enc) {
 329                                         dc->res_pool->link_encoders[i] = link_enc;
 330                                         dc->res_pool->dig_link_enc_count++;
 331                                 } else {
 332                                         res = false;
 333                                 }
 334                         }
 335                 }
 336         }
 337
 338         return res;
 339 }
 340
 341 /* Destroy any additional DIG link encoder objects created by
 342  * create_link_encoders().
 343  * NB: Must only be called after destroy_links().
 344  */
 345 static void destroy_link_encoders(struct dc *dc)
 346 {
 347         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 348         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 349         int i;
 350
 351         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 352          * link encoders and physical display endpoints and does not require
 353          * additional link encoder objects.
 354          */
 355         if (num_usb4_dpia == 0)
 356                 return;
 357
 358         for (i = 0; i < num_dig_link_enc; i++) {
 359                 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 360
 361                 if (link_enc) {
 362                         link_enc->funcs->destroy(&link_enc);
 363                         dc->res_pool->link_encoders[i] = NULL;
 364                         dc->res_pool->dig_link_enc_count--;
 365                 }
 366         }
 367 }
 368
 369 static struct dc_perf_trace *dc_perf_trace_create(void)
 370 {
 371         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 372 }
 373
 374 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 375 {
 376         kfree(*perf_trace);
 377         *perf_trace = NULL;
 378 }
 379
 380 /**
 381  *  dc_stream_adjust_vmin_vmax:
 382  *
 383  *  Looks up the pipe context of dc_stream_state and updates the
 384  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 385  *  Rate, which is a power-saving feature that targets reducing panel
 386  *  refresh rate while the screen is static
 387  *
 388  *  @dc:     dc reference
 389  *  @stream: Initial dc stream state
 390  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 391  */
 392 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 393                 struct dc_stream_state *stream,
 394                 struct dc_crtc_timing_adjust *adjust)
 395 {
 396         int i;
 397         bool ret = false;
 398
 399         stream->adjust.v_total_max = adjust->v_total_max;
 400         stream->adjust.v_total_mid = adjust->v_total_mid;
 401         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 402         stream->adjust.v_total_min = adjust->v_total_min;
 403
 404         for (i = 0; i < MAX_PIPES; i++) {
 405                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 406
 407                 if (pipe->stream == stream && pipe->stream_res.tg) {
 408                         dc->hwss.set_drr(&pipe,
 409                                         1,
 410                                         *adjust);
 411
 412                         ret = true;
 413                 }
 414         }
 415         return ret;
 416 }
 417
 418 /**
 419  *****************************************************************************
 420  *  Function: dc_stream_get_last_vrr_vtotal
 421  *
 422  *  @brief
 423  *     Looks up the pipe context of dc_stream_state and gets the
 424  *     last VTOTAL used by DRR (Dynamic Refresh Rate)
 425  *
 426  *  @param [in] dc: dc reference
 427  *  @param [in] stream: Initial dc stream state
 428  *  @param [in] adjust: Updated parameters for vertical_total_min and
 429  *  vertical_total_max
 430  *****************************************************************************
 431  */
 432 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 433                 struct dc_stream_state *stream,
 434                 uint32_t *refresh_rate)
 435 {
 436         bool status = false;
 437
 438         int i = 0;
 439
 440         for (i = 0; i < MAX_PIPES; i++) {
 441                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 442
 443                 if (pipe->stream == stream && pipe->stream_res.tg) {
 444                         /* Only execute if a function pointer has been defined for
 445                          * the DC version in question
 446                          */
 447                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 448                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 449
 450                                 status = true;
 451
 452                                 break;
 453                         }
 454                 }
 455         }
 456
 457         return status;
 458 }
 459
 460 bool dc_stream_get_crtc_position(struct dc *dc,
 461                 struct dc_stream_state **streams, int num_streams,
 462                 unsigned int *v_pos, unsigned int *nom_v_pos)
 463 {
 464         /* TODO: Support multiple streams */
 465         const struct dc_stream_state *stream = streams[0];
 466         int i;
 467         bool ret = false;
 468         struct crtc_position position;
 469
 470         for (i = 0; i < MAX_PIPES; i++) {
 471                 struct pipe_ctx *pipe =
 472                                 &dc->current_state->res_ctx.pipe_ctx[i];
 473
 474                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 475                         dc->hwss.get_position(&pipe, 1, &position);
 476
 477                         *v_pos = position.vertical_count;
 478                         *nom_v_pos = position.nominal_vcount;
 479                         ret = true;
 480                 }
 481         }
 482         return ret;
 483 }
 484
 485 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 486 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
 487                              struct crc_params *crc_window)
 488 {
 489         int i;
 490         struct dmcu *dmcu = dc->res_pool->dmcu;
 491         struct pipe_ctx *pipe;
 492         struct crc_region tmp_win, *crc_win;
 493         struct otg_phy_mux mapping_tmp, *mux_mapping;
 494
 495         /*crc window can't be null*/
 496         if (!crc_window)
 497                 return false;
 498
 499         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 500                 crc_win = &tmp_win;
 501                 mux_mapping = &mapping_tmp;
 502                 /*set crc window*/
 503                 tmp_win.x_start = crc_window->windowa_x_start;
 504                 tmp_win.y_start = crc_window->windowa_y_start;
 505                 tmp_win.x_end = crc_window->windowa_x_end;
 506                 tmp_win.y_end = crc_window->windowa_y_end;
 507
 508                 for (i = 0; i < MAX_PIPES; i++) {
 509                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 510                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 511                                 break;
 512                 }
 513
 514                 /* Stream not found */
 515                 if (i == MAX_PIPES)
 516                         return false;
 517
 518
 519                 /*set mux routing info*/
 520                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 521                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 522
 523                 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
 524         } else {
 525                 DC_LOG_DC("dmcu is not initialized");
 526                 return false;
 527         }
 528
 529         return true;
 530 }
 531
 532 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
 533 {
 534         int i;
 535         struct dmcu *dmcu = dc->res_pool->dmcu;
 536         struct pipe_ctx *pipe;
 537         struct otg_phy_mux mapping_tmp, *mux_mapping;
 538
 539         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 540                 mux_mapping = &mapping_tmp;
 541
 542                 for (i = 0; i < MAX_PIPES; i++) {
 543                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 544                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 545                                 break;
 546                 }
 547
 548                 /* Stream not found */
 549                 if (i == MAX_PIPES)
 550                         return false;
 551
 552
 553                 /*set mux routing info*/
 554                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 555                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 556
 557                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 558         } else {
 559                 DC_LOG_DC("dmcu is not initialized");
 560                 return false;
 561         }
 562
 563         return true;
 564 }
 565 #endif
 566
 567 /**
 568  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 569  * @dc: DC Object
 570  * @stream: The stream to configure CRC on.
 571  * @enable: Enable CRC if true, disable otherwise.
 572  * @crc_window: CRC window (x/y start/end) information
 573  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 574  *              once.
 575  *
 576  * By default, only CRC0 is configured, and the entire frame is used to
 577  * calculate the crc.
 578  */
 579 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 580                              struct crc_params *crc_window, bool enable, bool continuous)
 581 {
 582         int i;
 583         struct pipe_ctx *pipe;
 584         struct crc_params param;
 585         struct timing_generator *tg;
 586
 587         for (i = 0; i < MAX_PIPES; i++) {
 588                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 589                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 590                         break;
 591         }
 592         /* Stream not found */
 593         if (i == MAX_PIPES)
 594                 return false;
 595
 596         /* By default, capture the full frame */
 597         param.windowa_x_start = 0;
 598         param.windowa_y_start = 0;
 599         param.windowa_x_end = pipe->stream->timing.h_addressable;
 600         param.windowa_y_end = pipe->stream->timing.v_addressable;
 601         param.windowb_x_start = 0;
 602         param.windowb_y_start = 0;
 603         param.windowb_x_end = pipe->stream->timing.h_addressable;
 604         param.windowb_y_end = pipe->stream->timing.v_addressable;
 605
 606         if (crc_window) {
 607                 param.windowa_x_start = crc_window->windowa_x_start;
 608                 param.windowa_y_start = crc_window->windowa_y_start;
 609                 param.windowa_x_end = crc_window->windowa_x_end;
 610                 param.windowa_y_end = crc_window->windowa_y_end;
 611                 param.windowb_x_start = crc_window->windowb_x_start;
 612                 param.windowb_y_start = crc_window->windowb_y_start;
 613                 param.windowb_x_end = crc_window->windowb_x_end;
 614                 param.windowb_y_end = crc_window->windowb_y_end;
 615         }
 616
 617         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 618         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 619
 620         /* Default to the union of both windows */
 621         param.selection = UNION_WINDOW_A_B;
 622         param.continuous_mode = continuous;
 623         param.enable = enable;
 624
 625         tg = pipe->stream_res.tg;
 626
 627         /* Only call if supported */
 628         if (tg->funcs->configure_crc)
 629                 return tg->funcs->configure_crc(tg, &param);
 630         DC_LOG_WARNING("CRC capture not supported.");
 631         return false;
 632 }
 633
 634 /**
 635  * dc_stream_get_crc() - Get CRC values for the given stream.
 636  * @dc: DC object
 637  * @stream: The DC stream state of the stream to get CRCs from.
 638  * @r_cr: CRC value for the first of the 3 channels stored here.
 639  * @g_y:  CRC value for the second of the 3 channels stored here.
 640  * @b_cb: CRC value for the third of the 3 channels stored here.
 641  *
 642  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 643  * Return false if stream is not found, or if CRCs are not enabled.
 644  */
 645 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 646                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 647 {
 648         int i;
 649         struct pipe_ctx *pipe;
 650         struct timing_generator *tg;
 651
 652         for (i = 0; i < MAX_PIPES; i++) {
 653                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 654                 if (pipe->stream == stream)
 655                         break;
 656         }
 657         /* Stream not found */
 658         if (i == MAX_PIPES)
 659                 return false;
 660
 661         tg = pipe->stream_res.tg;
 662
 663         if (tg->funcs->get_crc)
 664                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 665         DC_LOG_WARNING("CRC capture not supported.");
 666         return false;
 667 }
 668
 669 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 670                 enum dc_dynamic_expansion option)
 671 {
 672         /* OPP FMT dyn expansion updates*/
 673         int i;
 674         struct pipe_ctx *pipe_ctx;
 675
 676         for (i = 0; i < MAX_PIPES; i++) {
 677                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 678                                 == stream) {
 679                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 680                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 681                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 682                                         pipe_ctx->stream_res.opp,
 683                                         COLOR_SPACE_YCBCR601,
 684                                         stream->timing.display_color_depth,
 685                                         stream->signal);
 686                 }
 687         }
 688 }
 689
 690 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 691                 enum dc_dither_option option)
 692 {
 693         struct bit_depth_reduction_params params;
 694         struct dc_link *link = stream->link;
 695         struct pipe_ctx *pipes = NULL;
 696         int i;
 697
 698         for (i = 0; i < MAX_PIPES; i++) {
 699                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 700                                 stream) {
 701                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 702                         break;
 703                 }
 704         }
 705
 706         if (!pipes)
 707                 return;
 708         if (option > DITHER_OPTION_MAX)
 709                 return;
 710
 711         stream->dither_option = option;
 712
 713         memset(&params, 0, sizeof(params));
 714         resource_build_bit_depth_reduction_params(stream, &params);
 715         stream->bit_depth_params = params;
 716
 717         if (pipes->plane_res.xfm &&
 718             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 719                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 720                         pipes->plane_res.xfm,
 721                         pipes->plane_res.scl_data.lb_params.depth,
 722                         &stream->bit_depth_params);
 723         }
 724
 725         pipes->stream_res.opp->funcs->
 726                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 727 }
 728
 729 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 730 {
 731         int i;
 732         bool ret = false;
 733         struct pipe_ctx *pipes;
 734
 735         for (i = 0; i < MAX_PIPES; i++) {
 736                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 737                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 738                         dc->hwss.program_gamut_remap(pipes);
 739                         ret = true;
 740                 }
 741         }
 742
 743         return ret;
 744 }
 745
 746 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 747 {
 748         int i;
 749         bool ret = false;
 750         struct pipe_ctx *pipes;
 751
 752         for (i = 0; i < MAX_PIPES; i++) {
 753                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 754                                 == stream) {
 755
 756                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 757                         dc->hwss.program_output_csc(dc,
 758                                         pipes,
 759                                         stream->output_color_space,
 760                                         stream->csc_color_matrix.matrix,
 761                                         pipes->stream_res.opp->inst);
 762                         ret = true;
 763                 }
 764         }
 765
 766         return ret;
 767 }
 768
 769 void dc_stream_set_static_screen_params(struct dc *dc,
 770                 struct dc_stream_state **streams,
 771                 int num_streams,
 772                 const struct dc_static_screen_params *params)
 773 {
 774         int i, j;
 775         struct pipe_ctx *pipes_affected[MAX_PIPES];
 776         int num_pipes_affected = 0;
 777
 778         for (i = 0; i < num_streams; i++) {
 779                 struct dc_stream_state *stream = streams[i];
 780
 781                 for (j = 0; j < MAX_PIPES; j++) {
 782                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 783                                         == stream) {
 784                                 pipes_affected[num_pipes_affected++] =
 785                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 786                         }
 787                 }
 788         }
 789
 790         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 791 }
 792
 793 static void dc_destruct(struct dc *dc)
 794 {
 795         // reset link encoder assignment table on destruct
 796         if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
 797                 link_enc_cfg_init(dc, dc->current_state);
 798
 799         if (dc->current_state) {
 800                 dc_release_state(dc->current_state);
 801                 dc->current_state = NULL;
 802         }
 803
 804         destroy_links(dc);
 805
 806         destroy_link_encoders(dc);
 807
 808         if (dc->clk_mgr) {
 809                 dc_destroy_clk_mgr(dc->clk_mgr);
 810                 dc->clk_mgr = NULL;
 811         }
 812
 813         dc_destroy_resource_pool(dc);
 814
 815         if (dc->ctx->gpio_service)
 816                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 817
 818         if (dc->ctx->created_bios)
 819                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 820
 821         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 822
 823         kfree(dc->ctx);
 824         dc->ctx = NULL;
 825
 826         kfree(dc->bw_vbios);
 827         dc->bw_vbios = NULL;
 828
 829         kfree(dc->bw_dceip);
 830         dc->bw_dceip = NULL;
 831
 832 #ifdef CONFIG_DRM_AMD_DC_DCN
 833         kfree(dc->dcn_soc);
 834         dc->dcn_soc = NULL;
 835
 836         kfree(dc->dcn_ip);
 837         dc->dcn_ip = NULL;
 838
 839 #endif
 840         kfree(dc->vm_helper);
 841         dc->vm_helper = NULL;
 842
 843 }
 844
 845 static bool dc_construct_ctx(struct dc *dc,
 846                 const struct dc_init_data *init_params)
 847 {
 848         struct dc_context *dc_ctx;
 849         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 850
 851         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 852         if (!dc_ctx)
 853                 return false;
 854
 855         dc_ctx->cgs_device = init_params->cgs_device;
 856         dc_ctx->driver_context = init_params->driver;
 857         dc_ctx->dc = dc;
 858         dc_ctx->asic_id = init_params->asic_id;
 859         dc_ctx->dc_sink_id_count = 0;
 860         dc_ctx->dc_stream_id_count = 0;
 861         dc_ctx->dce_environment = init_params->dce_environment;
 862
 863         /* Create logger */
 864
 865         dc_version = resource_parse_asic_id(init_params->asic_id);
 866         dc_ctx->dce_version = dc_version;
 867
 868         dc_ctx->perf_trace = dc_perf_trace_create();
 869         if (!dc_ctx->perf_trace) {
 870                 ASSERT_CRITICAL(false);
 871                 return false;
 872         }
 873
 874         dc->ctx = dc_ctx;
 875
 876         return true;
 877 }
 878
 879 static bool dc_construct(struct dc *dc,
 880                 const struct dc_init_data *init_params)
 881 {
 882         struct dc_context *dc_ctx;
 883         struct bw_calcs_dceip *dc_dceip;
 884         struct bw_calcs_vbios *dc_vbios;
 885 #ifdef CONFIG_DRM_AMD_DC_DCN
 886         struct dcn_soc_bounding_box *dcn_soc;
 887         struct dcn_ip_params *dcn_ip;
 888 #endif
 889
 890         dc->config = init_params->flags;
 891
 892         // Allocate memory for the vm_helper
 893         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 894         if (!dc->vm_helper) {
 895                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 896                 goto fail;
 897         }
 898
 899         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 900
 901         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 902         if (!dc_dceip) {
 903                 dm_error("%s: failed to create dceip\n", __func__);
 904                 goto fail;
 905         }
 906
 907         dc->bw_dceip = dc_dceip;
 908
 909         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 910         if (!dc_vbios) {
 911                 dm_error("%s: failed to create vbios\n", __func__);
 912                 goto fail;
 913         }
 914
 915         dc->bw_vbios = dc_vbios;
 916 #ifdef CONFIG_DRM_AMD_DC_DCN
 917         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 918         if (!dcn_soc) {
 919                 dm_error("%s: failed to create dcn_soc\n", __func__);
 920                 goto fail;
 921         }
 922
 923         dc->dcn_soc = dcn_soc;
 924
 925         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 926         if (!dcn_ip) {
 927                 dm_error("%s: failed to create dcn_ip\n", __func__);
 928                 goto fail;
 929         }
 930
 931         dc->dcn_ip = dcn_ip;
 932 #endif
 933
 934         if (!dc_construct_ctx(dc, init_params)) {
 935                 dm_error("%s: failed to create ctx\n", __func__);
 936                 goto fail;
 937         }
 938
 939         dc_ctx = dc->ctx;
 940
 941         /* Resource should construct all asic specific resources.
 942          * This should be the only place where we need to parse the asic id
 943          */
 944         if (init_params->vbios_override)
 945                 dc_ctx->dc_bios = init_params->vbios_override;
 946         else {
 947                 /* Create BIOS parser */
 948                 struct bp_init_data bp_init_data;
 949
 950                 bp_init_data.ctx = dc_ctx;
 951                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 952
 953                 dc_ctx->dc_bios = dal_bios_parser_create(
 954                                 &bp_init_data, dc_ctx->dce_version);
 955
 956                 if (!dc_ctx->dc_bios) {
 957                         ASSERT_CRITICAL(false);
 958                         goto fail;
 959                 }
 960
 961                 dc_ctx->created_bios = true;
 962         }
 963
 964         dc->vendor_signature = init_params->vendor_signature;
 965
 966         /* Create GPIO service */
 967         dc_ctx->gpio_service = dal_gpio_service_create(
 968                         dc_ctx->dce_version,
 969                         dc_ctx->dce_environment,
 970                         dc_ctx);
 971
 972         if (!dc_ctx->gpio_service) {
 973                 ASSERT_CRITICAL(false);
 974                 goto fail;
 975         }
 976
 977         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 978         if (!dc->res_pool)
 979                 goto fail;
 980
 981         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 982         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 983                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 984
 985         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 986         if (!dc->clk_mgr)
 987                 goto fail;
 988 #ifdef CONFIG_DRM_AMD_DC_DCN
 989         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 990
 991         if (dc->res_pool->funcs->update_bw_bounding_box) {
 992                 DC_FP_START();
 993                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 994                 DC_FP_END();
 995         }
 996 #endif
 997
 998         /* Creation of current_state must occur after dc->dml
 999          * is initialized in dc_create_resource_pool because
1000          * on creation it copies the contents of dc->dml
1001          */
1002
1003         dc->current_state = dc_create_state(dc);
1004
1005         if (!dc->current_state) {
1006                 dm_error("%s: failed to create validate ctx\n", __func__);
1007                 goto fail;
1008         }
1009
1010         if (!create_links(dc, init_params->num_virtual_links))
1011                 goto fail;
1012
1013         /* Create additional DIG link encoder objects if fewer than the platform
1014          * supports were created during link construction.
1015          */
1016         if (!create_link_encoders(dc))
1017                 goto fail;
1018
1019         dc_resource_state_construct(dc, dc->current_state);
1020
1021         return true;
1022
1023 fail:
1024         return false;
1025 }
1026
1027 static void disable_all_writeback_pipes_for_stream(
1028                 const struct dc *dc,
1029                 struct dc_stream_state *stream,
1030                 struct dc_state *context)
1031 {
1032         int i;
1033
1034         for (i = 0; i < stream->num_wb_info; i++)
1035                 stream->writeback_info[i].wb_enabled = false;
1036 }
1037
1038 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
1039                                           struct dc_stream_state *stream, bool lock)
1040 {
1041         int i;
1042
1043         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1044         if (dc->hwss.interdependent_update_lock)
1045                 dc->hwss.interdependent_update_lock(dc, context, lock);
1046         else {
1047                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1048                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1049                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1050
1051                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
1052                         if (stream == pipe_ctx->stream) {
1053                                 if (!pipe_ctx->top_pipe &&
1054                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1055                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1056                         }
1057                 }
1058         }
1059 }
1060
1061 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1062 {
1063         int i, j;
1064         struct dc_state *dangling_context = dc_create_state(dc);
1065         struct dc_state *current_ctx;
1066
1067         if (dangling_context == NULL)
1068                 return;
1069
1070         dc_resource_state_copy_construct(dc->current_state, dangling_context);
1071
1072         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1073                 struct dc_stream_state *old_stream =
1074                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
1075                 bool should_disable = true;
1076                 bool pipe_split_change =
1077                         context->res_ctx.pipe_ctx[i].top_pipe != dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1078
1079                 for (j = 0; j < context->stream_count; j++) {
1080                         if (old_stream == context->streams[j]) {
1081                                 should_disable = false;
1082                                 break;
1083                         }
1084                 }
1085                 if (!should_disable && pipe_split_change &&
1086                                 dc->current_state->stream_count != context->stream_count)
1087                         should_disable = true;
1088
1089                 if (should_disable && old_stream) {
1090                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1091                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1092
1093                         if (dc->hwss.apply_ctx_for_surface) {
1094                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1095                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1096                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1097                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1098                         }
1099                         if (dc->hwss.program_front_end_for_ctx) {
1100                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1101                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1102                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1103                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1104                         }
1105                 }
1106         }
1107
1108         current_ctx = dc->current_state;
1109         dc->current_state = dangling_context;
1110         dc_release_state(current_ctx);
1111 }
1112
1113 static void disable_vbios_mode_if_required(
1114                 struct dc *dc,
1115                 struct dc_state *context)
1116 {
1117         unsigned int i, j;
1118
1119         /* check if timing_changed, disable stream*/
1120         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1121                 struct dc_stream_state *stream = NULL;
1122                 struct dc_link *link = NULL;
1123                 struct pipe_ctx *pipe = NULL;
1124
1125                 pipe = &context->res_ctx.pipe_ctx[i];
1126                 stream = pipe->stream;
1127                 if (stream == NULL)
1128                         continue;
1129
1130                 // only looking for first odm pipe
1131                 if (pipe->prev_odm_pipe)
1132                         continue;
1133
1134                 if (stream->link->local_sink &&
1135                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1136                         link = stream->link;
1137                 }
1138
1139                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1140                         unsigned int enc_inst, tg_inst = 0;
1141                         unsigned int pix_clk_100hz;
1142
1143                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1144                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1145                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1146                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1147                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1148                                                         dc->res_pool->stream_enc[j]);
1149                                                 break;
1150                                         }
1151                                 }
1152
1153                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1154                                         dc->res_pool->dp_clock_source,
1155                                         tg_inst, &pix_clk_100hz);
1156
1157                                 if (link->link_status.link_active) {
1158                                         uint32_t requested_pix_clk_100hz =
1159                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1160
1161                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1162                                                 core_link_disable_stream(pipe);
1163                                                 pipe->stream->dpms_off = false;
1164                                         }
1165                                 }
1166                         }
1167                 }
1168         }
1169 }
1170
1171 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1172 {
1173         int i;
1174         PERF_TRACE();
1175         for (i = 0; i < MAX_PIPES; i++) {
1176                 int count = 0;
1177                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1178
1179                 if (!pipe->plane_state)
1180                         continue;
1181
1182                 /* Timeout 100 ms */
1183                 while (count < 100000) {
1184                         /* Must set to false to start with, due to OR in update function */
1185                         pipe->plane_state->status.is_flip_pending = false;
1186                         dc->hwss.update_pending_status(pipe);
1187                         if (!pipe->plane_state->status.is_flip_pending)
1188                                 break;
1189                         udelay(1);
1190                         count++;
1191                 }
1192                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1193         }
1194         PERF_TRACE();
1195 }
1196
1197 /*******************************************************************************
1198  * Public functions
1199  ******************************************************************************/
1200
1201 struct dc *dc_create(const struct dc_init_data *init_params)
1202 {
1203         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1204         unsigned int full_pipe_count;
1205
1206         if (!dc)
1207                 return NULL;
1208
1209         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1210                 if (!dc_construct_ctx(dc, init_params))
1211                         goto destruct_dc;
1212         } else {
1213                 if (!dc_construct(dc, init_params))
1214                         goto destruct_dc;
1215
1216                 full_pipe_count = dc->res_pool->pipe_count;
1217                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1218                         full_pipe_count--;
1219                 dc->caps.max_streams = min(
1220                                 full_pipe_count,
1221                                 dc->res_pool->stream_enc_count);
1222
1223                 dc->caps.max_links = dc->link_count;
1224                 dc->caps.max_audios = dc->res_pool->audio_count;
1225                 dc->caps.linear_pitch_alignment = 64;
1226
1227                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1228
1229                 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1230
1231                 if (dc->res_pool->dmcu != NULL)
1232                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1233         }
1234
1235         /* Populate versioning information */
1236         dc->versions.dc_ver = DC_VER;
1237
1238         dc->build_id = DC_BUILD_ID;
1239
1240         DC_LOG_DC("Display Core initialized\n");
1241
1242
1243
1244         return dc;
1245
1246 destruct_dc:
1247         dc_destruct(dc);
1248         kfree(dc);
1249         return NULL;
1250 }
1251
1252 static void detect_edp_presence(struct dc *dc)
1253 {
1254         struct dc_link *edp_links[MAX_NUM_EDP];
1255         struct dc_link *edp_link = NULL;
1256         enum dc_connection_type type;
1257         int i;
1258         int edp_num;
1259
1260         get_edp_links(dc, edp_links, &edp_num);
1261         if (!edp_num)
1262                 return;
1263
1264         for (i = 0; i < edp_num; i++) {
1265                 edp_link = edp_links[i];
1266                 if (dc->config.edp_not_connected) {
1267                         edp_link->edp_sink_present = false;
1268                 } else {
1269                         dc_link_detect_sink(edp_link, &type);
1270                         edp_link->edp_sink_present = (type != dc_connection_none);
1271                 }
1272         }
1273 }
1274
1275 void dc_hardware_init(struct dc *dc)
1276 {
1277
1278         detect_edp_presence(dc);
1279         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1280                 dc->hwss.init_hw(dc);
1281 }
1282
1283 void dc_init_callbacks(struct dc *dc,
1284                 const struct dc_callback_init *init_params)
1285 {
1286 #ifdef CONFIG_DRM_AMD_DC_HDCP
1287         dc->ctx->cp_psp = init_params->cp_psp;
1288 #endif
1289 }
1290
1291 void dc_deinit_callbacks(struct dc *dc)
1292 {
1293 #ifdef CONFIG_DRM_AMD_DC_HDCP
1294         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1295 #endif
1296 }
1297
1298 void dc_destroy(struct dc **dc)
1299 {
1300         dc_destruct(*dc);
1301         kfree(*dc);
1302         *dc = NULL;
1303 }
1304
1305 static void enable_timing_multisync(
1306                 struct dc *dc,
1307                 struct dc_state *ctx)
1308 {
1309         int i, multisync_count = 0;
1310         int pipe_count = dc->res_pool->pipe_count;
1311         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1312
1313         for (i = 0; i < pipe_count; i++) {
1314                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1315                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1316                         continue;
1317                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1318                         continue;
1319                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1320                 multisync_count++;
1321         }
1322
1323         if (multisync_count > 0) {
1324                 dc->hwss.enable_per_frame_crtc_position_reset(
1325                         dc, multisync_count, multisync_pipes);
1326         }
1327 }
1328
1329 static void program_timing_sync(
1330                 struct dc *dc,
1331                 struct dc_state *ctx)
1332 {
1333         int i, j, k;
1334         int group_index = 0;
1335         int num_group = 0;
1336         int pipe_count = dc->res_pool->pipe_count;
1337         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1338
1339         for (i = 0; i < pipe_count; i++) {
1340                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1341                         continue;
1342
1343                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1344         }
1345
1346         for (i = 0; i < pipe_count; i++) {
1347                 int group_size = 1;
1348                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1349                 struct pipe_ctx *pipe_set[MAX_PIPES];
1350
1351                 if (!unsynced_pipes[i])
1352                         continue;
1353
1354                 pipe_set[0] = unsynced_pipes[i];
1355                 unsynced_pipes[i] = NULL;
1356
1357                 /* Add tg to the set, search rest of the tg's for ones with
1358                  * same timing, add all tgs with same timing to the group
1359                  */
1360                 for (j = i + 1; j < pipe_count; j++) {
1361                         if (!unsynced_pipes[j])
1362                                 continue;
1363                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1364                                 dc->hwss.enable_vblanks_synchronization &&
1365                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1366                                 resource_are_vblanks_synchronizable(
1367                                         unsynced_pipes[j]->stream,
1368                                         pipe_set[0]->stream)) {
1369                                 sync_type = VBLANK_SYNCHRONIZABLE;
1370                                 pipe_set[group_size] = unsynced_pipes[j];
1371                                 unsynced_pipes[j] = NULL;
1372                                 group_size++;
1373                         } else
1374                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1375                                 resource_are_streams_timing_synchronizable(
1376                                         unsynced_pipes[j]->stream,
1377                                         pipe_set[0]->stream)) {
1378                                 sync_type = TIMING_SYNCHRONIZABLE;
1379                                 pipe_set[group_size] = unsynced_pipes[j];
1380                                 unsynced_pipes[j] = NULL;
1381                                 group_size++;
1382                         }
1383                 }
1384
1385                 /* set first unblanked pipe as master */
1386                 for (j = 0; j < group_size; j++) {
1387                         bool is_blanked;
1388
1389                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1390                                 is_blanked =
1391                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1392                         else
1393                                 is_blanked =
1394                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1395                         if (!is_blanked) {
1396                                 if (j == 0)
1397                                         break;
1398
1399                                 swap(pipe_set[0], pipe_set[j]);
1400                                 break;
1401                         }
1402                 }
1403
1404                 for (k = 0; k < group_size; k++) {
1405                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1406
1407                         status->timing_sync_info.group_id = num_group;
1408                         status->timing_sync_info.group_size = group_size;
1409                         if (k == 0)
1410                                 status->timing_sync_info.master = true;
1411                         else
1412                                 status->timing_sync_info.master = false;
1413
1414                 }
1415
1416                 /* remove any other pipes that are already been synced */
1417                 if (dc->config.use_pipe_ctx_sync_logic) {
1418                         /* check pipe's syncd to decide which pipe to be removed */
1419                         for (j = 1; j < group_size; j++) {
1420                                 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1421                                         group_size--;
1422                                         pipe_set[j] = pipe_set[group_size];
1423                                         j--;
1424                                 } else
1425                                         /* link slave pipe's syncd with master pipe */
1426                                         pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1427                         }
1428                 } else {
1429                         for (j = j + 1; j < group_size; j++) {
1430                                 bool is_blanked;
1431
1432                                 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1433                                         is_blanked =
1434                                                 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1435                                 else
1436                                         is_blanked =
1437                                                 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1438                                 if (!is_blanked) {
1439                                         group_size--;
1440                                         pipe_set[j] = pipe_set[group_size];
1441                                         j--;
1442                                 }
1443                         }
1444                 }
1445
1446                 if (group_size > 1) {
1447                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1448                                 dc->hwss.enable_timing_synchronization(
1449                                         dc, group_index, group_size, pipe_set);
1450                         } else
1451                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1452                                 dc->hwss.enable_vblanks_synchronization(
1453                                         dc, group_index, group_size, pipe_set);
1454                                 }
1455                         group_index++;
1456                 }
1457                 num_group++;
1458         }
1459 }
1460
1461 static bool context_changed(
1462                 struct dc *dc,
1463                 struct dc_state *context)
1464 {
1465         uint8_t i;
1466
1467         if (context->stream_count != dc->current_state->stream_count)
1468                 return true;
1469
1470         for (i = 0; i < dc->current_state->stream_count; i++) {
1471                 if (dc->current_state->streams[i] != context->streams[i])
1472                         return true;
1473         }
1474
1475         return false;
1476 }
1477
1478 bool dc_validate_boot_timing(const struct dc *dc,
1479                                 const struct dc_sink *sink,
1480                                 struct dc_crtc_timing *crtc_timing)
1481 {
1482         struct timing_generator *tg;
1483         struct stream_encoder *se = NULL;
1484
1485         struct dc_crtc_timing hw_crtc_timing = {0};
1486
1487         struct dc_link *link = sink->link;
1488         unsigned int i, enc_inst, tg_inst = 0;
1489
1490         /* Support seamless boot on EDP displays only */
1491         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1492                 return false;
1493         }
1494
1495         /* Check for enabled DIG to identify enabled display */
1496         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1497                 return false;
1498
1499         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1500
1501         if (enc_inst == ENGINE_ID_UNKNOWN)
1502                 return false;
1503
1504         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1505                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1506
1507                         se = dc->res_pool->stream_enc[i];
1508
1509                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1510                                 dc->res_pool->stream_enc[i]);
1511                         break;
1512                 }
1513         }
1514
1515         // tg_inst not found
1516         if (i == dc->res_pool->stream_enc_count)
1517                 return false;
1518
1519         if (tg_inst >= dc->res_pool->timing_generator_count)
1520                 return false;
1521
1522         tg = dc->res_pool->timing_generators[tg_inst];
1523
1524         if (!tg->funcs->get_hw_timing)
1525                 return false;
1526
1527         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1528                 return false;
1529
1530         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1531                 return false;
1532
1533         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1534                 return false;
1535
1536         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1537                 return false;
1538
1539         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1540                 return false;
1541
1542         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1543                 return false;
1544
1545         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1546                 return false;
1547
1548         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1549                 return false;
1550
1551         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1552                 return false;
1553
1554         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1555                 return false;
1556
1557         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1558                 return false;
1559
1560         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1561                 return false;
1562
1563         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1564                 return false;
1565
1566         /* block DSC for now, as VBIOS does not currently support DSC timings */
1567         if (crtc_timing->flags.DSC)
1568                 return false;
1569
1570         if (dc_is_dp_signal(link->connector_signal)) {
1571                 unsigned int pix_clk_100hz;
1572
1573                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1574                         dc->res_pool->dp_clock_source,
1575                         tg_inst, &pix_clk_100hz);
1576
1577                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1578                         return false;
1579
1580                 if (!se->funcs->dp_get_pixel_format)
1581                         return false;
1582
1583                 if (!se->funcs->dp_get_pixel_format(
1584                         se,
1585                         &hw_crtc_timing.pixel_encoding,
1586                         &hw_crtc_timing.display_color_depth))
1587                         return false;
1588
1589                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1590                         return false;
1591
1592                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1593                         return false;
1594         }
1595
1596         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1597                 return false;
1598         }
1599
1600         if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1601                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1602                 return false;
1603         }
1604
1605         return true;
1606 }
1607
1608 static inline bool should_update_pipe_for_stream(
1609                 struct dc_state *context,
1610                 struct pipe_ctx *pipe_ctx,
1611                 struct dc_stream_state *stream)
1612 {
1613         return (pipe_ctx->stream && pipe_ctx->stream == stream);
1614 }
1615
1616 static inline bool should_update_pipe_for_plane(
1617                 struct dc_state *context,
1618                 struct pipe_ctx *pipe_ctx,
1619                 struct dc_plane_state *plane_state)
1620 {
1621         return (pipe_ctx->plane_state == plane_state);
1622 }
1623
1624 void dc_enable_stereo(
1625         struct dc *dc,
1626         struct dc_state *context,
1627         struct dc_stream_state *streams[],
1628         uint8_t stream_count)
1629 {
1630         int i, j;
1631         struct pipe_ctx *pipe;
1632
1633         for (i = 0; i < MAX_PIPES; i++) {
1634                 if (context != NULL) {
1635                         pipe = &context->res_ctx.pipe_ctx[i];
1636                 } else {
1637                         context = dc->current_state;
1638                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1639                 }
1640
1641                 for (j = 0; pipe && j < stream_count; j++)  {
1642                         if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1643                                 dc->hwss.setup_stereo)
1644                                 dc->hwss.setup_stereo(pipe, dc);
1645                 }
1646         }
1647 }
1648
1649 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1650 {
1651         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1652                 enable_timing_multisync(dc, context);
1653                 program_timing_sync(dc, context);
1654         }
1655 }
1656
1657 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1658 {
1659         int i;
1660         unsigned int stream_mask = 0;
1661
1662         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1663                 if (context->res_ctx.pipe_ctx[i].stream)
1664                         stream_mask |= 1 << i;
1665         }
1666
1667         return stream_mask;
1668 }
1669
1670 #if defined(CONFIG_DRM_AMD_DC_DCN)
1671 void dc_z10_restore(const struct dc *dc)
1672 {
1673         if (dc->hwss.z10_restore)
1674                 dc->hwss.z10_restore(dc);
1675 }
1676
1677 void dc_z10_save_init(struct dc *dc)
1678 {
1679         if (dc->hwss.z10_save_init)
1680                 dc->hwss.z10_save_init(dc);
1681 }
1682 #endif
1683 /*
1684  * Applies given context to HW and copy it into current context.
1685  * It's up to the user to release the src context afterwards.
1686  */
1687 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1688 {
1689         struct dc_bios *dcb = dc->ctx->dc_bios;
1690         enum dc_status result = DC_ERROR_UNEXPECTED;
1691         struct pipe_ctx *pipe;
1692         int i, k, l;
1693         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1694         struct dc_state *old_state;
1695
1696 #if defined(CONFIG_DRM_AMD_DC_DCN)
1697         dc_z10_restore(dc);
1698         dc_allow_idle_optimizations(dc, false);
1699 #endif
1700
1701         for (i = 0; i < context->stream_count; i++)
1702                 dc_streams[i] =  context->streams[i];
1703
1704         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1705                 disable_vbios_mode_if_required(dc, context);
1706                 dc->hwss.enable_accelerated_mode(dc, context);
1707         }
1708
1709         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1710                 context->stream_count == 0)
1711                 dc->hwss.prepare_bandwidth(dc, context);
1712
1713         disable_dangling_plane(dc, context);
1714         /* re-program planes for existing stream, in case we need to
1715          * free up plane resource for later use
1716          */
1717         if (dc->hwss.apply_ctx_for_surface) {
1718                 for (i = 0; i < context->stream_count; i++) {
1719                         if (context->streams[i]->mode_changed)
1720                                 continue;
1721                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1722                         dc->hwss.apply_ctx_for_surface(
1723                                 dc, context->streams[i],
1724                                 context->stream_status[i].plane_count,
1725                                 context); /* use new pipe config in new context */
1726                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1727                         dc->hwss.post_unlock_program_front_end(dc, context);
1728                 }
1729         }
1730
1731         /* Program hardware */
1732         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1733                 pipe = &context->res_ctx.pipe_ctx[i];
1734                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1735         }
1736
1737         result = dc->hwss.apply_ctx_to_hw(dc, context);
1738
1739         if (result != DC_OK)
1740                 return result;
1741
1742         dc_trigger_sync(dc, context);
1743
1744         /* Program all planes within new context*/
1745         if (dc->hwss.program_front_end_for_ctx) {
1746                 dc->hwss.interdependent_update_lock(dc, context, true);
1747                 dc->hwss.program_front_end_for_ctx(dc, context);
1748                 dc->hwss.interdependent_update_lock(dc, context, false);
1749                 dc->hwss.post_unlock_program_front_end(dc, context);
1750         }
1751         for (i = 0; i < context->stream_count; i++) {
1752                 const struct dc_link *link = context->streams[i]->link;
1753
1754                 if (!context->streams[i]->mode_changed)
1755                         continue;
1756
1757                 if (dc->hwss.apply_ctx_for_surface) {
1758                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1759                         dc->hwss.apply_ctx_for_surface(
1760                                         dc, context->streams[i],
1761                                         context->stream_status[i].plane_count,
1762                                         context);
1763                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1764                         dc->hwss.post_unlock_program_front_end(dc, context);
1765                 }
1766
1767                 /*
1768                  * enable stereo
1769                  * TODO rework dc_enable_stereo call to work with validation sets?
1770                  */
1771                 for (k = 0; k < MAX_PIPES; k++) {
1772                         pipe = &context->res_ctx.pipe_ctx[k];
1773
1774                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1775                                 if (context->streams[l] &&
1776                                         context->streams[l] == pipe->stream &&
1777                                         dc->hwss.setup_stereo)
1778                                         dc->hwss.setup_stereo(pipe, dc);
1779                         }
1780                 }
1781
1782                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1783                                 context->streams[i]->timing.h_addressable,
1784                                 context->streams[i]->timing.v_addressable,
1785                                 context->streams[i]->timing.h_total,
1786                                 context->streams[i]->timing.v_total,
1787                                 context->streams[i]->timing.pix_clk_100hz / 10);
1788         }
1789
1790         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1791
1792         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1793                 context->stream_count == 0) {
1794                 /* Must wait for no flips to be pending before doing optimize bw */
1795                 wait_for_no_pipes_pending(dc, context);
1796                 /* pplib is notified if disp_num changed */
1797                 dc->hwss.optimize_bandwidth(dc, context);
1798         }
1799
1800         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1801                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1802         else
1803                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1804
1805         context->stream_mask = get_stream_mask(dc, context);
1806
1807         if (context->stream_mask != dc->current_state->stream_mask)
1808                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1809
1810         for (i = 0; i < context->stream_count; i++)
1811                 context->streams[i]->mode_changed = false;
1812
1813         old_state = dc->current_state;
1814         dc->current_state = context;
1815
1816         dc_release_state(old_state);
1817
1818         dc_retain_state(dc->current_state);
1819
1820         return result;
1821 }
1822
1823 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1824 {
1825         enum dc_status result = DC_ERROR_UNEXPECTED;
1826         int i;
1827
1828         if (!context_changed(dc, context))
1829                 return DC_OK;
1830
1831         DC_LOG_DC("%s: %d streams\n",
1832                                 __func__, context->stream_count);
1833
1834         for (i = 0; i < context->stream_count; i++) {
1835                 struct dc_stream_state *stream = context->streams[i];
1836
1837                 dc_stream_log(dc, stream);
1838         }
1839
1840         /*
1841          * Previous validation was perfomred with fast_validation = true and
1842          * the full DML state required for hardware programming was skipped.
1843          *
1844          * Re-validate here to calculate these parameters / watermarks.
1845          */
1846         result = dc_validate_global_state(dc, context, false);
1847         if (result != DC_OK) {
1848                 DC_LOG_ERROR("DC commit global validation failure: %s (%d)",
1849                              dc_status_to_str(result), result);
1850                 return result;
1851         }
1852
1853         result = dc_commit_state_no_check(dc, context);
1854
1855         return (result == DC_OK);
1856 }
1857
1858 #if defined(CONFIG_DRM_AMD_DC_DCN)
1859 bool dc_acquire_release_mpc_3dlut(
1860                 struct dc *dc, bool acquire,
1861                 struct dc_stream_state *stream,
1862                 struct dc_3dlut **lut,
1863                 struct dc_transfer_func **shaper)
1864 {
1865         int pipe_idx;
1866         bool ret = false;
1867         bool found_pipe_idx = false;
1868         const struct resource_pool *pool = dc->res_pool;
1869         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1870         int mpcc_id = 0;
1871
1872         if (pool && res_ctx) {
1873                 if (acquire) {
1874                         /*find pipe idx for the given stream*/
1875                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1876                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1877                                         found_pipe_idx = true;
1878                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1879                                         break;
1880                                 }
1881                         }
1882                 } else
1883                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1884
1885                 if (found_pipe_idx) {
1886                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1887                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1888                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
1889                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1890                 }
1891         }
1892         return ret;
1893 }
1894 #endif
1895 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1896 {
1897         int i;
1898         struct pipe_ctx *pipe;
1899
1900         for (i = 0; i < MAX_PIPES; i++) {
1901                 pipe = &context->res_ctx.pipe_ctx[i];
1902
1903                 if (!pipe->plane_state)
1904                         continue;
1905
1906                 /* Must set to false to start with, due to OR in update function */
1907                 pipe->plane_state->status.is_flip_pending = false;
1908                 dc->hwss.update_pending_status(pipe);
1909                 if (pipe->plane_state->status.is_flip_pending)
1910                         return true;
1911         }
1912         return false;
1913 }
1914
1915 #ifdef CONFIG_DRM_AMD_DC_DCN
1916 /* Perform updates here which need to be deferred until next vupdate
1917  *
1918  * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
1919  * but forcing lut memory to shutdown state is immediate. This causes
1920  * single frame corruption as lut gets disabled mid-frame unless shutdown
1921  * is deferred until after entering bypass.
1922  */
1923 static void process_deferred_updates(struct dc *dc)
1924 {
1925         int i = 0;
1926
1927         if (dc->debug.enable_mem_low_power.bits.cm) {
1928                 ASSERT(dc->dcn_ip->max_num_dpp);
1929                 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
1930                         if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
1931                                 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
1932         }
1933 }
1934 #endif /* CONFIG_DRM_AMD_DC_DCN */
1935
1936 void dc_post_update_surfaces_to_stream(struct dc *dc)
1937 {
1938         int i;
1939         struct dc_state *context = dc->current_state;
1940
1941         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
1942                 return;
1943
1944         post_surface_trace(dc);
1945
1946         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1947                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1948         else
1949                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1950
1951         if (is_flip_pending_in_pipes(dc, context))
1952                 return;
1953
1954         for (i = 0; i < dc->res_pool->pipe_count; i++)
1955                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1956                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1957                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1958                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1959                 }
1960
1961 #ifdef CONFIG_DRM_AMD_DC_DCN
1962         process_deferred_updates(dc);
1963 #endif
1964
1965         dc->hwss.optimize_bandwidth(dc, context);
1966
1967         dc->optimized_required = false;
1968         dc->wm_optimized_required = false;
1969 }
1970
1971 static void init_state(struct dc *dc, struct dc_state *context)
1972 {
1973         /* Each context must have their own instance of VBA and in order to
1974          * initialize and obtain IP and SOC the base DML instance from DC is
1975          * initially copied into every context
1976          */
1977 #ifdef CONFIG_DRM_AMD_DC_DCN
1978         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1979 #endif
1980 }
1981
1982 struct dc_state *dc_create_state(struct dc *dc)
1983 {
1984         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1985                                             GFP_KERNEL);
1986
1987         if (!context)
1988                 return NULL;
1989
1990         init_state(dc, context);
1991
1992         kref_init(&context->refcount);
1993
1994         return context;
1995 }
1996
1997 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1998 {
1999         int i, j;
2000         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2001
2002         if (!new_ctx)
2003                 return NULL;
2004         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
2005
2006         for (i = 0; i < MAX_PIPES; i++) {
2007                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
2008
2009                         if (cur_pipe->top_pipe)
2010                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2011
2012                         if (cur_pipe->bottom_pipe)
2013                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2014
2015                         if (cur_pipe->prev_odm_pipe)
2016                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2017
2018                         if (cur_pipe->next_odm_pipe)
2019                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2020
2021         }
2022
2023         for (i = 0; i < new_ctx->stream_count; i++) {
2024                         dc_stream_retain(new_ctx->streams[i]);
2025                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
2026                                 dc_plane_state_retain(
2027                                         new_ctx->stream_status[i].plane_states[j]);
2028         }
2029
2030         kref_init(&new_ctx->refcount);
2031
2032         return new_ctx;
2033 }
2034
2035 void dc_retain_state(struct dc_state *context)
2036 {
2037         kref_get(&context->refcount);
2038 }
2039
2040 static void dc_state_free(struct kref *kref)
2041 {
2042         struct dc_state *context = container_of(kref, struct dc_state, refcount);
2043         dc_resource_state_destruct(context);
2044         kvfree(context);
2045 }
2046
2047 void dc_release_state(struct dc_state *context)
2048 {
2049         kref_put(&context->refcount, dc_state_free);
2050 }
2051
2052 bool dc_set_generic_gpio_for_stereo(bool enable,
2053                 struct gpio_service *gpio_service)
2054 {
2055         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2056         struct gpio_pin_info pin_info;
2057         struct gpio *generic;
2058         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2059                            GFP_KERNEL);
2060
2061         if (!config)
2062                 return false;
2063         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2064
2065         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2066                 kfree(config);
2067                 return false;
2068         } else {
2069                 generic = dal_gpio_service_create_generic_mux(
2070                         gpio_service,
2071                         pin_info.offset,
2072                         pin_info.mask);
2073         }
2074
2075         if (!generic) {
2076                 kfree(config);
2077                 return false;
2078         }
2079
2080         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2081
2082         config->enable_output_from_mux = enable;
2083         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2084
2085         if (gpio_result == GPIO_RESULT_OK)
2086                 gpio_result = dal_mux_setup_config(generic, config);
2087
2088         if (gpio_result == GPIO_RESULT_OK) {
2089                 dal_gpio_close(generic);
2090                 dal_gpio_destroy_generic_mux(&generic);
2091                 kfree(config);
2092                 return true;
2093         } else {
2094                 dal_gpio_close(generic);
2095                 dal_gpio_destroy_generic_mux(&generic);
2096                 kfree(config);
2097                 return false;
2098         }
2099 }
2100
2101 static bool is_surface_in_context(
2102                 const struct dc_state *context,
2103                 const struct dc_plane_state *plane_state)
2104 {
2105         int j;
2106
2107         for (j = 0; j < MAX_PIPES; j++) {
2108                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2109
2110                 if (plane_state == pipe_ctx->plane_state) {
2111                         return true;
2112                 }
2113         }
2114
2115         return false;
2116 }
2117
2118 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2119 {
2120         union surface_update_flags *update_flags = &u->surface->update_flags;
2121         enum surface_update_type update_type = UPDATE_TYPE_FAST;
2122
2123         if (!u->plane_info)
2124                 return UPDATE_TYPE_FAST;
2125
2126         if (u->plane_info->color_space != u->surface->color_space) {
2127                 update_flags->bits.color_space_change = 1;
2128                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2129         }
2130
2131         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2132                 update_flags->bits.horizontal_mirror_change = 1;
2133                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2134         }
2135
2136         if (u->plane_info->rotation != u->surface->rotation) {
2137                 update_flags->bits.rotation_change = 1;
2138                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2139         }
2140
2141         if (u->plane_info->format != u->surface->format) {
2142                 update_flags->bits.pixel_format_change = 1;
2143                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2144         }
2145
2146         if (u->plane_info->stereo_format != u->surface->stereo_format) {
2147                 update_flags->bits.stereo_format_change = 1;
2148                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2149         }
2150
2151         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2152                 update_flags->bits.per_pixel_alpha_change = 1;
2153                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2154         }
2155
2156         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2157                 update_flags->bits.global_alpha_change = 1;
2158                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2159         }
2160
2161         if (u->plane_info->dcc.enable != u->surface->dcc.enable
2162                         || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2163                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2164                 /* During DCC on/off, stutter period is calculated before
2165                  * DCC has fully transitioned. This results in incorrect
2166                  * stutter period calculation. Triggering a full update will
2167                  * recalculate stutter period.
2168                  */
2169                 update_flags->bits.dcc_change = 1;
2170                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2171         }
2172
2173         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2174                         resource_pixel_format_to_bpp(u->surface->format)) {
2175                 /* different bytes per element will require full bandwidth
2176                  * and DML calculation
2177                  */
2178                 update_flags->bits.bpp_change = 1;
2179                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2180         }
2181
2182         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2183                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2184                 update_flags->bits.plane_size_change = 1;
2185                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2186         }
2187
2188
2189         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2190                         sizeof(union dc_tiling_info)) != 0) {
2191                 update_flags->bits.swizzle_change = 1;
2192                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2193
2194                 /* todo: below are HW dependent, we should add a hook to
2195                  * DCE/N resource and validated there.
2196                  */
2197                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2198                         /* swizzled mode requires RQ to be setup properly,
2199                          * thus need to run DML to calculate RQ settings
2200                          */
2201                         update_flags->bits.bandwidth_change = 1;
2202                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2203                 }
2204         }
2205
2206         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2207         return update_type;
2208 }
2209
2210 static enum surface_update_type get_scaling_info_update_type(
2211                 const struct dc_surface_update *u)
2212 {
2213         union surface_update_flags *update_flags = &u->surface->update_flags;
2214
2215         if (!u->scaling_info)
2216                 return UPDATE_TYPE_FAST;
2217
2218         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
2219                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
2220                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2221                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2222                         || u->scaling_info->scaling_quality.integer_scaling !=
2223                                 u->surface->scaling_quality.integer_scaling
2224                         ) {
2225                 update_flags->bits.scaling_change = 1;
2226
2227                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2228                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2229                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2230                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2231                         /* Making dst rect smaller requires a bandwidth change */
2232                         update_flags->bits.bandwidth_change = 1;
2233         }
2234
2235         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2236                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2237
2238                 update_flags->bits.scaling_change = 1;
2239                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2240                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2241                         /* Making src rect bigger requires a bandwidth change */
2242                         update_flags->bits.clock_change = 1;
2243         }
2244
2245         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2246                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2247                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2248                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2249                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2250                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2251                 update_flags->bits.position_change = 1;
2252
2253         if (update_flags->bits.clock_change
2254                         || update_flags->bits.bandwidth_change
2255                         || update_flags->bits.scaling_change)
2256                 return UPDATE_TYPE_FULL;
2257
2258         if (update_flags->bits.position_change)
2259                 return UPDATE_TYPE_MED;
2260
2261         return UPDATE_TYPE_FAST;
2262 }
2263
2264 static enum surface_update_type det_surface_update(const struct dc *dc,
2265                 const struct dc_surface_update *u)
2266 {
2267         const struct dc_state *context = dc->current_state;
2268         enum surface_update_type type;
2269         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2270         union surface_update_flags *update_flags = &u->surface->update_flags;
2271
2272         if (u->flip_addr)
2273                 update_flags->bits.addr_update = 1;
2274
2275         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2276                 update_flags->raw = 0xFFFFFFFF;
2277                 return UPDATE_TYPE_FULL;
2278         }
2279
2280         update_flags->raw = 0; // Reset all flags
2281
2282         type = get_plane_info_update_type(u);
2283         elevate_update_type(&overall_type, type);
2284
2285         type = get_scaling_info_update_type(u);
2286         elevate_update_type(&overall_type, type);
2287
2288         if (u->flip_addr)
2289                 update_flags->bits.addr_update = 1;
2290
2291         if (u->in_transfer_func)
2292                 update_flags->bits.in_transfer_func_change = 1;
2293
2294         if (u->input_csc_color_matrix)
2295                 update_flags->bits.input_csc_change = 1;
2296
2297         if (u->coeff_reduction_factor)
2298                 update_flags->bits.coeff_reduction_change = 1;
2299
2300         if (u->gamut_remap_matrix)
2301                 update_flags->bits.gamut_remap_change = 1;
2302
2303         if (u->gamma) {
2304                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2305
2306                 if (u->plane_info)
2307                         format = u->plane_info->format;
2308                 else if (u->surface)
2309                         format = u->surface->format;
2310
2311                 if (dce_use_lut(format))
2312                         update_flags->bits.gamma_change = 1;
2313         }
2314
2315         if (u->lut3d_func || u->func_shaper)
2316                 update_flags->bits.lut_3d = 1;
2317
2318         if (u->hdr_mult.value)
2319                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2320                         update_flags->bits.hdr_mult = 1;
2321                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2322                 }
2323
2324         if (update_flags->bits.in_transfer_func_change) {
2325                 type = UPDATE_TYPE_MED;
2326                 elevate_update_type(&overall_type, type);
2327         }
2328
2329         if (update_flags->bits.input_csc_change
2330                         || update_flags->bits.coeff_reduction_change
2331                         || update_flags->bits.lut_3d
2332                         || update_flags->bits.gamma_change
2333                         || update_flags->bits.gamut_remap_change) {
2334                 type = UPDATE_TYPE_FULL;
2335                 elevate_update_type(&overall_type, type);
2336         }
2337
2338         return overall_type;
2339 }
2340
2341 static enum surface_update_type check_update_surfaces_for_stream(
2342                 struct dc *dc,
2343                 struct dc_surface_update *updates,
2344                 int surface_count,
2345                 struct dc_stream_update *stream_update,
2346                 const struct dc_stream_status *stream_status)
2347 {
2348         int i;
2349         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2350
2351 #if defined(CONFIG_DRM_AMD_DC_DCN)
2352         if (dc->idle_optimizations_allowed)
2353                 overall_type = UPDATE_TYPE_FULL;
2354
2355 #endif
2356         if (stream_status == NULL || stream_status->plane_count != surface_count)
2357                 overall_type = UPDATE_TYPE_FULL;
2358
2359         if (stream_update && stream_update->pending_test_pattern) {
2360                 overall_type = UPDATE_TYPE_FULL;
2361         }
2362
2363         /* some stream updates require passive update */
2364         if (stream_update) {
2365                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2366
2367                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2368                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2369                         stream_update->integer_scaling_update)
2370                         su_flags->bits.scaling = 1;
2371
2372                 if (stream_update->out_transfer_func)
2373                         su_flags->bits.out_tf = 1;
2374
2375                 if (stream_update->abm_level)
2376                         su_flags->bits.abm_level = 1;
2377
2378                 if (stream_update->dpms_off)
2379                         su_flags->bits.dpms_off = 1;
2380
2381                 if (stream_update->gamut_remap)
2382                         su_flags->bits.gamut_remap = 1;
2383
2384                 if (stream_update->wb_update)
2385                         su_flags->bits.wb_update = 1;
2386
2387                 if (stream_update->dsc_config)
2388                         su_flags->bits.dsc_changed = 1;
2389
2390                 if (stream_update->mst_bw_update)
2391                         su_flags->bits.mst_bw = 1;
2392                 if (stream_update->crtc_timing_adjust && dc_extended_blank_supported(dc))
2393                         su_flags->bits.crtc_timing_adjust = 1;
2394
2395                 if (su_flags->raw != 0)
2396                         overall_type = UPDATE_TYPE_FULL;
2397
2398                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2399                         su_flags->bits.out_csc = 1;
2400         }
2401
2402         for (i = 0 ; i < surface_count; i++) {
2403                 enum surface_update_type type =
2404                                 det_surface_update(dc, &updates[i]);
2405
2406                 elevate_update_type(&overall_type, type);
2407         }
2408
2409         return overall_type;
2410 }
2411
2412 /*
2413  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2414  *
2415  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2416  */
2417 enum surface_update_type dc_check_update_surfaces_for_stream(
2418                 struct dc *dc,
2419                 struct dc_surface_update *updates,
2420                 int surface_count,
2421                 struct dc_stream_update *stream_update,
2422                 const struct dc_stream_status *stream_status)
2423 {
2424         int i;
2425         enum surface_update_type type;
2426
2427         if (stream_update)
2428                 stream_update->stream->update_flags.raw = 0;
2429         for (i = 0; i < surface_count; i++)
2430                 updates[i].surface->update_flags.raw = 0;
2431
2432         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2433         if (type == UPDATE_TYPE_FULL) {
2434                 if (stream_update) {
2435                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2436                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2437                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2438                 }
2439                 for (i = 0; i < surface_count; i++)
2440                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2441         }
2442
2443         if (type == UPDATE_TYPE_FAST) {
2444                 // If there's an available clock comparator, we use that.
2445                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2446                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2447                                 dc->optimized_required = true;
2448                 // Else we fallback to mem compare.
2449                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2450                         dc->optimized_required = true;
2451                 }
2452
2453                 dc->optimized_required |= dc->wm_optimized_required;
2454         }
2455
2456         return type;
2457 }
2458
2459 static struct dc_stream_status *stream_get_status(
2460         struct dc_state *ctx,
2461         struct dc_stream_state *stream)
2462 {
2463         uint8_t i;
2464
2465         for (i = 0; i < ctx->stream_count; i++) {
2466                 if (stream == ctx->streams[i]) {
2467                         return &ctx->stream_status[i];
2468                 }
2469         }
2470
2471         return NULL;
2472 }
2473
2474 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2475
2476 static void copy_surface_update_to_plane(
2477                 struct dc_plane_state *surface,
2478                 struct dc_surface_update *srf_update)
2479 {
2480         if (srf_update->flip_addr) {
2481                 surface->address = srf_update->flip_addr->address;
2482                 surface->flip_immediate =
2483                         srf_update->flip_addr->flip_immediate;
2484                 surface->time.time_elapsed_in_us[surface->time.index] =
2485                         srf_update->flip_addr->flip_timestamp_in_us -
2486                                 surface->time.prev_update_time_in_us;
2487                 surface->time.prev_update_time_in_us =
2488                         srf_update->flip_addr->flip_timestamp_in_us;
2489                 surface->time.index++;
2490                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2491                         surface->time.index = 0;
2492
2493                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2494         }
2495
2496         if (srf_update->scaling_info) {
2497                 surface->scaling_quality =
2498                                 srf_update->scaling_info->scaling_quality;
2499                 surface->dst_rect =
2500                                 srf_update->scaling_info->dst_rect;
2501                 surface->src_rect =
2502                                 srf_update->scaling_info->src_rect;
2503                 surface->clip_rect =
2504                                 srf_update->scaling_info->clip_rect;
2505         }
2506
2507         if (srf_update->plane_info) {
2508                 surface->color_space =
2509                                 srf_update->plane_info->color_space;
2510                 surface->format =
2511                                 srf_update->plane_info->format;
2512                 surface->plane_size =
2513                                 srf_update->plane_info->plane_size;
2514                 surface->rotation =
2515                                 srf_update->plane_info->rotation;
2516                 surface->horizontal_mirror =
2517                                 srf_update->plane_info->horizontal_mirror;
2518                 surface->stereo_format =
2519                                 srf_update->plane_info->stereo_format;
2520                 surface->tiling_info =
2521                                 srf_update->plane_info->tiling_info;
2522                 surface->visible =
2523                                 srf_update->plane_info->visible;
2524                 surface->per_pixel_alpha =
2525                                 srf_update->plane_info->per_pixel_alpha;
2526                 surface->global_alpha =
2527                                 srf_update->plane_info->global_alpha;
2528                 surface->global_alpha_value =
2529                                 srf_update->plane_info->global_alpha_value;
2530                 surface->dcc =
2531                                 srf_update->plane_info->dcc;
2532                 surface->layer_index =
2533                                 srf_update->plane_info->layer_index;
2534         }
2535
2536         if (srf_update->gamma &&
2537                         (surface->gamma_correction !=
2538                                         srf_update->gamma)) {
2539                 memcpy(&surface->gamma_correction->entries,
2540                         &srf_update->gamma->entries,
2541                         sizeof(struct dc_gamma_entries));
2542                 surface->gamma_correction->is_identity =
2543                         srf_update->gamma->is_identity;
2544                 surface->gamma_correction->num_entries =
2545                         srf_update->gamma->num_entries;
2546                 surface->gamma_correction->type =
2547                         srf_update->gamma->type;
2548         }
2549
2550         if (srf_update->in_transfer_func &&
2551                         (surface->in_transfer_func !=
2552                                 srf_update->in_transfer_func)) {
2553                 surface->in_transfer_func->sdr_ref_white_level =
2554                         srf_update->in_transfer_func->sdr_ref_white_level;
2555                 surface->in_transfer_func->tf =
2556                         srf_update->in_transfer_func->tf;
2557                 surface->in_transfer_func->type =
2558                         srf_update->in_transfer_func->type;
2559                 memcpy(&surface->in_transfer_func->tf_pts,
2560                         &srf_update->in_transfer_func->tf_pts,
2561                         sizeof(struct dc_transfer_func_distributed_points));
2562         }
2563
2564         if (srf_update->func_shaper &&
2565                         (surface->in_shaper_func !=
2566                         srf_update->func_shaper))
2567                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2568                 sizeof(*surface->in_shaper_func));
2569
2570         if (srf_update->lut3d_func &&
2571                         (surface->lut3d_func !=
2572                         srf_update->lut3d_func))
2573                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2574                 sizeof(*surface->lut3d_func));
2575
2576         if (srf_update->hdr_mult.value)
2577                 surface->hdr_mult =
2578                                 srf_update->hdr_mult;
2579
2580         if (srf_update->blend_tf &&
2581                         (surface->blend_tf !=
2582                         srf_update->blend_tf))
2583                 memcpy(surface->blend_tf, srf_update->blend_tf,
2584                 sizeof(*surface->blend_tf));
2585
2586         if (srf_update->input_csc_color_matrix)
2587                 surface->input_csc_color_matrix =
2588                         *srf_update->input_csc_color_matrix;
2589
2590         if (srf_update->coeff_reduction_factor)
2591                 surface->coeff_reduction_factor =
2592                         *srf_update->coeff_reduction_factor;
2593
2594         if (srf_update->gamut_remap_matrix)
2595                 surface->gamut_remap_matrix =
2596                         *srf_update->gamut_remap_matrix;
2597 }
2598
2599 static void copy_stream_update_to_stream(struct dc *dc,
2600                                          struct dc_state *context,
2601                                          struct dc_stream_state *stream,
2602                                          struct dc_stream_update *update)
2603 {
2604         struct dc_context *dc_ctx = dc->ctx;
2605
2606         if (update == NULL || stream == NULL)
2607                 return;
2608
2609         if (update->src.height && update->src.width)
2610                 stream->src = update->src;
2611
2612         if (update->dst.height && update->dst.width)
2613                 stream->dst = update->dst;
2614
2615         if (update->out_transfer_func &&
2616             stream->out_transfer_func != update->out_transfer_func) {
2617                 stream->out_transfer_func->sdr_ref_white_level =
2618                         update->out_transfer_func->sdr_ref_white_level;
2619                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2620                 stream->out_transfer_func->type =
2621                         update->out_transfer_func->type;
2622                 memcpy(&stream->out_transfer_func->tf_pts,
2623                        &update->out_transfer_func->tf_pts,
2624                        sizeof(struct dc_transfer_func_distributed_points));
2625         }
2626
2627         if (update->hdr_static_metadata)
2628                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2629
2630         if (update->abm_level)
2631                 stream->abm_level = *update->abm_level;
2632
2633         if (update->periodic_interrupt0)
2634                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2635
2636         if (update->periodic_interrupt1)
2637                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2638
2639         if (update->gamut_remap)
2640                 stream->gamut_remap_matrix = *update->gamut_remap;
2641
2642         /* Note: this being updated after mode set is currently not a use case
2643          * however if it arises OCSC would need to be reprogrammed at the
2644          * minimum
2645          */
2646         if (update->output_color_space)
2647                 stream->output_color_space = *update->output_color_space;
2648
2649         if (update->output_csc_transform)
2650                 stream->csc_color_matrix = *update->output_csc_transform;
2651
2652         if (update->vrr_infopacket)
2653                 stream->vrr_infopacket = *update->vrr_infopacket;
2654
2655         if (update->crtc_timing_adjust)
2656                 stream->adjust = *update->crtc_timing_adjust;
2657
2658         if (update->dpms_off)
2659                 stream->dpms_off = *update->dpms_off;
2660
2661         if (update->vsc_infopacket)
2662                 stream->vsc_infopacket = *update->vsc_infopacket;
2663
2664         if (update->vsp_infopacket)
2665                 stream->vsp_infopacket = *update->vsp_infopacket;
2666
2667         if (update->dither_option)
2668                 stream->dither_option = *update->dither_option;
2669
2670         if (update->pending_test_pattern)
2671                 stream->test_pattern = *update->pending_test_pattern;
2672         /* update current stream with writeback info */
2673         if (update->wb_update) {
2674                 int i;
2675
2676                 stream->num_wb_info = update->wb_update->num_wb_info;
2677                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2678                 for (i = 0; i < stream->num_wb_info; i++)
2679                         stream->writeback_info[i] =
2680                                 update->wb_update->writeback_info[i];
2681         }
2682         if (update->dsc_config) {
2683                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2684                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2685                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2686                                        update->dsc_config->num_slices_v != 0);
2687
2688                 /* Use temporarry context for validating new DSC config */
2689                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2690
2691                 if (dsc_validate_context) {
2692                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2693
2694                         stream->timing.dsc_cfg = *update->dsc_config;
2695                         stream->timing.flags.DSC = enable_dsc;
2696                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2697                                 stream->timing.dsc_cfg = old_dsc_cfg;
2698                                 stream->timing.flags.DSC = old_dsc_enabled;
2699                                 update->dsc_config = NULL;
2700                         }
2701
2702                         dc_release_state(dsc_validate_context);
2703                 } else {
2704                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2705                         update->dsc_config = NULL;
2706                 }
2707         }
2708 }
2709
2710 static void commit_planes_do_stream_update(struct dc *dc,
2711                 struct dc_stream_state *stream,
2712                 struct dc_stream_update *stream_update,
2713                 enum surface_update_type update_type,
2714                 struct dc_state *context)
2715 {
2716         int j;
2717
2718         // Stream updates
2719         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2720                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2721
2722                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2723
2724                         if (stream_update->periodic_interrupt0 &&
2725                                         dc->hwss.setup_periodic_interrupt)
2726                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2727
2728                         if (stream_update->periodic_interrupt1 &&
2729                                         dc->hwss.setup_periodic_interrupt)
2730                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2731
2732                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2733                                         stream_update->vrr_infopacket ||
2734                                         stream_update->vsc_infopacket ||
2735                                         stream_update->vsp_infopacket) {
2736                                 resource_build_info_frame(pipe_ctx);
2737                                 dc->hwss.update_info_frame(pipe_ctx);
2738
2739                                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2740                                         dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
2741                         }
2742
2743                         if (stream_update->hdr_static_metadata &&
2744                                         stream->use_dynamic_meta &&
2745                                         dc->hwss.set_dmdata_attributes &&
2746                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2747                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2748
2749                         if (stream_update->gamut_remap)
2750                                 dc_stream_set_gamut_remap(dc, stream);
2751
2752                         if (stream_update->output_csc_transform)
2753                                 dc_stream_program_csc_matrix(dc, stream);
2754
2755                         if (stream_update->dither_option) {
2756                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2757                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2758                                                                         &pipe_ctx->stream->bit_depth_params);
2759                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2760                                                 &stream->bit_depth_params,
2761                                                 &stream->clamping);
2762                                 while (odm_pipe) {
2763                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2764                                                         &stream->bit_depth_params,
2765                                                         &stream->clamping);
2766                                         odm_pipe = odm_pipe->next_odm_pipe;
2767                                 }
2768                         }
2769
2770
2771                         /* Full fe update*/
2772                         if (update_type == UPDATE_TYPE_FAST)
2773                                 continue;
2774
2775                         if (stream_update->dsc_config)
2776                                 dp_update_dsc_config(pipe_ctx);
2777
2778                         if (stream_update->mst_bw_update) {
2779                                 if (stream_update->mst_bw_update->is_increase)
2780                                         dc_link_increase_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw);
2781                                 else
2782                                         dc_link_reduce_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw);
2783                         }
2784
2785                         if (stream_update->pending_test_pattern) {
2786                                 dc_link_dp_set_test_pattern(stream->link,
2787                                         stream->test_pattern.type,
2788                                         stream->test_pattern.color_space,
2789                                         stream->test_pattern.p_link_settings,
2790                                         stream->test_pattern.p_custom_pattern,
2791                                         stream->test_pattern.cust_pattern_size);
2792                         }
2793
2794                         if (stream_update->dpms_off) {
2795                                 if (*stream_update->dpms_off) {
2796                                         core_link_disable_stream(pipe_ctx);
2797                                         /* for dpms, keep acquired resources*/
2798                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2799                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2800
2801                                         dc->optimized_required = true;
2802
2803                                 } else {
2804                                         if (get_seamless_boot_stream_count(context) == 0)
2805                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2806
2807                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2808                                 }
2809                         }
2810
2811                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2812                                 bool should_program_abm = true;
2813
2814                                 // if otg funcs defined check if blanked before programming
2815                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2816                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2817                                                 should_program_abm = false;
2818
2819                                 if (should_program_abm) {
2820                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2821                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2822                                         } else {
2823                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2824                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2825                                         }
2826                                 }
2827                         }
2828                 }
2829         }
2830 }
2831
2832 static void commit_planes_for_stream(struct dc *dc,
2833                 struct dc_surface_update *srf_updates,
2834                 int surface_count,
2835                 struct dc_stream_state *stream,
2836                 struct dc_stream_update *stream_update,
2837                 enum surface_update_type update_type,
2838                 struct dc_state *context)
2839 {
2840         int i, j;
2841         struct pipe_ctx *top_pipe_to_program = NULL;
2842         bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
2843
2844 #if defined(CONFIG_DRM_AMD_DC_DCN)
2845         dc_z10_restore(dc);
2846 #endif
2847
2848         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2849                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2850                  * first flip. After first flip, optimization is required to lower
2851                  * bandwidth. Important to note that it is expected UEFI will
2852                  * only light up a single display on POST, therefore we only expect
2853                  * one stream with seamless boot flag set.
2854                  */
2855                 if (stream->apply_seamless_boot_optimization) {
2856                         stream->apply_seamless_boot_optimization = false;
2857
2858                         if (get_seamless_boot_stream_count(context) == 0)
2859                                 dc->optimized_required = true;
2860                 }
2861         }
2862
2863         if (update_type == UPDATE_TYPE_FULL) {
2864 #if defined(CONFIG_DRM_AMD_DC_DCN)
2865                 dc_allow_idle_optimizations(dc, false);
2866
2867 #endif
2868                 if (get_seamless_boot_stream_count(context) == 0)
2869                         dc->hwss.prepare_bandwidth(dc, context);
2870
2871                 context_clock_trace(dc, context);
2872         }
2873
2874         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2875                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2876
2877                 if (!pipe_ctx->top_pipe &&
2878                         !pipe_ctx->prev_odm_pipe &&
2879                         pipe_ctx->stream &&
2880                         pipe_ctx->stream == stream) {
2881                         top_pipe_to_program = pipe_ctx;
2882                 }
2883         }
2884
2885 #ifdef CONFIG_DRM_AMD_DC_DCN
2886         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2887                 struct pipe_ctx *mpcc_pipe;
2888                 struct pipe_ctx *odm_pipe;
2889
2890                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2891                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2892                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2893         }
2894 #endif
2895
2896         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2897                 if (top_pipe_to_program &&
2898                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2899                         if (should_use_dmub_lock(stream->link)) {
2900                                 union dmub_hw_lock_flags hw_locks = { 0 };
2901                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2902
2903                                 hw_locks.bits.lock_dig = 1;
2904                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2905
2906                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2907                                                         true,
2908                                                         &hw_locks,
2909                                                         &inst_flags);
2910                         } else
2911                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2912                                                 top_pipe_to_program->stream_res.tg);
2913                 }
2914
2915         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
2916                 dc->hwss.interdependent_update_lock(dc, context, true);
2917         else
2918                 /* Lock the top pipe while updating plane addrs, since freesync requires
2919                  *  plane addr update event triggers to be synchronized.
2920                  *  top_pipe_to_program is expected to never be NULL
2921                  */
2922                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2923
2924         // Stream updates
2925         if (stream_update)
2926                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2927
2928         if (surface_count == 0) {
2929                 /*
2930                  * In case of turning off screen, no need to program front end a second time.
2931                  * just return after program blank.
2932                  */
2933                 if (dc->hwss.apply_ctx_for_surface)
2934                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2935                 if (dc->hwss.program_front_end_for_ctx)
2936                         dc->hwss.program_front_end_for_ctx(dc, context);
2937
2938                 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
2939                         dc->hwss.interdependent_update_lock(dc, context, false);
2940                 else
2941                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2942                 dc->hwss.post_unlock_program_front_end(dc, context);
2943                 return;
2944         }
2945
2946         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2947                 for (i = 0; i < surface_count; i++) {
2948                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2949                         /*set logical flag for lock/unlock use*/
2950                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2951                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2952                                 if (!pipe_ctx->plane_state)
2953                                         continue;
2954                                 if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
2955                                         continue;
2956                                 pipe_ctx->plane_state->triplebuffer_flips = false;
2957                                 if (update_type == UPDATE_TYPE_FAST &&
2958                                         dc->hwss.program_triplebuffer != NULL &&
2959                                         !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2960                                                 /*triple buffer for VUpdate  only*/
2961                                                 pipe_ctx->plane_state->triplebuffer_flips = true;
2962                                 }
2963                         }
2964                         if (update_type == UPDATE_TYPE_FULL) {
2965                                 /* force vsync flip when reconfiguring pipes to prevent underflow */
2966                                 plane_state->flip_immediate = false;
2967                         }
2968                 }
2969         }
2970
2971         // Update Type FULL, Surface updates
2972         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2973                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2974
2975                 if (!pipe_ctx->top_pipe &&
2976                         !pipe_ctx->prev_odm_pipe &&
2977                         should_update_pipe_for_stream(context, pipe_ctx, stream)) {
2978                         struct dc_stream_status *stream_status = NULL;
2979
2980                         if (!pipe_ctx->plane_state)
2981                                 continue;
2982
2983                         /* Full fe update*/
2984                         if (update_type == UPDATE_TYPE_FAST)
2985                                 continue;
2986
2987                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2988
2989                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2990                                 /*turn off triple buffer for full update*/
2991                                 dc->hwss.program_triplebuffer(
2992                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2993                         }
2994                         stream_status =
2995                                 stream_get_status(context, pipe_ctx->stream);
2996
2997                         if (dc->hwss.apply_ctx_for_surface)
2998                                 dc->hwss.apply_ctx_for_surface(
2999                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
3000                 }
3001         }
3002         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
3003                 dc->hwss.program_front_end_for_ctx(dc, context);
3004 #ifdef CONFIG_DRM_AMD_DC_DCN
3005                 if (dc->debug.validate_dml_output) {
3006                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3007                                 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
3008                                 if (cur_pipe->stream == NULL)
3009                                         continue;
3010
3011                                 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
3012                                                 cur_pipe->plane_res.hubp, dc->ctx,
3013                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
3014                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
3015                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
3016                         }
3017                 }
3018 #endif
3019         }
3020
3021         // Update Type FAST, Surface updates
3022         if (update_type == UPDATE_TYPE_FAST) {
3023                 if (dc->hwss.set_flip_control_gsl)
3024                         for (i = 0; i < surface_count; i++) {
3025                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3026
3027                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3028                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3029
3030                                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3031                                                 continue;
3032
3033                                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3034                                                 continue;
3035
3036                                         // GSL has to be used for flip immediate
3037                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
3038                                                         pipe_ctx->plane_state->flip_immediate);
3039                                 }
3040                         }
3041
3042                 /* Perform requested Updates */
3043                 for (i = 0; i < surface_count; i++) {
3044                         struct dc_plane_state *plane_state = srf_updates[i].surface;
3045
3046                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3047                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3048
3049                                 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3050                                         continue;
3051
3052                                 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3053                                         continue;
3054
3055                                 /*program triple buffer after lock based on flip type*/
3056                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3057                                         /*only enable triplebuffer for  fast_update*/
3058                                         dc->hwss.program_triplebuffer(
3059                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3060                                 }
3061                                 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3062                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
3063                         }
3064                 }
3065
3066         }
3067
3068         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
3069                 dc->hwss.interdependent_update_lock(dc, context, false);
3070         else
3071                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3072
3073         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3074                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3075                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3076                                         top_pipe_to_program->stream_res.tg,
3077                                         CRTC_STATE_VACTIVE);
3078                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3079                                         top_pipe_to_program->stream_res.tg,
3080                                         CRTC_STATE_VBLANK);
3081                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3082                                         top_pipe_to_program->stream_res.tg,
3083                                         CRTC_STATE_VACTIVE);
3084
3085                         if (stream && should_use_dmub_lock(stream->link)) {
3086                                 union dmub_hw_lock_flags hw_locks = { 0 };
3087                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3088
3089                                 hw_locks.bits.lock_dig = 1;
3090                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3091
3092                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3093                                                         false,
3094                                                         &hw_locks,
3095                                                         &inst_flags);
3096                         } else
3097                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
3098                                         top_pipe_to_program->stream_res.tg);
3099                 }
3100
3101         if (update_type != UPDATE_TYPE_FAST)
3102                 dc->hwss.post_unlock_program_front_end(dc, context);
3103
3104         // Fire manual trigger only when bottom plane is flipped
3105         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3106                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3107
3108                 if (!pipe_ctx->plane_state)
3109                         continue;
3110
3111                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
3112                                 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
3113                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
3114                                 pipe_ctx->plane_state->skip_manual_trigger)
3115                         continue;
3116
3117                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
3118                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
3119         }
3120 }
3121
3122 void dc_commit_updates_for_stream(struct dc *dc,
3123                 struct dc_surface_update *srf_updates,
3124                 int surface_count,
3125                 struct dc_stream_state *stream,
3126                 struct dc_stream_update *stream_update,
3127                 struct dc_state *state)
3128 {
3129         const struct dc_stream_status *stream_status;
3130         enum surface_update_type update_type;
3131         struct dc_state *context;
3132         struct dc_context *dc_ctx = dc->ctx;
3133         int i, j;
3134
3135         stream_status = dc_stream_get_status(stream);
3136         context = dc->current_state;
3137
3138         update_type = dc_check_update_surfaces_for_stream(
3139                                 dc, srf_updates, surface_count, stream_update, stream_status);
3140
3141         if (update_type >= update_surface_trace_level)
3142                 update_surface_trace(dc, srf_updates, surface_count);
3143
3144
3145         if (update_type >= UPDATE_TYPE_FULL) {
3146
3147                 /* initialize scratch memory for building context */
3148                 context = dc_create_state(dc);
3149                 if (context == NULL) {
3150                         DC_ERROR("Failed to allocate new validate context!\n");
3151                         return;
3152                 }
3153
3154                 dc_resource_state_copy_construct(state, context);
3155
3156                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3157                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
3158                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3159
3160                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
3161                                 new_pipe->plane_state->force_full_update = true;
3162                 }
3163         } else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {
3164                 /*
3165                  * Previous frame finished and HW is ready for optimization.
3166                  *
3167                  * Only relevant for DCN behavior where we can guarantee the optimization
3168                  * is safe to apply - retain the legacy behavior for DCE.
3169                  */
3170                 dc_post_update_surfaces_to_stream(dc);
3171         }
3172
3173
3174         for (i = 0; i < surface_count; i++) {
3175                 struct dc_plane_state *surface = srf_updates[i].surface;
3176
3177                 copy_surface_update_to_plane(surface, &srf_updates[i]);
3178
3179                 if (update_type >= UPDATE_TYPE_MED) {
3180                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3181                                 struct pipe_ctx *pipe_ctx =
3182                                         &context->res_ctx.pipe_ctx[j];
3183
3184                                 if (pipe_ctx->plane_state != surface)
3185                                         continue;
3186
3187                                 resource_build_scaling_params(pipe_ctx);
3188                         }
3189                 }
3190         }
3191
3192         copy_stream_update_to_stream(dc, context, stream, stream_update);
3193
3194         if (update_type >= UPDATE_TYPE_FULL) {
3195                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3196                         DC_ERROR("Mode validation failed for stream update!\n");
3197                         dc_release_state(context);
3198                         return;
3199                 }
3200         }
3201
3202         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
3203
3204         commit_planes_for_stream(
3205                                 dc,
3206                                 srf_updates,
3207                                 surface_count,
3208                                 stream,
3209                                 stream_update,
3210                                 update_type,
3211                                 context);
3212         /*update current_State*/
3213         if (dc->current_state != context) {
3214
3215                 struct dc_state *old = dc->current_state;
3216
3217                 dc->current_state = context;
3218                 dc_release_state(old);
3219
3220                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3221                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3222
3223                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
3224                                 pipe_ctx->plane_state->force_full_update = false;
3225                 }
3226         }
3227
3228         /* Legacy optimization path for DCE. */
3229         if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
3230                 dc_post_update_surfaces_to_stream(dc);
3231                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
3232         }
3233
3234         return;
3235
3236 }
3237
3238 uint8_t dc_get_current_stream_count(struct dc *dc)
3239 {
3240         return dc->current_state->stream_count;
3241 }
3242
3243 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
3244 {
3245         if (i < dc->current_state->stream_count)
3246                 return dc->current_state->streams[i];
3247         return NULL;
3248 }
3249
3250 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
3251 {
3252         uint8_t i;
3253         struct dc_context *ctx = link->ctx;
3254
3255         for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
3256                 if (ctx->dc->current_state->streams[i]->link == link)
3257                         return ctx->dc->current_state->streams[i];
3258         }
3259
3260         return NULL;
3261 }
3262
3263 enum dc_irq_source dc_interrupt_to_irq_source(
3264                 struct dc *dc,
3265                 uint32_t src_id,
3266                 uint32_t ext_id)
3267 {
3268         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
3269 }
3270
3271 /*
3272  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
3273  */
3274 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
3275 {
3276
3277         if (dc == NULL)
3278                 return false;
3279
3280         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
3281 }
3282
3283 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
3284 {
3285         dal_irq_service_ack(dc->res_pool->irqs, src);
3286 }
3287
3288 void dc_power_down_on_boot(struct dc *dc)
3289 {
3290         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
3291                         dc->hwss.power_down_on_boot)
3292                 dc->hwss.power_down_on_boot(dc);
3293 }
3294
3295 void dc_set_power_state(
3296         struct dc *dc,
3297         enum dc_acpi_cm_power_state power_state)
3298 {
3299         struct kref refcount;
3300         struct display_mode_lib *dml;
3301
3302         if (!dc->current_state)
3303                 return;
3304
3305         switch (power_state) {
3306         case DC_ACPI_CM_POWER_STATE_D0:
3307                 dc_resource_state_construct(dc, dc->current_state);
3308
3309 #if defined(CONFIG_DRM_AMD_DC_DCN)
3310                 dc_z10_restore(dc);
3311 #endif
3312                 if (dc->ctx->dmub_srv)
3313                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
3314
3315                 dc->hwss.init_hw(dc);
3316
3317                 if (dc->hwss.init_sys_ctx != NULL &&
3318                         dc->vm_pa_config.valid) {
3319                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
3320                 }
3321
3322                 break;
3323         default:
3324                 ASSERT(dc->current_state->stream_count == 0);
3325                 /* Zero out the current context so that on resume we start with
3326                  * clean state, and dc hw programming optimizations will not
3327                  * cause any trouble.
3328                  */
3329                 dml = kzalloc(sizeof(struct display_mode_lib),
3330                                 GFP_KERNEL);
3331
3332                 ASSERT(dml);
3333                 if (!dml)
3334                         return;
3335
3336                 /* Preserve refcount */
3337                 refcount = dc->current_state->refcount;
3338                 /* Preserve display mode lib */
3339                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
3340
3341                 dc_resource_state_destruct(dc->current_state);
3342                 memset(dc->current_state, 0,
3343                                 sizeof(*dc->current_state));
3344
3345                 dc->current_state->refcount = refcount;
3346                 dc->current_state->bw_ctx.dml = *dml;
3347
3348                 kfree(dml);
3349
3350                 break;
3351         }
3352 }
3353
3354 void dc_resume(struct dc *dc)
3355 {
3356         uint32_t i;
3357
3358         for (i = 0; i < dc->link_count; i++)
3359                 core_link_resume(dc->links[i]);
3360 }
3361
3362 bool dc_is_dmcu_initialized(struct dc *dc)
3363 {
3364         struct dmcu *dmcu = dc->res_pool->dmcu;
3365
3366         if (dmcu)
3367                 return dmcu->funcs->is_dmcu_initialized(dmcu);
3368         return false;
3369 }
3370
3371 bool dc_is_oem_i2c_device_present(
3372         struct dc *dc,
3373         size_t slave_address)
3374 {
3375         if (dc->res_pool->oem_device)
3376                 return dce_i2c_oem_device_present(
3377                         dc->res_pool,
3378                         dc->res_pool->oem_device,
3379                         slave_address);
3380
3381         return false;
3382 }
3383
3384 bool dc_submit_i2c(
3385                 struct dc *dc,
3386                 uint32_t link_index,
3387                 struct i2c_command *cmd)
3388 {
3389
3390         struct dc_link *link = dc->links[link_index];
3391         struct ddc_service *ddc = link->ddc;
3392         return dce_i2c_submit_command(
3393                 dc->res_pool,
3394                 ddc->ddc_pin,
3395                 cmd);
3396 }
3397
3398 bool dc_submit_i2c_oem(
3399                 struct dc *dc,
3400                 struct i2c_command *cmd)
3401 {
3402         struct ddc_service *ddc = dc->res_pool->oem_device;
3403         return dce_i2c_submit_command(
3404                 dc->res_pool,
3405                 ddc->ddc_pin,
3406                 cmd);
3407 }
3408
3409 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
3410 {
3411         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
3412                 BREAK_TO_DEBUGGER();
3413                 return false;
3414         }
3415
3416         dc_sink_retain(sink);
3417
3418         dc_link->remote_sinks[dc_link->sink_count] = sink;
3419         dc_link->sink_count++;
3420
3421         return true;
3422 }
3423
3424 /*
3425  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
3426  *
3427  * EDID length is in bytes
3428  */
3429 struct dc_sink *dc_link_add_remote_sink(
3430                 struct dc_link *link,
3431                 const uint8_t *edid,
3432                 int len,
3433                 struct dc_sink_init_data *init_data)
3434 {
3435         struct dc_sink *dc_sink;
3436         enum dc_edid_status edid_status;
3437
3438         if (len > DC_MAX_EDID_BUFFER_SIZE) {
3439                 dm_error("Max EDID buffer size breached!\n");
3440                 return NULL;
3441         }
3442
3443         if (!init_data) {
3444                 BREAK_TO_DEBUGGER();
3445                 return NULL;
3446         }
3447
3448         if (!init_data->link) {
3449                 BREAK_TO_DEBUGGER();
3450                 return NULL;
3451         }
3452
3453         dc_sink = dc_sink_create(init_data);
3454
3455         if (!dc_sink)
3456                 return NULL;
3457
3458         memmove(dc_sink->dc_edid.raw_edid, edid, len);
3459         dc_sink->dc_edid.length = len;
3460
3461         if (!link_add_remote_sink_helper(
3462                         link,
3463                         dc_sink))
3464                 goto fail_add_sink;
3465
3466         edid_status = dm_helpers_parse_edid_caps(
3467                         link,
3468                         &dc_sink->dc_edid,
3469                         &dc_sink->edid_caps);
3470
3471         /*
3472          * Treat device as no EDID device if EDID
3473          * parsing fails
3474          */
3475         if (edid_status != EDID_OK) {
3476                 dc_sink->dc_edid.length = 0;
3477                 dm_error("Bad EDID, status%d!\n", edid_status);
3478         }
3479
3480         return dc_sink;
3481
3482 fail_add_sink:
3483         dc_sink_release(dc_sink);
3484         return NULL;
3485 }
3486
3487 /*
3488  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3489  *
3490  * Note that this just removes the struct dc_sink - it doesn't
3491  * program hardware or alter other members of dc_link
3492  */
3493 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3494 {
3495         int i;
3496
3497         if (!link->sink_count) {
3498                 BREAK_TO_DEBUGGER();
3499                 return;
3500         }
3501
3502         for (i = 0; i < link->sink_count; i++) {
3503                 if (link->remote_sinks[i] == sink) {
3504                         dc_sink_release(sink);
3505                         link->remote_sinks[i] = NULL;
3506
3507                         /* shrink array to remove empty place */
3508                         while (i < link->sink_count - 1) {
3509                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3510                                 i++;
3511                         }
3512                         link->remote_sinks[i] = NULL;
3513                         link->sink_count--;
3514                         return;
3515                 }
3516         }
3517 }
3518
3519 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3520 {
3521         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3522         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3523         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3524         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3525         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3526         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3527         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3528         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3529         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3530 }
3531 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3532 {
3533         if (dc->hwss.set_clock)
3534                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3535         return DC_ERROR_UNEXPECTED;
3536 }
3537 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3538 {
3539         if (dc->hwss.get_clock)
3540                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3541 }
3542
3543 /* enable/disable eDP PSR without specify stream for eDP */
3544 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3545 {
3546         int i;
3547         bool allow_active;
3548
3549         for (i = 0; i < dc->current_state->stream_count ; i++) {
3550                 struct dc_link *link;
3551                 struct dc_stream_state *stream = dc->current_state->streams[i];
3552
3553                 link = stream->link;
3554                 if (!link)
3555                         continue;
3556
3557                 if (link->psr_settings.psr_feature_enabled) {
3558                         if (enable && !link->psr_settings.psr_allow_active) {
3559                                 allow_active = true;
3560                                 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
3561                                         return false;
3562                         } else if (!enable && link->psr_settings.psr_allow_active) {
3563                                 allow_active = false;
3564                                 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
3565                                         return false;
3566                         }
3567                 }
3568         }
3569
3570         return true;
3571 }
3572
3573 #if defined(CONFIG_DRM_AMD_DC_DCN)
3574
3575 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3576 {
3577         if (dc->debug.disable_idle_power_optimizations)
3578                 return;
3579
3580         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
3581                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
3582                         return;
3583
3584         if (allow == dc->idle_optimizations_allowed)
3585                 return;
3586
3587         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3588                 dc->idle_optimizations_allowed = allow;
3589 }
3590
3591 /*
3592  * blank all streams, and set min and max memory clock to
3593  * lowest and highest DPM level, respectively
3594  */
3595 void dc_unlock_memory_clock_frequency(struct dc *dc)
3596 {
3597         unsigned int i;
3598
3599         for (i = 0; i < MAX_PIPES; i++)
3600                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3601                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3602
3603         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3604         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3605 }
3606
3607 /*
3608  * set min memory clock to the min required for current mode,
3609  * max to maxDPM, and unblank streams
3610  */
3611 void dc_lock_memory_clock_frequency(struct dc *dc)
3612 {
3613         unsigned int i;
3614
3615         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3616         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3617         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3618
3619         for (i = 0; i < MAX_PIPES; i++)
3620                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3621                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3622 }
3623
3624 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
3625 {
3626         struct dc_state *context = dc->current_state;
3627         struct hubp *hubp;
3628         struct pipe_ctx *pipe;
3629         int i;
3630
3631         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3632                 pipe = &context->res_ctx.pipe_ctx[i];
3633
3634                 if (pipe->stream != NULL) {
3635                         dc->hwss.disable_pixel_data(dc, pipe, true);
3636
3637                         // wait for double buffer
3638                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
3639                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
3640                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
3641
3642                         hubp = pipe->plane_res.hubp;
3643                         hubp->funcs->set_blank_regs(hubp, true);
3644                 }
3645         }
3646
3647         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
3648         dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
3649
3650         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3651                 pipe = &context->res_ctx.pipe_ctx[i];
3652
3653                 if (pipe->stream != NULL) {
3654                         dc->hwss.disable_pixel_data(dc, pipe, false);
3655
3656                         hubp = pipe->plane_res.hubp;
3657                         hubp->funcs->set_blank_regs(hubp, false);
3658                 }
3659         }
3660 }
3661
3662
3663 /**
3664  * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
3665  * @dc: pointer to dc of the dm calling this
3666  * @enable: True = transition to DC mode, false = transition back to AC mode
3667  *
3668  * Some SoCs define additional clock limits when in DC mode, DM should
3669  * invoke this function when the platform undergoes a power source transition
3670  * so DC can apply/unapply the limit. This interface may be disruptive to
3671  * the onscreen content.
3672  *
3673  * Context: Triggered by OS through DM interface, or manually by escape calls.
3674  * Need to hold a dclock when doing so.
3675  *
3676  * Return: none (void function)
3677  *
3678  */
3679 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
3680 {
3681         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
3682         unsigned int softMax, maxDPM, funcMin;
3683         bool p_state_change_support;
3684
3685         if (!ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
3686                 return;
3687
3688         softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
3689         maxDPM = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz;
3690         funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
3691         p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
3692
3693         if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
3694                 if (p_state_change_support) {
3695                         if (funcMin <= softMax)
3696                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
3697                         // else: No-Op
3698                 } else {
3699                         if (funcMin <= softMax)
3700                                 blank_and_force_memclk(dc, true, softMax);
3701                         // else: No-Op
3702                 }
3703         } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
3704                 if (p_state_change_support) {
3705                         if (funcMin <= softMax)
3706                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
3707                         // else: No-Op
3708                 } else {
3709                         if (funcMin <= softMax)
3710                                 blank_and_force_memclk(dc, true, maxDPM);
3711                         // else: No-Op
3712                 }
3713         }
3714         dc->clk_mgr->dc_mode_softmax_enabled = enable;
3715 }
3716 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
3717                 struct dc_cursor_attributes *cursor_attr)
3718 {
3719         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
3720                 return true;
3721         return false;
3722 }
3723
3724 /* cleanup on driver unload */
3725 void dc_hardware_release(struct dc *dc)
3726 {
3727         if (dc->hwss.hardware_release)
3728                 dc->hwss.hardware_release(dc);
3729 }
3730 #endif
3731
3732 /*
3733  *****************************************************************************
3734  * Function: dc_is_dmub_outbox_supported -
3735  *
3736  * @brief
3737  *      Checks whether DMUB FW supports outbox notifications, if supported
3738  *              DM should register outbox interrupt prior to actually enabling interrupts
3739  *              via dc_enable_dmub_outbox
3740  *
3741  *  @param
3742  *              [in] dc: dc structure
3743  *
3744  *  @return
3745  *              True if DMUB FW supports outbox notifications, False otherwise
3746  *****************************************************************************
3747  */
3748 bool dc_is_dmub_outbox_supported(struct dc *dc)
3749 {
3750 #if defined(CONFIG_DRM_AMD_DC_DCN)
3751         /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */
3752         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
3753             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
3754             !dc->debug.dpia_debug.bits.disable_dpia)
3755                 return true;
3756 #endif
3757         /* dmub aux needs dmub notifications to be enabled */
3758         return dc->debug.enable_dmub_aux_for_legacy_ddc;
3759 }
3760
3761 /*
3762  *****************************************************************************
3763  *  Function: dc_enable_dmub_notifications
3764  *
3765  *  @brief
3766  *              Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
3767  *              notifications. All DMs shall switch to dc_is_dmub_outbox_supported.
3768  *              This API shall be removed after switching.
3769  *
3770  *  @param
3771  *              [in] dc: dc structure
3772  *
3773  *  @return
3774  *              True if DMUB FW supports outbox notifications, False otherwise
3775  *****************************************************************************
3776  */
3777 bool dc_enable_dmub_notifications(struct dc *dc)
3778 {
3779         return dc_is_dmub_outbox_supported(dc);
3780 }
3781
3782 /**
3783  *****************************************************************************
3784  *  Function: dc_enable_dmub_outbox
3785  *
3786  *  @brief
3787  *              Enables DMUB unsolicited notifications to x86 via outbox
3788  *
3789  *  @param
3790  *              [in] dc: dc structure
3791  *
3792  *  @return
3793  *              None
3794  *****************************************************************************
3795  */
3796 void dc_enable_dmub_outbox(struct dc *dc)
3797 {
3798         struct dc_context *dc_ctx = dc->ctx;
3799
3800         dmub_enable_outbox_notification(dc_ctx->dmub_srv);
3801 }
3802
3803 /**
3804  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
3805  *                                      Sets port index appropriately for legacy DDC
3806  * @dc: dc structure
3807  * @link_index: link index
3808  * @payload: aux payload
3809  *
3810  * Returns: True if successful, False if failure
3811  */
3812 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3813                                 uint32_t link_index,
3814                                 struct aux_payload *payload)
3815 {
3816         uint8_t action;
3817         union dmub_rb_cmd cmd = {0};
3818         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3819
3820         ASSERT(payload->length <= 16);
3821
3822         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
3823         cmd.dp_aux_access.header.payload_bytes = 0;
3824         /* For dpia, ddc_pin is set to NULL */
3825         if (!dc->links[link_index]->ddc->ddc_pin)
3826                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
3827         else
3828                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
3829
3830         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
3831         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
3832         cmd.dp_aux_access.aux_control.timeout = 0;
3833         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
3834         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
3835         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
3836
3837         /* set aux action */
3838         if (payload->i2c_over_aux) {
3839                 if (payload->write) {
3840                         if (payload->mot)
3841                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
3842                         else
3843                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
3844                 } else {
3845                         if (payload->mot)
3846                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
3847                         else
3848                                 action = DP_AUX_REQ_ACTION_I2C_READ;
3849                         }
3850         } else {
3851                 if (payload->write)
3852                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
3853                 else
3854                         action = DP_AUX_REQ_ACTION_DPCD_READ;
3855         }
3856
3857         cmd.dp_aux_access.aux_control.dpaux.action = action;
3858
3859         if (payload->length && payload->write) {
3860                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
3861                         payload->data,
3862                         payload->length
3863                         );
3864         }
3865
3866         dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
3867         dc_dmub_srv_cmd_execute(dmub_srv);
3868         dc_dmub_srv_wait_idle(dmub_srv);
3869
3870         return true;
3871 }
3872
3873 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
3874                                             uint8_t dpia_port_index)
3875 {
3876         uint8_t index, link_index = 0xFF;
3877
3878         for (index = 0; index < dc->link_count; index++) {
3879                 /* ddc_hw_inst has dpia port index for dpia links
3880                  * and ddc instance for legacy links
3881                  */
3882                 if (!dc->links[index]->ddc->ddc_pin) {
3883                         if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
3884                                 link_index = index;
3885                                 break;
3886                         }
3887                 }
3888         }
3889         ASSERT(link_index != 0xFF);
3890         return link_index;
3891 }
3892
3893 /**
3894  *****************************************************************************
3895  *  Function: dc_process_dmub_set_config_async
3896  *
3897  *  @brief
3898  *              Submits set_config command to dmub via inbox message
3899  *
3900  *  @param
3901  *              [in] dc: dc structure
3902  *              [in] link_index: link index
3903  *              [in] payload: aux payload
3904  *              [out] notify: set_config immediate reply
3905  *
3906  *  @return
3907  *              True if successful, False if failure
3908  *****************************************************************************
3909  */
3910 bool dc_process_dmub_set_config_async(struct dc *dc,
3911                                 uint32_t link_index,
3912                                 struct set_config_cmd_payload *payload,
3913                                 struct dmub_notification *notify)
3914 {
3915         union dmub_rb_cmd cmd = {0};
3916         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3917         bool is_cmd_complete = true;
3918
3919         /* prepare SET_CONFIG command */
3920         cmd.set_config_access.header.type = DMUB_CMD__DPIA;
3921         cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
3922
3923         cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
3924         cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
3925         cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
3926
3927         if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd)) {
3928                 /* command is not processed by dmub */
3929                 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
3930                 return is_cmd_complete;
3931         }
3932
3933         /* command processed by dmub, if ret_status is 1, it is completed instantly */
3934         if (cmd.set_config_access.header.ret_status == 1)
3935                 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
3936         else
3937                 /* cmd pending, will receive notification via outbox */
3938                 is_cmd_complete = false;
3939
3940         return is_cmd_complete;
3941 }
3942
3943 /**
3944  *****************************************************************************
3945  *  Function: dc_process_dmub_set_mst_slots
3946  *
3947  *  @brief
3948  *              Submits mst slot allocation command to dmub via inbox message
3949  *
3950  *  @param
3951  *              [in] dc: dc structure
3952  *              [in] link_index: link index
3953  *              [in] mst_alloc_slots: mst slots to be allotted
3954  *              [out] mst_slots_in_use: mst slots in use returned in failure case
3955  *
3956  *      @return
3957  *              DC_OK if successful, DC_ERROR if failure
3958  *****************************************************************************
3959  */
3960 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
3961                                 uint32_t link_index,
3962                                 uint8_t mst_alloc_slots,
3963                                 uint8_t *mst_slots_in_use)
3964 {
3965         union dmub_rb_cmd cmd = {0};
3966         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3967
3968         /* prepare MST_ALLOC_SLOTS command */
3969         cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
3970         cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
3971
3972         cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
3973         cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
3974
3975         if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd))
3976                 /* command is not processed by dmub */
3977                 return DC_ERROR_UNEXPECTED;
3978
3979         /* command processed by dmub, if ret_status is 1 */
3980         if (cmd.set_config_access.header.ret_status != 1)
3981                 /* command processing error */
3982                 return DC_ERROR_UNEXPECTED;
3983
3984         /* command processed and we have a status of 2, mst not enabled in dpia */
3985         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
3986                 return DC_FAIL_UNSUPPORTED_1;
3987
3988         /* previously configured mst alloc and used slots did not match */
3989         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
3990                 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
3991                 return DC_NOT_SUPPORTED;
3992         }
3993
3994         return DC_OK;
3995 }
3996
3997 /**
3998  * dc_disable_accelerated_mode - disable accelerated mode
3999  * @dc: dc structure
4000  */
4001 void dc_disable_accelerated_mode(struct dc *dc)
4002 {
4003         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
4004 }
4005
4006
4007 /**
4008  *****************************************************************************
4009  *  dc_notify_vsync_int_state() - notifies vsync enable/disable state
4010  *  @dc: dc structure
4011  *      @stream: stream where vsync int state changed
4012  *      @enable: whether vsync is enabled or disabled
4013  *
4014  *  Called when vsync is enabled/disabled
4015  *      Will notify DMUB to start/stop ABM interrupts after steady state is reached
4016  *
4017  *****************************************************************************
4018  */
4019 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
4020 {
4021         int i;
4022         int edp_num;
4023         struct pipe_ctx *pipe = NULL;
4024         struct dc_link *link = stream->sink->link;
4025         struct dc_link *edp_links[MAX_NUM_EDP];
4026
4027
4028         if (link->psr_settings.psr_feature_enabled)
4029                 return;
4030
4031         /*find primary pipe associated with stream*/
4032         for (i = 0; i < MAX_PIPES; i++) {
4033                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4034
4035                 if (pipe->stream == stream && pipe->stream_res.tg)
4036                         break;
4037         }
4038
4039         if (i == MAX_PIPES) {
4040                 ASSERT(0);
4041                 return;
4042         }
4043
4044         get_edp_links(dc, edp_links, &edp_num);
4045
4046         /* Determine panel inst */
4047         for (i = 0; i < edp_num; i++) {
4048                 if (edp_links[i] == link)
4049                         break;
4050         }
4051
4052         if (i == edp_num) {
4053                 return;
4054         }
4055
4056         if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
4057                 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
4058 }
4059 /*
4060  * dc_extended_blank_supported: Decide whether extended blank is supported
4061  *
4062  * Extended blank is a freesync optimization feature to be enabled in the future.
4063  * During the extra vblank period gained from freesync, we have the ability to enter z9/z10.
4064  *
4065  * @param [in] dc: Current DC state
4066  * @return: Indicate whether extended blank is supported (true or false)
4067  */
4068 bool dc_extended_blank_supported(struct dc *dc)
4069 {
4070         return dc->debug.extended_blank_optimization && !dc->debug.disable_z10
4071                 && dc->caps.zstate_support && dc->caps.is_apu;
4072 }