drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_cs.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_hw_ip.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v4_0.h"
  34 #include "vcn_v4_0.h"
  35
  36 #include "vcn/vcn_4_0_0_offset.h"
  37 #include "vcn/vcn_4_0_0_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #include <drm/drm_drv.h>
  41
  42 #define mmUVD_DPG_LMA_CTL                                                       regUVD_DPG_LMA_CTL
  43 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                              regUVD_DPG_LMA_CTL_BASE_IDX
  44 #define mmUVD_DPG_LMA_DATA                                                      regUVD_DPG_LMA_DATA
  45 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                             regUVD_DPG_LMA_DATA_BASE_IDX
  46
  47 #define VCN_VID_SOC_ADDRESS_2_0                                                 0x1fb00
  48 #define VCN1_VID_SOC_ADDRESS_3_0                                                0x48300
  49
  50 #define VCN_HARVEST_MMSCH                                                               0
  51
  52 #define RDECODE_MSG_CREATE                                                      0x00000000
  53 #define RDECODE_MESSAGE_CREATE                                                  0x00000001
  54
  55 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = {
  56         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
  57         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
  58         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
  59         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
  60         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
  61         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
  62         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
  63         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
  64         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
  65         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
  66         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
  67         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
  68         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
  69         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
  70         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
  71         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
  72         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
  73         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
  74         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
  75         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
  76         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
  77         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
  78         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
  79         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
  80         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
  81         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
  82         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
  83         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
  84         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
  85         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
  86         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
  87         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
  88         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
  89 };
  90
  91 static int amdgpu_ih_clientid_vcns[] = {
  92         SOC15_IH_CLIENTID_VCN,
  93         SOC15_IH_CLIENTID_VCN1
  94 };
  95
  96 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
  97 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
  98 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  99 static int vcn_v4_0_set_powergating_state(void *handle,
 100         enum amd_powergating_state state);
 101 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
 102         int inst_idx, struct dpg_pause_state *new_state);
 103 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
 104 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
 105
 106 /**
 107  * vcn_v4_0_early_init - set function pointers and load microcode
 108  *
 109  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 110  *
 111  * Set ring and irq function pointers
 112  * Load microcode from filesystem
 113  */
 114 static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)
 115 {
 116         struct amdgpu_device *adev = ip_block->adev;
 117         int i;
 118
 119         if (amdgpu_sriov_vf(adev)) {
 120                 adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
 121                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 122                         if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
 123                                 adev->vcn.harvest_config |= 1 << i;
 124                                 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
 125                         }
 126                 }
 127         }
 128
 129         /* re-use enc ring as unified ring */
 130         adev->vcn.num_enc_rings = 1;
 131
 132         vcn_v4_0_set_unified_ring_funcs(adev);
 133         vcn_v4_0_set_irq_funcs(adev);
 134         vcn_v4_0_set_ras_funcs(adev);
 135
 136         return amdgpu_vcn_early_init(adev);
 137 }
 138
 139 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
 140 {
 141         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 142
 143         fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 144         fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 145         fw_shared->sq.is_enabled = 1;
 146
 147         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
 148         fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
 149                 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
 150
 151         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
 152             IP_VERSION(4, 0, 2)) {
 153                 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;
 154                 fw_shared->drm_key_wa.method =
 155                         AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;
 156         }
 157
 158         if (amdgpu_vcnfw_log)
 159                 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
 160
 161         return 0;
 162 }
 163
 164 /**
 165  * vcn_v4_0_sw_init - sw init for VCN block
 166  *
 167  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 168  *
 169  * Load firmware and sw initialization
 170  */
 171 static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
 172 {
 173         struct amdgpu_ring *ring;
 174         struct amdgpu_device *adev = ip_block->adev;
 175         int i, r;
 176         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
 177         uint32_t *ptr;
 178
 179         r = amdgpu_vcn_sw_init(adev);
 180         if (r)
 181                 return r;
 182
 183         amdgpu_vcn_setup_ucode(adev);
 184
 185         r = amdgpu_vcn_resume(adev);
 186         if (r)
 187                 return r;
 188
 189         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 190                 if (adev->vcn.harvest_config & (1 << i))
 191                         continue;
 192
 193                 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
 194                 if (i == 0)
 195                         atomic_set(&adev->vcn.inst[i].sched_score, 1);
 196                 else
 197                         atomic_set(&adev->vcn.inst[i].sched_score, 0);
 198
 199                 /* VCN UNIFIED TRAP */
 200                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 201                                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 202                 if (r)
 203                         return r;
 204
 205                 /* VCN POISON TRAP */
 206                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 207                                 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
 208                 if (r)
 209                         return r;
 210
 211                 ring = &adev->vcn.inst[i].ring_enc[0];
 212                 ring->use_doorbell = true;
 213                 if (amdgpu_sriov_vf(adev))
 214                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
 215                 else
 216                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 217                 ring->vm_hub = AMDGPU_MMHUB0(0);
 218                 sprintf(ring->name, "vcn_unified_%d", i);
 219
 220                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 221                                                 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 222                 if (r)
 223                         return r;
 224
 225                 vcn_v4_0_fw_shared_init(adev, i);
 226         }
 227
 228         if (amdgpu_sriov_vf(adev)) {
 229                 r = amdgpu_virt_alloc_mm_table(adev);
 230                 if (r)
 231                         return r;
 232         }
 233
 234         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 235                 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
 236
 237         r = amdgpu_vcn_ras_sw_init(adev);
 238         if (r)
 239                 return r;
 240
 241         /* Allocate memory for VCN IP Dump buffer */
 242         ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
 243         if (!ptr) {
 244                 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
 245                 adev->vcn.ip_dump = NULL;
 246         } else {
 247                 adev->vcn.ip_dump = ptr;
 248         }
 249
 250         return 0;
 251 }
 252
 253 /**
 254  * vcn_v4_0_sw_fini - sw fini for VCN block
 255  *
 256  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 257  *
 258  * VCN suspend and free up sw allocation
 259  */
 260 static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
 261 {
 262         struct amdgpu_device *adev = ip_block->adev;
 263         int i, r, idx;
 264
 265         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 266                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 267                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 268
 269                         if (adev->vcn.harvest_config & (1 << i))
 270                                 continue;
 271
 272                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 273                         fw_shared->present_flag_0 = 0;
 274                         fw_shared->sq.is_enabled = 0;
 275                 }
 276
 277                 drm_dev_exit(idx);
 278         }
 279
 280         if (amdgpu_sriov_vf(adev))
 281                 amdgpu_virt_free_mm_table(adev);
 282
 283         r = amdgpu_vcn_suspend(adev);
 284         if (r)
 285                 return r;
 286
 287         r = amdgpu_vcn_sw_fini(adev);
 288
 289         kfree(adev->vcn.ip_dump);
 290
 291         return r;
 292 }
 293
 294 /**
 295  * vcn_v4_0_hw_init - start and test VCN block
 296  *
 297  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 298  *
 299  * Initialize the hardware, boot up the VCPU and do some testing
 300  */
 301 static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
 302 {
 303         struct amdgpu_device *adev = ip_block->adev;
 304         struct amdgpu_ring *ring;
 305         int i, r;
 306
 307         if (amdgpu_sriov_vf(adev)) {
 308                 r = vcn_v4_0_start_sriov(adev);
 309                 if (r)
 310                         return r;
 311
 312                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 313                         if (adev->vcn.harvest_config & (1 << i))
 314                                 continue;
 315
 316                         ring = &adev->vcn.inst[i].ring_enc[0];
 317                         ring->wptr = 0;
 318                         ring->wptr_old = 0;
 319                         vcn_v4_0_unified_ring_set_wptr(ring);
 320                         ring->sched.ready = true;
 321                 }
 322         } else {
 323                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 324                         if (adev->vcn.harvest_config & (1 << i))
 325                                 continue;
 326
 327                         ring = &adev->vcn.inst[i].ring_enc[0];
 328
 329                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 330                                         ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 331
 332                         r = amdgpu_ring_test_helper(ring);
 333                         if (r)
 334                                 return r;
 335                 }
 336         }
 337
 338         return 0;
 339 }
 340
 341 /**
 342  * vcn_v4_0_hw_fini - stop the hardware block
 343  *
 344  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 345  *
 346  * Stop the VCN block, mark ring as not ready any more
 347  */
 348 static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
 349 {
 350         struct amdgpu_device *adev = ip_block->adev;
 351         int i;
 352
 353         cancel_delayed_work_sync(&adev->vcn.idle_work);
 354
 355         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 356                 if (adev->vcn.harvest_config & (1 << i))
 357                         continue;
 358                 if (!amdgpu_sriov_vf(adev)) {
 359                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 360                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 361                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
 362                         vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 363                         }
 364                 }
 365                 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 366                         amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
 367         }
 368
 369         return 0;
 370 }
 371
 372 /**
 373  * vcn_v4_0_suspend - suspend VCN block
 374  *
 375  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 376  *
 377  * HW fini and suspend VCN block
 378  */
 379 static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block)
 380 {
 381         int r;
 382
 383         r = vcn_v4_0_hw_fini(ip_block);
 384         if (r)
 385                 return r;
 386
 387         r = amdgpu_vcn_suspend(ip_block->adev);
 388
 389         return r;
 390 }
 391
 392 /**
 393  * vcn_v4_0_resume - resume VCN block
 394  *
 395  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 396  *
 397  * Resume firmware and hw init VCN block
 398  */
 399 static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block)
 400 {
 401         int r;
 402
 403         r = amdgpu_vcn_resume(ip_block->adev);
 404         if (r)
 405                 return r;
 406
 407         r = vcn_v4_0_hw_init(ip_block);
 408
 409         return r;
 410 }
 411
 412 /**
 413  * vcn_v4_0_mc_resume - memory controller programming
 414  *
 415  * @adev: amdgpu_device pointer
 416  * @inst: instance number
 417  *
 418  * Let the VCN memory controller know it's offsets
 419  */
 420 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
 421 {
 422         uint32_t offset, size;
 423         const struct common_firmware_header *hdr;
 424
 425         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
 426         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 427
 428         /* cache window 0: fw */
 429         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 430                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 431                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 432                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 433                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 434                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 435                 offset = 0;
 436         } else {
 437                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 438                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 439                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 440                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 441                 offset = size;
 442                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 443         }
 444         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
 445
 446         /* cache window 1: stack */
 447         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 448                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 449         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 450                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 451         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 452         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 453
 454         /* cache window 2: context */
 455         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 456                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 457         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 458                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 459         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 460         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 461
 462         /* non-cache window */
 463         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 464                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 465         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 466                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 467         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 468         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
 469                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 470 }
 471
 472 /**
 473  * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
 474  *
 475  * @adev: amdgpu_device pointer
 476  * @inst_idx: instance number index
 477  * @indirect: indirectly write sram
 478  *
 479  * Let the VCN memory controller know it's offsets with dpg mode
 480  */
 481 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 482 {
 483         uint32_t offset, size;
 484         const struct common_firmware_header *hdr;
 485         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 486         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 487
 488         /* cache window 0: fw */
 489         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 490                 if (!indirect) {
 491                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 492                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 493                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 494                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 495                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 496                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 497                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 498                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 499                 } else {
 500                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 501                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 502                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 503                                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 504                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 505                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 506                 }
 507                 offset = 0;
 508         } else {
 509                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 510                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 511                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 512                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 513                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 514                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 515                 offset = size;
 516                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 517                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 518                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 519         }
 520
 521         if (!indirect)
 522                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 523                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 524         else
 525                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 526                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 527
 528         /* cache window 1: stack */
 529         if (!indirect) {
 530                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 531                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 532                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 533                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 534                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 535                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 536                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 537                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 538         } else {
 539                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 540                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 541                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 542                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 543                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 544                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 545         }
 546         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 547                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 548
 549         /* cache window 2: context */
 550         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 551                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 552                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 553         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 554                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 555                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 556         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 557                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 558         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 559                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 560
 561         /* non-cache window */
 562         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 563                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 564                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 565         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 566                         VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 567                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 568         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 569                         VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 570         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 571                         VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
 572                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 573
 574         /* VCN global tiling registers */
 575         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 576                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 577 }
 578
 579 /**
 580  * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
 581  *
 582  * @adev: amdgpu_device pointer
 583  * @inst: instance number
 584  *
 585  * Disable static power gating for VCN block
 586  */
 587 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 588 {
 589         uint32_t data = 0;
 590
 591         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 592                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 593                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 594                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 595                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 596                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 597                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 598                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 599                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 600                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 601                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 602                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 603                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 604                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 605                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 606
 607                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 608                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
 609                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 610         } else {
 611                 uint32_t value;
 612
 613                 value = (inst) ? 0x2200800 : 0;
 614                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 615                         | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 616                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 617                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 618                         | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 619                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 620                         | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 621                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 622                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 623                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 624                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 625                         | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 626                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 627                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 628
 629                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 630                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value,  0x3F3FFFFF);
 631         }
 632
 633         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 634         data &= ~0x103;
 635         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 636                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 637                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 638
 639         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 640
 641         return;
 642 }
 643
 644 /**
 645  * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
 646  *
 647  * @adev: amdgpu_device pointer
 648  * @inst: instance number
 649  *
 650  * Enable static power gating for VCN block
 651  */
 652 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 653 {
 654         uint32_t data;
 655
 656         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 657                 /* Before power off, this indicator has to be turned on */
 658                 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 659                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 660                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 661                 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 662
 663                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 664                         | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
 665                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 666                         | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
 667                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 668                         | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
 669                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 670                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 671                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 672                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 673                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 674                         | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
 675                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 676                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 677                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
 678
 679                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 680                         | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
 681                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 682                         | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
 683                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 684                         | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
 685                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 686                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 687                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 688                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 689                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 690                         | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
 691                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 692                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 693                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 694         }
 695
 696         return;
 697 }
 698
 699 /**
 700  * vcn_v4_0_disable_clock_gating - disable VCN clock gating
 701  *
 702  * @adev: amdgpu_device pointer
 703  * @inst: instance number
 704  *
 705  * Disable clock gating for VCN block
 706  */
 707 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 708 {
 709         uint32_t data;
 710
 711         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 712                 return;
 713
 714         /* VCN disable CGC */
 715         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 716         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 717         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 718         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 719         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 720
 721         data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
 722         data &= ~(UVD_CGC_GATE__SYS_MASK
 723                 | UVD_CGC_GATE__UDEC_MASK
 724                 | UVD_CGC_GATE__MPEG2_MASK
 725                 | UVD_CGC_GATE__REGS_MASK
 726                 | UVD_CGC_GATE__RBC_MASK
 727                 | UVD_CGC_GATE__LMI_MC_MASK
 728                 | UVD_CGC_GATE__LMI_UMC_MASK
 729                 | UVD_CGC_GATE__IDCT_MASK
 730                 | UVD_CGC_GATE__MPRD_MASK
 731                 | UVD_CGC_GATE__MPC_MASK
 732                 | UVD_CGC_GATE__LBSI_MASK
 733                 | UVD_CGC_GATE__LRBBM_MASK
 734                 | UVD_CGC_GATE__UDEC_RE_MASK
 735                 | UVD_CGC_GATE__UDEC_CM_MASK
 736                 | UVD_CGC_GATE__UDEC_IT_MASK
 737                 | UVD_CGC_GATE__UDEC_DB_MASK
 738                 | UVD_CGC_GATE__UDEC_MP_MASK
 739                 | UVD_CGC_GATE__WCB_MASK
 740                 | UVD_CGC_GATE__VCPU_MASK
 741                 | UVD_CGC_GATE__MMSCH_MASK);
 742
 743         WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
 744         SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);
 745
 746         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 747         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 748                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 749                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 750                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 751                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 752                 | UVD_CGC_CTRL__SYS_MODE_MASK
 753                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 754                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 755                 | UVD_CGC_CTRL__REGS_MODE_MASK
 756                 | UVD_CGC_CTRL__RBC_MODE_MASK
 757                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 758                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 759                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 760                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 761                 | UVD_CGC_CTRL__MPC_MODE_MASK
 762                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 763                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 764                 | UVD_CGC_CTRL__WCB_MODE_MASK
 765                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 766                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 767         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 768
 769         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
 770         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 771                 | UVD_SUVD_CGC_GATE__SIT_MASK
 772                 | UVD_SUVD_CGC_GATE__SMP_MASK
 773                 | UVD_SUVD_CGC_GATE__SCM_MASK
 774                 | UVD_SUVD_CGC_GATE__SDB_MASK
 775                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 776                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 777                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 778                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 779                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 780                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 781                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 782                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 783                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 784                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 785                 | UVD_SUVD_CGC_GATE__ENT_MASK
 786                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 787                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 788                 | UVD_SUVD_CGC_GATE__SITE_MASK
 789                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 790                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 791                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 792                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 793                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 794         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
 795
 796         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 797         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 798                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 799                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 800                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 801                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 802                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 803                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 804                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 805                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 806                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 807         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 808 }
 809
 810 /**
 811  * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 812  *
 813  * @adev: amdgpu_device pointer
 814  * @sram_sel: sram select
 815  * @inst_idx: instance number index
 816  * @indirect: indirectly write sram
 817  *
 818  * Disable clock gating for VCN block with dpg mode
 819  */
 820 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 821       int inst_idx, uint8_t indirect)
 822 {
 823         uint32_t reg_data = 0;
 824
 825         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 826                 return;
 827
 828         /* enable sw clock gating control */
 829         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 830         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 831         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 832         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 833                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 834                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 835                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 836                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 837                  UVD_CGC_CTRL__SYS_MODE_MASK |
 838                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 839                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 840                  UVD_CGC_CTRL__REGS_MODE_MASK |
 841                  UVD_CGC_CTRL__RBC_MODE_MASK |
 842                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 843                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 844                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 845                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 846                  UVD_CGC_CTRL__MPC_MODE_MASK |
 847                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 848                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 849                  UVD_CGC_CTRL__WCB_MODE_MASK |
 850                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 851         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 852                 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 853
 854         /* turn off clock gating */
 855         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 856                 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
 857
 858         /* turn on SUVD clock gating */
 859         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 860                 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 861
 862         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 863         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 864                 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 865 }
 866
 867 /**
 868  * vcn_v4_0_enable_clock_gating - enable VCN clock gating
 869  *
 870  * @adev: amdgpu_device pointer
 871  * @inst: instance number
 872  *
 873  * Enable clock gating for VCN block
 874  */
 875 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 876 {
 877         uint32_t data;
 878
 879         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 880                 return;
 881
 882         /* enable VCN CGC */
 883         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 884         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 885         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 886         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 887         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 888
 889         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 890         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 891                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 892                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 893                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 894                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 895                 | UVD_CGC_CTRL__SYS_MODE_MASK
 896                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 897                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 898                 | UVD_CGC_CTRL__REGS_MODE_MASK
 899                 | UVD_CGC_CTRL__RBC_MODE_MASK
 900                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 901                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 902                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 903                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 904                 | UVD_CGC_CTRL__MPC_MODE_MASK
 905                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 906                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 907                 | UVD_CGC_CTRL__WCB_MODE_MASK
 908                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 909                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 910         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 911
 912         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 913         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 914                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 915                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 916                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 917                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 918                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 919                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 920                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 921                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 922                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 923         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 924 }
 925
 926 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
 927                                 bool indirect)
 928 {
 929         uint32_t tmp;
 930
 931         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 932                 return;
 933
 934         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
 935               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
 936               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
 937               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
 938         WREG32_SOC15_DPG_MODE(inst_idx,
 939                               SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
 940                               tmp, 0, indirect);
 941
 942         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 943         WREG32_SOC15_DPG_MODE(inst_idx,
 944                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
 945                               tmp, 0, indirect);
 946 }
 947
 948 /**
 949  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
 950  *
 951  * @adev: amdgpu_device pointer
 952  * @inst_idx: instance number index
 953  * @indirect: indirectly write sram
 954  *
 955  * Start VCN block with dpg mode
 956  */
 957 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 958 {
 959         volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 960         struct amdgpu_ring *ring;
 961         uint32_t tmp;
 962
 963         /* disable register anti-hang mechanism */
 964         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
 965                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 966         /* enable dynamic power gating mode */
 967         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
 968         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 969         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 970         WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
 971
 972         if (indirect)
 973                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 974
 975         /* enable clock gating */
 976         vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 977
 978         /* enable VCPU clock */
 979         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 980         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 981         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 982                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 983
 984         /* disable master interupt */
 985         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 986                 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
 987
 988         /* setup regUVD_LMI_CTRL */
 989         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 990                 UVD_LMI_CTRL__REQ_MODE_MASK |
 991                 UVD_LMI_CTRL__CRC_RESET_MASK |
 992                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 993                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 994                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 995                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 996                 0x00100000L);
 997         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 998                 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
 999
1000         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1001                 VCN, inst_idx, regUVD_MPC_CNTL),
1002                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
1003
1004         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1005                 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
1006                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1007                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1008                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1009                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
1010
1011         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1012                 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
1013                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1014                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1015                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1016                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
1017
1018         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1019                 VCN, inst_idx, regUVD_MPC_SET_MUX),
1020                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1021                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1022                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1023
1024         vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
1025
1026         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1027         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1028         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1029                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
1030
1031         /* enable LMI MC and UMC channels */
1032         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
1033         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1034                 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
1035
1036         vcn_v4_0_enable_ras(adev, inst_idx, indirect);
1037
1038         /* enable master interrupt */
1039         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1040                 VCN, inst_idx, regUVD_MASTINT_EN),
1041                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1042
1043
1044         if (indirect)
1045                 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
1046
1047         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1048
1049         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
1050         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1051         WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1052
1053         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1054         tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1055         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1056         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1057         WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1058         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1059
1060         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1061         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1062         ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1063
1064         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1065         tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1066         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1067         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1068
1069         WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1070                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1071                         VCN_RB1_DB_CTRL__EN_MASK);
1072
1073         return 0;
1074 }
1075
1076
1077 /**
1078  * vcn_v4_0_start - VCN start
1079  *
1080  * @adev: amdgpu_device pointer
1081  *
1082  * Start VCN block
1083  */
1084 static int vcn_v4_0_start(struct amdgpu_device *adev)
1085 {
1086         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1087         struct amdgpu_ring *ring;
1088         uint32_t tmp;
1089         int i, j, k, r;
1090
1091         if (adev->pm.dpm_enabled)
1092                 amdgpu_dpm_enable_uvd(adev, true);
1093
1094         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1095                 if (adev->vcn.harvest_config & (1 << i))
1096                         continue;
1097
1098                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1099
1100                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1101                         r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1102                         continue;
1103                 }
1104
1105                 /* disable VCN power gating */
1106                 vcn_v4_0_disable_static_power_gating(adev, i);
1107
1108                 /* set VCN status busy */
1109                 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1110                 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1111
1112                 /*SW clock gating */
1113                 vcn_v4_0_disable_clock_gating(adev, i);
1114
1115                 /* enable VCPU clock */
1116                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1117                                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1118
1119                 /* disable master interrupt */
1120                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1121                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1122
1123                 /* enable LMI MC and UMC channels */
1124                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1125                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1126
1127                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1128                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1129                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1130                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1131
1132                 /* setup regUVD_LMI_CTRL */
1133                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1134                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1135                                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1136                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1137                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1138                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1139
1140                 /* setup regUVD_MPC_CNTL */
1141                 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1142                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1143                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1144                 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1145
1146                 /* setup UVD_MPC_SET_MUXA0 */
1147                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1148                                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1149                                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1150                                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1151                                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1152
1153                 /* setup UVD_MPC_SET_MUXB0 */
1154                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1155                                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1156                                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1157                                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1158                                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1159
1160                 /* setup UVD_MPC_SET_MUX */
1161                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1162                                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1163                                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1164                                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1165
1166                 vcn_v4_0_mc_resume(adev, i);
1167
1168                 /* VCN global tiling registers */
1169                 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1170                                 adev->gfx.config.gb_addr_config);
1171
1172                 /* unblock VCPU register access */
1173                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1174                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1175
1176                 /* release VCPU reset to boot */
1177                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1178                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1179
1180                 for (j = 0; j < 10; ++j) {
1181                         uint32_t status;
1182
1183                         for (k = 0; k < 100; ++k) {
1184                                 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1185                                 if (status & 2)
1186                                         break;
1187                                 mdelay(10);
1188                                 if (amdgpu_emu_mode == 1)
1189                                         msleep(1);
1190                         }
1191
1192                         if (amdgpu_emu_mode == 1) {
1193                                 r = -1;
1194                                 if (status & 2) {
1195                                         r = 0;
1196                                         break;
1197                                 }
1198                         } else {
1199                                 r = 0;
1200                                 if (status & 2)
1201                                         break;
1202
1203                                 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1204                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1205                                                         UVD_VCPU_CNTL__BLK_RST_MASK,
1206                                                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1207                                 mdelay(10);
1208                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1209                                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1210
1211                                 mdelay(10);
1212                                 r = -1;
1213                         }
1214                 }
1215
1216                 if (r) {
1217                         dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1218                         return r;
1219                 }
1220
1221                 /* enable master interrupt */
1222                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1223                                 UVD_MASTINT_EN__VCPU_EN_MASK,
1224                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1225
1226                 /* clear the busy bit of VCN_STATUS */
1227                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1228                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1229
1230                 ring = &adev->vcn.inst[i].ring_enc[0];
1231                 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1232                                 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1233                                 VCN_RB1_DB_CTRL__EN_MASK);
1234
1235                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1236                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1237                 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1238
1239                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1240                 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1241                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1242                 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1243                 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1244                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1245
1246                 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1247                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1248                 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1249
1250                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1251                 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1252                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1253                 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc)
1260 {
1261         struct amdgpu_vcn_rb_metadata *rb_metadata = NULL;
1262         uint8_t *rb_ptr = (uint8_t *)ring_enc->ring;
1263
1264         rb_ptr += ring_enc->ring_size;
1265         rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr;
1266
1267         memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata));
1268         rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata);
1269         rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1270         rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1271         rb_metadata->version = 1;
1272         rb_metadata->ring_id = vcn_inst & 0xFF;
1273
1274         return 0;
1275 }
1276
1277 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1278 {
1279         int i;
1280         struct amdgpu_ring *ring_enc;
1281         uint64_t cache_addr;
1282         uint64_t rb_enc_addr;
1283         uint64_t ctx_addr;
1284         uint32_t param, resp, expected;
1285         uint32_t offset, cache_size;
1286         uint32_t tmp, timeout;
1287
1288         struct amdgpu_mm_table *table = &adev->virt.mm_table;
1289         uint32_t *table_loc;
1290         uint32_t table_size;
1291         uint32_t size, size_dw;
1292         uint32_t init_status;
1293         uint32_t enabled_vcn;
1294
1295         struct mmsch_v4_0_cmd_direct_write
1296                 direct_wt = { {0} };
1297         struct mmsch_v4_0_cmd_direct_read_modify_write
1298                 direct_rd_mod_wt = { {0} };
1299         struct mmsch_v4_0_cmd_end end = { {0} };
1300         struct mmsch_v4_0_init_header header;
1301
1302         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1303         volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1304
1305         direct_wt.cmd_header.command_type =
1306                 MMSCH_COMMAND__DIRECT_REG_WRITE;
1307         direct_rd_mod_wt.cmd_header.command_type =
1308                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1309         end.cmd_header.command_type =
1310                 MMSCH_COMMAND__END;
1311
1312         header.version = MMSCH_VERSION;
1313         header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1314         for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
1315                 header.inst[i].init_status = 0;
1316                 header.inst[i].table_offset = 0;
1317                 header.inst[i].table_size = 0;
1318         }
1319
1320         table_loc = (uint32_t *)table->cpu_addr;
1321         table_loc += header.total_size;
1322         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1323                 if (adev->vcn.harvest_config & (1 << i))
1324                         continue;
1325
1326                 // Must re/init fw_shared at beginning
1327                 vcn_v4_0_fw_shared_init(adev, i);
1328
1329                 table_size = 0;
1330
1331                 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1332                         regUVD_STATUS),
1333                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1334
1335                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
1336
1337                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1338                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1339                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1340                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1341                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1342                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1343                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1344                         offset = 0;
1345                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1346                                 regUVD_VCPU_CACHE_OFFSET0),
1347                                 0);
1348                 } else {
1349                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1350                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1351                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1352                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1353                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1354                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1355                         offset = cache_size;
1356                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1357                                 regUVD_VCPU_CACHE_OFFSET0),
1358                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1359                 }
1360
1361                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1362                         regUVD_VCPU_CACHE_SIZE0),
1363                         cache_size);
1364
1365                 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1366                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1367                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1368                         lower_32_bits(cache_addr));
1369                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1370                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1371                         upper_32_bits(cache_addr));
1372                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1373                         regUVD_VCPU_CACHE_OFFSET1),
1374                         0);
1375                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1376                         regUVD_VCPU_CACHE_SIZE1),
1377                         AMDGPU_VCN_STACK_SIZE);
1378
1379                 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1380                         AMDGPU_VCN_STACK_SIZE;
1381                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1382                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1383                         lower_32_bits(cache_addr));
1384                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1385                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1386                         upper_32_bits(cache_addr));
1387                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1388                         regUVD_VCPU_CACHE_OFFSET2),
1389                         0);
1390                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1391                         regUVD_VCPU_CACHE_SIZE2),
1392                         AMDGPU_VCN_CONTEXT_SIZE);
1393
1394                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1395                 rb_setup = &fw_shared->rb_setup;
1396
1397                 ring_enc = &adev->vcn.inst[i].ring_enc[0];
1398                 ring_enc->wptr = 0;
1399                 rb_enc_addr = ring_enc->gpu_addr;
1400
1401                 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1402                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1403
1404                 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
1405                         vcn_v4_0_init_ring_metadata(adev, i, ring_enc);
1406
1407                         memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP);
1408                         if (!(adev->vcn.harvest_config & (1 << 0))) {
1409                                 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1410                                 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
1411                                 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4;
1412                         }
1413                         if (!(adev->vcn.harvest_config & (1 << 1))) {
1414                                 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1415                                 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
1416                                 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4;
1417                         }
1418                         fw_shared->decouple.is_enabled = 1;
1419                         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG);
1420                 } else {
1421                         rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1422                         rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1423                         rb_setup->rb_size = ring_enc->ring_size / 4;
1424                 }
1425
1426                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1427                         regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1428                         lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1429                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1430                         regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1431                         upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1432                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1433                         regUVD_VCPU_NONCACHE_SIZE0),
1434                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1435
1436                 /* add end packet */
1437                 MMSCH_V4_0_INSERT_END();
1438
1439                 /* refine header */
1440                 header.inst[i].init_status = 0;
1441                 header.inst[i].table_offset = header.total_size;
1442                 header.inst[i].table_size = table_size;
1443                 header.total_size += table_size;
1444         }
1445
1446         /* Update init table header in memory */
1447         size = sizeof(struct mmsch_v4_0_init_header);
1448         table_loc = (uint32_t *)table->cpu_addr;
1449         memcpy((void *)table_loc, &header, size);
1450
1451         /* message MMSCH (in VCN[0]) to initialize this client
1452          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1453          * of memory descriptor location
1454          */
1455         ctx_addr = table->gpu_addr;
1456         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1457         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1458
1459         /* 2, update vmid of descriptor */
1460         tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1461         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1462         /* use domain0 for MM scheduler */
1463         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1464         WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1465
1466         /* 3, notify mmsch about the size of this descriptor */
1467         size = header.total_size;
1468         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1469
1470         /* 4, set resp to zero */
1471         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1472
1473         /* 5, kick off the initialization and wait until
1474          * MMSCH_VF_MAILBOX_RESP becomes non-zero
1475          */
1476         param = 0x00000001;
1477         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1478         tmp = 0;
1479         timeout = 1000;
1480         resp = 0;
1481         expected = MMSCH_VF_MAILBOX_RESP__OK;
1482         while (resp != expected) {
1483                 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1484                 if (resp != 0)
1485                         break;
1486
1487                 udelay(10);
1488                 tmp = tmp + 10;
1489                 if (tmp >= timeout) {
1490                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1491                                 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1492                                 "(expected=0x%08x, readback=0x%08x)\n",
1493                                 tmp, expected, resp);
1494                         return -EBUSY;
1495                 }
1496         }
1497         enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1498         init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1499         if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1500         && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1501                 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1502                         "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1503
1504         return 0;
1505 }
1506
1507 /**
1508  * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1509  *
1510  * @adev: amdgpu_device pointer
1511  * @inst_idx: instance number index
1512  *
1513  * Stop VCN block with dpg mode
1514  */
1515 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1516 {
1517         struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1518         uint32_t tmp;
1519
1520         vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
1521         /* Wait for power status to be 1 */
1522         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1523                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1524
1525         /* wait for read ptr to be equal to write ptr */
1526         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1527         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1528
1529         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1530                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1531
1532         /* disable dynamic power gating mode */
1533         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1534                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1535 }
1536
1537 /**
1538  * vcn_v4_0_stop - VCN stop
1539  *
1540  * @adev: amdgpu_device pointer
1541  *
1542  * Stop VCN block
1543  */
1544 static int vcn_v4_0_stop(struct amdgpu_device *adev)
1545 {
1546         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1547         uint32_t tmp;
1548         int i, r = 0;
1549
1550         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1551                 if (adev->vcn.harvest_config & (1 << i))
1552                         continue;
1553
1554                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1555                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1556
1557                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1558                         vcn_v4_0_stop_dpg_mode(adev, i);
1559                         continue;
1560                 }
1561
1562                 /* wait for vcn idle */
1563                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1564                 if (r)
1565                         return r;
1566
1567                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1568                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1569                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1570                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1571                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1572                 if (r)
1573                         return r;
1574
1575                 /* disable LMI UMC channel */
1576                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1577                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1578                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1579                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1580                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1581                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1582                 if (r)
1583                         return r;
1584
1585                 /* block VCPU register access */
1586                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1587                                 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1588                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1589
1590                 /* reset VCPU */
1591                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1592                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1593                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1594
1595                 /* disable VCPU clock */
1596                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1597                                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1598
1599                 /* apply soft reset */
1600                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1601                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1602                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1603                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1604                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1605                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1606
1607                 /* clear status */
1608                 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1609
1610                 /* apply HW clock gating */
1611                 vcn_v4_0_enable_clock_gating(adev, i);
1612
1613                 /* enable VCN power gating */
1614                 vcn_v4_0_enable_static_power_gating(adev, i);
1615         }
1616
1617         if (adev->pm.dpm_enabled)
1618                 amdgpu_dpm_enable_uvd(adev, false);
1619
1620         return 0;
1621 }
1622
1623 /**
1624  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1625  *
1626  * @adev: amdgpu_device pointer
1627  * @inst_idx: instance number index
1628  * @new_state: pause state
1629  *
1630  * Pause dpg mode for VCN block
1631  */
1632 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1633       struct dpg_pause_state *new_state)
1634 {
1635         uint32_t reg_data = 0;
1636         int ret_code;
1637
1638         /* pause/unpause if state is changed */
1639         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1640                 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1641                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1642                 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1643                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1644
1645                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1646                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1647                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1648
1649                         if (!ret_code) {
1650                                 /* pause DPG */
1651                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1652                                 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1653
1654                                 /* wait for ACK */
1655                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1656                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1657                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1658
1659                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1660                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1661                         }
1662                 } else {
1663                         /* unpause dpg, no need to wait */
1664                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1665                         WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1666                 }
1667                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1668         }
1669
1670         return 0;
1671 }
1672
1673 /**
1674  * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1675  *
1676  * @ring: amdgpu_ring pointer
1677  *
1678  * Returns the current hardware unified read pointer
1679  */
1680 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1681 {
1682         struct amdgpu_device *adev = ring->adev;
1683
1684         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1685                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1686
1687         return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1688 }
1689
1690 /**
1691  * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1692  *
1693  * @ring: amdgpu_ring pointer
1694  *
1695  * Returns the current hardware unified write pointer
1696  */
1697 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1698 {
1699         struct amdgpu_device *adev = ring->adev;
1700
1701         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1702                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1703
1704         if (ring->use_doorbell)
1705                 return *ring->wptr_cpu_addr;
1706         else
1707                 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1708 }
1709
1710 /**
1711  * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1712  *
1713  * @ring: amdgpu_ring pointer
1714  *
1715  * Commits the enc write pointer to the hardware
1716  */
1717 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1718 {
1719         struct amdgpu_device *adev = ring->adev;
1720
1721         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1722                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1723
1724         if (ring->use_doorbell) {
1725                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1726                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1727         } else {
1728                 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1729         }
1730 }
1731
1732 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1733                                 struct amdgpu_job *job)
1734 {
1735         struct drm_gpu_scheduler **scheds;
1736
1737         /* The create msg must be in the first IB submitted */
1738         if (atomic_read(&job->base.entity->fence_seq))
1739                 return -EINVAL;
1740
1741         /* if VCN0 is harvested, we can't support AV1 */
1742         if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1743                 return -EINVAL;
1744
1745         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1746                 [AMDGPU_RING_PRIO_0].sched;
1747         drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1748         return 0;
1749 }
1750
1751 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1752                             uint64_t addr)
1753 {
1754         struct ttm_operation_ctx ctx = { false, false };
1755         struct amdgpu_bo_va_mapping *map;
1756         uint32_t *msg, num_buffers;
1757         struct amdgpu_bo *bo;
1758         uint64_t start, end;
1759         unsigned int i;
1760         void *ptr;
1761         int r;
1762
1763         addr &= AMDGPU_GMC_HOLE_MASK;
1764         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1765         if (r) {
1766                 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1767                 return r;
1768         }
1769
1770         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1771         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1772         if (addr & 0x7) {
1773                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1774                 return -EINVAL;
1775         }
1776
1777         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1778         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1779         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1780         if (r) {
1781                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1782                 return r;
1783         }
1784
1785         r = amdgpu_bo_kmap(bo, &ptr);
1786         if (r) {
1787                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1788                 return r;
1789         }
1790
1791         msg = ptr + addr - start;
1792
1793         /* Check length */
1794         if (msg[1] > end - addr) {
1795                 r = -EINVAL;
1796                 goto out;
1797         }
1798
1799         if (msg[3] != RDECODE_MSG_CREATE)
1800                 goto out;
1801
1802         num_buffers = msg[2];
1803         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1804                 uint32_t offset, size, *create;
1805
1806                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1807                         continue;
1808
1809                 offset = msg[1];
1810                 size = msg[2];
1811
1812                 if (offset + size > end) {
1813                         r = -EINVAL;
1814                         goto out;
1815                 }
1816
1817                 create = ptr + addr + offset - start;
1818
1819                 /* H264, HEVC and VP9 can run on any instance */
1820                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1821                         continue;
1822
1823                 r = vcn_v4_0_limit_sched(p, job);
1824                 if (r)
1825                         goto out;
1826         }
1827
1828 out:
1829         amdgpu_bo_kunmap(bo);
1830         return r;
1831 }
1832
1833 #define RADEON_VCN_ENGINE_TYPE_ENCODE                   (0x00000002)
1834 #define RADEON_VCN_ENGINE_TYPE_DECODE                   (0x00000003)
1835
1836 #define RADEON_VCN_ENGINE_INFO                          (0x30000001)
1837 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET               16
1838
1839 #define RENCODE_ENCODE_STANDARD_AV1                     2
1840 #define RENCODE_IB_PARAM_SESSION_INIT                   0x00000003
1841 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET        64
1842
1843 /* return the offset in ib if id is found, -1 otherwise
1844  * to speed up the searching we only search upto max_offset
1845  */
1846 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1847 {
1848         int i;
1849
1850         for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1851                 if (ib->ptr[i + 1] == id)
1852                         return i;
1853         }
1854         return -1;
1855 }
1856
1857 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1858                                            struct amdgpu_job *job,
1859                                            struct amdgpu_ib *ib)
1860 {
1861         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1862         struct amdgpu_vcn_decode_buffer *decode_buffer;
1863         uint64_t addr;
1864         uint32_t val;
1865         int idx;
1866
1867         /* The first instance can decode anything */
1868         if (!ring->me)
1869                 return 0;
1870
1871         /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1872         idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1873                         RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1874         if (idx < 0) /* engine info is missing */
1875                 return 0;
1876
1877         val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1878         if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1879                 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1880
1881                 if (!(decode_buffer->valid_buf_flag  & 0x1))
1882                         return 0;
1883
1884                 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1885                         decode_buffer->msg_buffer_address_lo;
1886                 return vcn_v4_0_dec_msg(p, job, addr);
1887         } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1888                 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1889                         RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1890                 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1891                         return vcn_v4_0_limit_sched(p, job);
1892         }
1893         return 0;
1894 }
1895
1896 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1897         .type = AMDGPU_RING_TYPE_VCN_ENC,
1898         .align_mask = 0x3f,
1899         .nop = VCN_ENC_CMD_NO_OP,
1900         .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata),
1901         .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1902         .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1903         .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1904         .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
1905         .emit_frame_size =
1906                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1907                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1908                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1909                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1910                 1, /* vcn_v2_0_enc_ring_insert_end */
1911         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1912         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1913         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1914         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1915         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1916         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1917         .insert_nop = amdgpu_ring_insert_nop,
1918         .insert_end = vcn_v2_0_enc_ring_insert_end,
1919         .pad_ib = amdgpu_ring_generic_pad_ib,
1920         .begin_use = amdgpu_vcn_ring_begin_use,
1921         .end_use = amdgpu_vcn_ring_end_use,
1922         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1923         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1924         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1925 };
1926
1927 /**
1928  * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
1929  *
1930  * @adev: amdgpu_device pointer
1931  *
1932  * Set unified ring functions
1933  */
1934 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
1935 {
1936         int i;
1937
1938         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1939                 if (adev->vcn.harvest_config & (1 << i))
1940                         continue;
1941
1942                 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
1943                         vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
1944
1945                 adev->vcn.inst[i].ring_enc[0].funcs =
1946                        (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
1947                 adev->vcn.inst[i].ring_enc[0].me = i;
1948         }
1949 }
1950
1951 /**
1952  * vcn_v4_0_is_idle - check VCN block is idle
1953  *
1954  * @handle: amdgpu_device pointer
1955  *
1956  * Check whether VCN block is idle
1957  */
1958 static bool vcn_v4_0_is_idle(void *handle)
1959 {
1960         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1961         int i, ret = 1;
1962
1963         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1964                 if (adev->vcn.harvest_config & (1 << i))
1965                         continue;
1966
1967                 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1968         }
1969
1970         return ret;
1971 }
1972
1973 /**
1974  * vcn_v4_0_wait_for_idle - wait for VCN block idle
1975  *
1976  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
1977  *
1978  * Wait for VCN block idle
1979  */
1980 static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1981 {
1982         struct amdgpu_device *adev = ip_block->adev;
1983         int i, ret = 0;
1984
1985         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1986                 if (adev->vcn.harvest_config & (1 << i))
1987                         continue;
1988
1989                 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1990                         UVD_STATUS__IDLE);
1991                 if (ret)
1992                         return ret;
1993         }
1994
1995         return ret;
1996 }
1997
1998 /**
1999  * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
2000  *
2001  * @handle: amdgpu_device pointer
2002  * @state: clock gating state
2003  *
2004  * Set VCN block clockgating state
2005  */
2006 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
2007 {
2008         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2009         bool enable = state == AMD_CG_STATE_GATE;
2010         int i;
2011
2012         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2013                 if (adev->vcn.harvest_config & (1 << i))
2014                         continue;
2015
2016                 if (enable) {
2017                         if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
2018                                 return -EBUSY;
2019                         vcn_v4_0_enable_clock_gating(adev, i);
2020                 } else {
2021                         vcn_v4_0_disable_clock_gating(adev, i);
2022                 }
2023         }
2024
2025         return 0;
2026 }
2027
2028 /**
2029  * vcn_v4_0_set_powergating_state - set VCN block powergating state
2030  *
2031  * @handle: amdgpu_device pointer
2032  * @state: power gating state
2033  *
2034  * Set VCN block powergating state
2035  */
2036 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
2037 {
2038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2039         int ret;
2040
2041         /* for SRIOV, guest should not control VCN Power-gating
2042          * MMSCH FW should control Power-gating and clock-gating
2043          * guest should avoid touching CGC and PG
2044          */
2045         if (amdgpu_sriov_vf(adev)) {
2046                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2047                 return 0;
2048         }
2049
2050         if (state == adev->vcn.cur_state)
2051                 return 0;
2052
2053         if (state == AMD_PG_STATE_GATE)
2054                 ret = vcn_v4_0_stop(adev);
2055         else
2056                 ret = vcn_v4_0_start(adev);
2057
2058         if (!ret)
2059                 adev->vcn.cur_state = state;
2060
2061         return ret;
2062 }
2063
2064 /**
2065  * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state
2066  *
2067  * @adev: amdgpu_device pointer
2068  * @source: interrupt sources
2069  * @type: interrupt types
2070  * @state: interrupt states
2071  *
2072  * Set VCN block RAS interrupt state
2073  */
2074 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
2075         struct amdgpu_irq_src *source,
2076         unsigned int type,
2077         enum amdgpu_interrupt_state state)
2078 {
2079         return 0;
2080 }
2081
2082 /**
2083  * vcn_v4_0_process_interrupt - process VCN block interrupt
2084  *
2085  * @adev: amdgpu_device pointer
2086  * @source: interrupt sources
2087  * @entry: interrupt entry from clients and sources
2088  *
2089  * Process VCN block interrupt
2090  */
2091 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
2092       struct amdgpu_iv_entry *entry)
2093 {
2094         uint32_t ip_instance;
2095
2096         if (amdgpu_sriov_is_vcn_rb_decouple(adev)) {
2097                 ip_instance = entry->ring_id;
2098         } else {
2099                 switch (entry->client_id) {
2100                 case SOC15_IH_CLIENTID_VCN:
2101                         ip_instance = 0;
2102                         break;
2103                 case SOC15_IH_CLIENTID_VCN1:
2104                         ip_instance = 1;
2105                         break;
2106                 default:
2107                         DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2108                         return 0;
2109                 }
2110         }
2111
2112         DRM_DEBUG("IH: VCN TRAP\n");
2113
2114         switch (entry->src_id) {
2115         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2116                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2117                 break;
2118         default:
2119                 DRM_ERROR("Unhandled interrupt: %d %d\n",
2120                           entry->src_id, entry->src_data[0]);
2121                 break;
2122         }
2123
2124         return 0;
2125 }
2126
2127 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
2128         .process = vcn_v4_0_process_interrupt,
2129 };
2130
2131 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
2132         .set = vcn_v4_0_set_ras_interrupt_state,
2133         .process = amdgpu_vcn_process_poison_irq,
2134 };
2135
2136 /**
2137  * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
2138  *
2139  * @adev: amdgpu_device pointer
2140  *
2141  * Set VCN block interrupt irq functions
2142  */
2143 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2144 {
2145         int i;
2146
2147         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2148                 if (adev->vcn.harvest_config & (1 << i))
2149                         continue;
2150
2151                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2152                 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
2153
2154                 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
2155                 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
2156         }
2157 }
2158
2159 static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2160 {
2161         struct amdgpu_device *adev = ip_block->adev;
2162         int i, j;
2163         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
2164         uint32_t inst_off, is_powered;
2165
2166         if (!adev->vcn.ip_dump)
2167                 return;
2168
2169         drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2170         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2171                 if (adev->vcn.harvest_config & (1 << i)) {
2172                         drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2173                         continue;
2174                 }
2175
2176                 inst_off = i * reg_count;
2177                 is_powered = (adev->vcn.ip_dump[inst_off] &
2178                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2179
2180                 if (is_powered) {
2181                         drm_printf(p, "\nActive Instance:VCN%d\n", i);
2182                         for (j = 0; j < reg_count; j++)
2183                                 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
2184                                            adev->vcn.ip_dump[inst_off + j]);
2185                 } else {
2186                         drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2187                 }
2188         }
2189 }
2190
2191 static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2192 {
2193         struct amdgpu_device *adev = ip_block->adev;
2194         int i, j;
2195         bool is_powered;
2196         uint32_t inst_off;
2197         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
2198
2199         if (!adev->vcn.ip_dump)
2200                 return;
2201
2202         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2203                 if (adev->vcn.harvest_config & (1 << i))
2204                         continue;
2205
2206                 inst_off = i * reg_count;
2207                 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
2208                 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
2209                 is_powered = (adev->vcn.ip_dump[inst_off] &
2210                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2211
2212                 if (is_powered)
2213                         for (j = 1; j < reg_count; j++)
2214                                 adev->vcn.ip_dump[inst_off + j] =
2215                                         RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
2216                                                                            i));
2217         }
2218 }
2219
2220 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
2221         .name = "vcn_v4_0",
2222         .early_init = vcn_v4_0_early_init,
2223         .sw_init = vcn_v4_0_sw_init,
2224         .sw_fini = vcn_v4_0_sw_fini,
2225         .hw_init = vcn_v4_0_hw_init,
2226         .hw_fini = vcn_v4_0_hw_fini,
2227         .suspend = vcn_v4_0_suspend,
2228         .resume = vcn_v4_0_resume,
2229         .is_idle = vcn_v4_0_is_idle,
2230         .wait_for_idle = vcn_v4_0_wait_for_idle,
2231         .set_clockgating_state = vcn_v4_0_set_clockgating_state,
2232         .set_powergating_state = vcn_v4_0_set_powergating_state,
2233         .dump_ip_state = vcn_v4_0_dump_ip_state,
2234         .print_ip_state = vcn_v4_0_print_ip_state,
2235 };
2236
2237 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
2238         .type = AMD_IP_BLOCK_TYPE_VCN,
2239         .major = 4,
2240         .minor = 0,
2241         .rev = 0,
2242         .funcs = &vcn_v4_0_ip_funcs,
2243 };
2244
2245 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2246                         uint32_t instance, uint32_t sub_block)
2247 {
2248         uint32_t poison_stat = 0, reg_value = 0;
2249
2250         switch (sub_block) {
2251         case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2252                 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2253                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2254                 break;
2255         default:
2256                 break;
2257         }
2258
2259         if (poison_stat)
2260                 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2261                         instance, sub_block);
2262
2263         return poison_stat;
2264 }
2265
2266 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2267 {
2268         uint32_t inst, sub;
2269         uint32_t poison_stat = 0;
2270
2271         for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2272                 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2273                         poison_stat +=
2274                                 vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2275
2276         return !!poison_stat;
2277 }
2278
2279 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2280         .query_poison_status = vcn_v4_0_query_ras_poison_status,
2281 };
2282
2283 static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2284         .ras_block = {
2285                 .hw_ops = &vcn_v4_0_ras_hw_ops,
2286                 .ras_late_init = amdgpu_vcn_ras_late_init,
2287         },
2288 };
2289
2290 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2291 {
2292         switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2293         case IP_VERSION(4, 0, 0):
2294                 adev->vcn.ras = &vcn_v4_0_ras;
2295                 break;
2296         default:
2297                 break;
2298         }
2299 }