drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_cs.h"
  28 #include "amdgpu_vcn.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15.h"
  31 #include "soc15d.h"
  32 #include "soc15_common.h"
  33
  34 #include "vcn/vcn_1_0_offset.h"
  35 #include "vcn/vcn_1_0_sh_mask.h"
  36 #include "mmhub/mmhub_9_1_offset.h"
  37 #include "mmhub/mmhub_9_1_sh_mask.h"
  38
  39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  40 #include "jpeg_v1_0.h"
  41 #include "vcn_v1_0.h"
  42
  43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0           0x05ab
  44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX  1
  45 #define mmUVD_REG_XX_MASK_1_0                   0x05ac
  46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX          1
  47
  48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {
  49         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
  50         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
  51         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
  52         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
  53         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
  54         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
  55         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
  56         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
  57         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
  58         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
  59         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
  60         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
  61         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
  62         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
  63         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
  64         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
  65         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
  66         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
  67         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
  68         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
  69         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
  70         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
  71         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
  72         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
  73         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
  74         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
  75         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
  76         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
  77         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
  78         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
  79         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
  80         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
  81         SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
  82 };
  83
  84 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  85 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  86 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  87 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  88 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
  89 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
  90                                 int inst_idx, struct dpg_pause_state *new_state);
  91
  92 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
  93 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
  94
  95 /**
  96  * vcn_v1_0_early_init - set function pointers and load microcode
  97  *
  98  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
  99  *
 100  * Set ring and irq function pointers
 101  * Load microcode from filesystem
 102  */
 103 static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
 104 {
 105         struct amdgpu_device *adev = ip_block->adev;
 106
 107         adev->vcn.num_enc_rings = 2;
 108
 109         vcn_v1_0_set_dec_ring_funcs(adev);
 110         vcn_v1_0_set_enc_ring_funcs(adev);
 111         vcn_v1_0_set_irq_funcs(adev);
 112
 113         jpeg_v1_0_early_init(ip_block);
 114
 115         return amdgpu_vcn_early_init(adev);
 116 }
 117
 118 /**
 119  * vcn_v1_0_sw_init - sw init for VCN block
 120  *
 121  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 122  *
 123  * Load firmware and sw initialization
 124  */
 125 static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
 126 {
 127         struct amdgpu_ring *ring;
 128         int i, r;
 129         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
 130         uint32_t *ptr;
 131         struct amdgpu_device *adev = ip_block->adev;
 132
 133         /* VCN DEC TRAP */
 134         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 135                         VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
 136         if (r)
 137                 return r;
 138
 139         /* VCN ENC TRAP */
 140         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 141                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
 142                                         &adev->vcn.inst->irq);
 143                 if (r)
 144                         return r;
 145         }
 146
 147         r = amdgpu_vcn_sw_init(adev);
 148         if (r)
 149                 return r;
 150
 151         /* Override the work func */
 152         adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
 153
 154         amdgpu_vcn_setup_ucode(adev);
 155
 156         r = amdgpu_vcn_resume(adev);
 157         if (r)
 158                 return r;
 159
 160         ring = &adev->vcn.inst->ring_dec;
 161         ring->vm_hub = AMDGPU_MMHUB0(0);
 162         sprintf(ring->name, "vcn_dec");
 163         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 164                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 165         if (r)
 166                 return r;
 167
 168         adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
 169                 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
 170         adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
 171                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
 172         adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
 173                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
 174         adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
 175                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
 176         adev->vcn.internal.nop = adev->vcn.inst->external.nop =
 177                 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 178
 179         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 180                 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
 181
 182                 ring = &adev->vcn.inst->ring_enc[i];
 183                 ring->vm_hub = AMDGPU_MMHUB0(0);
 184                 sprintf(ring->name, "vcn_enc%d", i);
 185                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 186                                      hw_prio, NULL);
 187                 if (r)
 188                         return r;
 189         }
 190
 191         adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
 192
 193         if (amdgpu_vcnfw_log) {
 194                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
 195
 196                 fw_shared->present_flag_0 = 0;
 197                 amdgpu_vcn_fwlog_init(adev->vcn.inst);
 198         }
 199
 200         r = jpeg_v1_0_sw_init(ip_block);
 201
 202         /* Allocate memory for VCN IP Dump buffer */
 203         ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
 204         if (!ptr) {
 205                 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
 206                 adev->vcn.ip_dump = NULL;
 207         } else {
 208                 adev->vcn.ip_dump = ptr;
 209         }
 210         return r;
 211 }
 212
 213 /**
 214  * vcn_v1_0_sw_fini - sw fini for VCN block
 215  *
 216  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 217  *
 218  * VCN suspend and free up sw allocation
 219  */
 220 static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
 221 {
 222         int r;
 223         struct amdgpu_device *adev = ip_block->adev;
 224
 225         r = amdgpu_vcn_suspend(adev);
 226         if (r)
 227                 return r;
 228
 229         jpeg_v1_0_sw_fini(ip_block);
 230
 231         r = amdgpu_vcn_sw_fini(adev);
 232
 233         kfree(adev->vcn.ip_dump);
 234
 235         return r;
 236 }
 237
 238 /**
 239  * vcn_v1_0_hw_init - start and test VCN block
 240  *
 241  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 242  *
 243  * Initialize the hardware, boot up the VCPU and do some testing
 244  */
 245 static int vcn_v1_0_hw_init(struct amdgpu_ip_block *ip_block)
 246 {
 247         struct amdgpu_device *adev = ip_block->adev;
 248         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 249         int i, r;
 250
 251         r = amdgpu_ring_test_helper(ring);
 252         if (r)
 253                 return r;
 254
 255         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 256                 ring = &adev->vcn.inst->ring_enc[i];
 257                 r = amdgpu_ring_test_helper(ring);
 258                 if (r)
 259                         return r;
 260         }
 261
 262         ring = adev->jpeg.inst->ring_dec;
 263         r = amdgpu_ring_test_helper(ring);
 264
 265         return r;
 266 }
 267
 268 /**
 269  * vcn_v1_0_hw_fini - stop the hardware block
 270  *
 271  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 272  *
 273  * Stop the VCN block, mark ring as not ready any more
 274  */
 275 static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
 276 {
 277         struct amdgpu_device *adev = ip_block->adev;
 278
 279         cancel_delayed_work_sync(&adev->vcn.idle_work);
 280
 281         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 282                 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 283                  RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
 284                 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 285         }
 286
 287         return 0;
 288 }
 289
 290 /**
 291  * vcn_v1_0_suspend - suspend VCN block
 292  *
 293  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 294  *
 295  * HW fini and suspend VCN block
 296  */
 297 static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
 298 {
 299         int r;
 300         struct amdgpu_device *adev = ip_block->adev;
 301         bool idle_work_unexecuted;
 302
 303         idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
 304         if (idle_work_unexecuted) {
 305                 if (adev->pm.dpm_enabled)
 306                         amdgpu_dpm_enable_uvd(adev, false);
 307         }
 308
 309         r = vcn_v1_0_hw_fini(ip_block);
 310         if (r)
 311                 return r;
 312
 313         r = amdgpu_vcn_suspend(adev);
 314
 315         return r;
 316 }
 317
 318 /**
 319  * vcn_v1_0_resume - resume VCN block
 320  *
 321  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 322  *
 323  * Resume firmware and hw init VCN block
 324  */
 325 static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
 326 {
 327         int r;
 328
 329         r = amdgpu_vcn_resume(ip_block->adev);
 330         if (r)
 331                 return r;
 332
 333         r = vcn_v1_0_hw_init(ip_block);
 334
 335         return r;
 336 }
 337
 338 /**
 339  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 340  *
 341  * @adev: amdgpu_device pointer
 342  *
 343  * Let the VCN memory controller know it's offsets
 344  */
 345 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 346 {
 347         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
 348         uint32_t offset;
 349
 350         /* cache window 0: fw */
 351         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 352                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 353                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 354                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 355                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 356                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 357                 offset = 0;
 358         } else {
 359                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 360                         lower_32_bits(adev->vcn.inst->gpu_addr));
 361                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 362                         upper_32_bits(adev->vcn.inst->gpu_addr));
 363                 offset = size;
 364                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 365                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 366         }
 367
 368         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 369
 370         /* cache window 1: stack */
 371         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 372                      lower_32_bits(adev->vcn.inst->gpu_addr + offset));
 373         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 374                      upper_32_bits(adev->vcn.inst->gpu_addr + offset));
 375         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 376         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 377
 378         /* cache window 2: context */
 379         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 380                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 381         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 382                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 383         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 384         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 385
 386         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 387                         adev->gfx.config.gb_addr_config);
 388         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 389                         adev->gfx.config.gb_addr_config);
 390         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 391                         adev->gfx.config.gb_addr_config);
 392         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 393                         adev->gfx.config.gb_addr_config);
 394         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 395                         adev->gfx.config.gb_addr_config);
 396         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 397                         adev->gfx.config.gb_addr_config);
 398         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 399                         adev->gfx.config.gb_addr_config);
 400         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 401                         adev->gfx.config.gb_addr_config);
 402         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 403                         adev->gfx.config.gb_addr_config);
 404         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 405                         adev->gfx.config.gb_addr_config);
 406         WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 407                         adev->gfx.config.gb_addr_config);
 408         WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 409                         adev->gfx.config.gb_addr_config);
 410 }
 411
 412 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 413 {
 414         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
 415         uint32_t offset;
 416
 417         /* cache window 0: fw */
 418         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 419                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 420                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 421                              0xFFFFFFFF, 0);
 422                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 423                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 424                              0xFFFFFFFF, 0);
 425                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 426                              0xFFFFFFFF, 0);
 427                 offset = 0;
 428         } else {
 429                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 430                         lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 431                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 432                         upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 433                 offset = size;
 434                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 435                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 436         }
 437
 438         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 439
 440         /* cache window 1: stack */
 441         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 442                      lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 443         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 444                      upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 445         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 446                              0xFFFFFFFF, 0);
 447         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 448                              0xFFFFFFFF, 0);
 449
 450         /* cache window 2: context */
 451         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 452                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 453                              0xFFFFFFFF, 0);
 454         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 455                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 456                              0xFFFFFFFF, 0);
 457         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 458         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 459                              0xFFFFFFFF, 0);
 460
 461         /* VCN global tiling registers */
 462         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 463                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 464         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 465                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 466         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 467                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 468         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 469                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 470         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 471                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 472         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 473                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 474         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 475                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 476         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 477                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 478         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 479                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 480         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 481                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 482 }
 483
 484 /**
 485  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 486  *
 487  * @adev: amdgpu_device pointer
 488  *
 489  * Disable clock gating for VCN block
 490  */
 491 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 492 {
 493         uint32_t data;
 494
 495         /* JPEG disable CGC */
 496         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 497
 498         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 499                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 500         else
 501                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 502
 503         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 504         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 505         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 506
 507         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 508         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 509         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 510
 511         /* UVD disable CGC */
 512         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 513         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 514                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 515         else
 516                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 517
 518         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 519         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 520         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 521
 522         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 523         data &= ~(UVD_CGC_GATE__SYS_MASK
 524                 | UVD_CGC_GATE__UDEC_MASK
 525                 | UVD_CGC_GATE__MPEG2_MASK
 526                 | UVD_CGC_GATE__REGS_MASK
 527                 | UVD_CGC_GATE__RBC_MASK
 528                 | UVD_CGC_GATE__LMI_MC_MASK
 529                 | UVD_CGC_GATE__LMI_UMC_MASK
 530                 | UVD_CGC_GATE__IDCT_MASK
 531                 | UVD_CGC_GATE__MPRD_MASK
 532                 | UVD_CGC_GATE__MPC_MASK
 533                 | UVD_CGC_GATE__LBSI_MASK
 534                 | UVD_CGC_GATE__LRBBM_MASK
 535                 | UVD_CGC_GATE__UDEC_RE_MASK
 536                 | UVD_CGC_GATE__UDEC_CM_MASK
 537                 | UVD_CGC_GATE__UDEC_IT_MASK
 538                 | UVD_CGC_GATE__UDEC_DB_MASK
 539                 | UVD_CGC_GATE__UDEC_MP_MASK
 540                 | UVD_CGC_GATE__WCB_MASK
 541                 | UVD_CGC_GATE__VCPU_MASK
 542                 | UVD_CGC_GATE__SCPU_MASK);
 543         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 544
 545         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 546         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 547                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 548                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 549                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 550                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 551                 | UVD_CGC_CTRL__SYS_MODE_MASK
 552                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 553                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 554                 | UVD_CGC_CTRL__REGS_MODE_MASK
 555                 | UVD_CGC_CTRL__RBC_MODE_MASK
 556                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 557                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 558                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 559                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 560                 | UVD_CGC_CTRL__MPC_MODE_MASK
 561                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 562                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 563                 | UVD_CGC_CTRL__WCB_MODE_MASK
 564                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 565                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 566         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 567
 568         /* turn on */
 569         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 570         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 571                 | UVD_SUVD_CGC_GATE__SIT_MASK
 572                 | UVD_SUVD_CGC_GATE__SMP_MASK
 573                 | UVD_SUVD_CGC_GATE__SCM_MASK
 574                 | UVD_SUVD_CGC_GATE__SDB_MASK
 575                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 576                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 577                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 578                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 579                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 580                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 581                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 582                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 583                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 584                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 585                 | UVD_SUVD_CGC_GATE__ENT_MASK
 586                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 587                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 588                 | UVD_SUVD_CGC_GATE__SITE_MASK
 589                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 590                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 591                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 592                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 593                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 594         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 595
 596         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 597         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 598                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 599                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 600                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 601                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 602                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 603                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 604                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 605                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 606                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 607         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 608 }
 609
 610 /**
 611  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Enable clock gating for VCN block
 616  */
 617 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 618 {
 619         uint32_t data = 0;
 620
 621         /* enable JPEG CGC */
 622         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 623         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 624                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 625         else
 626                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 627         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 628         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 629         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 630
 631         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 632         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 633         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 634
 635         /* enable UVD CGC */
 636         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 637         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 638                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 639         else
 640                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 641         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 642         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 643         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 644
 645         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 646         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 647                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 648                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 649                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 650                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 651                 | UVD_CGC_CTRL__SYS_MODE_MASK
 652                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 653                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 654                 | UVD_CGC_CTRL__REGS_MODE_MASK
 655                 | UVD_CGC_CTRL__RBC_MODE_MASK
 656                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 657                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 658                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 659                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 660                 | UVD_CGC_CTRL__MPC_MODE_MASK
 661                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 662                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 663                 | UVD_CGC_CTRL__WCB_MODE_MASK
 664                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 665                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 666         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 667
 668         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 669         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 670                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 671                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 672                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 673                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 674                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 675                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 676                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 677                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 678                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 679         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 680 }
 681
 682 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 683 {
 684         uint32_t reg_data = 0;
 685
 686         /* disable JPEG CGC */
 687         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 688                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 689         else
 690                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 691         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 692         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 693         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 694
 695         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 696
 697         /* enable sw clock gating control */
 698         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 699                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 700         else
 701                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 702         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 703         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 704         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 705                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 706                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 707                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 708                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 709                  UVD_CGC_CTRL__SYS_MODE_MASK |
 710                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 711                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 712                  UVD_CGC_CTRL__REGS_MODE_MASK |
 713                  UVD_CGC_CTRL__RBC_MODE_MASK |
 714                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 715                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 716                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 717                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 718                  UVD_CGC_CTRL__MPC_MODE_MASK |
 719                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 720                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 721                  UVD_CGC_CTRL__WCB_MODE_MASK |
 722                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 723                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 724         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 725
 726         /* turn off clock gating */
 727         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 728
 729         /* turn on SUVD clock gating */
 730         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 731
 732         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 733         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 734 }
 735
 736 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 737 {
 738         uint32_t data = 0;
 739
 740         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 741                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 742                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 743                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 744                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 745                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 746                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 747                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 748                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 749                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 750                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 751                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 752
 753                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 754                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
 755         } else {
 756                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 757                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 758                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 759                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 760                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 761                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 762                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 763                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 764                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 765                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 766                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 767                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 768                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);
 769         }
 770
 771         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 772
 773         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 774         data &= ~0x103;
 775         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 776                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 777
 778         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 779 }
 780
 781 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 782 {
 783         uint32_t data = 0;
 784
 785         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 786                 /* Before power off, this indicator has to be turned on */
 787                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 788                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 789                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 790                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 791
 792
 793                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 794                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 795                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 796                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 797                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 798                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 799                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 800                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 801                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 802                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 803                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 804
 805                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 806
 807                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 808                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 809                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 810                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 811                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 812                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 813                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 814                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 815                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 816                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 817                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 818                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
 819         }
 820 }
 821
 822 /**
 823  * vcn_v1_0_start_spg_mode - start VCN block
 824  *
 825  * @adev: amdgpu_device pointer
 826  *
 827  * Setup and start the VCN block
 828  */
 829 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 830 {
 831         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 832         uint32_t rb_bufsz, tmp;
 833         uint32_t lmi_swap_cntl;
 834         int i, j, r;
 835
 836         /* disable byte swapping */
 837         lmi_swap_cntl = 0;
 838
 839         vcn_1_0_disable_static_power_gating(adev);
 840
 841         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 842         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 843
 844         /* disable clock gating */
 845         vcn_v1_0_disable_clock_gating(adev);
 846
 847         /* disable interupt */
 848         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 849                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 850
 851         /* initialize VCN memory controller */
 852         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 853         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
 854                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 855                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
 856                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
 857                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 858
 859 #ifdef __BIG_ENDIAN
 860         /* swap (8 in 32) RB and IB */
 861         lmi_swap_cntl = 0xa;
 862 #endif
 863         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 864
 865         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 866         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 867         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 868         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 869
 870         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 871                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 872                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 873                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 874                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 875
 876         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 877                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 878                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 879                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 880                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 881
 882         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 883                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 884                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 885                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 886
 887         vcn_v1_0_mc_resume_spg_mode(adev);
 888
 889         WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
 890         WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
 891                 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
 892
 893         /* enable VCPU clock */
 894         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 895
 896         /* boot up the VCPU */
 897         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 898                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 899
 900         /* enable UMC */
 901         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 902                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 903
 904         tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
 905         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 906         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 907         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
 908
 909         for (i = 0; i < 10; ++i) {
 910                 uint32_t status;
 911
 912                 for (j = 0; j < 100; ++j) {
 913                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 914                         if (status & UVD_STATUS__IDLE)
 915                                 break;
 916                         mdelay(10);
 917                 }
 918                 r = 0;
 919                 if (status & UVD_STATUS__IDLE)
 920                         break;
 921
 922                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 923                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 924                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 925                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 926                 mdelay(10);
 927                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 928                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 929                 mdelay(10);
 930                 r = -1;
 931         }
 932
 933         if (r) {
 934                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 935                 return r;
 936         }
 937         /* enable master interrupt */
 938         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 939                 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 940
 941         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 942         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 943                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 944                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 945
 946         /* clear the busy bit of UVD_STATUS */
 947         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
 948         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 949
 950         /* force RBC into idle state */
 951         rb_bufsz = order_base_2(ring->ring_size);
 952         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 953         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 954         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 955         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 956         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 957         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 958
 959         /* set the write pointer delay */
 960         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 961
 962         /* set the wb address */
 963         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 964                         (upper_32_bits(ring->gpu_addr) >> 2));
 965
 966         /* program the RB_BASE for ring buffer */
 967         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 968                         lower_32_bits(ring->gpu_addr));
 969         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 970                         upper_32_bits(ring->gpu_addr));
 971
 972         /* Initialize the ring buffer's read and write pointers */
 973         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 974
 975         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 976
 977         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 978         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 979                         lower_32_bits(ring->wptr));
 980
 981         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 982                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 983
 984         ring = &adev->vcn.inst->ring_enc[0];
 985         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 986         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 987         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 988         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 989         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 990
 991         ring = &adev->vcn.inst->ring_enc[1];
 992         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 993         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 994         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 995         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 996         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 997
 998         jpeg_v1_0_start(adev, 0);
 999
1000         return 0;
1001 }
1002
1003 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
1004 {
1005         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1006         uint32_t rb_bufsz, tmp;
1007         uint32_t lmi_swap_cntl;
1008
1009         /* disable byte swapping */
1010         lmi_swap_cntl = 0;
1011
1012         vcn_1_0_enable_static_power_gating(adev);
1013
1014         /* enable dynamic power gating mode */
1015         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1016         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
1017         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
1018         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
1019
1020         /* enable clock gating */
1021         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
1022
1023         /* enable VCPU clock */
1024         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1025         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1026         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
1027         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
1028
1029         /* disable interupt */
1030         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1031                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1032
1033         /* initialize VCN memory controller */
1034         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1035                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1036                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1037                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1038                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1039                 UVD_LMI_CTRL__REQ_MODE_MASK |
1040                 UVD_LMI_CTRL__CRC_RESET_MASK |
1041                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1042                 0x00100000L, 0xFFFFFFFF, 0);
1043
1044 #ifdef __BIG_ENDIAN
1045         /* swap (8 in 32) RB and IB */
1046         lmi_swap_cntl = 0xa;
1047 #endif
1048         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1049
1050         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1051                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1052
1053         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1054                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1055                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1056                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1057                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1058
1059         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1060                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1061                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1062                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1063                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1064
1065         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1066                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1067                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1068                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1069
1070         vcn_v1_0_mc_resume_dpg_mode(adev);
1071
1072         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1073         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1074
1075         /* boot up the VCPU */
1076         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1077
1078         /* enable UMC */
1079         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1080                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1081                 0xFFFFFFFF, 0);
1082
1083         /* enable master interrupt */
1084         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1085                         UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1086
1087         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1088         /* setup mmUVD_LMI_CTRL */
1089         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1090                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1091                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1092                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1093                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1094                 UVD_LMI_CTRL__REQ_MODE_MASK |
1095                 UVD_LMI_CTRL__CRC_RESET_MASK |
1096                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1097                 0x00100000L, 0xFFFFFFFF, 1);
1098
1099         tmp = adev->gfx.config.gb_addr_config;
1100         /* setup VCN global tiling registers */
1101         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1102         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1103
1104         /* enable System Interrupt for JRBC */
1105         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1106                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1107
1108         /* force RBC into idle state */
1109         rb_bufsz = order_base_2(ring->ring_size);
1110         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1111         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1112         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1113         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1114         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1115         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1116
1117         /* set the write pointer delay */
1118         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1119
1120         /* set the wb address */
1121         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1122                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1123
1124         /* program the RB_BASE for ring buffer */
1125         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1126                                                                 lower_32_bits(ring->gpu_addr));
1127         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1128                                                                 upper_32_bits(ring->gpu_addr));
1129
1130         /* Initialize the ring buffer's read and write pointers */
1131         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1132
1133         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1134
1135         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1136         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1137                                                                 lower_32_bits(ring->wptr));
1138
1139         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1140                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1141
1142         jpeg_v1_0_start(adev, 1);
1143
1144         return 0;
1145 }
1146
1147 static int vcn_v1_0_start(struct amdgpu_device *adev)
1148 {
1149         return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ?
1150                 vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev);
1151 }
1152
1153 /**
1154  * vcn_v1_0_stop_spg_mode - stop VCN block
1155  *
1156  * @adev: amdgpu_device pointer
1157  *
1158  * stop the VCN block
1159  */
1160 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1161 {
1162         int tmp;
1163
1164         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1165
1166         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1167                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1168                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1169                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1170         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1171
1172         /* stall UMC channel */
1173         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1174                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1175                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1176
1177         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1178                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1179         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1180
1181         /* disable VCPU clock */
1182         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1183                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1184
1185         /* reset LMI UMC/LMI */
1186         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1187                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1188                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1189
1190         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1191                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1192                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1193
1194         /* put VCPU into reset */
1195         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1196                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1197                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1198
1199         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1200
1201         vcn_v1_0_enable_clock_gating(adev);
1202         vcn_1_0_enable_static_power_gating(adev);
1203         return 0;
1204 }
1205
1206 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1207 {
1208         uint32_t tmp;
1209
1210         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1211         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1212                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1213                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1214
1215         /* wait for read ptr to be equal to write ptr */
1216         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1217         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1218
1219         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1220         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1221
1222         tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1223         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1224
1225         tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1226         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1227
1228         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1229                 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1230                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1231
1232         /* disable dynamic power gating mode */
1233         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1234                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1235
1236         return 0;
1237 }
1238
1239 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1240 {
1241         int r;
1242
1243         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1244                 r = vcn_v1_0_stop_dpg_mode(adev);
1245         else
1246                 r = vcn_v1_0_stop_spg_mode(adev);
1247
1248         return r;
1249 }
1250
1251 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1252                                 int inst_idx, struct dpg_pause_state *new_state)
1253 {
1254         int ret_code;
1255         uint32_t reg_data = 0;
1256         uint32_t reg_data2 = 0;
1257         struct amdgpu_ring *ring;
1258
1259         /* pause/unpause if state is changed */
1260         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1261                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1262                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1263                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1264                         new_state->fw_based, new_state->jpeg);
1265
1266                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1267                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1268
1269                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1270                         ret_code = 0;
1271
1272                         if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1273                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1274                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1275                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1276
1277                         if (!ret_code) {
1278                                 /* pause DPG non-jpeg */
1279                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1280                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1281                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1282                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1283                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1284
1285                                 /* Restore */
1286                                 ring = &adev->vcn.inst->ring_enc[0];
1287                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1288                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1289                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1290                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1291                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1292
1293                                 ring = &adev->vcn.inst->ring_enc[1];
1294                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1295                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1296                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1297                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1298                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1299
1300                                 ring = &adev->vcn.inst->ring_dec;
1301                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1302                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1303                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1304                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1305                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1306                         }
1307                 } else {
1308                         /* unpause dpg non-jpeg, no need to wait */
1309                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1310                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1311                 }
1312                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1313         }
1314
1315         /* pause/unpause if state is changed */
1316         if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1317                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1318                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1319                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1320                         new_state->fw_based, new_state->jpeg);
1321
1322                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1323                         (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1324
1325                 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1326                         ret_code = 0;
1327
1328                         if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1329                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1330                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1331                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1332
1333                         if (!ret_code) {
1334                                 /* Make sure JPRG Snoop is disabled before sending the pause */
1335                                 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1336                                 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1337                                 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1338
1339                                 /* pause DPG jpeg */
1340                                 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1341                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1342                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1343                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1344                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1345
1346                                 /* Restore */
1347                                 ring = adev->jpeg.inst->ring_dec;
1348                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1349                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1350                                                         UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1351                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1352                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1353                                                         lower_32_bits(ring->gpu_addr));
1354                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1355                                                         upper_32_bits(ring->gpu_addr));
1356                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1357                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1358                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1359                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1360
1361                                 ring = &adev->vcn.inst->ring_dec;
1362                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1363                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1364                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1365                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1366                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1367                         }
1368                 } else {
1369                         /* unpause dpg jpeg, no need to wait */
1370                         reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1371                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1372                 }
1373                 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1374         }
1375
1376         return 0;
1377 }
1378
1379 static bool vcn_v1_0_is_idle(void *handle)
1380 {
1381         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1382
1383         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1384 }
1385
1386 static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1387 {
1388         struct amdgpu_device *adev = ip_block->adev;
1389         int ret;
1390
1391         ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1392                 UVD_STATUS__IDLE);
1393
1394         return ret;
1395 }
1396
1397 static int vcn_v1_0_set_clockgating_state(void *handle,
1398                                           enum amd_clockgating_state state)
1399 {
1400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1401         bool enable = (state == AMD_CG_STATE_GATE);
1402
1403         if (enable) {
1404                 /* wait for STATUS to clear */
1405                 if (!vcn_v1_0_is_idle(handle))
1406                         return -EBUSY;
1407                 vcn_v1_0_enable_clock_gating(adev);
1408         } else {
1409                 /* disable HW gating and enable Sw gating */
1410                 vcn_v1_0_disable_clock_gating(adev);
1411         }
1412         return 0;
1413 }
1414
1415 /**
1416  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1417  *
1418  * @ring: amdgpu_ring pointer
1419  *
1420  * Returns the current hardware read pointer
1421  */
1422 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1423 {
1424         struct amdgpu_device *adev = ring->adev;
1425
1426         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1427 }
1428
1429 /**
1430  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1431  *
1432  * @ring: amdgpu_ring pointer
1433  *
1434  * Returns the current hardware write pointer
1435  */
1436 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1437 {
1438         struct amdgpu_device *adev = ring->adev;
1439
1440         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1441 }
1442
1443 /**
1444  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1445  *
1446  * @ring: amdgpu_ring pointer
1447  *
1448  * Commits the write pointer to the hardware
1449  */
1450 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1451 {
1452         struct amdgpu_device *adev = ring->adev;
1453
1454         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1455                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1456                         lower_32_bits(ring->wptr) | 0x80000000);
1457
1458         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1459 }
1460
1461 /**
1462  * vcn_v1_0_dec_ring_insert_start - insert a start command
1463  *
1464  * @ring: amdgpu_ring pointer
1465  *
1466  * Write a start command to the ring.
1467  */
1468 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1469 {
1470         struct amdgpu_device *adev = ring->adev;
1471
1472         amdgpu_ring_write(ring,
1473                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1474         amdgpu_ring_write(ring, 0);
1475         amdgpu_ring_write(ring,
1476                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1477         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1478 }
1479
1480 /**
1481  * vcn_v1_0_dec_ring_insert_end - insert a end command
1482  *
1483  * @ring: amdgpu_ring pointer
1484  *
1485  * Write a end command to the ring.
1486  */
1487 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1488 {
1489         struct amdgpu_device *adev = ring->adev;
1490
1491         amdgpu_ring_write(ring,
1492                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1493         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1494 }
1495
1496 /**
1497  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1498  *
1499  * @ring: amdgpu_ring pointer
1500  * @addr: address
1501  * @seq: sequence number
1502  * @flags: fence related flags
1503  *
1504  * Write a fence and a trap command to the ring.
1505  */
1506 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1507                                      unsigned flags)
1508 {
1509         struct amdgpu_device *adev = ring->adev;
1510
1511         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1512
1513         amdgpu_ring_write(ring,
1514                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1515         amdgpu_ring_write(ring, seq);
1516         amdgpu_ring_write(ring,
1517                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1518         amdgpu_ring_write(ring, addr & 0xffffffff);
1519         amdgpu_ring_write(ring,
1520                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1521         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1522         amdgpu_ring_write(ring,
1523                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1524         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1525
1526         amdgpu_ring_write(ring,
1527                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1528         amdgpu_ring_write(ring, 0);
1529         amdgpu_ring_write(ring,
1530                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1531         amdgpu_ring_write(ring, 0);
1532         amdgpu_ring_write(ring,
1533                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1534         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1535 }
1536
1537 /**
1538  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1539  *
1540  * @ring: amdgpu_ring pointer
1541  * @job: job to retrieve vmid from
1542  * @ib: indirect buffer to execute
1543  * @flags: unused
1544  *
1545  * Write ring commands to execute the indirect buffer
1546  */
1547 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1548                                         struct amdgpu_job *job,
1549                                         struct amdgpu_ib *ib,
1550                                         uint32_t flags)
1551 {
1552         struct amdgpu_device *adev = ring->adev;
1553         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1554
1555         amdgpu_ring_write(ring,
1556                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1557         amdgpu_ring_write(ring, vmid);
1558
1559         amdgpu_ring_write(ring,
1560                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1561         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1562         amdgpu_ring_write(ring,
1563                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1564         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1565         amdgpu_ring_write(ring,
1566                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1567         amdgpu_ring_write(ring, ib->length_dw);
1568 }
1569
1570 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1571                                             uint32_t reg, uint32_t val,
1572                                             uint32_t mask)
1573 {
1574         struct amdgpu_device *adev = ring->adev;
1575
1576         amdgpu_ring_write(ring,
1577                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1578         amdgpu_ring_write(ring, reg << 2);
1579         amdgpu_ring_write(ring,
1580                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1581         amdgpu_ring_write(ring, val);
1582         amdgpu_ring_write(ring,
1583                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1584         amdgpu_ring_write(ring, mask);
1585         amdgpu_ring_write(ring,
1586                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1587         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1588 }
1589
1590 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1591                                             unsigned vmid, uint64_t pd_addr)
1592 {
1593         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1594         uint32_t data0, data1, mask;
1595
1596         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1597
1598         /* wait for register write */
1599         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1600         data1 = lower_32_bits(pd_addr);
1601         mask = 0xffffffff;
1602         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1603 }
1604
1605 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1606                                         uint32_t reg, uint32_t val)
1607 {
1608         struct amdgpu_device *adev = ring->adev;
1609
1610         amdgpu_ring_write(ring,
1611                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1612         amdgpu_ring_write(ring, reg << 2);
1613         amdgpu_ring_write(ring,
1614                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1615         amdgpu_ring_write(ring, val);
1616         amdgpu_ring_write(ring,
1617                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1618         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1619 }
1620
1621 /**
1622  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1623  *
1624  * @ring: amdgpu_ring pointer
1625  *
1626  * Returns the current hardware enc read pointer
1627  */
1628 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1629 {
1630         struct amdgpu_device *adev = ring->adev;
1631
1632         if (ring == &adev->vcn.inst->ring_enc[0])
1633                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1634         else
1635                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1636 }
1637
1638  /**
1639  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1640  *
1641  * @ring: amdgpu_ring pointer
1642  *
1643  * Returns the current hardware enc write pointer
1644  */
1645 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1646 {
1647         struct amdgpu_device *adev = ring->adev;
1648
1649         if (ring == &adev->vcn.inst->ring_enc[0])
1650                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1651         else
1652                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1653 }
1654
1655  /**
1656  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1657  *
1658  * @ring: amdgpu_ring pointer
1659  *
1660  * Commits the enc write pointer to the hardware
1661  */
1662 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1663 {
1664         struct amdgpu_device *adev = ring->adev;
1665
1666         if (ring == &adev->vcn.inst->ring_enc[0])
1667                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1668                         lower_32_bits(ring->wptr));
1669         else
1670                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1671                         lower_32_bits(ring->wptr));
1672 }
1673
1674 /**
1675  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1676  *
1677  * @ring: amdgpu_ring pointer
1678  * @addr: address
1679  * @seq: sequence number
1680  * @flags: fence related flags
1681  *
1682  * Write enc a fence and a trap command to the ring.
1683  */
1684 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1685                         u64 seq, unsigned flags)
1686 {
1687         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1688
1689         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1690         amdgpu_ring_write(ring, addr);
1691         amdgpu_ring_write(ring, upper_32_bits(addr));
1692         amdgpu_ring_write(ring, seq);
1693         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1694 }
1695
1696 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1697 {
1698         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1699 }
1700
1701 /**
1702  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1703  *
1704  * @ring: amdgpu_ring pointer
1705  * @job: job to retrive vmid from
1706  * @ib: indirect buffer to execute
1707  * @flags: unused
1708  *
1709  * Write enc ring commands to execute the indirect buffer
1710  */
1711 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1712                                         struct amdgpu_job *job,
1713                                         struct amdgpu_ib *ib,
1714                                         uint32_t flags)
1715 {
1716         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1717
1718         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1719         amdgpu_ring_write(ring, vmid);
1720         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1721         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1722         amdgpu_ring_write(ring, ib->length_dw);
1723 }
1724
1725 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1726                                             uint32_t reg, uint32_t val,
1727                                             uint32_t mask)
1728 {
1729         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1730         amdgpu_ring_write(ring, reg << 2);
1731         amdgpu_ring_write(ring, mask);
1732         amdgpu_ring_write(ring, val);
1733 }
1734
1735 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1736                                             unsigned int vmid, uint64_t pd_addr)
1737 {
1738         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1739
1740         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1741
1742         /* wait for reg writes */
1743         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1744                                         vmid * hub->ctx_addr_distance,
1745                                         lower_32_bits(pd_addr), 0xffffffff);
1746 }
1747
1748 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1749                                         uint32_t reg, uint32_t val)
1750 {
1751         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1752         amdgpu_ring_write(ring, reg << 2);
1753         amdgpu_ring_write(ring, val);
1754 }
1755
1756 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1757                                         struct amdgpu_irq_src *source,
1758                                         unsigned type,
1759                                         enum amdgpu_interrupt_state state)
1760 {
1761         return 0;
1762 }
1763
1764 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1765                                       struct amdgpu_irq_src *source,
1766                                       struct amdgpu_iv_entry *entry)
1767 {
1768         DRM_DEBUG("IH: VCN TRAP\n");
1769
1770         switch (entry->src_id) {
1771         case 124:
1772                 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1773                 break;
1774         case 119:
1775                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1776                 break;
1777         case 120:
1778                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1779                 break;
1780         default:
1781                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1782                           entry->src_id, entry->src_data[0]);
1783                 break;
1784         }
1785
1786         return 0;
1787 }
1788
1789 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1790 {
1791         struct amdgpu_device *adev = ring->adev;
1792         int i;
1793
1794         WARN_ON(ring->wptr % 2 || count % 2);
1795
1796         for (i = 0; i < count / 2; i++) {
1797                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1798                 amdgpu_ring_write(ring, 0);
1799         }
1800 }
1801
1802 static int vcn_v1_0_set_powergating_state(void *handle,
1803                                           enum amd_powergating_state state)
1804 {
1805         /* This doesn't actually powergate the VCN block.
1806          * That's done in the dpm code via the SMC.  This
1807          * just re-inits the block as necessary.  The actual
1808          * gating still happens in the dpm code.  We should
1809          * revisit this when there is a cleaner line between
1810          * the smc and the hw blocks
1811          */
1812         int ret;
1813         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1814
1815         if (state == adev->vcn.cur_state)
1816                 return 0;
1817
1818         if (state == AMD_PG_STATE_GATE)
1819                 ret = vcn_v1_0_stop(adev);
1820         else
1821                 ret = vcn_v1_0_start(adev);
1822
1823         if (!ret)
1824                 adev->vcn.cur_state = state;
1825         return ret;
1826 }
1827
1828 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1829 {
1830         struct amdgpu_device *adev =
1831                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1832         unsigned int fences = 0, i;
1833
1834         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1835                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1836
1837         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1838                 struct dpg_pause_state new_state;
1839
1840                 if (fences)
1841                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1842                 else
1843                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1844
1845                 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1846                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1847                 else
1848                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1849
1850                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1851         }
1852
1853         fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);
1854         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1855
1856         if (fences == 0) {
1857                 amdgpu_gfx_off_ctrl(adev, true);
1858                 if (adev->pm.dpm_enabled)
1859                         amdgpu_dpm_enable_uvd(adev, false);
1860                 else
1861                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1862                                AMD_PG_STATE_GATE);
1863         } else {
1864                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1865         }
1866 }
1867
1868 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1869 {
1870         struct  amdgpu_device *adev = ring->adev;
1871         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1872
1873         mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1874
1875         if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec))
1876                 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1877
1878         vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1879
1880 }
1881
1882 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1883 {
1884         struct amdgpu_device *adev = ring->adev;
1885
1886         if (set_clocks) {
1887                 amdgpu_gfx_off_ctrl(adev, false);
1888                 if (adev->pm.dpm_enabled)
1889                         amdgpu_dpm_enable_uvd(adev, true);
1890                 else
1891                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1892                                AMD_PG_STATE_UNGATE);
1893         }
1894
1895         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1896                 struct dpg_pause_state new_state;
1897                 unsigned int fences = 0, i;
1898
1899                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1900                         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1901
1902                 if (fences)
1903                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1904                 else
1905                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1906
1907                 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1908                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1909                 else
1910                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1911
1912                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1913                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1914                 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1915                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1916
1917                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1918         }
1919 }
1920
1921 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1922 {
1923         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1924         mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1925 }
1926
1927 static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1928 {
1929         struct amdgpu_device *adev = ip_block->adev;
1930         int i, j;
1931         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1932         uint32_t inst_off, is_powered;
1933
1934         if (!adev->vcn.ip_dump)
1935                 return;
1936
1937         drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1938         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1939                 if (adev->vcn.harvest_config & (1 << i)) {
1940                         drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1941                         continue;
1942                 }
1943
1944                 inst_off = i * reg_count;
1945                 is_powered = (adev->vcn.ip_dump[inst_off] &
1946                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1947
1948                 if (is_powered) {
1949                         drm_printf(p, "\nActive Instance:VCN%d\n", i);
1950                         for (j = 0; j < reg_count; j++)
1951                                 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
1952                                            adev->vcn.ip_dump[inst_off + j]);
1953                 } else {
1954                         drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1955                 }
1956         }
1957 }
1958
1959 static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1960 {
1961         struct amdgpu_device *adev = ip_block->adev;
1962         int i, j;
1963         bool is_powered;
1964         uint32_t inst_off;
1965         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1966
1967         if (!adev->vcn.ip_dump)
1968                 return;
1969
1970         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1971                 if (adev->vcn.harvest_config & (1 << i))
1972                         continue;
1973
1974                 inst_off = i * reg_count;
1975                 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1976                 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
1977                 is_powered = (adev->vcn.ip_dump[inst_off] &
1978                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1979
1980                 if (is_powered)
1981                         for (j = 1; j < reg_count; j++)
1982                                 adev->vcn.ip_dump[inst_off + j] =
1983                                         RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
1984         }
1985 }
1986
1987 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1988         .name = "vcn_v1_0",
1989         .early_init = vcn_v1_0_early_init,
1990         .sw_init = vcn_v1_0_sw_init,
1991         .sw_fini = vcn_v1_0_sw_fini,
1992         .hw_init = vcn_v1_0_hw_init,
1993         .hw_fini = vcn_v1_0_hw_fini,
1994         .suspend = vcn_v1_0_suspend,
1995         .resume = vcn_v1_0_resume,
1996         .is_idle = vcn_v1_0_is_idle,
1997         .wait_for_idle = vcn_v1_0_wait_for_idle,
1998         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1999         .set_powergating_state = vcn_v1_0_set_powergating_state,
2000         .dump_ip_state = vcn_v1_0_dump_ip_state,
2001         .print_ip_state = vcn_v1_0_print_ip_state,
2002 };
2003
2004 /*
2005  * It is a hardware issue that VCN can't handle a GTT TMZ buffer on
2006  * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain
2007  * before command submission as a workaround.
2008  */
2009 static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser,
2010                                 struct amdgpu_job *job,
2011                                 uint64_t addr)
2012 {
2013         struct ttm_operation_ctx ctx = { false, false };
2014         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
2015         struct amdgpu_vm *vm = &fpriv->vm;
2016         struct amdgpu_bo_va_mapping *mapping;
2017         struct amdgpu_bo *bo;
2018         int r;
2019
2020         addr &= AMDGPU_GMC_HOLE_MASK;
2021         if (addr & 0x7) {
2022                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
2023                 return -EINVAL;
2024         }
2025
2026         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr/AMDGPU_GPU_PAGE_SIZE);
2027         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
2028                 return -EINVAL;
2029
2030         bo = mapping->bo_va->base.bo;
2031         if (!(bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED))
2032                 return 0;
2033
2034         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
2035         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2036         if (r) {
2037                 DRM_ERROR("Failed to validate the VCN message BO (%d)!\n", r);
2038                 return r;
2039         }
2040
2041         return r;
2042 }
2043
2044 static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
2045                                            struct amdgpu_job *job,
2046                                            struct amdgpu_ib *ib)
2047 {
2048         uint32_t msg_lo = 0, msg_hi = 0;
2049         int i, r;
2050
2051         if (!(ib->flags & AMDGPU_IB_FLAGS_SECURE))
2052                 return 0;
2053
2054         for (i = 0; i < ib->length_dw; i += 2) {
2055                 uint32_t reg = amdgpu_ib_get_value(ib, i);
2056                 uint32_t val = amdgpu_ib_get_value(ib, i + 1);
2057
2058                 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
2059                         msg_lo = val;
2060                 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
2061                         msg_hi = val;
2062                 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) {
2063                         r = vcn_v1_0_validate_bo(p, job,
2064                                                  ((u64)msg_hi) << 32 | msg_lo);
2065                         if (r)
2066                                 return r;
2067                 }
2068         }
2069
2070         return 0;
2071 }
2072
2073 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2074         .type = AMDGPU_RING_TYPE_VCN_DEC,
2075         .align_mask = 0xf,
2076         .support_64bit_ptrs = false,
2077         .no_user_fence = true,
2078         .secure_submission_supported = true,
2079         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2080         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2081         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2082         .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place,
2083         .emit_frame_size =
2084                 6 + 6 + /* hdp invalidate / flush */
2085                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2086                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2087                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2088                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2089                 6,
2090         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2091         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2092         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2093         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2094         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2095         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2096         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2097         .insert_start = vcn_v1_0_dec_ring_insert_start,
2098         .insert_end = vcn_v1_0_dec_ring_insert_end,
2099         .pad_ib = amdgpu_ring_generic_pad_ib,
2100         .begin_use = vcn_v1_0_ring_begin_use,
2101         .end_use = vcn_v1_0_ring_end_use,
2102         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2103         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2104         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2105 };
2106
2107 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2108         .type = AMDGPU_RING_TYPE_VCN_ENC,
2109         .align_mask = 0x3f,
2110         .nop = VCN_ENC_CMD_NO_OP,
2111         .support_64bit_ptrs = false,
2112         .no_user_fence = true,
2113         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2114         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2115         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2116         .emit_frame_size =
2117                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2118                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2119                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2120                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2121                 1, /* vcn_v1_0_enc_ring_insert_end */
2122         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2123         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2124         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2125         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2126         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2127         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2128         .insert_nop = amdgpu_ring_insert_nop,
2129         .insert_end = vcn_v1_0_enc_ring_insert_end,
2130         .pad_ib = amdgpu_ring_generic_pad_ib,
2131         .begin_use = vcn_v1_0_ring_begin_use,
2132         .end_use = vcn_v1_0_ring_end_use,
2133         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2134         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2135         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2136 };
2137
2138 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2139 {
2140         adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2141 }
2142
2143 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2144 {
2145         int i;
2146
2147         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2148                 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2149 }
2150
2151 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2152         .set = vcn_v1_0_set_interrupt_state,
2153         .process = vcn_v1_0_process_interrupt,
2154 };
2155
2156 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2157 {
2158         adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
2159         adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
2160 }
2161
2162 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = {
2163                 .type = AMD_IP_BLOCK_TYPE_VCN,
2164                 .major = 1,
2165                 .minor = 0,
2166                 .rev = 0,
2167                 .funcs = &vcn_v1_0_ip_funcs,
2168 };