drivers/devfreq/exynos/exynos4_bus.c

   1 /* drivers/devfreq/exynos4210_memorybus.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *      MyungJoo Ham <[email protected]>
   6  *
   7  * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
   8  *      This version supports EXYNOS4210 only. This changes bus frequencies
   9  *      and vddint voltages. Exynos4412/4212 should be able to be supported
  10  *      with minor modifications.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  */
  17
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20 #include <linux/mutex.h>
  21 #include <linux/suspend.h>
  22 #include <linux/pm_opp.h>
  23 #include <linux/devfreq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/module.h>
  27
  28 #include <mach/map.h>
  29
  30 #include "exynos_ppmu.h"
  31 #include "exynos4_bus.h"
  32
  33 #define MAX_SAFEVOLT    1200000 /* 1.2V */
  34
  35 enum exynos4_busf_type {
  36         TYPE_BUSF_EXYNOS4210,
  37         TYPE_BUSF_EXYNOS4x12,
  38 };
  39
  40 /* Assume that the bus is saturated if the utilization is 40% */
  41 #define BUS_SATURATION_RATIO    40
  42
  43 enum busclk_level_idx {
  44         LV_0 = 0,
  45         LV_1,
  46         LV_2,
  47         LV_3,
  48         LV_4,
  49         _LV_END
  50 };
  51
  52 enum exynos_ppmu_idx {
  53         PPMU_DMC0,
  54         PPMU_DMC1,
  55         PPMU_END,
  56 };
  57
  58 #define EX4210_LV_MAX   LV_2
  59 #define EX4x12_LV_MAX   LV_4
  60 #define EX4210_LV_NUM   (LV_2 + 1)
  61 #define EX4x12_LV_NUM   (LV_4 + 1)
  62
  63 /**
  64  * struct busfreq_opp_info - opp information for bus
  65  * @rate:       Frequency in hertz
  66  * @volt:       Voltage in microvolts corresponding to this OPP
  67  */
  68 struct busfreq_opp_info {
  69         unsigned long rate;
  70         unsigned long volt;
  71 };
  72
  73 struct busfreq_data {
  74         enum exynos4_busf_type type;
  75         struct device *dev;
  76         struct devfreq *devfreq;
  77         bool disabled;
  78         struct regulator *vdd_int;
  79         struct regulator *vdd_mif; /* Exynos4412/4212 only */
  80         struct busfreq_opp_info curr_oppinfo;
  81         struct busfreq_ppmu_data ppmu_data;
  82
  83         struct notifier_block pm_notifier;
  84         struct mutex lock;
  85
  86         /* Dividers calculated at boot/probe-time */
  87         unsigned int dmc_divtable[_LV_END]; /* DMC0 */
  88         unsigned int top_divtable[_LV_END];
  89 };
  90
  91 /* 4210 controls clock of mif and voltage of int */
  92 static struct bus_opp_table exynos4210_busclk_table[] = {
  93         {LV_0, 400000, 1150000},
  94         {LV_1, 267000, 1050000},
  95         {LV_2, 133000, 1025000},
  96         {0, 0, 0},
  97 };
  98
  99 /*
 100  * MIF is the main control knob clock for Exynos4x12 MIF/INT
 101  * clock and voltage of both mif/int are controlled.
 102  */
 103 static struct bus_opp_table exynos4x12_mifclk_table[] = {
 104         {LV_0, 400000, 1100000},
 105         {LV_1, 267000, 1000000},
 106         {LV_2, 160000, 950000},
 107         {LV_3, 133000, 950000},
 108         {LV_4, 100000, 950000},
 109         {0, 0, 0},
 110 };
 111
 112 /*
 113  * INT is not the control knob of 4x12. LV_x is not meant to represent
 114  * the current performance. (MIF does)
 115  */
 116 static struct bus_opp_table exynos4x12_intclk_table[] = {
 117         {LV_0, 200000, 1000000},
 118         {LV_1, 160000, 950000},
 119         {LV_2, 133000, 925000},
 120         {LV_3, 100000, 900000},
 121         {0, 0, 0},
 122 };
 123
 124 /* TODO: asv volt definitions are "__initdata"? */
 125 /* Some chips have different operating voltages */
 126 static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
 127         {1150000, 1050000, 1050000},
 128         {1125000, 1025000, 1025000},
 129         {1100000, 1000000, 1000000},
 130         {1075000, 975000, 975000},
 131         {1050000, 950000, 950000},
 132 };
 133
 134 static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
 135         /* 400      267     160     133     100 */
 136         {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
 137         {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
 138         {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
 139         {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
 140         {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
 141         {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
 142         {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
 143         {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
 144         {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
 145 };
 146
 147 static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
 148         /* 200    160      133     100 */
 149         {1000000, 950000, 925000, 900000}, /* ASV0 */
 150         {975000,  925000, 925000, 900000}, /* ASV1 */
 151         {950000,  925000, 900000, 875000}, /* ASV2 */
 152         {950000,  900000, 900000, 875000}, /* ASV3 */
 153         {925000,  875000, 875000, 875000}, /* ASV4 */
 154         {900000,  850000, 850000, 850000}, /* ASV5 */
 155         {900000,  850000, 850000, 850000}, /* ASV6 */
 156         {900000,  850000, 850000, 850000}, /* ASV7 */
 157         {900000,  850000, 850000, 850000}, /* ASV8 */
 158 };
 159
 160 /*** Clock Divider Data for Exynos4210 ***/
 161 static unsigned int exynos4210_clkdiv_dmc0[][8] = {
 162         /*
 163          * Clock divider value for following
 164          * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
 165          *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
 166          */
 167
 168         /* DMC L0: 400MHz */
 169         { 3, 1, 1, 1, 1, 1, 3, 1 },
 170         /* DMC L1: 266.7MHz */
 171         { 4, 1, 1, 2, 1, 1, 3, 1 },
 172         /* DMC L2: 133MHz */
 173         { 5, 1, 1, 5, 1, 1, 3, 1 },
 174 };
 175 static unsigned int exynos4210_clkdiv_top[][5] = {
 176         /*
 177          * Clock divider value for following
 178          * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
 179          */
 180         /* ACLK200 L0: 200MHz */
 181         { 3, 7, 4, 5, 1 },
 182         /* ACLK200 L1: 160MHz */
 183         { 4, 7, 5, 6, 1 },
 184         /* ACLK200 L2: 133MHz */
 185         { 5, 7, 7, 7, 1 },
 186 };
 187 static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
 188         /*
 189          * Clock divider value for following
 190          * { DIVGDL/R, DIVGPL/R }
 191          */
 192         /* ACLK_GDL/R L1: 200MHz */
 193         { 3, 1 },
 194         /* ACLK_GDL/R L2: 160MHz */
 195         { 4, 1 },
 196         /* ACLK_GDL/R L3: 133MHz */
 197         { 5, 1 },
 198 };
 199
 200 /*** Clock Divider Data for Exynos4212/4412 ***/
 201 static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
 202         /*
 203          * Clock divider value for following
 204          * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
 205          *              DIVDMCP}
 206          */
 207
 208         /* DMC L0: 400MHz */
 209         {3, 1, 1, 1, 1, 1},
 210         /* DMC L1: 266.7MHz */
 211         {4, 1, 1, 2, 1, 1},
 212         /* DMC L2: 160MHz */
 213         {5, 1, 1, 4, 1, 1},
 214         /* DMC L3: 133MHz */
 215         {5, 1, 1, 5, 1, 1},
 216         /* DMC L4: 100MHz */
 217         {7, 1, 1, 7, 1, 1},
 218 };
 219 static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
 220         /*
 221          * Clock divider value for following
 222          * { G2DACP, DIVC2C, DIVC2C_ACLK }
 223          */
 224
 225         /* DMC L0: 400MHz */
 226         {3, 1, 1},
 227         /* DMC L1: 266.7MHz */
 228         {4, 2, 1},
 229         /* DMC L2: 160MHz */
 230         {5, 4, 1},
 231         /* DMC L3: 133MHz */
 232         {5, 5, 1},
 233         /* DMC L4: 100MHz */
 234         {7, 7, 1},
 235 };
 236 static unsigned int exynos4x12_clkdiv_top[][5] = {
 237         /*
 238          * Clock divider value for following
 239          * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
 240                 DIVACLK133, DIVONENAND }
 241          */
 242
 243         /* ACLK_GDL/R L0: 200MHz */
 244         {2, 7, 4, 5, 1},
 245         /* ACLK_GDL/R L1: 200MHz */
 246         {2, 7, 4, 5, 1},
 247         /* ACLK_GDL/R L2: 160MHz */
 248         {4, 7, 5, 7, 1},
 249         /* ACLK_GDL/R L3: 133MHz */
 250         {4, 7, 5, 7, 1},
 251         /* ACLK_GDL/R L4: 100MHz */
 252         {7, 7, 7, 7, 1},
 253 };
 254 static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
 255         /*
 256          * Clock divider value for following
 257          * { DIVGDL/R, DIVGPL/R }
 258          */
 259
 260         /* ACLK_GDL/R L0: 200MHz */
 261         {3, 1},
 262         /* ACLK_GDL/R L1: 200MHz */
 263         {3, 1},
 264         /* ACLK_GDL/R L2: 160MHz */
 265         {4, 1},
 266         /* ACLK_GDL/R L3: 133MHz */
 267         {5, 1},
 268         /* ACLK_GDL/R L4: 100MHz */
 269         {7, 1},
 270 };
 271 static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
 272         /*
 273          * Clock divider value for following
 274          * { DIVMFC, DIVJPEG, DIVFIMC0~3}
 275          */
 276
 277         /* SCLK_MFC: 200MHz */
 278         {3, 3, 4},
 279         /* SCLK_MFC: 200MHz */
 280         {3, 3, 4},
 281         /* SCLK_MFC: 160MHz */
 282         {4, 4, 5},
 283         /* SCLK_MFC: 133MHz */
 284         {5, 5, 5},
 285         /* SCLK_MFC: 100MHz */
 286         {7, 7, 7},
 287 };
 288
 289
 290 static int exynos4210_set_busclk(struct busfreq_data *data,
 291                                  struct busfreq_opp_info *oppi)
 292 {
 293         unsigned int index;
 294         unsigned int tmp;
 295
 296         for (index = LV_0; index < EX4210_LV_NUM; index++)
 297                 if (oppi->rate == exynos4210_busclk_table[index].clk)
 298                         break;
 299
 300         if (index == EX4210_LV_NUM)
 301                 return -EINVAL;
 302
 303         /* Change Divider - DMC0 */
 304         tmp = data->dmc_divtable[index];
 305
 306         __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
 307
 308         do {
 309                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
 310         } while (tmp & 0x11111111);
 311
 312         /* Change Divider - TOP */
 313         tmp = data->top_divtable[index];
 314
 315         __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
 316
 317         do {
 318                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
 319         } while (tmp & 0x11111);
 320
 321         /* Change Divider - LEFTBUS */
 322         tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
 323
 324         tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 325
 326         tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
 327                                 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 328                 (exynos4210_clkdiv_lr_bus[index][1] <<
 329                                 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 330
 331         __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
 332
 333         do {
 334                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
 335         } while (tmp & 0x11);
 336
 337         /* Change Divider - RIGHTBUS */
 338         tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
 339
 340         tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 341
 342         tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
 343                                 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 344                 (exynos4210_clkdiv_lr_bus[index][1] <<
 345                                 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 346
 347         __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
 348
 349         do {
 350                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
 351         } while (tmp & 0x11);
 352
 353         return 0;
 354 }
 355
 356 static int exynos4x12_set_busclk(struct busfreq_data *data,
 357                                  struct busfreq_opp_info *oppi)
 358 {
 359         unsigned int index;
 360         unsigned int tmp;
 361
 362         for (index = LV_0; index < EX4x12_LV_NUM; index++)
 363                 if (oppi->rate == exynos4x12_mifclk_table[index].clk)
 364                         break;
 365
 366         if (index == EX4x12_LV_NUM)
 367                 return -EINVAL;
 368
 369         /* Change Divider - DMC0 */
 370         tmp = data->dmc_divtable[index];
 371
 372         __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
 373
 374         do {
 375                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
 376         } while (tmp & 0x11111111);
 377
 378         /* Change Divider - DMC1 */
 379         tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
 380
 381         tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
 382                 EXYNOS4_CLKDIV_DMC1_C2C_MASK |
 383                 EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
 384
 385         tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
 386                                 EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
 387                 (exynos4x12_clkdiv_dmc1[index][1] <<
 388                                 EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
 389                 (exynos4x12_clkdiv_dmc1[index][2] <<
 390                                 EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
 391
 392         __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
 393
 394         do {
 395                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
 396         } while (tmp & 0x111111);
 397
 398         /* Change Divider - TOP */
 399         tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
 400
 401         tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
 402                 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
 403                 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
 404                 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
 405                 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
 406
 407         tmp |= ((exynos4x12_clkdiv_top[index][0] <<
 408                                 EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
 409                 (exynos4x12_clkdiv_top[index][1] <<
 410                                 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
 411                 (exynos4x12_clkdiv_top[index][2] <<
 412                                 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
 413                 (exynos4x12_clkdiv_top[index][3] <<
 414                                 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
 415                 (exynos4x12_clkdiv_top[index][4] <<
 416                                 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
 417
 418         __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
 419
 420         do {
 421                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
 422         } while (tmp & 0x11111);
 423
 424         /* Change Divider - LEFTBUS */
 425         tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
 426
 427         tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 428
 429         tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
 430                                 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 431                 (exynos4x12_clkdiv_lr_bus[index][1] <<
 432                                 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 433
 434         __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
 435
 436         do {
 437                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
 438         } while (tmp & 0x11);
 439
 440         /* Change Divider - RIGHTBUS */
 441         tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
 442
 443         tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 444
 445         tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
 446                                 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 447                 (exynos4x12_clkdiv_lr_bus[index][1] <<
 448                                 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 449
 450         __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
 451
 452         do {
 453                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
 454         } while (tmp & 0x11);
 455
 456         /* Change Divider - MFC */
 457         tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
 458
 459         tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
 460
 461         tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
 462                                 EXYNOS4_CLKDIV_MFC_SHIFT));
 463
 464         __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
 465
 466         do {
 467                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
 468         } while (tmp & 0x1);
 469
 470         /* Change Divider - JPEG */
 471         tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
 472
 473         tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
 474
 475         tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
 476                                 EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
 477
 478         __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
 479
 480         do {
 481                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
 482         } while (tmp & 0x1);
 483
 484         /* Change Divider - FIMC0~3 */
 485         tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
 486
 487         tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
 488                 EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
 489
 490         tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
 491                                 EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
 492                 (exynos4x12_clkdiv_sclkip[index][2] <<
 493                                 EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
 494                 (exynos4x12_clkdiv_sclkip[index][2] <<
 495                                 EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
 496                 (exynos4x12_clkdiv_sclkip[index][2] <<
 497                                 EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
 498
 499         __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
 500
 501         do {
 502                 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
 503         } while (tmp & 0x1111);
 504
 505         return 0;
 506 }
 507
 508 static int exynos4x12_get_intspec(unsigned long mifclk)
 509 {
 510         int i = 0;
 511
 512         while (exynos4x12_intclk_table[i].clk) {
 513                 if (exynos4x12_intclk_table[i].clk <= mifclk)
 514                         return i;
 515                 i++;
 516         }
 517
 518         return -EINVAL;
 519 }
 520
 521 static int exynos4_bus_setvolt(struct busfreq_data *data,
 522                                struct busfreq_opp_info *oppi,
 523                                struct busfreq_opp_info *oldoppi)
 524 {
 525         int err = 0, tmp;
 526         unsigned long volt = oppi->volt;
 527
 528         switch (data->type) {
 529         case TYPE_BUSF_EXYNOS4210:
 530                 /* OPP represents DMC clock + INT voltage */
 531                 err = regulator_set_voltage(data->vdd_int, volt,
 532                                             MAX_SAFEVOLT);
 533                 break;
 534         case TYPE_BUSF_EXYNOS4x12:
 535                 /* OPP represents MIF clock + MIF voltage */
 536                 err = regulator_set_voltage(data->vdd_mif, volt,
 537                                             MAX_SAFEVOLT);
 538                 if (err)
 539                         break;
 540
 541                 tmp = exynos4x12_get_intspec(oppi->rate);
 542                 if (tmp < 0) {
 543                         err = tmp;
 544                         regulator_set_voltage(data->vdd_mif,
 545                                               oldoppi->volt,
 546                                               MAX_SAFEVOLT);
 547                         break;
 548                 }
 549                 err = regulator_set_voltage(data->vdd_int,
 550                                             exynos4x12_intclk_table[tmp].volt,
 551                                             MAX_SAFEVOLT);
 552                 /*  Try to recover */
 553                 if (err)
 554                         regulator_set_voltage(data->vdd_mif,
 555                                               oldoppi->volt,
 556                                               MAX_SAFEVOLT);
 557                 break;
 558         default:
 559                 err = -EINVAL;
 560         }
 561
 562         return err;
 563 }
 564
 565 static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
 566                               u32 flags)
 567 {
 568         int err = 0;
 569         struct platform_device *pdev = container_of(dev, struct platform_device,
 570                                                     dev);
 571         struct busfreq_data *data = platform_get_drvdata(pdev);
 572         struct dev_pm_opp *opp;
 573         unsigned long freq;
 574         unsigned long old_freq = data->curr_oppinfo.rate;
 575         struct busfreq_opp_info new_oppinfo;
 576
 577         rcu_read_lock();
 578         opp = devfreq_recommended_opp(dev, _freq, flags);
 579         if (IS_ERR(opp)) {
 580                 rcu_read_unlock();
 581                 return PTR_ERR(opp);
 582         }
 583         new_oppinfo.rate = dev_pm_opp_get_freq(opp);
 584         new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
 585         rcu_read_unlock();
 586         freq = new_oppinfo.rate;
 587
 588         if (old_freq == freq)
 589                 return 0;
 590
 591         dev_dbg(dev, "targeting %lukHz %luuV\n", freq, new_oppinfo.volt);
 592
 593         mutex_lock(&data->lock);
 594
 595         if (data->disabled)
 596                 goto out;
 597
 598         if (old_freq < freq)
 599                 err = exynos4_bus_setvolt(data, &new_oppinfo,
 600                                           &data->curr_oppinfo);
 601         if (err)
 602                 goto out;
 603
 604         if (old_freq != freq) {
 605                 switch (data->type) {
 606                 case TYPE_BUSF_EXYNOS4210:
 607                         err = exynos4210_set_busclk(data, &new_oppinfo);
 608                         break;
 609                 case TYPE_BUSF_EXYNOS4x12:
 610                         err = exynos4x12_set_busclk(data, &new_oppinfo);
 611                         break;
 612                 default:
 613                         err = -EINVAL;
 614                 }
 615         }
 616         if (err)
 617                 goto out;
 618
 619         if (old_freq > freq)
 620                 err = exynos4_bus_setvolt(data, &new_oppinfo,
 621                                           &data->curr_oppinfo);
 622         if (err)
 623                 goto out;
 624
 625         data->curr_oppinfo = new_oppinfo;
 626 out:
 627         mutex_unlock(&data->lock);
 628         return err;
 629 }
 630
 631 static int exynos4_bus_get_dev_status(struct device *dev,
 632                                       struct devfreq_dev_status *stat)
 633 {
 634         struct busfreq_data *data = dev_get_drvdata(dev);
 635         struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
 636         int busier;
 637
 638         exynos_read_ppmu(ppmu_data);
 639         busier = exynos_get_busier_ppmu(ppmu_data);
 640         stat->current_frequency = data->curr_oppinfo.rate;
 641
 642         /* Number of cycles spent on memory access */
 643         stat->busy_time = ppmu_data->ppmu[busier].count[PPMU_PMNCNT3];
 644         stat->busy_time *= 100 / BUS_SATURATION_RATIO;
 645         stat->total_time = ppmu_data->ppmu[busier].ccnt;
 646
 647         /* If the counters have overflown, retry */
 648         if (ppmu_data->ppmu[busier].ccnt_overflow ||
 649             ppmu_data->ppmu[busier].count_overflow[0])
 650                 return -EAGAIN;
 651
 652         return 0;
 653 }
 654
 655 static struct devfreq_dev_profile exynos4_devfreq_profile = {
 656         .initial_freq   = 400000,
 657         .polling_ms     = 50,
 658         .target         = exynos4_bus_target,
 659         .get_dev_status = exynos4_bus_get_dev_status,
 660 };
 661
 662 static int exynos4210_init_tables(struct busfreq_data *data)
 663 {
 664         u32 tmp;
 665         int mgrp;
 666         int i, err = 0;
 667
 668         tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
 669         for (i = LV_0; i < EX4210_LV_NUM; i++) {
 670                 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
 671                         EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
 672                         EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
 673                         EXYNOS4_CLKDIV_DMC0_DMC_MASK |
 674                         EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
 675                         EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
 676                         EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
 677                         EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
 678
 679                 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
 680                                         EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
 681                         (exynos4210_clkdiv_dmc0[i][1] <<
 682                                         EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 683                         (exynos4210_clkdiv_dmc0[i][2] <<
 684                                         EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
 685                         (exynos4210_clkdiv_dmc0[i][3] <<
 686                                         EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
 687                         (exynos4210_clkdiv_dmc0[i][4] <<
 688                                         EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
 689                         (exynos4210_clkdiv_dmc0[i][5] <<
 690                                         EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
 691                         (exynos4210_clkdiv_dmc0[i][6] <<
 692                                         EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
 693                         (exynos4210_clkdiv_dmc0[i][7] <<
 694                                         EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
 695
 696                 data->dmc_divtable[i] = tmp;
 697         }
 698
 699         tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
 700         for (i = LV_0; i <  EX4210_LV_NUM; i++) {
 701                 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
 702                         EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
 703                         EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
 704                         EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
 705                         EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
 706
 707                 tmp |= ((exynos4210_clkdiv_top[i][0] <<
 708                                         EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
 709                         (exynos4210_clkdiv_top[i][1] <<
 710                                         EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
 711                         (exynos4210_clkdiv_top[i][2] <<
 712                                         EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
 713                         (exynos4210_clkdiv_top[i][3] <<
 714                                         EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
 715                         (exynos4210_clkdiv_top[i][4] <<
 716                                         EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
 717
 718                 data->top_divtable[i] = tmp;
 719         }
 720
 721         /*
 722          * TODO: init tmp based on busfreq_data
 723          * (device-tree or platform-data)
 724          */
 725         tmp = 0; /* Max voltages for the reliability of the unknown */
 726
 727         pr_debug("ASV Group of Exynos4 is %d\n", tmp);
 728         /* Use merged grouping for voltage */
 729         switch (tmp) {
 730         case 0:
 731                 mgrp = 0;
 732                 break;
 733         case 1:
 734         case 2:
 735                 mgrp = 1;
 736                 break;
 737         case 3:
 738         case 4:
 739                 mgrp = 2;
 740                 break;
 741         case 5:
 742         case 6:
 743                 mgrp = 3;
 744                 break;
 745         case 7:
 746                 mgrp = 4;
 747                 break;
 748         default:
 749                 pr_warn("Unknown ASV Group. Use max voltage.\n");
 750                 mgrp = 0;
 751         }
 752
 753         for (i = LV_0; i < EX4210_LV_NUM; i++)
 754                 exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
 755
 756         for (i = LV_0; i < EX4210_LV_NUM; i++) {
 757                 err = dev_pm_opp_add(data->dev, exynos4210_busclk_table[i].clk,
 758                               exynos4210_busclk_table[i].volt);
 759                 if (err) {
 760                         dev_err(data->dev, "Cannot add opp entries.\n");
 761                         return err;
 762                 }
 763         }
 764
 765
 766         return 0;
 767 }
 768
 769 static int exynos4x12_init_tables(struct busfreq_data *data)
 770 {
 771         unsigned int i;
 772         unsigned int tmp;
 773         int ret;
 774
 775         /* Enable pause function for DREX2 DVFS */
 776         tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
 777         tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
 778         __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
 779
 780         tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
 781
 782         for (i = 0; i <  EX4x12_LV_NUM; i++) {
 783                 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
 784                         EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
 785                         EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
 786                         EXYNOS4_CLKDIV_DMC0_DMC_MASK |
 787                         EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
 788                         EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
 789
 790                 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
 791                                         EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
 792                         (exynos4x12_clkdiv_dmc0[i][1] <<
 793                                         EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 794                         (exynos4x12_clkdiv_dmc0[i][2] <<
 795                                         EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
 796                         (exynos4x12_clkdiv_dmc0[i][3] <<
 797                                         EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
 798                         (exynos4x12_clkdiv_dmc0[i][4] <<
 799                                         EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
 800                         (exynos4x12_clkdiv_dmc0[i][5] <<
 801                                         EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
 802
 803                 data->dmc_divtable[i] = tmp;
 804         }
 805
 806         tmp = 0; /* Max voltages for the reliability of the unknown */
 807
 808         if (tmp > 8)
 809                 tmp = 0;
 810         pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
 811
 812         for (i = 0; i < EX4x12_LV_NUM; i++) {
 813                 exynos4x12_mifclk_table[i].volt =
 814                         exynos4x12_mif_step_50[tmp][i];
 815                 exynos4x12_intclk_table[i].volt =
 816                         exynos4x12_int_volt[tmp][i];
 817         }
 818
 819         for (i = 0; i < EX4x12_LV_NUM; i++) {
 820                 ret = dev_pm_opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
 821                               exynos4x12_mifclk_table[i].volt);
 822                 if (ret) {
 823                         dev_err(data->dev, "Fail to add opp entries.\n");
 824                         return ret;
 825                 }
 826         }
 827
 828         return 0;
 829 }
 830
 831 static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
 832                 unsigned long event, void *ptr)
 833 {
 834         struct busfreq_data *data = container_of(this, struct busfreq_data,
 835                                                  pm_notifier);
 836         struct dev_pm_opp *opp;
 837         struct busfreq_opp_info new_oppinfo;
 838         unsigned long maxfreq = ULONG_MAX;
 839         int err = 0;
 840
 841         switch (event) {
 842         case PM_SUSPEND_PREPARE:
 843                 /* Set Fastest and Deactivate DVFS */
 844                 mutex_lock(&data->lock);
 845
 846                 data->disabled = true;
 847
 848                 rcu_read_lock();
 849                 opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq);
 850                 if (IS_ERR(opp)) {
 851                         rcu_read_unlock();
 852                         dev_err(data->dev, "%s: unable to find a min freq\n",
 853                                 __func__);
 854                         mutex_unlock(&data->lock);
 855                         return PTR_ERR(opp);
 856                 }
 857                 new_oppinfo.rate = dev_pm_opp_get_freq(opp);
 858                 new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
 859                 rcu_read_unlock();
 860
 861                 err = exynos4_bus_setvolt(data, &new_oppinfo,
 862                                           &data->curr_oppinfo);
 863                 if (err)
 864                         goto unlock;
 865
 866                 switch (data->type) {
 867                 case TYPE_BUSF_EXYNOS4210:
 868                         err = exynos4210_set_busclk(data, &new_oppinfo);
 869                         break;
 870                 case TYPE_BUSF_EXYNOS4x12:
 871                         err = exynos4x12_set_busclk(data, &new_oppinfo);
 872                         break;
 873                 default:
 874                         err = -EINVAL;
 875                 }
 876                 if (err)
 877                         goto unlock;
 878
 879                 data->curr_oppinfo = new_oppinfo;
 880 unlock:
 881                 mutex_unlock(&data->lock);
 882                 if (err)
 883                         return err;
 884                 return NOTIFY_OK;
 885         case PM_POST_RESTORE:
 886         case PM_POST_SUSPEND:
 887                 /* Reactivate */
 888                 mutex_lock(&data->lock);
 889                 data->disabled = false;
 890                 mutex_unlock(&data->lock);
 891                 return NOTIFY_OK;
 892         }
 893
 894         return NOTIFY_DONE;
 895 }
 896
 897 static int exynos4_busfreq_probe(struct platform_device *pdev)
 898 {
 899         struct busfreq_data *data;
 900         struct busfreq_ppmu_data *ppmu_data;
 901         struct dev_pm_opp *opp;
 902         struct device *dev = &pdev->dev;
 903         int err = 0;
 904
 905         data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL);
 906         if (data == NULL) {
 907                 dev_err(dev, "Cannot allocate memory.\n");
 908                 return -ENOMEM;
 909         }
 910
 911         ppmu_data = &data->ppmu_data;
 912         ppmu_data->ppmu_end = PPMU_END;
 913         ppmu_data->ppmu = devm_kzalloc(dev,
 914                                        sizeof(struct exynos_ppmu) * PPMU_END,
 915                                        GFP_KERNEL);
 916         if (!ppmu_data->ppmu) {
 917                 dev_err(dev, "Failed to allocate memory for exynos_ppmu\n");
 918                 return -ENOMEM;
 919         }
 920
 921         data->type = pdev->id_entry->driver_data;
 922         ppmu_data->ppmu[PPMU_DMC0].hw_base = S5P_VA_DMC0;
 923         ppmu_data->ppmu[PPMU_DMC1].hw_base = S5P_VA_DMC1;
 924         data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
 925         data->dev = dev;
 926         mutex_init(&data->lock);
 927
 928         switch (data->type) {
 929         case TYPE_BUSF_EXYNOS4210:
 930                 err = exynos4210_init_tables(data);
 931                 break;
 932         case TYPE_BUSF_EXYNOS4x12:
 933                 err = exynos4x12_init_tables(data);
 934                 break;
 935         default:
 936                 dev_err(dev, "Cannot determine the device id %d\n", data->type);
 937                 err = -EINVAL;
 938         }
 939         if (err) {
 940                 dev_err(dev, "Cannot initialize busfreq table %d\n",
 941                              data->type);
 942                 return err;
 943         }
 944
 945         data->vdd_int = devm_regulator_get(dev, "vdd_int");
 946         if (IS_ERR(data->vdd_int)) {
 947                 dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
 948                 return PTR_ERR(data->vdd_int);
 949         }
 950         if (data->type == TYPE_BUSF_EXYNOS4x12) {
 951                 data->vdd_mif = devm_regulator_get(dev, "vdd_mif");
 952                 if (IS_ERR(data->vdd_mif)) {
 953                         dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
 954                         return PTR_ERR(data->vdd_mif);
 955                 }
 956         }
 957
 958         rcu_read_lock();
 959         opp = dev_pm_opp_find_freq_floor(dev,
 960                                          &exynos4_devfreq_profile.initial_freq);
 961         if (IS_ERR(opp)) {
 962                 rcu_read_unlock();
 963                 dev_err(dev, "Invalid initial frequency %lu kHz.\n",
 964                         exynos4_devfreq_profile.initial_freq);
 965                 return PTR_ERR(opp);
 966         }
 967         data->curr_oppinfo.rate = dev_pm_opp_get_freq(opp);
 968         data->curr_oppinfo.volt = dev_pm_opp_get_voltage(opp);
 969         rcu_read_unlock();
 970
 971         platform_set_drvdata(pdev, data);
 972
 973         data->devfreq = devm_devfreq_add_device(dev, &exynos4_devfreq_profile,
 974                                            "simple_ondemand", NULL);
 975         if (IS_ERR(data->devfreq))
 976                 return PTR_ERR(data->devfreq);
 977
 978         /*
 979          * Start PPMU (Performance Profiling Monitoring Unit) to check
 980          * utilization of each IP in the Exynos4 SoC.
 981          */
 982         busfreq_mon_reset(ppmu_data);
 983
 984         /* Register opp_notifier for Exynos4 busfreq */
 985         err = devm_devfreq_register_opp_notifier(dev, data->devfreq);
 986         if (err < 0) {
 987                 dev_err(dev, "Failed to register opp notifier\n");
 988                 return err;
 989         }
 990
 991         /* Register pm_notifier for Exynos4 busfreq */
 992         err = register_pm_notifier(&data->pm_notifier);
 993         if (err) {
 994                 dev_err(dev, "Failed to setup pm notifier\n");
 995                 return err;
 996         }
 997
 998         return 0;
 999 }
1000
1001 static int exynos4_busfreq_remove(struct platform_device *pdev)
1002 {
1003         struct busfreq_data *data = platform_get_drvdata(pdev);
1004
1005         /* Unregister all of notifier chain */
1006         unregister_pm_notifier(&data->pm_notifier);
1007
1008         return 0;
1009 }
1010
1011 #ifdef CONFIG_PM_SLEEP
1012 static int exynos4_busfreq_resume(struct device *dev)
1013 {
1014         struct busfreq_data *data = dev_get_drvdata(dev);
1015         struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
1016
1017         busfreq_mon_reset(ppmu_data);
1018         return 0;
1019 }
1020 #endif
1021
1022 static SIMPLE_DEV_PM_OPS(exynos4_busfreq_pm_ops, NULL, exynos4_busfreq_resume);
1023
1024 static const struct platform_device_id exynos4_busfreq_id[] = {
1025         { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
1026         { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
1027         { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
1028         { },
1029 };
1030
1031 static struct platform_driver exynos4_busfreq_driver = {
1032         .probe  = exynos4_busfreq_probe,
1033         .remove = exynos4_busfreq_remove,
1034         .id_table = exynos4_busfreq_id,
1035         .driver = {
1036                 .name   = "exynos4-busfreq",
1037                 .pm     = &exynos4_busfreq_pm_ops,
1038         },
1039 };
1040
1041 static int __init exynos4_busfreq_init(void)
1042 {
1043         return platform_driver_register(&exynos4_busfreq_driver);
1044 }
1045 late_initcall(exynos4_busfreq_init);
1046
1047 static void __exit exynos4_busfreq_exit(void)
1048 {
1049         platform_driver_unregister(&exynos4_busfreq_driver);
1050 }
1051 module_exit(exynos4_busfreq_exit);
1052
1053 MODULE_LICENSE("GPL");
1054 MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
1055 MODULE_AUTHOR("MyungJoo Ham <[email protected]>");