drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #ifdef CONFIG_ARM64
  52 #define UART_NR                 12
  53 #else
  54 #define UART_NR                 CONFIG_SERIAL_SAMSUNG_UARTS
  55 #endif
  56
  57 #define S3C24XX_TX_PIO                  1
  58 #define S3C24XX_TX_DMA                  2
  59 #define S3C24XX_RX_PIO                  1
  60 #define S3C24XX_RX_DMA                  2
  61
  62 /* flag to ignore all characters coming in */
  63 #define RXSTAT_DUMMY_READ (0x10000000)
  64
  65 enum s3c24xx_port_type {
  66         TYPE_S3C24XX,
  67         TYPE_S3C6400,
  68         TYPE_APPLE_S5L,
  69 };
  70
  71 struct s3c24xx_uart_info {
  72         const char              *name;
  73         enum s3c24xx_port_type  type;
  74         unsigned int            port_type;
  75         unsigned int            fifosize;
  76         unsigned long           rx_fifomask;
  77         unsigned long           rx_fifoshift;
  78         unsigned long           rx_fifofull;
  79         unsigned long           tx_fifomask;
  80         unsigned long           tx_fifoshift;
  81         unsigned long           tx_fifofull;
  82         unsigned int            def_clk_sel;
  83         unsigned long           num_clks;
  84         unsigned long           clksel_mask;
  85         unsigned long           clksel_shift;
  86         unsigned long           ucon_mask;
  87
  88         /* uart port features */
  89
  90         unsigned int            has_divslot:1;
  91 };
  92
  93 struct s3c24xx_serial_drv_data {
  94         const struct s3c24xx_uart_info  info;
  95         const struct s3c2410_uartcfg    def_cfg;
  96         const unsigned int              fifosize[UART_NR];
  97 };
  98
  99 struct s3c24xx_uart_dma {
 100         unsigned int                    rx_chan_id;
 101         unsigned int                    tx_chan_id;
 102
 103         struct dma_slave_config         rx_conf;
 104         struct dma_slave_config         tx_conf;
 105
 106         struct dma_chan                 *rx_chan;
 107         struct dma_chan                 *tx_chan;
 108
 109         dma_addr_t                      rx_addr;
 110         dma_addr_t                      tx_addr;
 111
 112         dma_cookie_t                    rx_cookie;
 113         dma_cookie_t                    tx_cookie;
 114
 115         char                            *rx_buf;
 116
 117         dma_addr_t                      tx_transfer_addr;
 118
 119         size_t                          rx_size;
 120         size_t                          tx_size;
 121
 122         struct dma_async_tx_descriptor  *tx_desc;
 123         struct dma_async_tx_descriptor  *rx_desc;
 124
 125         int                             tx_bytes_requested;
 126         int                             rx_bytes_requested;
 127 };
 128
 129 struct s3c24xx_uart_port {
 130         unsigned char                   rx_claimed;
 131         unsigned char                   tx_claimed;
 132         unsigned char                   rx_enabled;
 133         unsigned char                   tx_enabled;
 134         unsigned int                    pm_level;
 135         unsigned long                   baudclk_rate;
 136         unsigned int                    min_dma_size;
 137
 138         unsigned int                    rx_irq;
 139         unsigned int                    tx_irq;
 140
 141         unsigned int                    tx_in_progress;
 142         unsigned int                    tx_mode;
 143         unsigned int                    rx_mode;
 144
 145         const struct s3c24xx_uart_info  *info;
 146         struct clk                      *clk;
 147         struct clk                      *baudclk;
 148         struct uart_port                port;
 149         const struct s3c24xx_serial_drv_data    *drv_data;
 150
 151         /* reference to platform data */
 152         const struct s3c2410_uartcfg    *cfg;
 153
 154         struct s3c24xx_uart_dma         *dma;
 155
 156 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 157         struct notifier_block           freq_transition;
 158 #endif
 159 };
 160
 161 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 162
 163 /* conversion functions */
 164
 165 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 166
 167 /* register access controls */
 168
 169 #define portaddr(port, reg) ((port)->membase + (reg))
 170 #define portaddrl(port, reg) \
 171         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 172
 173 static u32 rd_reg(const struct uart_port *port, u32 reg)
 174 {
 175         switch (port->iotype) {
 176         case UPIO_MEM:
 177                 return readb_relaxed(portaddr(port, reg));
 178         case UPIO_MEM32:
 179                 return readl_relaxed(portaddr(port, reg));
 180         default:
 181                 return 0;
 182         }
 183         return 0;
 184 }
 185
 186 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 187
 188 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 189 {
 190         switch (port->iotype) {
 191         case UPIO_MEM:
 192                 writeb_relaxed(val, portaddr(port, reg));
 193                 break;
 194         case UPIO_MEM32:
 195                 writel_relaxed(val, portaddr(port, reg));
 196                 break;
 197         }
 198 }
 199
 200 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 201
 202 /* Byte-order aware bit setting/clearing functions. */
 203
 204 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 205                                    unsigned int reg)
 206 {
 207         unsigned long flags;
 208         u32 val;
 209
 210         local_irq_save(flags);
 211         val = rd_regl(port, reg);
 212         val |= (1 << idx);
 213         wr_regl(port, reg, val);
 214         local_irq_restore(flags);
 215 }
 216
 217 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 218                                      unsigned int reg)
 219 {
 220         unsigned long flags;
 221         u32 val;
 222
 223         local_irq_save(flags);
 224         val = rd_regl(port, reg);
 225         val &= ~(1 << idx);
 226         wr_regl(port, reg, val);
 227         local_irq_restore(flags);
 228 }
 229
 230 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 231 {
 232         return container_of(port, struct s3c24xx_uart_port, port);
 233 }
 234
 235 /* translate a port to the device name */
 236
 237 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 238 {
 239         return to_platform_device(port->dev)->name;
 240 }
 241
 242 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 243 {
 244         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 245 }
 246
 247 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 248 {
 249         struct s3c24xx_uart_port *ourport = to_ourport(port);
 250         unsigned long flags;
 251         unsigned int ucon, ufcon;
 252         int count = 10000;
 253
 254         spin_lock_irqsave(&port->lock, flags);
 255
 256         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 257                 udelay(100);
 258
 259         ufcon = rd_regl(port, S3C2410_UFCON);
 260         ufcon |= S3C2410_UFCON_RESETRX;
 261         wr_regl(port, S3C2410_UFCON, ufcon);
 262
 263         ucon = rd_regl(port, S3C2410_UCON);
 264         ucon |= S3C2410_UCON_RXIRQMODE;
 265         wr_regl(port, S3C2410_UCON, ucon);
 266
 267         ourport->rx_enabled = 1;
 268         spin_unlock_irqrestore(&port->lock, flags);
 269 }
 270
 271 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 272 {
 273         struct s3c24xx_uart_port *ourport = to_ourport(port);
 274         unsigned long flags;
 275         unsigned int ucon;
 276
 277         spin_lock_irqsave(&port->lock, flags);
 278
 279         ucon = rd_regl(port, S3C2410_UCON);
 280         ucon &= ~S3C2410_UCON_RXIRQMODE;
 281         wr_regl(port, S3C2410_UCON, ucon);
 282
 283         ourport->rx_enabled = 0;
 284         spin_unlock_irqrestore(&port->lock, flags);
 285 }
 286
 287 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 288 {
 289         struct s3c24xx_uart_port *ourport = to_ourport(port);
 290         struct s3c24xx_uart_dma *dma = ourport->dma;
 291         struct dma_tx_state state;
 292         int count;
 293
 294         if (!ourport->tx_enabled)
 295                 return;
 296
 297         switch (ourport->info->type) {
 298         case TYPE_S3C6400:
 299                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 300                 break;
 301         case TYPE_APPLE_S5L:
 302                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 303                 break;
 304         default:
 305                 disable_irq_nosync(ourport->tx_irq);
 306                 break;
 307         }
 308
 309         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 310                 dmaengine_pause(dma->tx_chan);
 311                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 312                 dmaengine_terminate_all(dma->tx_chan);
 313                 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 314                                         dma->tx_transfer_addr, dma->tx_size,
 315                                         DMA_TO_DEVICE);
 316                 async_tx_ack(dma->tx_desc);
 317                 count = dma->tx_bytes_requested - state.residue;
 318                 uart_xmit_advance(port, count);
 319         }
 320
 321         ourport->tx_enabled = 0;
 322         ourport->tx_in_progress = 0;
 323
 324         if (port->flags & UPF_CONS_FLOW)
 325                 s3c24xx_serial_rx_enable(port);
 326
 327         ourport->tx_mode = 0;
 328 }
 329
 330 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 331
 332 static void s3c24xx_serial_tx_dma_complete(void *args)
 333 {
 334         struct s3c24xx_uart_port *ourport = args;
 335         struct uart_port *port = &ourport->port;
 336         struct circ_buf *xmit = &port->state->xmit;
 337         struct s3c24xx_uart_dma *dma = ourport->dma;
 338         struct dma_tx_state state;
 339         unsigned long flags;
 340         int count;
 341
 342         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 343         count = dma->tx_bytes_requested - state.residue;
 344         async_tx_ack(dma->tx_desc);
 345
 346         dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 347                                 dma->tx_transfer_addr, dma->tx_size,
 348                                 DMA_TO_DEVICE);
 349
 350         spin_lock_irqsave(&port->lock, flags);
 351
 352         uart_xmit_advance(port, count);
 353         ourport->tx_in_progress = 0;
 354
 355         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 356                 uart_write_wakeup(port);
 357
 358         s3c24xx_serial_start_next_tx(ourport);
 359         spin_unlock_irqrestore(&port->lock, flags);
 360 }
 361
 362 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 363 {
 364         const struct uart_port *port = &ourport->port;
 365         u32 ucon;
 366
 367         /* Mask Tx interrupt */
 368         switch (ourport->info->type) {
 369         case TYPE_S3C6400:
 370                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 371                 break;
 372         case TYPE_APPLE_S5L:
 373                 WARN_ON(1); // No DMA
 374                 break;
 375         default:
 376                 disable_irq_nosync(ourport->tx_irq);
 377                 break;
 378         }
 379
 380         /* Enable tx dma mode */
 381         ucon = rd_regl(port, S3C2410_UCON);
 382         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 383         ucon |= S3C64XX_UCON_TXBURST_1;
 384         ucon |= S3C64XX_UCON_TXMODE_DMA;
 385         wr_regl(port,  S3C2410_UCON, ucon);
 386
 387         ourport->tx_mode = S3C24XX_TX_DMA;
 388 }
 389
 390 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 391 {
 392         const struct uart_port *port = &ourport->port;
 393         u32 ucon, ufcon;
 394
 395         /* Set ufcon txtrig */
 396         ourport->tx_in_progress = S3C24XX_TX_PIO;
 397         ufcon = rd_regl(port, S3C2410_UFCON);
 398         wr_regl(port,  S3C2410_UFCON, ufcon);
 399
 400         /* Enable tx pio mode */
 401         ucon = rd_regl(port, S3C2410_UCON);
 402         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 403         ucon |= S3C64XX_UCON_TXMODE_CPU;
 404         wr_regl(port,  S3C2410_UCON, ucon);
 405
 406         /* Unmask Tx interrupt */
 407         switch (ourport->info->type) {
 408         case TYPE_S3C6400:
 409                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 410                                   S3C64XX_UINTM);
 411                 break;
 412         case TYPE_APPLE_S5L:
 413                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 414                 wr_regl(port, S3C2410_UCON, ucon);
 415                 break;
 416         default:
 417                 enable_irq(ourport->tx_irq);
 418                 break;
 419         }
 420
 421         ourport->tx_mode = S3C24XX_TX_PIO;
 422
 423         /*
 424          * The Apple version only has edge triggered TX IRQs, so we need
 425          * to kick off the process by sending some characters here.
 426          */
 427         if (ourport->info->type == TYPE_APPLE_S5L)
 428                 s3c24xx_serial_tx_chars(ourport);
 429 }
 430
 431 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 432 {
 433         if (ourport->tx_mode != S3C24XX_TX_PIO)
 434                 enable_tx_pio(ourport);
 435 }
 436
 437 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 438                                       unsigned int count)
 439 {
 440         struct uart_port *port = &ourport->port;
 441         struct circ_buf *xmit = &port->state->xmit;
 442         struct s3c24xx_uart_dma *dma = ourport->dma;
 443
 444         if (ourport->tx_mode != S3C24XX_TX_DMA)
 445                 enable_tx_dma(ourport);
 446
 447         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 448         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 449
 450         dma_sync_single_for_device(dma->tx_chan->device->dev,
 451                                    dma->tx_transfer_addr, dma->tx_size,
 452                                    DMA_TO_DEVICE);
 453
 454         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 455                                 dma->tx_transfer_addr, dma->tx_size,
 456                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 457         if (!dma->tx_desc) {
 458                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 459                 return -EIO;
 460         }
 461
 462         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 463         dma->tx_desc->callback_param = ourport;
 464         dma->tx_bytes_requested = dma->tx_size;
 465
 466         ourport->tx_in_progress = S3C24XX_TX_DMA;
 467         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 468         dma_async_issue_pending(dma->tx_chan);
 469         return 0;
 470 }
 471
 472 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 473 {
 474         struct uart_port *port = &ourport->port;
 475         struct circ_buf *xmit = &port->state->xmit;
 476         unsigned long count;
 477
 478         /* Get data size up to the end of buffer */
 479         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 480
 481         if (!count) {
 482                 s3c24xx_serial_stop_tx(port);
 483                 return;
 484         }
 485
 486         if (!ourport->dma || !ourport->dma->tx_chan ||
 487             count < ourport->min_dma_size ||
 488             xmit->tail & (dma_get_cache_alignment() - 1))
 489                 s3c24xx_serial_start_tx_pio(ourport);
 490         else
 491                 s3c24xx_serial_start_tx_dma(ourport, count);
 492 }
 493
 494 static void s3c24xx_serial_start_tx(struct uart_port *port)
 495 {
 496         struct s3c24xx_uart_port *ourport = to_ourport(port);
 497         struct circ_buf *xmit = &port->state->xmit;
 498
 499         if (!ourport->tx_enabled) {
 500                 if (port->flags & UPF_CONS_FLOW)
 501                         s3c24xx_serial_rx_disable(port);
 502
 503                 ourport->tx_enabled = 1;
 504                 if (!ourport->dma || !ourport->dma->tx_chan)
 505                         s3c24xx_serial_start_tx_pio(ourport);
 506         }
 507
 508         if (ourport->dma && ourport->dma->tx_chan) {
 509                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 510                         s3c24xx_serial_start_next_tx(ourport);
 511         }
 512 }
 513
 514 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 515                 struct tty_port *tty, int count)
 516 {
 517         struct s3c24xx_uart_dma *dma = ourport->dma;
 518         int copied;
 519
 520         if (!count)
 521                 return;
 522
 523         dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 524                                 dma->rx_size, DMA_FROM_DEVICE);
 525
 526         ourport->port.icount.rx += count;
 527         if (!tty) {
 528                 dev_err(ourport->port.dev, "No tty port\n");
 529                 return;
 530         }
 531         copied = tty_insert_flip_string(tty,
 532                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 533         if (copied != count) {
 534                 WARN_ON(1);
 535                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 536         }
 537 }
 538
 539 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 540 {
 541         struct s3c24xx_uart_port *ourport = to_ourport(port);
 542         struct s3c24xx_uart_dma *dma = ourport->dma;
 543         struct tty_port *t = &port->state->port;
 544         struct dma_tx_state state;
 545         enum dma_status dma_status;
 546         unsigned int received;
 547
 548         if (ourport->rx_enabled) {
 549                 dev_dbg(port->dev, "stopping rx\n");
 550                 switch (ourport->info->type) {
 551                 case TYPE_S3C6400:
 552                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 553                                         S3C64XX_UINTM);
 554                         break;
 555                 case TYPE_APPLE_S5L:
 556                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 557                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 558                         break;
 559                 default:
 560                         disable_irq_nosync(ourport->rx_irq);
 561                         break;
 562                 }
 563                 ourport->rx_enabled = 0;
 564         }
 565         if (dma && dma->rx_chan) {
 566                 dmaengine_pause(dma->tx_chan);
 567                 dma_status = dmaengine_tx_status(dma->rx_chan,
 568                                 dma->rx_cookie, &state);
 569                 if (dma_status == DMA_IN_PROGRESS ||
 570                         dma_status == DMA_PAUSED) {
 571                         received = dma->rx_bytes_requested - state.residue;
 572                         dmaengine_terminate_all(dma->rx_chan);
 573                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 574                 }
 575         }
 576 }
 577
 578 static inline const struct s3c24xx_uart_info
 579         *s3c24xx_port_to_info(struct uart_port *port)
 580 {
 581         return to_ourport(port)->info;
 582 }
 583
 584 static inline const struct s3c2410_uartcfg
 585         *s3c24xx_port_to_cfg(const struct uart_port *port)
 586 {
 587         const struct s3c24xx_uart_port *ourport;
 588
 589         if (port->dev == NULL)
 590                 return NULL;
 591
 592         ourport = container_of(port, struct s3c24xx_uart_port, port);
 593         return ourport->cfg;
 594 }
 595
 596 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 597                                      unsigned long ufstat)
 598 {
 599         const struct s3c24xx_uart_info *info = ourport->info;
 600
 601         if (ufstat & info->rx_fifofull)
 602                 return ourport->port.fifosize;
 603
 604         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 605 }
 606
 607 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 608 static void s3c24xx_serial_rx_dma_complete(void *args)
 609 {
 610         struct s3c24xx_uart_port *ourport = args;
 611         struct uart_port *port = &ourport->port;
 612
 613         struct s3c24xx_uart_dma *dma = ourport->dma;
 614         struct tty_port *t = &port->state->port;
 615         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 616
 617         struct dma_tx_state state;
 618         unsigned long flags;
 619         int received;
 620
 621         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 622         received  = dma->rx_bytes_requested - state.residue;
 623         async_tx_ack(dma->rx_desc);
 624
 625         spin_lock_irqsave(&port->lock, flags);
 626
 627         if (received)
 628                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 629
 630         if (tty) {
 631                 tty_flip_buffer_push(t);
 632                 tty_kref_put(tty);
 633         }
 634
 635         s3c64xx_start_rx_dma(ourport);
 636
 637         spin_unlock_irqrestore(&port->lock, flags);
 638 }
 639
 640 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 641 {
 642         struct s3c24xx_uart_dma *dma = ourport->dma;
 643
 644         dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 645                                    dma->rx_size, DMA_FROM_DEVICE);
 646
 647         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 648                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 649                                 DMA_PREP_INTERRUPT);
 650         if (!dma->rx_desc) {
 651                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 652                 return;
 653         }
 654
 655         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 656         dma->rx_desc->callback_param = ourport;
 657         dma->rx_bytes_requested = dma->rx_size;
 658
 659         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 660         dma_async_issue_pending(dma->rx_chan);
 661 }
 662
 663 /* ? - where has parity gone?? */
 664 #define S3C2410_UERSTAT_PARITY (0x1000)
 665
 666 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 667 {
 668         struct uart_port *port = &ourport->port;
 669         unsigned int ucon;
 670
 671         /* set Rx mode to DMA mode */
 672         ucon = rd_regl(port, S3C2410_UCON);
 673         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 674                         S3C64XX_UCON_TIMEOUT_MASK |
 675                         S3C64XX_UCON_EMPTYINT_EN |
 676                         S3C64XX_UCON_DMASUS_EN |
 677                         S3C64XX_UCON_TIMEOUT_EN |
 678                         S3C64XX_UCON_RXMODE_MASK);
 679         ucon |= S3C64XX_UCON_RXBURST_1 |
 680                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 681                         S3C64XX_UCON_EMPTYINT_EN |
 682                         S3C64XX_UCON_TIMEOUT_EN |
 683                         S3C64XX_UCON_RXMODE_DMA;
 684         wr_regl(port, S3C2410_UCON, ucon);
 685
 686         ourport->rx_mode = S3C24XX_RX_DMA;
 687 }
 688
 689 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 690 {
 691         struct uart_port *port = &ourport->port;
 692         unsigned int ucon;
 693
 694         /* set Rx mode to DMA mode */
 695         ucon = rd_regl(port, S3C2410_UCON);
 696         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 697         ucon |= S3C64XX_UCON_RXMODE_CPU;
 698
 699         /* Apple types use these bits for IRQ masks */
 700         if (ourport->info->type != TYPE_APPLE_S5L) {
 701                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 702                                 S3C64XX_UCON_EMPTYINT_EN |
 703                                 S3C64XX_UCON_DMASUS_EN |
 704                                 S3C64XX_UCON_TIMEOUT_EN);
 705                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 706                                 S3C64XX_UCON_TIMEOUT_EN;
 707         }
 708         wr_regl(port, S3C2410_UCON, ucon);
 709
 710         ourport->rx_mode = S3C24XX_RX_PIO;
 711 }
 712
 713 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 714
 715 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 716 {
 717         unsigned int utrstat, received;
 718         struct s3c24xx_uart_port *ourport = dev_id;
 719         struct uart_port *port = &ourport->port;
 720         struct s3c24xx_uart_dma *dma = ourport->dma;
 721         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 722         struct tty_port *t = &port->state->port;
 723         struct dma_tx_state state;
 724
 725         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 726         rd_regl(port, S3C2410_UFSTAT);
 727
 728         spin_lock(&port->lock);
 729
 730         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 731                 s3c64xx_start_rx_dma(ourport);
 732                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 733                         enable_rx_dma(ourport);
 734                 goto finish;
 735         }
 736
 737         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 738                 dmaengine_pause(dma->rx_chan);
 739                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 740                 dmaengine_terminate_all(dma->rx_chan);
 741                 received = dma->rx_bytes_requested - state.residue;
 742                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 743
 744                 enable_rx_pio(ourport);
 745         }
 746
 747         s3c24xx_serial_rx_drain_fifo(ourport);
 748
 749         if (tty) {
 750                 tty_flip_buffer_push(t);
 751                 tty_kref_put(tty);
 752         }
 753
 754         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 755
 756 finish:
 757         spin_unlock(&port->lock);
 758
 759         return IRQ_HANDLED;
 760 }
 761
 762 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 763 {
 764         struct uart_port *port = &ourport->port;
 765         unsigned int ufcon, ch, flag, ufstat, uerstat;
 766         unsigned int fifocnt = 0;
 767         int max_count = port->fifosize;
 768
 769         while (max_count-- > 0) {
 770                 /*
 771                  * Receive all characters known to be in FIFO
 772                  * before reading FIFO level again
 773                  */
 774                 if (fifocnt == 0) {
 775                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 776                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 777                         if (fifocnt == 0)
 778                                 break;
 779                 }
 780                 fifocnt--;
 781
 782                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 783                 ch = rd_reg(port, S3C2410_URXH);
 784
 785                 if (port->flags & UPF_CONS_FLOW) {
 786                         int txe = s3c24xx_serial_txempty_nofifo(port);
 787
 788                         if (ourport->rx_enabled) {
 789                                 if (!txe) {
 790                                         ourport->rx_enabled = 0;
 791                                         continue;
 792                                 }
 793                         } else {
 794                                 if (txe) {
 795                                         ufcon = rd_regl(port, S3C2410_UFCON);
 796                                         ufcon |= S3C2410_UFCON_RESETRX;
 797                                         wr_regl(port, S3C2410_UFCON, ufcon);
 798                                         ourport->rx_enabled = 1;
 799                                         return;
 800                                 }
 801                                 continue;
 802                         }
 803                 }
 804
 805                 /* insert the character into the buffer */
 806
 807                 flag = TTY_NORMAL;
 808                 port->icount.rx++;
 809
 810                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 811                         dev_dbg(port->dev,
 812                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 813                                 ch, uerstat);
 814
 815                         /* check for break */
 816                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 817                                 dev_dbg(port->dev, "break!\n");
 818                                 port->icount.brk++;
 819                                 if (uart_handle_break(port))
 820                                         continue; /* Ignore character */
 821                         }
 822
 823                         if (uerstat & S3C2410_UERSTAT_FRAME)
 824                                 port->icount.frame++;
 825                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 826                                 port->icount.overrun++;
 827
 828                         uerstat &= port->read_status_mask;
 829
 830                         if (uerstat & S3C2410_UERSTAT_BREAK)
 831                                 flag = TTY_BREAK;
 832                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 833                                 flag = TTY_PARITY;
 834                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 835                                             S3C2410_UERSTAT_OVERRUN))
 836                                 flag = TTY_FRAME;
 837                 }
 838
 839                 if (uart_handle_sysrq_char(port, ch))
 840                         continue; /* Ignore character */
 841
 842                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 843                                  ch, flag);
 844         }
 845
 846         tty_flip_buffer_push(&port->state->port);
 847 }
 848
 849 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 850 {
 851         struct s3c24xx_uart_port *ourport = dev_id;
 852         struct uart_port *port = &ourport->port;
 853
 854         spin_lock(&port->lock);
 855         s3c24xx_serial_rx_drain_fifo(ourport);
 856         spin_unlock(&port->lock);
 857
 858         return IRQ_HANDLED;
 859 }
 860
 861 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 862 {
 863         struct s3c24xx_uart_port *ourport = dev_id;
 864
 865         if (ourport->dma && ourport->dma->rx_chan)
 866                 return s3c24xx_serial_rx_chars_dma(dev_id);
 867         return s3c24xx_serial_rx_chars_pio(dev_id);
 868 }
 869
 870 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 871 {
 872         struct uart_port *port = &ourport->port;
 873         struct circ_buf *xmit = &port->state->xmit;
 874         int count, dma_count = 0;
 875
 876         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 877
 878         if (ourport->dma && ourport->dma->tx_chan &&
 879             count >= ourport->min_dma_size) {
 880                 int align = dma_get_cache_alignment() -
 881                         (xmit->tail & (dma_get_cache_alignment() - 1));
 882                 if (count - align >= ourport->min_dma_size) {
 883                         dma_count = count - align;
 884                         count = align;
 885                 }
 886         }
 887
 888         if (port->x_char) {
 889                 wr_reg(port, S3C2410_UTXH, port->x_char);
 890                 port->icount.tx++;
 891                 port->x_char = 0;
 892                 return;
 893         }
 894
 895         /* if there isn't anything more to transmit, or the uart is now
 896          * stopped, disable the uart and exit
 897          */
 898
 899         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 900                 s3c24xx_serial_stop_tx(port);
 901                 return;
 902         }
 903
 904         /* try and drain the buffer... */
 905
 906         if (count > port->fifosize) {
 907                 count = port->fifosize;
 908                 dma_count = 0;
 909         }
 910
 911         while (!uart_circ_empty(xmit) && count > 0) {
 912                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 913                         break;
 914
 915                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 916                 uart_xmit_advance(port, 1);
 917                 count--;
 918         }
 919
 920         if (!count && dma_count) {
 921                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 922                 return;
 923         }
 924
 925         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 926                 uart_write_wakeup(port);
 927
 928         if (uart_circ_empty(xmit))
 929                 s3c24xx_serial_stop_tx(port);
 930 }
 931
 932 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 933 {
 934         struct s3c24xx_uart_port *ourport = id;
 935         struct uart_port *port = &ourport->port;
 936
 937         spin_lock(&port->lock);
 938
 939         s3c24xx_serial_tx_chars(ourport);
 940
 941         spin_unlock(&port->lock);
 942         return IRQ_HANDLED;
 943 }
 944
 945 /* interrupt handler for s3c64xx and later SoC's.*/
 946 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 947 {
 948         const struct s3c24xx_uart_port *ourport = id;
 949         const struct uart_port *port = &ourport->port;
 950         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 951         irqreturn_t ret = IRQ_HANDLED;
 952
 953         if (pend & S3C64XX_UINTM_RXD_MSK) {
 954                 ret = s3c24xx_serial_rx_irq(irq, id);
 955                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 956         }
 957         if (pend & S3C64XX_UINTM_TXD_MSK) {
 958                 ret = s3c24xx_serial_tx_irq(irq, id);
 959                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 960         }
 961         return ret;
 962 }
 963
 964 /* interrupt handler for Apple SoC's.*/
 965 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 966 {
 967         const struct s3c24xx_uart_port *ourport = id;
 968         const struct uart_port *port = &ourport->port;
 969         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 970         irqreturn_t ret = IRQ_NONE;
 971
 972         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 973                 wr_regl(port, S3C2410_UTRSTAT,
 974                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 975                 ret = s3c24xx_serial_rx_irq(irq, id);
 976         }
 977         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 978                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 979                 ret = s3c24xx_serial_tx_irq(irq, id);
 980         }
 981
 982         return ret;
 983 }
 984
 985 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 986 {
 987         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 988         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 989         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 990
 991         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 992                 if ((ufstat & info->tx_fifomask) != 0 ||
 993                     (ufstat & info->tx_fifofull))
 994                         return 0;
 995
 996                 return 1;
 997         }
 998
 999         return s3c24xx_serial_txempty_nofifo(port);
1000 }
1001
1002 /* no modem control lines */
1003 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1004 {
1005         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1006
1007         if (umstat & S3C2410_UMSTAT_CTS)
1008                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1009         else
1010                 return TIOCM_CAR | TIOCM_DSR;
1011 }
1012
1013 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1014 {
1015         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1016         unsigned int ucon = rd_regl(port, S3C2410_UCON);
1017
1018         if (mctrl & TIOCM_RTS)
1019                 umcon |= S3C2410_UMCOM_RTS_LOW;
1020         else
1021                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1022
1023         wr_regl(port, S3C2410_UMCON, umcon);
1024
1025         if (mctrl & TIOCM_LOOP)
1026                 ucon |= S3C2410_UCON_LOOPBACK;
1027         else
1028                 ucon &= ~S3C2410_UCON_LOOPBACK;
1029
1030         wr_regl(port, S3C2410_UCON, ucon);
1031 }
1032
1033 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1034 {
1035         unsigned long flags;
1036         unsigned int ucon;
1037
1038         spin_lock_irqsave(&port->lock, flags);
1039
1040         ucon = rd_regl(port, S3C2410_UCON);
1041
1042         if (break_state)
1043                 ucon |= S3C2410_UCON_SBREAK;
1044         else
1045                 ucon &= ~S3C2410_UCON_SBREAK;
1046
1047         wr_regl(port, S3C2410_UCON, ucon);
1048
1049         spin_unlock_irqrestore(&port->lock, flags);
1050 }
1051
1052 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1053 {
1054         struct s3c24xx_uart_dma *dma = p->dma;
1055         struct dma_slave_caps dma_caps;
1056         const char *reason = NULL;
1057         int ret;
1058
1059         /* Default slave configuration parameters */
1060         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1061         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1062         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1063         dma->rx_conf.src_maxburst       = 1;
1064
1065         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1066         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1067         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1068         dma->tx_conf.dst_maxburst       = 1;
1069
1070         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1071
1072         if (IS_ERR(dma->rx_chan)) {
1073                 reason = "DMA RX channel request failed";
1074                 ret = PTR_ERR(dma->rx_chan);
1075                 goto err_warn;
1076         }
1077
1078         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1079         if (ret < 0 ||
1080             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1081                 reason = "insufficient DMA RX engine capabilities";
1082                 ret = -EOPNOTSUPP;
1083                 goto err_release_rx;
1084         }
1085
1086         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1087
1088         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1089         if (IS_ERR(dma->tx_chan)) {
1090                 reason = "DMA TX channel request failed";
1091                 ret = PTR_ERR(dma->tx_chan);
1092                 goto err_release_rx;
1093         }
1094
1095         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1096         if (ret < 0 ||
1097             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1098                 reason = "insufficient DMA TX engine capabilities";
1099                 ret = -EOPNOTSUPP;
1100                 goto err_release_tx;
1101         }
1102
1103         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1104
1105         /* RX buffer */
1106         dma->rx_size = PAGE_SIZE;
1107
1108         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1109         if (!dma->rx_buf) {
1110                 ret = -ENOMEM;
1111                 goto err_release_tx;
1112         }
1113
1114         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1115                                       dma->rx_size, DMA_FROM_DEVICE);
1116         if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1117                 reason = "DMA mapping error for RX buffer";
1118                 ret = -EIO;
1119                 goto err_free_rx;
1120         }
1121
1122         /* TX buffer */
1123         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1124                                       p->port.state->xmit.buf, UART_XMIT_SIZE,
1125                                       DMA_TO_DEVICE);
1126         if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1127                 reason = "DMA mapping error for TX buffer";
1128                 ret = -EIO;
1129                 goto err_unmap_rx;
1130         }
1131
1132         return 0;
1133
1134 err_unmap_rx:
1135         dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1136                          dma->rx_size, DMA_FROM_DEVICE);
1137 err_free_rx:
1138         kfree(dma->rx_buf);
1139 err_release_tx:
1140         dma_release_channel(dma->tx_chan);
1141 err_release_rx:
1142         dma_release_channel(dma->rx_chan);
1143 err_warn:
1144         if (reason)
1145                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1146         return ret;
1147 }
1148
1149 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1150 {
1151         struct s3c24xx_uart_dma *dma = p->dma;
1152
1153         if (dma->rx_chan) {
1154                 dmaengine_terminate_all(dma->rx_chan);
1155                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1156                                  dma->rx_size, DMA_FROM_DEVICE);
1157                 kfree(dma->rx_buf);
1158                 dma_release_channel(dma->rx_chan);
1159                 dma->rx_chan = NULL;
1160         }
1161
1162         if (dma->tx_chan) {
1163                 dmaengine_terminate_all(dma->tx_chan);
1164                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1165                                  UART_XMIT_SIZE, DMA_TO_DEVICE);
1166                 dma_release_channel(dma->tx_chan);
1167                 dma->tx_chan = NULL;
1168         }
1169 }
1170
1171 static void s3c24xx_serial_shutdown(struct uart_port *port)
1172 {
1173         struct s3c24xx_uart_port *ourport = to_ourport(port);
1174
1175         if (ourport->tx_claimed) {
1176                 free_irq(ourport->tx_irq, ourport);
1177                 ourport->tx_enabled = 0;
1178                 ourport->tx_claimed = 0;
1179                 ourport->tx_mode = 0;
1180         }
1181
1182         if (ourport->rx_claimed) {
1183                 free_irq(ourport->rx_irq, ourport);
1184                 ourport->rx_claimed = 0;
1185                 ourport->rx_enabled = 0;
1186         }
1187
1188         if (ourport->dma)
1189                 s3c24xx_serial_release_dma(ourport);
1190
1191         ourport->tx_in_progress = 0;
1192 }
1193
1194 static void s3c64xx_serial_shutdown(struct uart_port *port)
1195 {
1196         struct s3c24xx_uart_port *ourport = to_ourport(port);
1197
1198         ourport->tx_enabled = 0;
1199         ourport->tx_mode = 0;
1200         ourport->rx_enabled = 0;
1201
1202         free_irq(port->irq, ourport);
1203
1204         wr_regl(port, S3C64XX_UINTP, 0xf);
1205         wr_regl(port, S3C64XX_UINTM, 0xf);
1206
1207         if (ourport->dma)
1208                 s3c24xx_serial_release_dma(ourport);
1209
1210         ourport->tx_in_progress = 0;
1211 }
1212
1213 static void apple_s5l_serial_shutdown(struct uart_port *port)
1214 {
1215         struct s3c24xx_uart_port *ourport = to_ourport(port);
1216
1217         unsigned int ucon;
1218
1219         ucon = rd_regl(port, S3C2410_UCON);
1220         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1221                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1222                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1223         wr_regl(port, S3C2410_UCON, ucon);
1224
1225         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1226
1227         free_irq(port->irq, ourport);
1228
1229         ourport->tx_enabled = 0;
1230         ourport->tx_mode = 0;
1231         ourport->rx_enabled = 0;
1232
1233         if (ourport->dma)
1234                 s3c24xx_serial_release_dma(ourport);
1235
1236         ourport->tx_in_progress = 0;
1237 }
1238
1239 static int s3c24xx_serial_startup(struct uart_port *port)
1240 {
1241         struct s3c24xx_uart_port *ourport = to_ourport(port);
1242         int ret;
1243
1244         ourport->rx_enabled = 1;
1245
1246         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1247                           s3c24xx_serial_portname(port), ourport);
1248
1249         if (ret != 0) {
1250                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1251                 return ret;
1252         }
1253
1254         ourport->rx_claimed = 1;
1255
1256         dev_dbg(port->dev, "requesting tx irq...\n");
1257
1258         ourport->tx_enabled = 1;
1259
1260         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1261                           s3c24xx_serial_portname(port), ourport);
1262
1263         if (ret) {
1264                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1265                 goto err;
1266         }
1267
1268         ourport->tx_claimed = 1;
1269
1270         /* the port reset code should have done the correct
1271          * register setup for the port controls
1272          */
1273
1274         return ret;
1275
1276 err:
1277         s3c24xx_serial_shutdown(port);
1278         return ret;
1279 }
1280
1281 static int s3c64xx_serial_startup(struct uart_port *port)
1282 {
1283         struct s3c24xx_uart_port *ourport = to_ourport(port);
1284         unsigned long flags;
1285         unsigned int ufcon;
1286         int ret;
1287
1288         wr_regl(port, S3C64XX_UINTM, 0xf);
1289         if (ourport->dma) {
1290                 ret = s3c24xx_serial_request_dma(ourport);
1291                 if (ret < 0) {
1292                         devm_kfree(port->dev, ourport->dma);
1293                         ourport->dma = NULL;
1294                 }
1295         }
1296
1297         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1298                           s3c24xx_serial_portname(port), ourport);
1299         if (ret) {
1300                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1301                 return ret;
1302         }
1303
1304         /* For compatibility with s3c24xx Soc's */
1305         ourport->rx_enabled = 1;
1306         ourport->tx_enabled = 0;
1307
1308         spin_lock_irqsave(&port->lock, flags);
1309
1310         ufcon = rd_regl(port, S3C2410_UFCON);
1311         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1312         if (!uart_console(port))
1313                 ufcon |= S3C2410_UFCON_RESETTX;
1314         wr_regl(port, S3C2410_UFCON, ufcon);
1315
1316         enable_rx_pio(ourport);
1317
1318         spin_unlock_irqrestore(&port->lock, flags);
1319
1320         /* Enable Rx Interrupt */
1321         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1322
1323         return ret;
1324 }
1325
1326 static int apple_s5l_serial_startup(struct uart_port *port)
1327 {
1328         struct s3c24xx_uart_port *ourport = to_ourport(port);
1329         unsigned long flags;
1330         unsigned int ufcon;
1331         int ret;
1332
1333         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1334
1335         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1336                           s3c24xx_serial_portname(port), ourport);
1337         if (ret) {
1338                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1339                 return ret;
1340         }
1341
1342         /* For compatibility with s3c24xx Soc's */
1343         ourport->rx_enabled = 1;
1344         ourport->tx_enabled = 0;
1345
1346         spin_lock_irqsave(&port->lock, flags);
1347
1348         ufcon = rd_regl(port, S3C2410_UFCON);
1349         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1350         if (!uart_console(port))
1351                 ufcon |= S3C2410_UFCON_RESETTX;
1352         wr_regl(port, S3C2410_UFCON, ufcon);
1353
1354         enable_rx_pio(ourport);
1355
1356         spin_unlock_irqrestore(&port->lock, flags);
1357
1358         /* Enable Rx Interrupt */
1359         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1360         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1361
1362         return ret;
1363 }
1364
1365 /* power power management control */
1366
1367 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1368                               unsigned int old)
1369 {
1370         struct s3c24xx_uart_port *ourport = to_ourport(port);
1371         int timeout = 10000;
1372
1373         ourport->pm_level = level;
1374
1375         switch (level) {
1376         case 3:
1377                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1378                         udelay(100);
1379
1380                 if (!IS_ERR(ourport->baudclk))
1381                         clk_disable_unprepare(ourport->baudclk);
1382
1383                 clk_disable_unprepare(ourport->clk);
1384                 break;
1385
1386         case 0:
1387                 clk_prepare_enable(ourport->clk);
1388
1389                 if (!IS_ERR(ourport->baudclk))
1390                         clk_prepare_enable(ourport->baudclk);
1391                 break;
1392         default:
1393                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1394         }
1395 }
1396
1397 /* baud rate calculation
1398  *
1399  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1400  * of different sources, including the peripheral clock ("pclk") and an
1401  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1402  * with a programmable extra divisor.
1403  *
1404  * The following code goes through the clock sources, and calculates the
1405  * baud clocks (and the resultant actual baud rates) and then tries to
1406  * pick the closest one and select that.
1407  *
1408  */
1409
1410 #define MAX_CLK_NAME_LENGTH 15
1411
1412 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1413 {
1414         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1415         unsigned int ucon;
1416
1417         if (info->num_clks == 1)
1418                 return 0;
1419
1420         ucon = rd_regl(port, S3C2410_UCON);
1421         ucon &= info->clksel_mask;
1422         return ucon >> info->clksel_shift;
1423 }
1424
1425 static void s3c24xx_serial_setsource(struct uart_port *port,
1426                         unsigned int clk_sel)
1427 {
1428         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1429         unsigned int ucon;
1430
1431         if (info->num_clks == 1)
1432                 return;
1433
1434         ucon = rd_regl(port, S3C2410_UCON);
1435         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1436                 return;
1437
1438         ucon &= ~info->clksel_mask;
1439         ucon |= clk_sel << info->clksel_shift;
1440         wr_regl(port, S3C2410_UCON, ucon);
1441 }
1442
1443 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1444                         unsigned int req_baud, struct clk **best_clk,
1445                         unsigned int *clk_num)
1446 {
1447         const struct s3c24xx_uart_info *info = ourport->info;
1448         struct clk *clk;
1449         unsigned long rate;
1450         unsigned int cnt, baud, quot, best_quot = 0;
1451         char clkname[MAX_CLK_NAME_LENGTH];
1452         int calc_deviation, deviation = (1 << 30) - 1;
1453
1454         for (cnt = 0; cnt < info->num_clks; cnt++) {
1455                 /* Keep selected clock if provided */
1456                 if (ourport->cfg->clk_sel &&
1457                         !(ourport->cfg->clk_sel & (1 << cnt)))
1458                         continue;
1459
1460                 sprintf(clkname, "clk_uart_baud%d", cnt);
1461                 clk = clk_get(ourport->port.dev, clkname);
1462                 if (IS_ERR(clk))
1463                         continue;
1464
1465                 rate = clk_get_rate(clk);
1466                 if (!rate)
1467                         continue;
1468
1469                 if (ourport->info->has_divslot) {
1470                         unsigned long div = rate / req_baud;
1471
1472                         /* The UDIVSLOT register on the newer UARTs allows us to
1473                          * get a divisor adjustment of 1/16th on the baud clock.
1474                          *
1475                          * We don't keep the UDIVSLOT value (the 16ths we
1476                          * calculated by not multiplying the baud by 16) as it
1477                          * is easy enough to recalculate.
1478                          */
1479
1480                         quot = div / 16;
1481                         baud = rate / div;
1482                 } else {
1483                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1484                         baud = rate / (quot * 16);
1485                 }
1486                 quot--;
1487
1488                 calc_deviation = req_baud - baud;
1489                 if (calc_deviation < 0)
1490                         calc_deviation = -calc_deviation;
1491
1492                 if (calc_deviation < deviation) {
1493                         *best_clk = clk;
1494                         best_quot = quot;
1495                         *clk_num = cnt;
1496                         deviation = calc_deviation;
1497                 }
1498         }
1499
1500         return best_quot;
1501 }
1502
1503 /* udivslot_table[]
1504  *
1505  * This table takes the fractional value of the baud divisor and gives
1506  * the recommended setting for the UDIVSLOT register.
1507  */
1508 static const u16 udivslot_table[16] = {
1509         [0] = 0x0000,
1510         [1] = 0x0080,
1511         [2] = 0x0808,
1512         [3] = 0x0888,
1513         [4] = 0x2222,
1514         [5] = 0x4924,
1515         [6] = 0x4A52,
1516         [7] = 0x54AA,
1517         [8] = 0x5555,
1518         [9] = 0xD555,
1519         [10] = 0xD5D5,
1520         [11] = 0xDDD5,
1521         [12] = 0xDDDD,
1522         [13] = 0xDFDD,
1523         [14] = 0xDFDF,
1524         [15] = 0xFFDF,
1525 };
1526
1527 static void s3c24xx_serial_set_termios(struct uart_port *port,
1528                                        struct ktermios *termios,
1529                                        const struct ktermios *old)
1530 {
1531         const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1532         struct s3c24xx_uart_port *ourport = to_ourport(port);
1533         struct clk *clk = ERR_PTR(-EINVAL);
1534         unsigned long flags;
1535         unsigned int baud, quot, clk_sel = 0;
1536         unsigned int ulcon;
1537         unsigned int umcon;
1538         unsigned int udivslot = 0;
1539
1540         /*
1541          * We don't support modem control lines.
1542          */
1543         termios->c_cflag &= ~(HUPCL | CMSPAR);
1544         termios->c_cflag |= CLOCAL;
1545
1546         /*
1547          * Ask the core to calculate the divisor for us.
1548          */
1549
1550         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1551         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1552         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1553                 quot = port->custom_divisor;
1554         if (IS_ERR(clk))
1555                 return;
1556
1557         /* check to see if we need  to change clock source */
1558
1559         if (ourport->baudclk != clk) {
1560                 clk_prepare_enable(clk);
1561
1562                 s3c24xx_serial_setsource(port, clk_sel);
1563
1564                 if (!IS_ERR(ourport->baudclk)) {
1565                         clk_disable_unprepare(ourport->baudclk);
1566                         ourport->baudclk = ERR_PTR(-EINVAL);
1567                 }
1568
1569                 ourport->baudclk = clk;
1570                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1571         }
1572
1573         if (ourport->info->has_divslot) {
1574                 unsigned int div = ourport->baudclk_rate / baud;
1575
1576                 if (cfg->has_fracval) {
1577                         udivslot = (div & 15);
1578                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1579                 } else {
1580                         udivslot = udivslot_table[div & 15];
1581                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1582                                 udivslot, div & 15);
1583                 }
1584         }
1585
1586         switch (termios->c_cflag & CSIZE) {
1587         case CS5:
1588                 dev_dbg(port->dev, "config: 5bits/char\n");
1589                 ulcon = S3C2410_LCON_CS5;
1590                 break;
1591         case CS6:
1592                 dev_dbg(port->dev, "config: 6bits/char\n");
1593                 ulcon = S3C2410_LCON_CS6;
1594                 break;
1595         case CS7:
1596                 dev_dbg(port->dev, "config: 7bits/char\n");
1597                 ulcon = S3C2410_LCON_CS7;
1598                 break;
1599         case CS8:
1600         default:
1601                 dev_dbg(port->dev, "config: 8bits/char\n");
1602                 ulcon = S3C2410_LCON_CS8;
1603                 break;
1604         }
1605
1606         /* preserve original lcon IR settings */
1607         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1608
1609         if (termios->c_cflag & CSTOPB)
1610                 ulcon |= S3C2410_LCON_STOPB;
1611
1612         if (termios->c_cflag & PARENB) {
1613                 if (termios->c_cflag & PARODD)
1614                         ulcon |= S3C2410_LCON_PODD;
1615                 else
1616                         ulcon |= S3C2410_LCON_PEVEN;
1617         } else {
1618                 ulcon |= S3C2410_LCON_PNONE;
1619         }
1620
1621         spin_lock_irqsave(&port->lock, flags);
1622
1623         dev_dbg(port->dev,
1624                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1625                 ulcon, quot, udivslot);
1626
1627         wr_regl(port, S3C2410_ULCON, ulcon);
1628         wr_regl(port, S3C2410_UBRDIV, quot);
1629
1630         port->status &= ~UPSTAT_AUTOCTS;
1631
1632         umcon = rd_regl(port, S3C2410_UMCON);
1633         if (termios->c_cflag & CRTSCTS) {
1634                 umcon |= S3C2410_UMCOM_AFC;
1635                 /* Disable RTS when RX FIFO contains 63 bytes */
1636                 umcon &= ~S3C2412_UMCON_AFC_8;
1637                 port->status = UPSTAT_AUTOCTS;
1638         } else {
1639                 umcon &= ~S3C2410_UMCOM_AFC;
1640         }
1641         wr_regl(port, S3C2410_UMCON, umcon);
1642
1643         if (ourport->info->has_divslot)
1644                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1645
1646         dev_dbg(port->dev,
1647                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1648                 rd_regl(port, S3C2410_ULCON),
1649                 rd_regl(port, S3C2410_UCON),
1650                 rd_regl(port, S3C2410_UFCON));
1651
1652         /*
1653          * Update the per-port timeout.
1654          */
1655         uart_update_timeout(port, termios->c_cflag, baud);
1656
1657         /*
1658          * Which character status flags are we interested in?
1659          */
1660         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1661         if (termios->c_iflag & INPCK)
1662                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1663                         S3C2410_UERSTAT_PARITY;
1664         /*
1665          * Which character status flags should we ignore?
1666          */
1667         port->ignore_status_mask = 0;
1668         if (termios->c_iflag & IGNPAR)
1669                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1670         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1671                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1672
1673         /*
1674          * Ignore all characters if CREAD is not set.
1675          */
1676         if ((termios->c_cflag & CREAD) == 0)
1677                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1678
1679         spin_unlock_irqrestore(&port->lock, flags);
1680 }
1681
1682 static const char *s3c24xx_serial_type(struct uart_port *port)
1683 {
1684         const struct s3c24xx_uart_port *ourport = to_ourport(port);
1685
1686         switch (ourport->info->type) {
1687         case TYPE_S3C24XX:
1688                 return "S3C24XX";
1689         case TYPE_S3C6400:
1690                 return "S3C6400/10";
1691         case TYPE_APPLE_S5L:
1692                 return "APPLE S5L";
1693         default:
1694                 return NULL;
1695         }
1696 }
1697
1698 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1699 {
1700         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1701
1702         if (flags & UART_CONFIG_TYPE)
1703                 port->type = info->port_type;
1704 }
1705
1706 /*
1707  * verify the new serial_struct (for TIOCSSERIAL).
1708  */
1709 static int
1710 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1711 {
1712         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1713
1714         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1715                 return -EINVAL;
1716
1717         return 0;
1718 }
1719
1720 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1721
1722 static struct console s3c24xx_serial_console;
1723
1724 static void __init s3c24xx_serial_register_console(void)
1725 {
1726         register_console(&s3c24xx_serial_console);
1727 }
1728
1729 static void s3c24xx_serial_unregister_console(void)
1730 {
1731         if (console_is_registered(&s3c24xx_serial_console))
1732                 unregister_console(&s3c24xx_serial_console);
1733 }
1734
1735 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1736 #else
1737 static inline void s3c24xx_serial_register_console(void) { }
1738 static inline void s3c24xx_serial_unregister_console(void) { }
1739 #define S3C24XX_SERIAL_CONSOLE NULL
1740 #endif
1741
1742 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1743 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1744 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1745                          unsigned char c);
1746 #endif
1747
1748 static const struct uart_ops s3c24xx_serial_ops = {
1749         .pm             = s3c24xx_serial_pm,
1750         .tx_empty       = s3c24xx_serial_tx_empty,
1751         .get_mctrl      = s3c24xx_serial_get_mctrl,
1752         .set_mctrl      = s3c24xx_serial_set_mctrl,
1753         .stop_tx        = s3c24xx_serial_stop_tx,
1754         .start_tx       = s3c24xx_serial_start_tx,
1755         .stop_rx        = s3c24xx_serial_stop_rx,
1756         .break_ctl      = s3c24xx_serial_break_ctl,
1757         .startup        = s3c24xx_serial_startup,
1758         .shutdown       = s3c24xx_serial_shutdown,
1759         .set_termios    = s3c24xx_serial_set_termios,
1760         .type           = s3c24xx_serial_type,
1761         .config_port    = s3c24xx_serial_config_port,
1762         .verify_port    = s3c24xx_serial_verify_port,
1763 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1764         .poll_get_char = s3c24xx_serial_get_poll_char,
1765         .poll_put_char = s3c24xx_serial_put_poll_char,
1766 #endif
1767 };
1768
1769 static const struct uart_ops s3c64xx_serial_ops = {
1770         .pm             = s3c24xx_serial_pm,
1771         .tx_empty       = s3c24xx_serial_tx_empty,
1772         .get_mctrl      = s3c24xx_serial_get_mctrl,
1773         .set_mctrl      = s3c24xx_serial_set_mctrl,
1774         .stop_tx        = s3c24xx_serial_stop_tx,
1775         .start_tx       = s3c24xx_serial_start_tx,
1776         .stop_rx        = s3c24xx_serial_stop_rx,
1777         .break_ctl      = s3c24xx_serial_break_ctl,
1778         .startup        = s3c64xx_serial_startup,
1779         .shutdown       = s3c64xx_serial_shutdown,
1780         .set_termios    = s3c24xx_serial_set_termios,
1781         .type           = s3c24xx_serial_type,
1782         .config_port    = s3c24xx_serial_config_port,
1783         .verify_port    = s3c24xx_serial_verify_port,
1784 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1785         .poll_get_char = s3c24xx_serial_get_poll_char,
1786         .poll_put_char = s3c24xx_serial_put_poll_char,
1787 #endif
1788 };
1789
1790 static const struct uart_ops apple_s5l_serial_ops = {
1791         .pm             = s3c24xx_serial_pm,
1792         .tx_empty       = s3c24xx_serial_tx_empty,
1793         .get_mctrl      = s3c24xx_serial_get_mctrl,
1794         .set_mctrl      = s3c24xx_serial_set_mctrl,
1795         .stop_tx        = s3c24xx_serial_stop_tx,
1796         .start_tx       = s3c24xx_serial_start_tx,
1797         .stop_rx        = s3c24xx_serial_stop_rx,
1798         .break_ctl      = s3c24xx_serial_break_ctl,
1799         .startup        = apple_s5l_serial_startup,
1800         .shutdown       = apple_s5l_serial_shutdown,
1801         .set_termios    = s3c24xx_serial_set_termios,
1802         .type           = s3c24xx_serial_type,
1803         .config_port    = s3c24xx_serial_config_port,
1804         .verify_port    = s3c24xx_serial_verify_port,
1805 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1806         .poll_get_char = s3c24xx_serial_get_poll_char,
1807         .poll_put_char = s3c24xx_serial_put_poll_char,
1808 #endif
1809 };
1810
1811 static struct uart_driver s3c24xx_uart_drv = {
1812         .owner          = THIS_MODULE,
1813         .driver_name    = "s3c2410_serial",
1814         .nr             = UART_NR,
1815         .cons           = S3C24XX_SERIAL_CONSOLE,
1816         .dev_name       = S3C24XX_SERIAL_NAME,
1817         .major          = S3C24XX_SERIAL_MAJOR,
1818         .minor          = S3C24XX_SERIAL_MINOR,
1819 };
1820
1821 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1822
1823 static void s3c24xx_serial_init_port_default(int index) {
1824         struct uart_port *port = &s3c24xx_serial_ports[index].port;
1825
1826         spin_lock_init(&port->lock);
1827
1828         port->iotype = UPIO_MEM;
1829         port->uartclk = 0;
1830         port->fifosize = 16;
1831         port->ops = &s3c24xx_serial_ops;
1832         port->flags = UPF_BOOT_AUTOCONF;
1833         port->line = index;
1834 }
1835
1836 /* s3c24xx_serial_resetport
1837  *
1838  * reset the fifos and other the settings.
1839  */
1840
1841 static void s3c24xx_serial_resetport(struct uart_port *port,
1842                                      const struct s3c2410_uartcfg *cfg)
1843 {
1844         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1845         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1846
1847         ucon &= (info->clksel_mask | info->ucon_mask);
1848         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1849
1850         /* reset both fifos */
1851         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1852         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1853
1854         /* some delay is required after fifo reset */
1855         udelay(1);
1856 }
1857
1858 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1859
1860 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1861                                              unsigned long val, void *data)
1862 {
1863         struct s3c24xx_uart_port *port;
1864         struct uart_port *uport;
1865
1866         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1867         uport = &port->port;
1868
1869         /* check to see if port is enabled */
1870
1871         if (port->pm_level != 0)
1872                 return 0;
1873
1874         /* try and work out if the baudrate is changing, we can detect
1875          * a change in rate, but we do not have support for detecting
1876          * a disturbance in the clock-rate over the change.
1877          */
1878
1879         if (IS_ERR(port->baudclk))
1880                 goto exit;
1881
1882         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1883                 goto exit;
1884
1885         if (val == CPUFREQ_PRECHANGE) {
1886                 /* we should really shut the port down whilst the
1887                  * frequency change is in progress.
1888                  */
1889
1890         } else if (val == CPUFREQ_POSTCHANGE) {
1891                 struct ktermios *termios;
1892                 struct tty_struct *tty;
1893
1894                 if (uport->state == NULL)
1895                         goto exit;
1896
1897                 tty = uport->state->port.tty;
1898
1899                 if (tty == NULL)
1900                         goto exit;
1901
1902                 termios = &tty->termios;
1903
1904                 if (termios == NULL) {
1905                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1906                         goto exit;
1907                 }
1908
1909                 s3c24xx_serial_set_termios(uport, termios, NULL);
1910         }
1911
1912 exit:
1913         return 0;
1914 }
1915
1916 static inline int
1917 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1918 {
1919         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1920
1921         return cpufreq_register_notifier(&port->freq_transition,
1922                                          CPUFREQ_TRANSITION_NOTIFIER);
1923 }
1924
1925 static inline void
1926 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1927 {
1928         cpufreq_unregister_notifier(&port->freq_transition,
1929                                     CPUFREQ_TRANSITION_NOTIFIER);
1930 }
1931
1932 #else
1933 static inline int
1934 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1935 {
1936         return 0;
1937 }
1938
1939 static inline void
1940 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1941 {
1942 }
1943 #endif
1944
1945 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1946 {
1947         struct device *dev = ourport->port.dev;
1948         const struct s3c24xx_uart_info *info = ourport->info;
1949         char clk_name[MAX_CLK_NAME_LENGTH];
1950         unsigned int clk_sel;
1951         struct clk *clk;
1952         int clk_num;
1953         int ret;
1954
1955         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1956         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1957                 if (!(clk_sel & (1 << clk_num)))
1958                         continue;
1959
1960                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1961                 clk = clk_get(dev, clk_name);
1962                 if (IS_ERR(clk))
1963                         continue;
1964
1965                 ret = clk_prepare_enable(clk);
1966                 if (ret) {
1967                         clk_put(clk);
1968                         continue;
1969                 }
1970
1971                 ourport->baudclk = clk;
1972                 ourport->baudclk_rate = clk_get_rate(clk);
1973                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1974
1975                 return 0;
1976         }
1977
1978         return -EINVAL;
1979 }
1980
1981 /* s3c24xx_serial_init_port
1982  *
1983  * initialise a single serial port from the platform device given
1984  */
1985
1986 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1987                                     struct platform_device *platdev)
1988 {
1989         struct uart_port *port = &ourport->port;
1990         const struct s3c2410_uartcfg *cfg = ourport->cfg;
1991         struct resource *res;
1992         int ret;
1993
1994         if (platdev == NULL)
1995                 return -ENODEV;
1996
1997         if (port->mapbase != 0)
1998                 return -EINVAL;
1999
2000         /* setup info for port */
2001         port->dev       = &platdev->dev;
2002
2003         port->uartclk = 1;
2004
2005         if (cfg->uart_flags & UPF_CONS_FLOW) {
2006                 dev_dbg(port->dev, "enabling flow control\n");
2007                 port->flags |= UPF_CONS_FLOW;
2008         }
2009
2010         /* sort our the physical and virtual addresses for each UART */
2011
2012         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2013         if (res == NULL) {
2014                 dev_err(port->dev, "failed to find memory resource for uart\n");
2015                 return -EINVAL;
2016         }
2017
2018         dev_dbg(port->dev, "resource %pR)\n", res);
2019
2020         port->membase = devm_ioremap_resource(port->dev, res);
2021         if (IS_ERR(port->membase)) {
2022                 dev_err(port->dev, "failed to remap controller address\n");
2023                 return -EBUSY;
2024         }
2025
2026         port->mapbase = res->start;
2027         ret = platform_get_irq(platdev, 0);
2028         if (ret < 0) {
2029                 port->irq = 0;
2030         } else {
2031                 port->irq = ret;
2032                 ourport->rx_irq = ret;
2033                 ourport->tx_irq = ret + 1;
2034         }
2035
2036         switch (ourport->info->type) {
2037         case TYPE_S3C24XX:
2038                 ret = platform_get_irq(platdev, 1);
2039                 if (ret > 0)
2040                         ourport->tx_irq = ret;
2041                 break;
2042         default:
2043                 break;
2044         }
2045
2046         /*
2047          * DMA is currently supported only on DT platforms, if DMA properties
2048          * are specified.
2049          */
2050         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2051                                                      "dmas", NULL)) {
2052                 ourport->dma = devm_kzalloc(port->dev,
2053                                             sizeof(*ourport->dma),
2054                                             GFP_KERNEL);
2055                 if (!ourport->dma) {
2056                         ret = -ENOMEM;
2057                         goto err;
2058                 }
2059         }
2060
2061         ourport->clk    = clk_get(&platdev->dev, "uart");
2062         if (IS_ERR(ourport->clk)) {
2063                 pr_err("%s: Controller clock not found\n",
2064                                 dev_name(&platdev->dev));
2065                 ret = PTR_ERR(ourport->clk);
2066                 goto err;
2067         }
2068
2069         ret = clk_prepare_enable(ourport->clk);
2070         if (ret) {
2071                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2072                 clk_put(ourport->clk);
2073                 goto err;
2074         }
2075
2076         ret = s3c24xx_serial_enable_baudclk(ourport);
2077         if (ret)
2078                 pr_warn("uart: failed to enable baudclk\n");
2079
2080         /* Keep all interrupts masked and cleared */
2081         switch (ourport->info->type) {
2082         case TYPE_S3C6400:
2083                 wr_regl(port, S3C64XX_UINTM, 0xf);
2084                 wr_regl(port, S3C64XX_UINTP, 0xf);
2085                 wr_regl(port, S3C64XX_UINTSP, 0xf);
2086                 break;
2087         case TYPE_APPLE_S5L: {
2088                 unsigned int ucon;
2089
2090                 ucon = rd_regl(port, S3C2410_UCON);
2091                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2092                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2093                         APPLE_S5L_UCON_RXTO_ENA_MSK);
2094                 wr_regl(port, S3C2410_UCON, ucon);
2095
2096                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2097                 break;
2098         }
2099         default:
2100                 break;
2101         }
2102
2103         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2104                 &port->mapbase, port->membase, port->irq,
2105                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2106
2107         /* reset the fifos (and setup the uart) */
2108         s3c24xx_serial_resetport(port, cfg);
2109
2110         return 0;
2111
2112 err:
2113         port->mapbase = 0;
2114         return ret;
2115 }
2116
2117 /* Device driver serial port probe */
2118
2119 static int probe_index;
2120
2121 static inline const struct s3c24xx_serial_drv_data *
2122 s3c24xx_get_driver_data(struct platform_device *pdev)
2123 {
2124         if (dev_of_node(&pdev->dev))
2125                 return of_device_get_match_data(&pdev->dev);
2126
2127         return (struct s3c24xx_serial_drv_data *)
2128                         platform_get_device_id(pdev)->driver_data;
2129 }
2130
2131 static int s3c24xx_serial_probe(struct platform_device *pdev)
2132 {
2133         struct device_node *np = pdev->dev.of_node;
2134         struct s3c24xx_uart_port *ourport;
2135         int index = probe_index;
2136         int ret, prop = 0;
2137
2138         if (np) {
2139                 ret = of_alias_get_id(np, "serial");
2140                 if (ret >= 0)
2141                         index = ret;
2142         }
2143
2144         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2145                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2146                 return -EINVAL;
2147         }
2148         ourport = &s3c24xx_serial_ports[index];
2149
2150         s3c24xx_serial_init_port_default(index);
2151
2152         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2153         if (!ourport->drv_data) {
2154                 dev_err(&pdev->dev, "could not find driver data\n");
2155                 return -ENODEV;
2156         }
2157
2158         ourport->baudclk = ERR_PTR(-EINVAL);
2159         ourport->info = &ourport->drv_data->info;
2160         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2161                         dev_get_platdata(&pdev->dev) :
2162                         &ourport->drv_data->def_cfg;
2163
2164         switch (ourport->info->type) {
2165         case TYPE_S3C24XX:
2166                 ourport->port.ops = &s3c24xx_serial_ops;
2167                 break;
2168         case TYPE_S3C6400:
2169                 ourport->port.ops = &s3c64xx_serial_ops;
2170                 break;
2171         case TYPE_APPLE_S5L:
2172                 ourport->port.ops = &apple_s5l_serial_ops;
2173                 break;
2174         }
2175
2176         if (np) {
2177                 of_property_read_u32(np,
2178                         "samsung,uart-fifosize", &ourport->port.fifosize);
2179
2180                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2181                         switch (prop) {
2182                         case 1:
2183                                 ourport->port.iotype = UPIO_MEM;
2184                                 break;
2185                         case 4:
2186                                 ourport->port.iotype = UPIO_MEM32;
2187                                 break;
2188                         default:
2189                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2190                                                 prop);
2191                                 return -EINVAL;
2192                         }
2193                 }
2194         }
2195
2196         if (ourport->drv_data->fifosize[index])
2197                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2198         else if (ourport->info->fifosize)
2199                 ourport->port.fifosize = ourport->info->fifosize;
2200         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2201
2202         /*
2203          * DMA transfers must be aligned at least to cache line size,
2204          * so find minimal transfer size suitable for DMA mode
2205          */
2206         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2207                                     dma_get_cache_alignment());
2208
2209         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2210
2211         ret = s3c24xx_serial_init_port(ourport, pdev);
2212         if (ret < 0)
2213                 return ret;
2214
2215         if (!s3c24xx_uart_drv.state) {
2216                 ret = uart_register_driver(&s3c24xx_uart_drv);
2217                 if (ret < 0) {
2218                         pr_err("Failed to register Samsung UART driver\n");
2219                         return ret;
2220                 }
2221         }
2222
2223         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2224         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2225         platform_set_drvdata(pdev, &ourport->port);
2226
2227         /*
2228          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2229          * so that a potential re-enablement through the pm-callback overlaps
2230          * and keeps the clock enabled in this case.
2231          */
2232         clk_disable_unprepare(ourport->clk);
2233         if (!IS_ERR(ourport->baudclk))
2234                 clk_disable_unprepare(ourport->baudclk);
2235
2236         ret = s3c24xx_serial_cpufreq_register(ourport);
2237         if (ret < 0)
2238                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2239
2240         probe_index++;
2241
2242         return 0;
2243 }
2244
2245 static int s3c24xx_serial_remove(struct platform_device *dev)
2246 {
2247         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2248
2249         if (port) {
2250                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2251                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2252         }
2253
2254         uart_unregister_driver(&s3c24xx_uart_drv);
2255
2256         return 0;
2257 }
2258
2259 /* UART power management code */
2260 #ifdef CONFIG_PM_SLEEP
2261 static int s3c24xx_serial_suspend(struct device *dev)
2262 {
2263         struct uart_port *port = s3c24xx_dev_to_port(dev);
2264
2265         if (port)
2266                 uart_suspend_port(&s3c24xx_uart_drv, port);
2267
2268         return 0;
2269 }
2270
2271 static int s3c24xx_serial_resume(struct device *dev)
2272 {
2273         struct uart_port *port = s3c24xx_dev_to_port(dev);
2274         struct s3c24xx_uart_port *ourport = to_ourport(port);
2275
2276         if (port) {
2277                 clk_prepare_enable(ourport->clk);
2278                 if (!IS_ERR(ourport->baudclk))
2279                         clk_prepare_enable(ourport->baudclk);
2280                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2281                 if (!IS_ERR(ourport->baudclk))
2282                         clk_disable_unprepare(ourport->baudclk);
2283                 clk_disable_unprepare(ourport->clk);
2284
2285                 uart_resume_port(&s3c24xx_uart_drv, port);
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int s3c24xx_serial_resume_noirq(struct device *dev)
2292 {
2293         struct uart_port *port = s3c24xx_dev_to_port(dev);
2294         struct s3c24xx_uart_port *ourport = to_ourport(port);
2295
2296         if (port) {
2297                 /* restore IRQ mask */
2298                 switch (ourport->info->type) {
2299                 case TYPE_S3C6400: {
2300                         unsigned int uintm = 0xf;
2301
2302                         if (ourport->tx_enabled)
2303                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2304                         if (ourport->rx_enabled)
2305                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2306                         clk_prepare_enable(ourport->clk);
2307                         if (!IS_ERR(ourport->baudclk))
2308                                 clk_prepare_enable(ourport->baudclk);
2309                         wr_regl(port, S3C64XX_UINTM, uintm);
2310                         if (!IS_ERR(ourport->baudclk))
2311                                 clk_disable_unprepare(ourport->baudclk);
2312                         clk_disable_unprepare(ourport->clk);
2313                         break;
2314                 }
2315                 case TYPE_APPLE_S5L: {
2316                         unsigned int ucon;
2317                         int ret;
2318
2319                         ret = clk_prepare_enable(ourport->clk);
2320                         if (ret) {
2321                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2322                                 return ret;
2323                         }
2324                         if (!IS_ERR(ourport->baudclk)) {
2325                                 ret = clk_prepare_enable(ourport->baudclk);
2326                                 if (ret) {
2327                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2328                                         clk_disable_unprepare(ourport->clk);
2329                                         return ret;
2330                                 }
2331                         }
2332
2333                         ucon = rd_regl(port, S3C2410_UCON);
2334
2335                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2336                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2337                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2338
2339                         if (ourport->tx_enabled)
2340                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2341                         if (ourport->rx_enabled)
2342                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2343                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2344
2345                         wr_regl(port, S3C2410_UCON, ucon);
2346
2347                         if (!IS_ERR(ourport->baudclk))
2348                                 clk_disable_unprepare(ourport->baudclk);
2349                         clk_disable_unprepare(ourport->clk);
2350                         break;
2351                 }
2352                 default:
2353                         break;
2354                 }
2355         }
2356
2357         return 0;
2358 }
2359
2360 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2361         .suspend = s3c24xx_serial_suspend,
2362         .resume = s3c24xx_serial_resume,
2363         .resume_noirq = s3c24xx_serial_resume_noirq,
2364 };
2365 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2366
2367 #else /* !CONFIG_PM_SLEEP */
2368
2369 #define SERIAL_SAMSUNG_PM_OPS   NULL
2370 #endif /* CONFIG_PM_SLEEP */
2371
2372 /* Console code */
2373
2374 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2375
2376 static struct uart_port *cons_uart;
2377
2378 static int
2379 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2380 {
2381         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2382         unsigned long ufstat, utrstat;
2383
2384         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2385                 /* fifo mode - check amount of data in fifo registers... */
2386
2387                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2388                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2389         }
2390
2391         /* in non-fifo mode, we go and use the tx buffer empty */
2392
2393         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2394         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2395 }
2396
2397 static bool
2398 s3c24xx_port_configured(unsigned int ucon)
2399 {
2400         /* consider the serial port configured if the tx/rx mode set */
2401         return (ucon & 0xf) != 0;
2402 }
2403
2404 #ifdef CONFIG_CONSOLE_POLL
2405 /*
2406  * Console polling routines for writing and reading from the uart while
2407  * in an interrupt or debug context.
2408  */
2409
2410 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2411 {
2412         const struct s3c24xx_uart_port *ourport = to_ourport(port);
2413         unsigned int ufstat;
2414
2415         ufstat = rd_regl(port, S3C2410_UFSTAT);
2416         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2417                 return NO_POLL_CHAR;
2418
2419         return rd_reg(port, S3C2410_URXH);
2420 }
2421
2422 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2423                 unsigned char c)
2424 {
2425         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2426         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2427
2428         /* not possible to xmit on unconfigured port */
2429         if (!s3c24xx_port_configured(ucon))
2430                 return;
2431
2432         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2433                 cpu_relax();
2434         wr_reg(port, S3C2410_UTXH, c);
2435 }
2436
2437 #endif /* CONFIG_CONSOLE_POLL */
2438
2439 static void
2440 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2441 {
2442         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2443
2444         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2445                 cpu_relax();
2446         wr_reg(port, S3C2410_UTXH, ch);
2447 }
2448
2449 static void
2450 s3c24xx_serial_console_write(struct console *co, const char *s,
2451                              unsigned int count)
2452 {
2453         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2454         unsigned long flags;
2455         bool locked = true;
2456
2457         /* not possible to xmit on unconfigured port */
2458         if (!s3c24xx_port_configured(ucon))
2459                 return;
2460
2461         if (cons_uart->sysrq)
2462                 locked = false;
2463         else if (oops_in_progress)
2464                 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2465         else
2466                 spin_lock_irqsave(&cons_uart->lock, flags);
2467
2468         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2469
2470         if (locked)
2471                 spin_unlock_irqrestore(&cons_uart->lock, flags);
2472 }
2473
2474 /* Shouldn't be __init, as it can be instantiated from other module */
2475 static void
2476 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2477                            int *parity, int *bits)
2478 {
2479         struct clk *clk;
2480         unsigned int ulcon;
2481         unsigned int ucon;
2482         unsigned int ubrdiv;
2483         unsigned long rate;
2484         unsigned int clk_sel;
2485         char clk_name[MAX_CLK_NAME_LENGTH];
2486
2487         ulcon  = rd_regl(port, S3C2410_ULCON);
2488         ucon   = rd_regl(port, S3C2410_UCON);
2489         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2490
2491         if (s3c24xx_port_configured(ucon)) {
2492                 switch (ulcon & S3C2410_LCON_CSMASK) {
2493                 case S3C2410_LCON_CS5:
2494                         *bits = 5;
2495                         break;
2496                 case S3C2410_LCON_CS6:
2497                         *bits = 6;
2498                         break;
2499                 case S3C2410_LCON_CS7:
2500                         *bits = 7;
2501                         break;
2502                 case S3C2410_LCON_CS8:
2503                 default:
2504                         *bits = 8;
2505                         break;
2506                 }
2507
2508                 switch (ulcon & S3C2410_LCON_PMASK) {
2509                 case S3C2410_LCON_PEVEN:
2510                         *parity = 'e';
2511                         break;
2512
2513                 case S3C2410_LCON_PODD:
2514                         *parity = 'o';
2515                         break;
2516
2517                 case S3C2410_LCON_PNONE:
2518                 default:
2519                         *parity = 'n';
2520                 }
2521
2522                 /* now calculate the baud rate */
2523
2524                 clk_sel = s3c24xx_serial_getsource(port);
2525                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2526
2527                 clk = clk_get(port->dev, clk_name);
2528                 if (!IS_ERR(clk))
2529                         rate = clk_get_rate(clk);
2530                 else
2531                         rate = 1;
2532
2533                 *baud = rate / (16 * (ubrdiv + 1));
2534                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2535         }
2536 }
2537
2538 /* Shouldn't be __init, as it can be instantiated from other module */
2539 static int
2540 s3c24xx_serial_console_setup(struct console *co, char *options)
2541 {
2542         struct uart_port *port;
2543         int baud = 9600;
2544         int bits = 8;
2545         int parity = 'n';
2546         int flow = 'n';
2547
2548         /* is this a valid port */
2549
2550         if (co->index == -1 || co->index >= UART_NR)
2551                 co->index = 0;
2552
2553         port = &s3c24xx_serial_ports[co->index].port;
2554
2555         /* is the port configured? */
2556
2557         if (port->mapbase == 0x0)
2558                 return -ENODEV;
2559
2560         cons_uart = port;
2561
2562         /*
2563          * Check whether an invalid uart number has been specified, and
2564          * if so, search for the first available port that does have
2565          * console support.
2566          */
2567         if (options)
2568                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2569         else
2570                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2571
2572         dev_dbg(port->dev, "baud %d\n", baud);
2573
2574         return uart_set_options(port, co, baud, parity, bits, flow);
2575 }
2576
2577 static struct console s3c24xx_serial_console = {
2578         .name           = S3C24XX_SERIAL_NAME,
2579         .device         = uart_console_device,
2580         .flags          = CON_PRINTBUFFER,
2581         .index          = -1,
2582         .write          = s3c24xx_serial_console_write,
2583         .setup          = s3c24xx_serial_console_setup,
2584         .data           = &s3c24xx_uart_drv,
2585 };
2586 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2587
2588 #ifdef CONFIG_CPU_S3C2410
2589 static const struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2590         .info = {
2591                 .name           = "Samsung S3C2410 UART",
2592                 .type           = TYPE_S3C24XX,
2593                 .port_type      = PORT_S3C2410,
2594                 .fifosize       = 16,
2595                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2596                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2597                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2598                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2599                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2600                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2601                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2602                 .num_clks       = 2,
2603                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2604                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2605         },
2606         .def_cfg = {
2607                 .ucon           = S3C2410_UCON_DEFAULT,
2608                 .ufcon          = S3C2410_UFCON_DEFAULT,
2609         },
2610 };
2611 #define S3C2410_SERIAL_DRV_DATA (&s3c2410_serial_drv_data)
2612 #else
2613 #define S3C2410_SERIAL_DRV_DATA NULL
2614 #endif
2615
2616 #ifdef CONFIG_CPU_S3C2412
2617 static const struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2618         .info = {
2619                 .name           = "Samsung S3C2412 UART",
2620                 .type           = TYPE_S3C24XX,
2621                 .port_type      = PORT_S3C2412,
2622                 .fifosize       = 64,
2623                 .has_divslot    = 1,
2624                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2625                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2626                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2627                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2628                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2629                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2630                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2631                 .num_clks       = 4,
2632                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2633                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2634         },
2635         .def_cfg = {
2636                 .ucon           = S3C2410_UCON_DEFAULT,
2637                 .ufcon          = S3C2410_UFCON_DEFAULT,
2638         },
2639 };
2640 #define S3C2412_SERIAL_DRV_DATA (&s3c2412_serial_drv_data)
2641 #else
2642 #define S3C2412_SERIAL_DRV_DATA NULL
2643 #endif
2644
2645 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2646         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2647 static const struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2648         .info = {
2649                 .name           = "Samsung S3C2440 UART",
2650                 .type           = TYPE_S3C24XX,
2651                 .port_type      = PORT_S3C2440,
2652                 .fifosize       = 64,
2653                 .has_divslot    = 1,
2654                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2655                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2656                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2657                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2658                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2659                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2660                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2661                 .num_clks       = 4,
2662                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2663                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2664                 .ucon_mask      = S3C2440_UCON0_DIVMASK,
2665         },
2666         .def_cfg = {
2667                 .ucon           = S3C2410_UCON_DEFAULT,
2668                 .ufcon          = S3C2410_UFCON_DEFAULT,
2669         },
2670 };
2671 #define S3C2440_SERIAL_DRV_DATA (&s3c2440_serial_drv_data)
2672 #else
2673 #define S3C2440_SERIAL_DRV_DATA NULL
2674 #endif
2675
2676 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2677 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2678         .info = {
2679                 .name           = "Samsung S3C6400 UART",
2680                 .type           = TYPE_S3C6400,
2681                 .port_type      = PORT_S3C6400,
2682                 .fifosize       = 64,
2683                 .has_divslot    = 1,
2684                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2685                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2686                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2687                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2688                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2689                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2690                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2691                 .num_clks       = 4,
2692                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2693                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2694         },
2695         .def_cfg = {
2696                 .ucon           = S3C2410_UCON_DEFAULT,
2697                 .ufcon          = S3C2410_UFCON_DEFAULT,
2698         },
2699 };
2700 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2701 #else
2702 #define S3C6400_SERIAL_DRV_DATA NULL
2703 #endif
2704
2705 #ifdef CONFIG_CPU_S5PV210
2706 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2707         .info = {
2708                 .name           = "Samsung S5PV210 UART",
2709                 .type           = TYPE_S3C6400,
2710                 .port_type      = PORT_S3C6400,
2711                 .has_divslot    = 1,
2712                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2713                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2714                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2715                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2716                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2717                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2718                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2719                 .num_clks       = 2,
2720                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2721                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2722         },
2723         .def_cfg = {
2724                 .ucon           = S5PV210_UCON_DEFAULT,
2725                 .ufcon          = S5PV210_UFCON_DEFAULT,
2726         },
2727         .fifosize = { 256, 64, 16, 16 },
2728 };
2729 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2730 #else
2731 #define S5PV210_SERIAL_DRV_DATA NULL
2732 #endif
2733
2734 #if defined(CONFIG_ARCH_EXYNOS)
2735 #define EXYNOS_COMMON_SERIAL_DRV_DATA()                         \
2736         .info = {                                               \
2737                 .name           = "Samsung Exynos UART",        \
2738                 .type           = TYPE_S3C6400,                 \
2739                 .port_type      = PORT_S3C6400,                 \
2740                 .has_divslot    = 1,                            \
2741                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2742                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2743                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2744                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2745                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2746                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2747                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2748                 .num_clks       = 1,                            \
2749                 .clksel_mask    = 0,                            \
2750                 .clksel_shift   = 0,                            \
2751         },                                                      \
2752         .def_cfg = {                                            \
2753                 .ucon           = S5PV210_UCON_DEFAULT,         \
2754                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2755                 .has_fracval    = 1,                            \
2756         }                                                       \
2757
2758 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2759         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2760         .fifosize = { 256, 64, 16, 16 },
2761 };
2762
2763 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2764         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2765         .fifosize = { 64, 256, 16, 256 },
2766 };
2767
2768 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2769         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2770         .fifosize = { 256, 64, 64, 64 },
2771 };
2772
2773 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2774 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2775 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2776
2777 #else
2778 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2779 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2780 #define EXYNOS850_SERIAL_DRV_DATA NULL
2781 #endif
2782
2783 #ifdef CONFIG_ARCH_APPLE
2784 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2785         .info = {
2786                 .name           = "Apple S5L UART",
2787                 .type           = TYPE_APPLE_S5L,
2788                 .port_type      = PORT_8250,
2789                 .fifosize       = 16,
2790                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2791                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2792                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2793                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2794                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2795                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2796                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2797                 .num_clks       = 1,
2798                 .clksel_mask    = 0,
2799                 .clksel_shift   = 0,
2800                 .ucon_mask      = APPLE_S5L_UCON_MASK,
2801         },
2802         .def_cfg = {
2803                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2804                 .ufcon          = S3C2410_UFCON_DEFAULT,
2805         },
2806 };
2807 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2808 #else
2809 #define S5L_SERIAL_DRV_DATA NULL
2810 #endif
2811
2812 #if defined(CONFIG_ARCH_ARTPEC)
2813 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2814         .info = {
2815                 .name           = "Axis ARTPEC-8 UART",
2816                 .type           = TYPE_S3C6400,
2817                 .port_type      = PORT_S3C6400,
2818                 .fifosize       = 64,
2819                 .has_divslot    = 1,
2820                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2821                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2822                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2823                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2824                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2825                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2826                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2827                 .num_clks       = 1,
2828                 .clksel_mask    = 0,
2829                 .clksel_shift   = 0,
2830         },
2831         .def_cfg = {
2832                 .ucon           = S5PV210_UCON_DEFAULT,
2833                 .ufcon          = S5PV210_UFCON_DEFAULT,
2834                 .has_fracval    = 1,
2835         }
2836 };
2837 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2838 #else
2839 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2840 #endif
2841
2842 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2843         {
2844                 .name           = "s3c2410-uart",
2845                 .driver_data    = (kernel_ulong_t)S3C2410_SERIAL_DRV_DATA,
2846         }, {
2847                 .name           = "s3c2412-uart",
2848                 .driver_data    = (kernel_ulong_t)S3C2412_SERIAL_DRV_DATA,
2849         }, {
2850                 .name           = "s3c2440-uart",
2851                 .driver_data    = (kernel_ulong_t)S3C2440_SERIAL_DRV_DATA,
2852         }, {
2853                 .name           = "s3c6400-uart",
2854                 .driver_data    = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2855         }, {
2856                 .name           = "s5pv210-uart",
2857                 .driver_data    = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2858         }, {
2859                 .name           = "exynos4210-uart",
2860                 .driver_data    = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2861         }, {
2862                 .name           = "exynos5433-uart",
2863                 .driver_data    = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2864         }, {
2865                 .name           = "s5l-uart",
2866                 .driver_data    = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2867         }, {
2868                 .name           = "exynos850-uart",
2869                 .driver_data    = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2870         }, {
2871                 .name           = "artpec8-uart",
2872                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2873         },
2874         { },
2875 };
2876 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2877
2878 #ifdef CONFIG_OF
2879 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2880         { .compatible = "samsung,s3c2410-uart",
2881                 .data = S3C2410_SERIAL_DRV_DATA },
2882         { .compatible = "samsung,s3c2412-uart",
2883                 .data = S3C2412_SERIAL_DRV_DATA },
2884         { .compatible = "samsung,s3c2440-uart",
2885                 .data = S3C2440_SERIAL_DRV_DATA },
2886         { .compatible = "samsung,s3c6400-uart",
2887                 .data = S3C6400_SERIAL_DRV_DATA },
2888         { .compatible = "samsung,s5pv210-uart",
2889                 .data = S5PV210_SERIAL_DRV_DATA },
2890         { .compatible = "samsung,exynos4210-uart",
2891                 .data = EXYNOS4210_SERIAL_DRV_DATA },
2892         { .compatible = "samsung,exynos5433-uart",
2893                 .data = EXYNOS5433_SERIAL_DRV_DATA },
2894         { .compatible = "apple,s5l-uart",
2895                 .data = S5L_SERIAL_DRV_DATA },
2896         { .compatible = "samsung,exynos850-uart",
2897                 .data = EXYNOS850_SERIAL_DRV_DATA },
2898         { .compatible = "axis,artpec8-uart",
2899                 .data = ARTPEC8_SERIAL_DRV_DATA },
2900         {},
2901 };
2902 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2903 #endif
2904
2905 static struct platform_driver samsung_serial_driver = {
2906         .probe          = s3c24xx_serial_probe,
2907         .remove         = s3c24xx_serial_remove,
2908         .id_table       = s3c24xx_serial_driver_ids,
2909         .driver         = {
2910                 .name   = "samsung-uart",
2911                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2912                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2913         },
2914 };
2915
2916 static int __init samsung_serial_init(void)
2917 {
2918         int ret;
2919
2920         s3c24xx_serial_register_console();
2921
2922         ret = platform_driver_register(&samsung_serial_driver);
2923         if (ret) {
2924                 s3c24xx_serial_unregister_console();
2925                 return ret;
2926         }
2927
2928         return 0;
2929 }
2930
2931 static void __exit samsung_serial_exit(void)
2932 {
2933         platform_driver_unregister(&samsung_serial_driver);
2934         s3c24xx_serial_unregister_console();
2935 }
2936
2937 module_init(samsung_serial_init);
2938 module_exit(samsung_serial_exit);
2939
2940 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2941 /*
2942  * Early console.
2943  */
2944
2945 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2946 {
2947         switch (port->iotype) {
2948         case UPIO_MEM:
2949                 writeb(val, portaddr(port, reg));
2950                 break;
2951         case UPIO_MEM32:
2952                 writel(val, portaddr(port, reg));
2953                 break;
2954         }
2955 }
2956
2957 struct samsung_early_console_data {
2958         u32 txfull_mask;
2959         u32 rxfifo_mask;
2960 };
2961
2962 static void samsung_early_busyuart(const struct uart_port *port)
2963 {
2964         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2965                 ;
2966 }
2967
2968 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2969 {
2970         const struct samsung_early_console_data *data = port->private_data;
2971
2972         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2973                 ;
2974 }
2975
2976 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2977 {
2978         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2979                 samsung_early_busyuart_fifo(port);
2980         else
2981                 samsung_early_busyuart(port);
2982
2983         wr_reg_barrier(port, S3C2410_UTXH, c);
2984 }
2985
2986 static void samsung_early_write(struct console *con, const char *s,
2987                                 unsigned int n)
2988 {
2989         struct earlycon_device *dev = con->data;
2990
2991         uart_console_write(&dev->port, s, n, samsung_early_putc);
2992 }
2993
2994 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2995 {
2996         struct earlycon_device *dev = con->data;
2997         const struct samsung_early_console_data *data = dev->port.private_data;
2998         int ch, ufstat, num_read = 0;
2999
3000         while (num_read < n) {
3001                 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
3002                 if (!(ufstat & data->rxfifo_mask))
3003                         break;
3004                 ch = rd_reg(&dev->port, S3C2410_URXH);
3005                 if (ch == NO_POLL_CHAR)
3006                         break;
3007
3008                 s[num_read++] = ch;
3009         }
3010
3011         return num_read;
3012 }
3013
3014 static int __init samsung_early_console_setup(struct earlycon_device *device,
3015                                               const char *opt)
3016 {
3017         if (!device->port.membase)
3018                 return -ENODEV;
3019
3020         device->con->write = samsung_early_write;
3021         device->con->read = samsung_early_read;
3022         return 0;
3023 }
3024
3025 /* S3C2410 */
3026 static struct samsung_early_console_data s3c2410_early_console_data = {
3027         .txfull_mask = S3C2410_UFSTAT_TXFULL,
3028         .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
3029 };
3030
3031 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
3032                                               const char *opt)
3033 {
3034         device->port.private_data = &s3c2410_early_console_data;
3035         return samsung_early_console_setup(device, opt);
3036 }
3037
3038 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
3039                         s3c2410_early_console_setup);
3040
3041 /* S3C2412, S3C2440, S3C64xx */
3042 static struct samsung_early_console_data s3c2440_early_console_data = {
3043         .txfull_mask = S3C2440_UFSTAT_TXFULL,
3044         .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
3045 };
3046
3047 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
3048                                               const char *opt)
3049 {
3050         device->port.private_data = &s3c2440_early_console_data;
3051         return samsung_early_console_setup(device, opt);
3052 }
3053
3054 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
3055                         s3c2440_early_console_setup);
3056 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
3057                         s3c2440_early_console_setup);
3058 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
3059                         s3c2440_early_console_setup);
3060
3061 /* S5PV210, Exynos */
3062 static struct samsung_early_console_data s5pv210_early_console_data = {
3063         .txfull_mask = S5PV210_UFSTAT_TXFULL,
3064         .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
3065 };
3066
3067 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
3068                                               const char *opt)
3069 {
3070         device->port.private_data = &s5pv210_early_console_data;
3071         return samsung_early_console_setup(device, opt);
3072 }
3073
3074 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
3075                         s5pv210_early_console_setup);
3076 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
3077                         s5pv210_early_console_setup);
3078 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
3079                         s5pv210_early_console_setup);
3080
3081 /* Apple S5L */
3082 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3083                                                 const char *opt)
3084 {
3085         /* Close enough to S3C2410 for earlycon... */
3086         device->port.private_data = &s3c2410_early_console_data;
3087
3088 #ifdef CONFIG_ARM64
3089         /* ... but we need to override the existing fixmap entry as nGnRnE */
3090         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3091                      __pgprot(PROT_DEVICE_nGnRnE));
3092 #endif
3093         return samsung_early_console_setup(device, opt);
3094 }
3095
3096 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3097 #endif
3098
3099 MODULE_ALIAS("platform:samsung-uart");
3100 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3101 MODULE_AUTHOR("Ben Dooks <[email protected]>");
3102 MODULE_LICENSE("GPL v2");