drivers/i2c/busses/i2c-cpm.c

   1 /*
   2  * Freescale CPM1/CPM2 I2C interface.
   3  * Copyright (c) 1999 Dan Malek ([email protected]).
   4  *
   5  * moved into proper i2c interface;
   6  * Brad Parker ([email protected])
   7  *
   8  * Parts from dbox2_i2c.c (cvs.tuxbox.org)
   9  * (C) 2000-2001 Felix Domke ([email protected]), Gillem ([email protected])
  10  *
  11  * (C) 2007 Montavista Software, Inc.
  12  * Vitaly Bordug <[email protected]>
  13  *
  14  * Converted to of_platform_device. Renamed to i2c-cpm.c.
  15  * (C) 2007,2008 Jochen Friedrich <[email protected]>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *  GNU General Public License for more details.
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/errno.h>
  34 #include <linux/stddef.h>
  35 #include <linux/i2c.h>
  36 #include <linux/io.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_device.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/of_platform.h>
  42 #include <sysdev/fsl_soc.h>
  43 #include <asm/cpm.h>
  44
  45 /* Try to define this if you have an older CPU (earlier than rev D4) */
  46 /* However, better use a GPIO based bitbang driver in this case :/   */
  47 #undef  I2C_CHIP_ERRATA
  48
  49 #define CPM_MAX_READ    513
  50 #define CPM_MAXBD       4
  51
  52 #define I2C_EB                  (0x10) /* Big endian mode */
  53 #define I2C_EB_CPM2             (0x30) /* Big endian mode, memory snoop */
  54
  55 #define DPRAM_BASE              ((u8 __iomem __force *)cpm_muram_addr(0))
  56
  57 /* I2C parameter RAM. */
  58 struct i2c_ram {
  59         ushort  rbase;          /* Rx Buffer descriptor base address */
  60         ushort  tbase;          /* Tx Buffer descriptor base address */
  61         u_char  rfcr;           /* Rx function code */
  62         u_char  tfcr;           /* Tx function code */
  63         ushort  mrblr;          /* Max receive buffer length */
  64         uint    rstate;         /* Internal */
  65         uint    rdp;            /* Internal */
  66         ushort  rbptr;          /* Rx Buffer descriptor pointer */
  67         ushort  rbc;            /* Internal */
  68         uint    rxtmp;          /* Internal */
  69         uint    tstate;         /* Internal */
  70         uint    tdp;            /* Internal */
  71         ushort  tbptr;          /* Tx Buffer descriptor pointer */
  72         ushort  tbc;            /* Internal */
  73         uint    txtmp;          /* Internal */
  74         char    res1[4];        /* Reserved */
  75         ushort  rpbase;         /* Relocation pointer */
  76         char    res2[2];        /* Reserved */
  77 };
  78
  79 #define I2COM_START     0x80
  80 #define I2COM_MASTER    0x01
  81 #define I2CER_TXE       0x10
  82 #define I2CER_BUSY      0x04
  83 #define I2CER_TXB       0x02
  84 #define I2CER_RXB       0x01
  85 #define I2MOD_EN        0x01
  86
  87 /* I2C Registers */
  88 struct i2c_reg {
  89         u8      i2mod;
  90         u8      res1[3];
  91         u8      i2add;
  92         u8      res2[3];
  93         u8      i2brg;
  94         u8      res3[3];
  95         u8      i2com;
  96         u8      res4[3];
  97         u8      i2cer;
  98         u8      res5[3];
  99         u8      i2cmr;
 100 };
 101
 102 struct cpm_i2c {
 103         char *base;
 104         struct platform_device *ofdev;
 105         struct i2c_adapter adap;
 106         uint dp_addr;
 107         int version; /* CPM1=1, CPM2=2 */
 108         int irq;
 109         int cp_command;
 110         int freq;
 111         struct i2c_reg __iomem *i2c_reg;
 112         struct i2c_ram __iomem *i2c_ram;
 113         u16 i2c_addr;
 114         wait_queue_head_t i2c_wait;
 115         cbd_t __iomem *tbase;
 116         cbd_t __iomem *rbase;
 117         u_char *txbuf[CPM_MAXBD];
 118         u_char *rxbuf[CPM_MAXBD];
 119         u32 txdma[CPM_MAXBD];
 120         u32 rxdma[CPM_MAXBD];
 121 };
 122
 123 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
 124 {
 125         struct cpm_i2c *cpm;
 126         struct i2c_reg __iomem *i2c_reg;
 127         struct i2c_adapter *adap = dev_id;
 128         int i;
 129
 130         cpm = i2c_get_adapdata(dev_id);
 131         i2c_reg = cpm->i2c_reg;
 132
 133         /* Clear interrupt. */
 134         i = in_8(&i2c_reg->i2cer);
 135         out_8(&i2c_reg->i2cer, i);
 136
 137         dev_dbg(&adap->dev, "Interrupt: %x\n", i);
 138
 139         wake_up(&cpm->i2c_wait);
 140
 141         return i ? IRQ_HANDLED : IRQ_NONE;
 142 }
 143
 144 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
 145 {
 146         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
 147
 148         /* Set up the I2C parameters in the parameter ram. */
 149         out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
 150         out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
 151
 152         if (cpm->version == 1) {
 153                 out_8(&i2c_ram->tfcr, I2C_EB);
 154                 out_8(&i2c_ram->rfcr, I2C_EB);
 155         } else {
 156                 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
 157                 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
 158         }
 159
 160         out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
 161
 162         out_be32(&i2c_ram->rstate, 0);
 163         out_be32(&i2c_ram->rdp, 0);
 164         out_be16(&i2c_ram->rbptr, 0);
 165         out_be16(&i2c_ram->rbc, 0);
 166         out_be32(&i2c_ram->rxtmp, 0);
 167         out_be32(&i2c_ram->tstate, 0);
 168         out_be32(&i2c_ram->tdp, 0);
 169         out_be16(&i2c_ram->tbptr, 0);
 170         out_be16(&i2c_ram->tbc, 0);
 171         out_be32(&i2c_ram->txtmp, 0);
 172 }
 173
 174 static void cpm_i2c_force_close(struct i2c_adapter *adap)
 175 {
 176         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 177         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
 178
 179         dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
 180
 181         cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
 182
 183         out_8(&i2c_reg->i2cmr, 0x00);   /* Disable all interrupts */
 184         out_8(&i2c_reg->i2cer, 0xff);
 185 }
 186
 187 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
 188         struct i2c_msg *pmsg, int num, int tx, int rx)
 189 {
 190         cbd_t __iomem *tbdf;
 191         cbd_t __iomem *rbdf;
 192         u_char addr;
 193         u_char *tb;
 194         u_char *rb;
 195         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 196
 197         tbdf = cpm->tbase + tx;
 198         rbdf = cpm->rbase + rx;
 199
 200         addr = pmsg->addr << 1;
 201         if (pmsg->flags & I2C_M_RD)
 202                 addr |= 1;
 203
 204         tb = cpm->txbuf[tx];
 205         rb = cpm->rxbuf[rx];
 206
 207         /* Align read buffer */
 208         rb = (u_char *) (((ulong) rb + 1) & ~1);
 209
 210         tb[0] = addr;           /* Device address byte w/rw flag */
 211
 212         out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
 213         out_be16(&tbdf->cbd_sc, 0);
 214
 215         if (!(pmsg->flags & I2C_M_NOSTART))
 216                 setbits16(&tbdf->cbd_sc, BD_I2C_START);
 217
 218         if (tx + 1 == num)
 219                 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
 220
 221         if (pmsg->flags & I2C_M_RD) {
 222                 /*
 223                  * To read, we need an empty buffer of the proper length.
 224                  * All that is used is the first byte for address, the remainder
 225                  * is just used for timing (and doesn't really have to exist).
 226                  */
 227
 228                 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
 229
 230                 out_be16(&rbdf->cbd_datlen, 0);
 231                 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
 232
 233                 if (rx + 1 == CPM_MAXBD)
 234                         setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
 235
 236                 eieio();
 237                 setbits16(&tbdf->cbd_sc, BD_SC_READY);
 238         } else {
 239                 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
 240
 241                 memcpy(tb+1, pmsg->buf, pmsg->len);
 242
 243                 eieio();
 244                 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
 245         }
 246 }
 247
 248 static int cpm_i2c_check_message(struct i2c_adapter *adap,
 249         struct i2c_msg *pmsg, int tx, int rx)
 250 {
 251         cbd_t __iomem *tbdf;
 252         cbd_t __iomem *rbdf;
 253         u_char *tb;
 254         u_char *rb;
 255         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 256
 257         tbdf = cpm->tbase + tx;
 258         rbdf = cpm->rbase + rx;
 259
 260         tb = cpm->txbuf[tx];
 261         rb = cpm->rxbuf[rx];
 262
 263         /* Align read buffer */
 264         rb = (u_char *) (((uint) rb + 1) & ~1);
 265
 266         eieio();
 267         if (pmsg->flags & I2C_M_RD) {
 268                 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
 269                         in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
 270
 271                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
 272                         dev_dbg(&adap->dev, "I2C read; No ack\n");
 273                         return -ENXIO;
 274                 }
 275                 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
 276                         dev_err(&adap->dev,
 277                                 "I2C read; complete but rbuf empty\n");
 278                         return -EREMOTEIO;
 279                 }
 280                 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
 281                         dev_err(&adap->dev, "I2C read; Overrun\n");
 282                         return -EREMOTEIO;
 283                 }
 284                 memcpy(pmsg->buf, rb, pmsg->len);
 285         } else {
 286                 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
 287                         in_be16(&tbdf->cbd_sc));
 288
 289                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
 290                         dev_dbg(&adap->dev, "I2C write; No ack\n");
 291                         return -ENXIO;
 292                 }
 293                 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
 294                         dev_err(&adap->dev, "I2C write; Underrun\n");
 295                         return -EIO;
 296                 }
 297                 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
 298                         dev_err(&adap->dev, "I2C write; Collision\n");
 299                         return -EIO;
 300                 }
 301         }
 302         return 0;
 303 }
 304
 305 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 306 {
 307         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 308         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
 309         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
 310         struct i2c_msg *pmsg;
 311         int ret, i;
 312         int tptr;
 313         int rptr;
 314         cbd_t __iomem *tbdf;
 315         cbd_t __iomem *rbdf;
 316
 317         if (num > CPM_MAXBD)
 318                 return -EINVAL;
 319
 320         /* Check if we have any oversized READ requests */
 321         for (i = 0; i < num; i++) {
 322                 pmsg = &msgs[i];
 323                 if (pmsg->len >= CPM_MAX_READ)
 324                         return -EINVAL;
 325         }
 326
 327         /* Reset to use first buffer */
 328         out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
 329         out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
 330
 331         tbdf = cpm->tbase;
 332         rbdf = cpm->rbase;
 333
 334         tptr = 0;
 335         rptr = 0;
 336
 337         /*
 338          * If there was a collision in the last i2c transaction,
 339          * Set I2COM_MASTER as it was cleared during collision.
 340          */
 341         if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
 342                 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
 343         }
 344
 345         while (tptr < num) {
 346                 pmsg = &msgs[tptr];
 347                 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
 348
 349                 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
 350                 if (pmsg->flags & I2C_M_RD)
 351                         rptr++;
 352                 tptr++;
 353         }
 354         /* Start transfer now */
 355         /* Enable RX/TX/Error interupts */
 356         out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
 357         out_8(&i2c_reg->i2cer, 0xff);   /* Clear interrupt status */
 358         /* Chip bug, set enable here */
 359         setbits8(&i2c_reg->i2mod, I2MOD_EN);    /* Enable */
 360         /* Begin transmission */
 361         setbits8(&i2c_reg->i2com, I2COM_START);
 362
 363         tptr = 0;
 364         rptr = 0;
 365
 366         while (tptr < num) {
 367                 /* Check for outstanding messages */
 368                 dev_dbg(&adap->dev, "test ready.\n");
 369                 pmsg = &msgs[tptr];
 370                 if (pmsg->flags & I2C_M_RD)
 371                         ret = wait_event_timeout(cpm->i2c_wait,
 372                                 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
 373                                 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
 374                                 1 * HZ);
 375                 else
 376                         ret = wait_event_timeout(cpm->i2c_wait,
 377                                 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
 378                                 1 * HZ);
 379                 if (ret == 0) {
 380                         ret = -EREMOTEIO;
 381                         dev_err(&adap->dev, "I2C transfer: timeout\n");
 382                         goto out_err;
 383                 }
 384                 if (ret > 0) {
 385                         dev_dbg(&adap->dev, "ready.\n");
 386                         ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
 387                         tptr++;
 388                         if (pmsg->flags & I2C_M_RD)
 389                                 rptr++;
 390                         if (ret)
 391                                 goto out_err;
 392                 }
 393         }
 394 #ifdef I2C_CHIP_ERRATA
 395         /*
 396          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
 397          * Disabling I2C too early may cause too short stop condition
 398          */
 399         udelay(4);
 400         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
 401 #endif
 402         return (num);
 403
 404 out_err:
 405         cpm_i2c_force_close(adap);
 406 #ifdef I2C_CHIP_ERRATA
 407         /*
 408          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
 409          */
 410         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
 411 #endif
 412         return ret;
 413 }
 414
 415 static u32 cpm_i2c_func(struct i2c_adapter *adap)
 416 {
 417         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 418 }
 419
 420 /* -----exported algorithm data: -------------------------------------  */
 421
 422 static const struct i2c_algorithm cpm_i2c_algo = {
 423         .master_xfer = cpm_i2c_xfer,
 424         .functionality = cpm_i2c_func,
 425 };
 426
 427 static const struct i2c_adapter cpm_ops = {
 428         .owner          = THIS_MODULE,
 429         .name           = "i2c-cpm",
 430         .algo           = &cpm_i2c_algo,
 431 };
 432
 433 static int cpm_i2c_setup(struct cpm_i2c *cpm)
 434 {
 435         struct platform_device *ofdev = cpm->ofdev;
 436         const u32 *data;
 437         int len, ret, i;
 438         void __iomem *i2c_base;
 439         cbd_t __iomem *tbdf;
 440         cbd_t __iomem *rbdf;
 441         unsigned char brg;
 442
 443         dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
 444
 445         init_waitqueue_head(&cpm->i2c_wait);
 446
 447         cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
 448         if (!cpm->irq)
 449                 return -EINVAL;
 450
 451         /* Install interrupt handler. */
 452         ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
 453                           &cpm->adap);
 454         if (ret)
 455                 return ret;
 456
 457         /* I2C parameter RAM */
 458         i2c_base = of_iomap(ofdev->dev.of_node, 1);
 459         if (i2c_base == NULL) {
 460                 ret = -EINVAL;
 461                 goto out_irq;
 462         }
 463
 464         if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
 465
 466                 /* Check for and use a microcode relocation patch. */
 467                 cpm->i2c_ram = i2c_base;
 468                 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
 469
 470                 /*
 471                  * Maybe should use cpm_muram_alloc instead of hardcoding
 472                  * this in micropatch.c
 473                  */
 474                 if (cpm->i2c_addr) {
 475                         cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
 476                         iounmap(i2c_base);
 477                 }
 478
 479                 cpm->version = 1;
 480
 481         } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
 482                 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
 483                 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
 484                 out_be16(i2c_base, cpm->i2c_addr);
 485                 iounmap(i2c_base);
 486
 487                 cpm->version = 2;
 488
 489         } else {
 490                 iounmap(i2c_base);
 491                 ret = -EINVAL;
 492                 goto out_irq;
 493         }
 494
 495         /* I2C control/status registers */
 496         cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
 497         if (cpm->i2c_reg == NULL) {
 498                 ret = -EINVAL;
 499                 goto out_ram;
 500         }
 501
 502         data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
 503         if (!data || len != 4) {
 504                 ret = -EINVAL;
 505                 goto out_reg;
 506         }
 507         cpm->cp_command = *data;
 508
 509         data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
 510         if (data && len == 4)
 511                 cpm->adap.class = *data;
 512
 513         data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
 514         if (data && len == 4)
 515                 cpm->freq = *data;
 516         else
 517                 cpm->freq = 60000; /* use 60kHz i2c clock by default */
 518
 519         /*
 520          * Allocate space for CPM_MAXBD transmit and receive buffer
 521          * descriptors in the DP ram.
 522          */
 523         cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
 524         if (!cpm->dp_addr) {
 525                 ret = -ENOMEM;
 526                 goto out_reg;
 527         }
 528
 529         cpm->tbase = cpm_muram_addr(cpm->dp_addr);
 530         cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
 531
 532         /* Allocate TX and RX buffers */
 533
 534         tbdf = cpm->tbase;
 535         rbdf = cpm->rbase;
 536
 537         for (i = 0; i < CPM_MAXBD; i++) {
 538                 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
 539                                                    CPM_MAX_READ + 1,
 540                                                    &cpm->rxdma[i], GFP_KERNEL);
 541                 if (!cpm->rxbuf[i]) {
 542                         ret = -ENOMEM;
 543                         goto out_muram;
 544                 }
 545                 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
 546
 547                 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
 548                 if (!cpm->txbuf[i]) {
 549                         ret = -ENOMEM;
 550                         goto out_muram;
 551                 }
 552                 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
 553         }
 554
 555         /* Initialize Tx/Rx parameters. */
 556
 557         cpm_reset_i2c_params(cpm);
 558
 559         dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
 560                 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
 561         dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
 562                 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
 563                 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
 564
 565         cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
 566
 567         /*
 568          * Select an invalid address. Just make sure we don't use loopback mode
 569          */
 570         out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
 571
 572         /*
 573          * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
 574          * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
 575          * the actual i2c bus frequency.
 576          */
 577         brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
 578         out_8(&cpm->i2c_reg->i2brg, brg);
 579
 580         out_8(&cpm->i2c_reg->i2mod, 0x00);
 581         out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);      /* Master mode */
 582
 583         /* Disable interrupts. */
 584         out_8(&cpm->i2c_reg->i2cmr, 0);
 585         out_8(&cpm->i2c_reg->i2cer, 0xff);
 586
 587         return 0;
 588
 589 out_muram:
 590         for (i = 0; i < CPM_MAXBD; i++) {
 591                 if (cpm->rxbuf[i])
 592                         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 593                                 cpm->rxbuf[i], cpm->rxdma[i]);
 594                 if (cpm->txbuf[i])
 595                         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 596                                 cpm->txbuf[i], cpm->txdma[i]);
 597         }
 598         cpm_muram_free(cpm->dp_addr);
 599 out_reg:
 600         iounmap(cpm->i2c_reg);
 601 out_ram:
 602         if ((cpm->version == 1) && (!cpm->i2c_addr))
 603                 iounmap(cpm->i2c_ram);
 604         if (cpm->version == 2)
 605                 cpm_muram_free(cpm->i2c_addr);
 606 out_irq:
 607         free_irq(cpm->irq, &cpm->adap);
 608         return ret;
 609 }
 610
 611 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
 612 {
 613         int i;
 614
 615         /* Shut down I2C. */
 616         clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
 617
 618         /* Disable interrupts */
 619         out_8(&cpm->i2c_reg->i2cmr, 0);
 620         out_8(&cpm->i2c_reg->i2cer, 0xff);
 621
 622         free_irq(cpm->irq, &cpm->adap);
 623
 624         /* Free all memory */
 625         for (i = 0; i < CPM_MAXBD; i++) {
 626                 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 627                         cpm->rxbuf[i], cpm->rxdma[i]);
 628                 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 629                         cpm->txbuf[i], cpm->txdma[i]);
 630         }
 631
 632         cpm_muram_free(cpm->dp_addr);
 633         iounmap(cpm->i2c_reg);
 634
 635         if ((cpm->version == 1) && (!cpm->i2c_addr))
 636                 iounmap(cpm->i2c_ram);
 637         if (cpm->version == 2)
 638                 cpm_muram_free(cpm->i2c_addr);
 639 }
 640
 641 static int cpm_i2c_probe(struct platform_device *ofdev)
 642 {
 643         int result, len;
 644         struct cpm_i2c *cpm;
 645         const u32 *data;
 646
 647         cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
 648         if (!cpm)
 649                 return -ENOMEM;
 650
 651         cpm->ofdev = ofdev;
 652
 653         platform_set_drvdata(ofdev, cpm);
 654
 655         cpm->adap = cpm_ops;
 656         i2c_set_adapdata(&cpm->adap, cpm);
 657         cpm->adap.dev.parent = &ofdev->dev;
 658         cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
 659
 660         result = cpm_i2c_setup(cpm);
 661         if (result) {
 662                 dev_err(&ofdev->dev, "Unable to init hardware\n");
 663                 goto out_free;
 664         }
 665
 666         /* register new adapter to i2c module... */
 667
 668         data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
 669         cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
 670         result = i2c_add_numbered_adapter(&cpm->adap);
 671
 672         if (result < 0) {
 673                 dev_err(&ofdev->dev, "Unable to register with I2C\n");
 674                 goto out_shut;
 675         }
 676
 677         dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
 678                 cpm->adap.name);
 679
 680         return 0;
 681 out_shut:
 682         cpm_i2c_shutdown(cpm);
 683 out_free:
 684         kfree(cpm);
 685
 686         return result;
 687 }
 688
 689 static int cpm_i2c_remove(struct platform_device *ofdev)
 690 {
 691         struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
 692
 693         i2c_del_adapter(&cpm->adap);
 694
 695         cpm_i2c_shutdown(cpm);
 696
 697         kfree(cpm);
 698
 699         return 0;
 700 }
 701
 702 static const struct of_device_id cpm_i2c_match[] = {
 703         {
 704                 .compatible = "fsl,cpm1-i2c",
 705         },
 706         {
 707                 .compatible = "fsl,cpm2-i2c",
 708         },
 709         {},
 710 };
 711
 712 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
 713
 714 static struct platform_driver cpm_i2c_driver = {
 715         .probe          = cpm_i2c_probe,
 716         .remove         = cpm_i2c_remove,
 717         .driver = {
 718                 .name = "fsl-i2c-cpm",
 719                 .of_match_table = cpm_i2c_match,
 720         },
 721 };
 722
 723 module_platform_driver(cpm_i2c_driver);
 724
 725 MODULE_AUTHOR("Jochen Friedrich <[email protected]>");
 726 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
 727 MODULE_LICENSE("GPL");