drivers/crypto/nx/nx-sha512.c

   1 /**
   2  * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
   3  *
   4  * Copyright (C) 2011-2012 International Business Machines Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 only.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Author: Kent Yoder <[email protected]>
  20  */
  21
  22 #include <crypto/internal/hash.h>
  23 #include <crypto/sha.h>
  24 #include <linux/module.h>
  25 #include <asm/vio.h>
  26
  27 #include "nx_csbcpb.h"
  28 #include "nx.h"
  29
  30
  31 static int nx_sha512_init(struct shash_desc *desc)
  32 {
  33         struct sha512_state *sctx = shash_desc_ctx(desc);
  34         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
  35         int len;
  36         int rc;
  37
  38         nx_ctx_init(nx_ctx, HCOP_FC_SHA);
  39
  40         memset(sctx, 0, sizeof *sctx);
  41
  42         nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
  43
  44         NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
  45
  46         len = SHA512_DIGEST_SIZE;
  47         rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
  48                                   &nx_ctx->op.outlen,
  49                                   &len,
  50                                   (u8 *)sctx->state,
  51                                   NX_DS_SHA512);
  52
  53         if (rc || len != SHA512_DIGEST_SIZE)
  54                 goto out;
  55
  56         sctx->state[0] = __cpu_to_be64(SHA512_H0);
  57         sctx->state[1] = __cpu_to_be64(SHA512_H1);
  58         sctx->state[2] = __cpu_to_be64(SHA512_H2);
  59         sctx->state[3] = __cpu_to_be64(SHA512_H3);
  60         sctx->state[4] = __cpu_to_be64(SHA512_H4);
  61         sctx->state[5] = __cpu_to_be64(SHA512_H5);
  62         sctx->state[6] = __cpu_to_be64(SHA512_H6);
  63         sctx->state[7] = __cpu_to_be64(SHA512_H7);
  64         sctx->count[0] = 0;
  65
  66 out:
  67         return 0;
  68 }
  69
  70 static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
  71                             unsigned int len)
  72 {
  73         struct sha512_state *sctx = shash_desc_ctx(desc);
  74         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
  75         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
  76         u64 to_process, leftover = 0, total;
  77         unsigned long irq_flags;
  78         int rc = 0;
  79         int data_len;
  80         u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);
  81
  82         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
  83
  84         /* 2 cases for total data len:
  85          *  1: < SHA512_BLOCK_SIZE: copy into state, return 0
  86          *  2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
  87          */
  88         total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
  89         if (total < SHA512_BLOCK_SIZE) {
  90                 memcpy(sctx->buf + buf_len, data, len);
  91                 sctx->count[0] += len;
  92                 goto out;
  93         }
  94
  95         memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
  96         NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
  97         NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
  98
  99         do {
 100                 /*
 101                  * to_process: the SHA512_BLOCK_SIZE data chunk to process in
 102                  * this update. This value is also restricted by the sg list
 103                  * limits.
 104                  */
 105                 to_process = total - leftover;
 106                 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
 107                 leftover = total - to_process;
 108
 109                 if (buf_len) {
 110                         data_len = buf_len;
 111                         rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
 112                                                   &nx_ctx->op.inlen,
 113                                                   &data_len,
 114                                                   (u8 *) sctx->buf,
 115                                                   NX_DS_SHA512);
 116
 117                         if (rc || data_len != buf_len)
 118                                 goto out;
 119                 }
 120
 121                 data_len = to_process - buf_len;
 122                 rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
 123                                           &nx_ctx->op.inlen,
 124                                           &data_len,
 125                                           (u8 *) data,
 126                                           NX_DS_SHA512);
 127
 128                 if (rc || data_len != (to_process - buf_len))
 129                         goto out;
 130
 131                 to_process = (data_len + buf_len);
 132                 leftover = total - to_process;
 133
 134                 /*
 135                  * we've hit the nx chip previously and we're updating
 136                  * again, so copy over the partial digest.
 137                  */
 138                 memcpy(csbcpb->cpb.sha512.input_partial_digest,
 139                                csbcpb->cpb.sha512.message_digest,
 140                                SHA512_DIGEST_SIZE);
 141
 142                 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
 143                         rc = -EINVAL;
 144                         goto out;
 145                 }
 146
 147                 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 148                                    desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 149                 if (rc)
 150                         goto out;
 151
 152                 atomic_inc(&(nx_ctx->stats->sha512_ops));
 153
 154                 total -= to_process;
 155                 data += to_process - buf_len;
 156                 buf_len = 0;
 157
 158         } while (leftover >= SHA512_BLOCK_SIZE);
 159
 160         /* copy the leftover back into the state struct */
 161         if (leftover)
 162                 memcpy(sctx->buf, data, leftover);
 163         sctx->count[0] += len;
 164         memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
 165 out:
 166         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 167         return rc;
 168 }
 169
 170 static int nx_sha512_final(struct shash_desc *desc, u8 *out)
 171 {
 172         struct sha512_state *sctx = shash_desc_ctx(desc);
 173         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
 174         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
 175         u64 count0;
 176         unsigned long irq_flags;
 177         int rc;
 178         int len;
 179
 180         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
 181
 182         /* final is represented by continuing the operation and indicating that
 183          * this is not an intermediate operation */
 184         if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
 185                 /* we've hit the nx chip previously, now we're finalizing,
 186                  * so copy over the partial digest */
 187                 memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
 188                                                         SHA512_DIGEST_SIZE);
 189                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 190                 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
 191         } else {
 192                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 193                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
 194         }
 195
 196         NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 197
 198         count0 = sctx->count[0] * 8;
 199
 200         csbcpb->cpb.sha512.message_bit_length_lo = count0;
 201
 202         len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
 203         rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
 204                                   &nx_ctx->op.inlen,
 205                                   &len,
 206                                   (u8 *)sctx->buf,
 207                                   NX_DS_SHA512);
 208
 209         if (rc || len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1)))
 210                 goto out;
 211
 212         len = SHA512_DIGEST_SIZE;
 213         rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
 214                                   &nx_ctx->op.outlen,
 215                                   &len,
 216                                   out,
 217                                   NX_DS_SHA512);
 218
 219         if (rc)
 220                 goto out;
 221
 222         if (!nx_ctx->op.outlen) {
 223                 rc = -EINVAL;
 224                 goto out;
 225         }
 226
 227         rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 228                            desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 229         if (rc)
 230                 goto out;
 231
 232         atomic_inc(&(nx_ctx->stats->sha512_ops));
 233         atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));
 234
 235         memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
 236 out:
 237         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 238         return rc;
 239 }
 240
 241 static int nx_sha512_export(struct shash_desc *desc, void *out)
 242 {
 243         struct sha512_state *sctx = shash_desc_ctx(desc);
 244
 245         memcpy(out, sctx, sizeof(*sctx));
 246
 247         return 0;
 248 }
 249
 250 static int nx_sha512_import(struct shash_desc *desc, const void *in)
 251 {
 252         struct sha512_state *sctx = shash_desc_ctx(desc);
 253
 254         memcpy(sctx, in, sizeof(*sctx));
 255
 256         return 0;
 257 }
 258
 259 struct shash_alg nx_shash_sha512_alg = {
 260         .digestsize = SHA512_DIGEST_SIZE,
 261         .init       = nx_sha512_init,
 262         .update     = nx_sha512_update,
 263         .final      = nx_sha512_final,
 264         .export     = nx_sha512_export,
 265         .import     = nx_sha512_import,
 266         .descsize   = sizeof(struct sha512_state),
 267         .statesize  = sizeof(struct sha512_state),
 268         .base       = {
 269                 .cra_name        = "sha512",
 270                 .cra_driver_name = "sha512-nx",
 271                 .cra_priority    = 300,
 272                 .cra_flags       = CRYPTO_ALG_TYPE_SHASH,
 273                 .cra_blocksize   = SHA512_BLOCK_SIZE,
 274                 .cra_module      = THIS_MODULE,
 275                 .cra_ctxsize     = sizeof(struct nx_crypto_ctx),
 276                 .cra_init        = nx_crypto_ctx_sha_init,
 277                 .cra_exit        = nx_crypto_ctx_exit,
 278         }
 279 };