drivers/spi/spi-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3 // Copyright (C) 2008 Juergen Beisert
   4
   5 #include <linux/clk.h>
   6 #include <linux/completion.h>
   7 #include <linux/delay.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/err.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/types.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/property.h>
  25
  26 #include <linux/dma/imx-dma.h>
  27
  28 #define DRIVER_NAME "spi_imx"
  29
  30 static bool use_dma = true;
  31 module_param(use_dma, bool, 0644);
  32 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
  33
  34 /* define polling limits */
  35 static unsigned int polling_limit_us = 30;
  36 module_param(polling_limit_us, uint, 0664);
  37 MODULE_PARM_DESC(polling_limit_us,
  38                  "time in us to run a transfer in polling mode\n");
  39
  40 #define MXC_RPM_TIMEOUT         2000 /* 2000ms */
  41
  42 #define MXC_CSPIRXDATA          0x00
  43 #define MXC_CSPITXDATA          0x04
  44 #define MXC_CSPICTRL            0x08
  45 #define MXC_CSPIINT             0x0c
  46 #define MXC_RESET               0x1c
  47
  48 /* generic defines to abstract from the different register layouts */
  49 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  50 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  51 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  52
  53 /* The maximum bytes that a sdma BD can transfer. */
  54 #define MAX_SDMA_BD_BYTES (1 << 15)
  55 #define MX51_ECSPI_CTRL_MAX_BURST       512
  56 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  57 #define MX53_MAX_TRANSFER_BYTES         512
  58
  59 enum spi_imx_devtype {
  60         IMX1_CSPI,
  61         IMX21_CSPI,
  62         IMX27_CSPI,
  63         IMX31_CSPI,
  64         IMX35_CSPI,     /* CSPI on all i.mx except above */
  65         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  66         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  67 };
  68
  69 struct spi_imx_data;
  70
  71 struct spi_imx_devtype_data {
  72         void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
  73         int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
  74         int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
  75         void (*trigger)(struct spi_imx_data *spi_imx);
  76         int (*rx_available)(struct spi_imx_data *spi_imx);
  77         void (*reset)(struct spi_imx_data *spi_imx);
  78         void (*setup_wml)(struct spi_imx_data *spi_imx);
  79         void (*disable)(struct spi_imx_data *spi_imx);
  80         bool has_dmamode;
  81         bool has_slavemode;
  82         unsigned int fifo_size;
  83         bool dynamic_burst;
  84         /*
  85          * ERR009165 fixed or not:
  86          * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
  87          */
  88         bool tx_glitch_fixed;
  89         enum spi_imx_devtype devtype;
  90 };
  91
  92 struct spi_imx_data {
  93         struct spi_controller *controller;
  94         struct device *dev;
  95
  96         struct completion xfer_done;
  97         void __iomem *base;
  98         unsigned long base_phys;
  99
 100         struct clk *clk_per;
 101         struct clk *clk_ipg;
 102         unsigned long spi_clk;
 103         unsigned int spi_bus_clk;
 104
 105         unsigned int bits_per_word;
 106         unsigned int spi_drctl;
 107
 108         unsigned int count, remainder;
 109         void (*tx)(struct spi_imx_data *spi_imx);
 110         void (*rx)(struct spi_imx_data *spi_imx);
 111         void *rx_buf;
 112         const void *tx_buf;
 113         unsigned int txfifo; /* number of words pushed in tx FIFO */
 114         unsigned int dynamic_burst;
 115         bool rx_only;
 116
 117         /* Slave mode */
 118         bool slave_mode;
 119         bool slave_aborted;
 120         unsigned int slave_burst;
 121
 122         /* DMA */
 123         bool usedma;
 124         u32 wml;
 125         struct completion dma_rx_completion;
 126         struct completion dma_tx_completion;
 127
 128         const struct spi_imx_devtype_data *devtype_data;
 129 };
 130
 131 static inline int is_imx27_cspi(struct spi_imx_data *d)
 132 {
 133         return d->devtype_data->devtype == IMX27_CSPI;
 134 }
 135
 136 static inline int is_imx35_cspi(struct spi_imx_data *d)
 137 {
 138         return d->devtype_data->devtype == IMX35_CSPI;
 139 }
 140
 141 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 142 {
 143         return d->devtype_data->devtype == IMX51_ECSPI;
 144 }
 145
 146 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 147 {
 148         return d->devtype_data->devtype == IMX53_ECSPI;
 149 }
 150
 151 #define MXC_SPI_BUF_RX(type)                                            \
 152 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 153 {                                                                       \
 154         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 155                                                                         \
 156         if (spi_imx->rx_buf) {                                          \
 157                 *(type *)spi_imx->rx_buf = val;                         \
 158                 spi_imx->rx_buf += sizeof(type);                        \
 159         }                                                               \
 160                                                                         \
 161         spi_imx->remainder -= sizeof(type);                             \
 162 }
 163
 164 #define MXC_SPI_BUF_TX(type)                                            \
 165 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 166 {                                                                       \
 167         type val = 0;                                                   \
 168                                                                         \
 169         if (spi_imx->tx_buf) {                                          \
 170                 val = *(type *)spi_imx->tx_buf;                         \
 171                 spi_imx->tx_buf += sizeof(type);                        \
 172         }                                                               \
 173                                                                         \
 174         spi_imx->count -= sizeof(type);                                 \
 175                                                                         \
 176         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 177 }
 178
 179 MXC_SPI_BUF_RX(u8)
 180 MXC_SPI_BUF_TX(u8)
 181 MXC_SPI_BUF_RX(u16)
 182 MXC_SPI_BUF_TX(u16)
 183 MXC_SPI_BUF_RX(u32)
 184 MXC_SPI_BUF_TX(u32)
 185
 186 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 187  * (which is currently not the case in this driver)
 188  */
 189 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 190         256, 384, 512, 768, 1024};
 191
 192 /* MX21, MX27 */
 193 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 194                 unsigned int fspi, unsigned int max, unsigned int *fres)
 195 {
 196         int i;
 197
 198         for (i = 2; i < max; i++)
 199                 if (fspi * mxc_clkdivs[i] >= fin)
 200                         break;
 201
 202         *fres = fin / mxc_clkdivs[i];
 203         return i;
 204 }
 205
 206 /* MX1, MX31, MX35, MX51 CSPI */
 207 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 208                 unsigned int fspi, unsigned int *fres)
 209 {
 210         int i, div = 4;
 211
 212         for (i = 0; i < 7; i++) {
 213                 if (fspi * div >= fin)
 214                         goto out;
 215                 div <<= 1;
 216         }
 217
 218 out:
 219         *fres = fin / div;
 220         return i;
 221 }
 222
 223 static int spi_imx_bytes_per_word(const int bits_per_word)
 224 {
 225         if (bits_per_word <= 8)
 226                 return 1;
 227         else if (bits_per_word <= 16)
 228                 return 2;
 229         else
 230                 return 4;
 231 }
 232
 233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
 234                          struct spi_transfer *transfer)
 235 {
 236         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
 237
 238         if (!use_dma || controller->fallback)
 239                 return false;
 240
 241         if (!controller->dma_rx)
 242                 return false;
 243
 244         if (spi_imx->slave_mode)
 245                 return false;
 246
 247         if (transfer->len < spi_imx->devtype_data->fifo_size)
 248                 return false;
 249
 250         spi_imx->dynamic_burst = 0;
 251
 252         return true;
 253 }
 254
 255 /*
 256  * Note the number of natively supported chip selects for MX51 is 4. Some
 257  * devices may have less actual SS pins but the register map supports 4. When
 258  * using gpio chip selects the cs values passed into the macros below can go
 259  * outside the range 0 - 3. We therefore need to limit the cs value to avoid
 260  * corrupting bits outside the allocated locations.
 261  *
 262  * The simplest way to do this is to just mask the cs bits to 2 bits. This
 263  * still allows all 4 native chip selects to work as well as gpio chip selects
 264  * (which can use any of the 4 chip select configurations).
 265  */
 266
 267 #define MX51_ECSPI_CTRL         0x08
 268 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 269 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 270 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 271 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 272 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 273 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 274 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 275 #define MX51_ECSPI_CTRL_CS(cs)          ((cs & 3) << 18)
 276 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 277 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 278
 279 #define MX51_ECSPI_CONFIG       0x0c
 280 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs & 3) +  0))
 281 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs & 3) +  4))
 282 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs & 3) +  8))
 283 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs & 3) + 12))
 284 #define MX51_ECSPI_CONFIG_DATACTL(cs)   (1 << ((cs & 3) + 16))
 285 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs & 3) + 20))
 286
 287 #define MX51_ECSPI_INT          0x10
 288 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 289 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 290 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 291
 292 #define MX51_ECSPI_DMA          0x14
 293 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 294 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 295 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 296
 297 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 298 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 299 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 300
 301 #define MX51_ECSPI_STAT         0x18
 302 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 303
 304 #define MX51_ECSPI_TESTREG      0x20
 305 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 306
 307 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 308 {
 309         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 310
 311         if (spi_imx->rx_buf) {
 312 #ifdef __LITTLE_ENDIAN
 313                 unsigned int bytes_per_word;
 314
 315                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 316                 if (bytes_per_word == 1)
 317                         swab32s(&val);
 318                 else if (bytes_per_word == 2)
 319                         swahw32s(&val);
 320 #endif
 321                 *(u32 *)spi_imx->rx_buf = val;
 322                 spi_imx->rx_buf += sizeof(u32);
 323         }
 324
 325         spi_imx->remainder -= sizeof(u32);
 326 }
 327
 328 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 329 {
 330         int unaligned;
 331         u32 val;
 332
 333         unaligned = spi_imx->remainder % 4;
 334
 335         if (!unaligned) {
 336                 spi_imx_buf_rx_swap_u32(spi_imx);
 337                 return;
 338         }
 339
 340         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 341                 spi_imx_buf_rx_u16(spi_imx);
 342                 return;
 343         }
 344
 345         val = readl(spi_imx->base + MXC_CSPIRXDATA);
 346
 347         while (unaligned--) {
 348                 if (spi_imx->rx_buf) {
 349                         *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
 350                         spi_imx->rx_buf++;
 351                 }
 352                 spi_imx->remainder--;
 353         }
 354 }
 355
 356 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 357 {
 358         u32 val = 0;
 359 #ifdef __LITTLE_ENDIAN
 360         unsigned int bytes_per_word;
 361 #endif
 362
 363         if (spi_imx->tx_buf) {
 364                 val = *(u32 *)spi_imx->tx_buf;
 365                 spi_imx->tx_buf += sizeof(u32);
 366         }
 367
 368         spi_imx->count -= sizeof(u32);
 369 #ifdef __LITTLE_ENDIAN
 370         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 371
 372         if (bytes_per_word == 1)
 373                 swab32s(&val);
 374         else if (bytes_per_word == 2)
 375                 swahw32s(&val);
 376 #endif
 377         writel(val, spi_imx->base + MXC_CSPITXDATA);
 378 }
 379
 380 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 381 {
 382         int unaligned;
 383         u32 val = 0;
 384
 385         unaligned = spi_imx->count % 4;
 386
 387         if (!unaligned) {
 388                 spi_imx_buf_tx_swap_u32(spi_imx);
 389                 return;
 390         }
 391
 392         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 393                 spi_imx_buf_tx_u16(spi_imx);
 394                 return;
 395         }
 396
 397         while (unaligned--) {
 398                 if (spi_imx->tx_buf) {
 399                         val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
 400                         spi_imx->tx_buf++;
 401                 }
 402                 spi_imx->count--;
 403         }
 404
 405         writel(val, spi_imx->base + MXC_CSPITXDATA);
 406 }
 407
 408 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
 409 {
 410         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 411
 412         if (spi_imx->rx_buf) {
 413                 int n_bytes = spi_imx->slave_burst % sizeof(val);
 414
 415                 if (!n_bytes)
 416                         n_bytes = sizeof(val);
 417
 418                 memcpy(spi_imx->rx_buf,
 419                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 420
 421                 spi_imx->rx_buf += n_bytes;
 422                 spi_imx->slave_burst -= n_bytes;
 423         }
 424
 425         spi_imx->remainder -= sizeof(u32);
 426 }
 427
 428 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
 429 {
 430         u32 val = 0;
 431         int n_bytes = spi_imx->count % sizeof(val);
 432
 433         if (!n_bytes)
 434                 n_bytes = sizeof(val);
 435
 436         if (spi_imx->tx_buf) {
 437                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 438                        spi_imx->tx_buf, n_bytes);
 439                 val = cpu_to_be32(val);
 440                 spi_imx->tx_buf += n_bytes;
 441         }
 442
 443         spi_imx->count -= n_bytes;
 444
 445         writel(val, spi_imx->base + MXC_CSPITXDATA);
 446 }
 447
 448 /* MX51 eCSPI */
 449 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 450                                       unsigned int fspi, unsigned int *fres)
 451 {
 452         /*
 453          * there are two 4-bit dividers, the pre-divider divides by
 454          * $pre, the post-divider by 2^$post
 455          */
 456         unsigned int pre, post;
 457         unsigned int fin = spi_imx->spi_clk;
 458
 459         fspi = min(fspi, fin);
 460
 461         post = fls(fin) - fls(fspi);
 462         if (fin > fspi << post)
 463                 post++;
 464
 465         /* now we have: (fin <= fspi << post) with post being minimal */
 466
 467         post = max(4U, post) - 4;
 468         if (unlikely(post > 0xf)) {
 469                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 470                                 fspi, fin);
 471                 return 0xff;
 472         }
 473
 474         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 475
 476         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 477                         __func__, fin, fspi, post, pre);
 478
 479         /* Resulting frequency for the SCLK line. */
 480         *fres = (fin / (pre + 1)) >> post;
 481
 482         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 483                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 484 }
 485
 486 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 487 {
 488         unsigned int val = 0;
 489
 490         if (enable & MXC_INT_TE)
 491                 val |= MX51_ECSPI_INT_TEEN;
 492
 493         if (enable & MXC_INT_RR)
 494                 val |= MX51_ECSPI_INT_RREN;
 495
 496         if (enable & MXC_INT_RDR)
 497                 val |= MX51_ECSPI_INT_RDREN;
 498
 499         writel(val, spi_imx->base + MX51_ECSPI_INT);
 500 }
 501
 502 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 503 {
 504         u32 reg;
 505
 506         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 507         reg |= MX51_ECSPI_CTRL_XCH;
 508         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 509 }
 510
 511 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 512 {
 513         u32 ctrl;
 514
 515         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 516         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 517         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 518 }
 519
 520 static int mx51_ecspi_channel(const struct spi_device *spi)
 521 {
 522         if (!spi_get_csgpiod(spi, 0))
 523                 return spi_get_chipselect(spi, 0);
 524         return spi->controller->unused_native_cs;
 525 }
 526
 527 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 528                                       struct spi_message *msg)
 529 {
 530         struct spi_device *spi = msg->spi;
 531         struct spi_transfer *xfer;
 532         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 533         u32 min_speed_hz = ~0U;
 534         u32 testreg, delay;
 535         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 536         u32 current_cfg = cfg;
 537         int channel = mx51_ecspi_channel(spi);
 538
 539         /* set Master or Slave mode */
 540         if (spi_imx->slave_mode)
 541                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 542         else
 543                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 544
 545         /*
 546          * Enable SPI_RDY handling (falling edge/level triggered).
 547          */
 548         if (spi->mode & SPI_READY)
 549                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 550
 551         /* set chip select to use */
 552         ctrl |= MX51_ECSPI_CTRL_CS(channel);
 553
 554         /*
 555          * The ctrl register must be written first, with the EN bit set other
 556          * registers must not be written to.
 557          */
 558         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 559
 560         testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 561         if (spi->mode & SPI_LOOP)
 562                 testreg |= MX51_ECSPI_TESTREG_LBC;
 563         else
 564                 testreg &= ~MX51_ECSPI_TESTREG_LBC;
 565         writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
 566
 567         /*
 568          * eCSPI burst completion by Chip Select signal in Slave mode
 569          * is not functional for imx53 Soc, config SPI burst completed when
 570          * BURST_LENGTH + 1 bits are received
 571          */
 572         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 573                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
 574         else
 575                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
 576
 577         if (spi->mode & SPI_CPOL) {
 578                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
 579                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
 580         } else {
 581                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
 582                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
 583         }
 584
 585         if (spi->mode & SPI_MOSI_IDLE_LOW)
 586                 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
 587         else
 588                 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
 589
 590         if (spi->mode & SPI_CS_HIGH)
 591                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
 592         else
 593                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
 594
 595         if (cfg == current_cfg)
 596                 return 0;
 597
 598         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 599
 600         /*
 601          * Wait until the changes in the configuration register CONFIGREG
 602          * propagate into the hardware. It takes exactly one tick of the
 603          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 604          * effect of the delay it takes for the hardware to apply changes
 605          * is noticable if the SCLK clock run very slow. In such a case, if
 606          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 607          * be asserted before the SCLK polarity changes, which would disrupt
 608          * the SPI communication as the device on the other end would consider
 609          * the change of SCLK polarity as a clock tick already.
 610          *
 611          * Because spi_imx->spi_bus_clk is only set in prepare_message
 612          * callback, iterate over all the transfers in spi_message, find the
 613          * one with lowest bus frequency, and use that bus frequency for the
 614          * delay calculation. In case all transfers have speed_hz == 0, then
 615          * min_speed_hz is ~0 and the resulting delay is zero.
 616          */
 617         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 618                 if (!xfer->speed_hz)
 619                         continue;
 620                 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
 621         }
 622
 623         delay = (2 * 1000000) / min_speed_hz;
 624         if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
 625                 udelay(delay);
 626         else                    /* SCLK is _very_ slow */
 627                 usleep_range(delay, delay + 10);
 628
 629         return 0;
 630 }
 631
 632 static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
 633                                 struct spi_device *spi)
 634 {
 635         bool cpha = (spi->mode & SPI_CPHA);
 636         bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
 637         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 638         int channel = mx51_ecspi_channel(spi);
 639
 640         /* Flip cpha logical value iff flip_cpha */
 641         cpha ^= flip_cpha;
 642
 643         if (cpha)
 644                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
 645         else
 646                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
 647
 648         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 649 }
 650
 651 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 652                                        struct spi_device *spi)
 653 {
 654         u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 655         u32 clk;
 656
 657         /* Clear BL field and set the right value */
 658         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 659         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 660                 ctrl |= (spi_imx->slave_burst * 8 - 1)
 661                         << MX51_ECSPI_CTRL_BL_OFFSET;
 662         else
 663                 ctrl |= (spi_imx->bits_per_word - 1)
 664                         << MX51_ECSPI_CTRL_BL_OFFSET;
 665
 666         /* set clock speed */
 667         ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
 668                   0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
 669         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
 670         spi_imx->spi_bus_clk = clk;
 671
 672         mx51_configure_cpha(spi_imx, spi);
 673
 674         /*
 675          * ERR009165: work in XHC mode instead of SMC as PIO on the chips
 676          * before i.mx6ul.
 677          */
 678         if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
 679                 ctrl |= MX51_ECSPI_CTRL_SMC;
 680         else
 681                 ctrl &= ~MX51_ECSPI_CTRL_SMC;
 682
 683         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 684
 685         return 0;
 686 }
 687
 688 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
 689 {
 690         u32 tx_wml = 0;
 691
 692         if (spi_imx->devtype_data->tx_glitch_fixed)
 693                 tx_wml = spi_imx->wml;
 694         /*
 695          * Configure the DMA register: setup the watermark
 696          * and enable DMA request.
 697          */
 698         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
 699                 MX51_ECSPI_DMA_TX_WML(tx_wml) |
 700                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 701                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 702                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 703 }
 704
 705 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 706 {
 707         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 708 }
 709
 710 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 711 {
 712         /* drain receive buffer */
 713         while (mx51_ecspi_rx_available(spi_imx))
 714                 readl(spi_imx->base + MXC_CSPIRXDATA);
 715 }
 716
 717 #define MX31_INTREG_TEEN        (1 << 0)
 718 #define MX31_INTREG_RREN        (1 << 3)
 719
 720 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 721 #define MX31_CSPICTRL_MASTER    (1 << 1)
 722 #define MX31_CSPICTRL_XCH       (1 << 2)
 723 #define MX31_CSPICTRL_SMC       (1 << 3)
 724 #define MX31_CSPICTRL_POL       (1 << 4)
 725 #define MX31_CSPICTRL_PHA       (1 << 5)
 726 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 727 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 728 #define MX31_CSPICTRL_BC_SHIFT  8
 729 #define MX35_CSPICTRL_BL_SHIFT  20
 730 #define MX31_CSPICTRL_CS_SHIFT  24
 731 #define MX35_CSPICTRL_CS_SHIFT  12
 732 #define MX31_CSPICTRL_DR_SHIFT  16
 733
 734 #define MX31_CSPI_DMAREG        0x10
 735 #define MX31_DMAREG_RH_DEN      (1<<4)
 736 #define MX31_DMAREG_TH_DEN      (1<<1)
 737
 738 #define MX31_CSPISTATUS         0x14
 739 #define MX31_STATUS_RR          (1 << 3)
 740
 741 #define MX31_CSPI_TESTREG       0x1C
 742 #define MX31_TEST_LBC           (1 << 14)
 743
 744 /* These functions also work for the i.MX35, but be aware that
 745  * the i.MX35 has a slightly different register layout for bits
 746  * we do not use here.
 747  */
 748 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 749 {
 750         unsigned int val = 0;
 751
 752         if (enable & MXC_INT_TE)
 753                 val |= MX31_INTREG_TEEN;
 754         if (enable & MXC_INT_RR)
 755                 val |= MX31_INTREG_RREN;
 756
 757         writel(val, spi_imx->base + MXC_CSPIINT);
 758 }
 759
 760 static void mx31_trigger(struct spi_imx_data *spi_imx)
 761 {
 762         unsigned int reg;
 763
 764         reg = readl(spi_imx->base + MXC_CSPICTRL);
 765         reg |= MX31_CSPICTRL_XCH;
 766         writel(reg, spi_imx->base + MXC_CSPICTRL);
 767 }
 768
 769 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
 770                                 struct spi_message *msg)
 771 {
 772         return 0;
 773 }
 774
 775 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
 776                                  struct spi_device *spi)
 777 {
 778         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 779         unsigned int clk;
 780
 781         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 782                 MX31_CSPICTRL_DR_SHIFT;
 783         spi_imx->spi_bus_clk = clk;
 784
 785         if (is_imx35_cspi(spi_imx)) {
 786                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 787                 reg |= MX31_CSPICTRL_SSCTL;
 788         } else {
 789                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 790         }
 791
 792         if (spi->mode & SPI_CPHA)
 793                 reg |= MX31_CSPICTRL_PHA;
 794         if (spi->mode & SPI_CPOL)
 795                 reg |= MX31_CSPICTRL_POL;
 796         if (spi->mode & SPI_CS_HIGH)
 797                 reg |= MX31_CSPICTRL_SSPOL;
 798         if (!spi_get_csgpiod(spi, 0))
 799                 reg |= (spi_get_chipselect(spi, 0)) <<
 800                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 801                                                   MX31_CSPICTRL_CS_SHIFT);
 802
 803         if (spi_imx->usedma)
 804                 reg |= MX31_CSPICTRL_SMC;
 805
 806         writel(reg, spi_imx->base + MXC_CSPICTRL);
 807
 808         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 809         if (spi->mode & SPI_LOOP)
 810                 reg |= MX31_TEST_LBC;
 811         else
 812                 reg &= ~MX31_TEST_LBC;
 813         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 814
 815         if (spi_imx->usedma) {
 816                 /*
 817                  * configure DMA requests when RXFIFO is half full and
 818                  * when TXFIFO is half empty
 819                  */
 820                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 821                         spi_imx->base + MX31_CSPI_DMAREG);
 822         }
 823
 824         return 0;
 825 }
 826
 827 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 828 {
 829         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 830 }
 831
 832 static void mx31_reset(struct spi_imx_data *spi_imx)
 833 {
 834         /* drain receive buffer */
 835         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 836                 readl(spi_imx->base + MXC_CSPIRXDATA);
 837 }
 838
 839 #define MX21_INTREG_RR          (1 << 4)
 840 #define MX21_INTREG_TEEN        (1 << 9)
 841 #define MX21_INTREG_RREN        (1 << 13)
 842
 843 #define MX21_CSPICTRL_POL       (1 << 5)
 844 #define MX21_CSPICTRL_PHA       (1 << 6)
 845 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 846 #define MX21_CSPICTRL_XCH       (1 << 9)
 847 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 848 #define MX21_CSPICTRL_MASTER    (1 << 11)
 849 #define MX21_CSPICTRL_DR_SHIFT  14
 850 #define MX21_CSPICTRL_CS_SHIFT  19
 851
 852 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 853 {
 854         unsigned int val = 0;
 855
 856         if (enable & MXC_INT_TE)
 857                 val |= MX21_INTREG_TEEN;
 858         if (enable & MXC_INT_RR)
 859                 val |= MX21_INTREG_RREN;
 860
 861         writel(val, spi_imx->base + MXC_CSPIINT);
 862 }
 863
 864 static void mx21_trigger(struct spi_imx_data *spi_imx)
 865 {
 866         unsigned int reg;
 867
 868         reg = readl(spi_imx->base + MXC_CSPICTRL);
 869         reg |= MX21_CSPICTRL_XCH;
 870         writel(reg, spi_imx->base + MXC_CSPICTRL);
 871 }
 872
 873 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
 874                                 struct spi_message *msg)
 875 {
 876         return 0;
 877 }
 878
 879 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
 880                                  struct spi_device *spi)
 881 {
 882         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 883         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 884         unsigned int clk;
 885
 886         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
 887                 << MX21_CSPICTRL_DR_SHIFT;
 888         spi_imx->spi_bus_clk = clk;
 889
 890         reg |= spi_imx->bits_per_word - 1;
 891
 892         if (spi->mode & SPI_CPHA)
 893                 reg |= MX21_CSPICTRL_PHA;
 894         if (spi->mode & SPI_CPOL)
 895                 reg |= MX21_CSPICTRL_POL;
 896         if (spi->mode & SPI_CS_HIGH)
 897                 reg |= MX21_CSPICTRL_SSPOL;
 898         if (!spi_get_csgpiod(spi, 0))
 899                 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
 900
 901         writel(reg, spi_imx->base + MXC_CSPICTRL);
 902
 903         return 0;
 904 }
 905
 906 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 907 {
 908         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 909 }
 910
 911 static void mx21_reset(struct spi_imx_data *spi_imx)
 912 {
 913         writel(1, spi_imx->base + MXC_RESET);
 914 }
 915
 916 #define MX1_INTREG_RR           (1 << 3)
 917 #define MX1_INTREG_TEEN         (1 << 8)
 918 #define MX1_INTREG_RREN         (1 << 11)
 919
 920 #define MX1_CSPICTRL_POL        (1 << 4)
 921 #define MX1_CSPICTRL_PHA        (1 << 5)
 922 #define MX1_CSPICTRL_XCH        (1 << 8)
 923 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 924 #define MX1_CSPICTRL_MASTER     (1 << 10)
 925 #define MX1_CSPICTRL_DR_SHIFT   13
 926
 927 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 928 {
 929         unsigned int val = 0;
 930
 931         if (enable & MXC_INT_TE)
 932                 val |= MX1_INTREG_TEEN;
 933         if (enable & MXC_INT_RR)
 934                 val |= MX1_INTREG_RREN;
 935
 936         writel(val, spi_imx->base + MXC_CSPIINT);
 937 }
 938
 939 static void mx1_trigger(struct spi_imx_data *spi_imx)
 940 {
 941         unsigned int reg;
 942
 943         reg = readl(spi_imx->base + MXC_CSPICTRL);
 944         reg |= MX1_CSPICTRL_XCH;
 945         writel(reg, spi_imx->base + MXC_CSPICTRL);
 946 }
 947
 948 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
 949                                struct spi_message *msg)
 950 {
 951         return 0;
 952 }
 953
 954 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
 955                                 struct spi_device *spi)
 956 {
 957         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 958         unsigned int clk;
 959
 960         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 961                 MX1_CSPICTRL_DR_SHIFT;
 962         spi_imx->spi_bus_clk = clk;
 963
 964         reg |= spi_imx->bits_per_word - 1;
 965
 966         if (spi->mode & SPI_CPHA)
 967                 reg |= MX1_CSPICTRL_PHA;
 968         if (spi->mode & SPI_CPOL)
 969                 reg |= MX1_CSPICTRL_POL;
 970
 971         writel(reg, spi_imx->base + MXC_CSPICTRL);
 972
 973         return 0;
 974 }
 975
 976 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 977 {
 978         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 979 }
 980
 981 static void mx1_reset(struct spi_imx_data *spi_imx)
 982 {
 983         writel(1, spi_imx->base + MXC_RESET);
 984 }
 985
 986 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 987         .intctrl = mx1_intctrl,
 988         .prepare_message = mx1_prepare_message,
 989         .prepare_transfer = mx1_prepare_transfer,
 990         .trigger = mx1_trigger,
 991         .rx_available = mx1_rx_available,
 992         .reset = mx1_reset,
 993         .fifo_size = 8,
 994         .has_dmamode = false,
 995         .dynamic_burst = false,
 996         .has_slavemode = false,
 997         .devtype = IMX1_CSPI,
 998 };
 999
1000 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1001         .intctrl = mx21_intctrl,
1002         .prepare_message = mx21_prepare_message,
1003         .prepare_transfer = mx21_prepare_transfer,
1004         .trigger = mx21_trigger,
1005         .rx_available = mx21_rx_available,
1006         .reset = mx21_reset,
1007         .fifo_size = 8,
1008         .has_dmamode = false,
1009         .dynamic_burst = false,
1010         .has_slavemode = false,
1011         .devtype = IMX21_CSPI,
1012 };
1013
1014 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1015         /* i.mx27 cspi shares the functions with i.mx21 one */
1016         .intctrl = mx21_intctrl,
1017         .prepare_message = mx21_prepare_message,
1018         .prepare_transfer = mx21_prepare_transfer,
1019         .trigger = mx21_trigger,
1020         .rx_available = mx21_rx_available,
1021         .reset = mx21_reset,
1022         .fifo_size = 8,
1023         .has_dmamode = false,
1024         .dynamic_burst = false,
1025         .has_slavemode = false,
1026         .devtype = IMX27_CSPI,
1027 };
1028
1029 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1030         .intctrl = mx31_intctrl,
1031         .prepare_message = mx31_prepare_message,
1032         .prepare_transfer = mx31_prepare_transfer,
1033         .trigger = mx31_trigger,
1034         .rx_available = mx31_rx_available,
1035         .reset = mx31_reset,
1036         .fifo_size = 8,
1037         .has_dmamode = false,
1038         .dynamic_burst = false,
1039         .has_slavemode = false,
1040         .devtype = IMX31_CSPI,
1041 };
1042
1043 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1044         /* i.mx35 and later cspi shares the functions with i.mx31 one */
1045         .intctrl = mx31_intctrl,
1046         .prepare_message = mx31_prepare_message,
1047         .prepare_transfer = mx31_prepare_transfer,
1048         .trigger = mx31_trigger,
1049         .rx_available = mx31_rx_available,
1050         .reset = mx31_reset,
1051         .fifo_size = 8,
1052         .has_dmamode = true,
1053         .dynamic_burst = false,
1054         .has_slavemode = false,
1055         .devtype = IMX35_CSPI,
1056 };
1057
1058 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1059         .intctrl = mx51_ecspi_intctrl,
1060         .prepare_message = mx51_ecspi_prepare_message,
1061         .prepare_transfer = mx51_ecspi_prepare_transfer,
1062         .trigger = mx51_ecspi_trigger,
1063         .rx_available = mx51_ecspi_rx_available,
1064         .reset = mx51_ecspi_reset,
1065         .setup_wml = mx51_setup_wml,
1066         .fifo_size = 64,
1067         .has_dmamode = true,
1068         .dynamic_burst = true,
1069         .has_slavemode = true,
1070         .disable = mx51_ecspi_disable,
1071         .devtype = IMX51_ECSPI,
1072 };
1073
1074 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1075         .intctrl = mx51_ecspi_intctrl,
1076         .prepare_message = mx51_ecspi_prepare_message,
1077         .prepare_transfer = mx51_ecspi_prepare_transfer,
1078         .trigger = mx51_ecspi_trigger,
1079         .rx_available = mx51_ecspi_rx_available,
1080         .reset = mx51_ecspi_reset,
1081         .fifo_size = 64,
1082         .has_dmamode = true,
1083         .has_slavemode = true,
1084         .disable = mx51_ecspi_disable,
1085         .devtype = IMX53_ECSPI,
1086 };
1087
1088 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1089         .intctrl = mx51_ecspi_intctrl,
1090         .prepare_message = mx51_ecspi_prepare_message,
1091         .prepare_transfer = mx51_ecspi_prepare_transfer,
1092         .trigger = mx51_ecspi_trigger,
1093         .rx_available = mx51_ecspi_rx_available,
1094         .reset = mx51_ecspi_reset,
1095         .setup_wml = mx51_setup_wml,
1096         .fifo_size = 64,
1097         .has_dmamode = true,
1098         .dynamic_burst = true,
1099         .has_slavemode = true,
1100         .tx_glitch_fixed = true,
1101         .disable = mx51_ecspi_disable,
1102         .devtype = IMX51_ECSPI,
1103 };
1104
1105 static const struct of_device_id spi_imx_dt_ids[] = {
1106         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1107         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1108         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1109         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1110         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1111         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1112         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1113         { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1114         { /* sentinel */ }
1115 };
1116 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1117
1118 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1119 {
1120         u32 ctrl;
1121
1122         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1123         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1124         ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1125         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1126 }
1127
1128 static void spi_imx_push(struct spi_imx_data *spi_imx)
1129 {
1130         unsigned int burst_len;
1131
1132         /*
1133          * Reload the FIFO when the remaining bytes to be transferred in the
1134          * current burst is 0. This only applies when bits_per_word is a
1135          * multiple of 8.
1136          */
1137         if (!spi_imx->remainder) {
1138                 if (spi_imx->dynamic_burst) {
1139
1140                         /* We need to deal unaligned data first */
1141                         burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1142
1143                         if (!burst_len)
1144                                 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1145
1146                         spi_imx_set_burst_len(spi_imx, burst_len * 8);
1147
1148                         spi_imx->remainder = burst_len;
1149                 } else {
1150                         spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1151                 }
1152         }
1153
1154         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1155                 if (!spi_imx->count)
1156                         break;
1157                 if (spi_imx->dynamic_burst &&
1158                     spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1159                         break;
1160                 spi_imx->tx(spi_imx);
1161                 spi_imx->txfifo++;
1162         }
1163
1164         if (!spi_imx->slave_mode)
1165                 spi_imx->devtype_data->trigger(spi_imx);
1166 }
1167
1168 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1169 {
1170         struct spi_imx_data *spi_imx = dev_id;
1171
1172         while (spi_imx->txfifo &&
1173                spi_imx->devtype_data->rx_available(spi_imx)) {
1174                 spi_imx->rx(spi_imx);
1175                 spi_imx->txfifo--;
1176         }
1177
1178         if (spi_imx->count) {
1179                 spi_imx_push(spi_imx);
1180                 return IRQ_HANDLED;
1181         }
1182
1183         if (spi_imx->txfifo) {
1184                 /* No data left to push, but still waiting for rx data,
1185                  * enable receive data available interrupt.
1186                  */
1187                 spi_imx->devtype_data->intctrl(
1188                                 spi_imx, MXC_INT_RR);
1189                 return IRQ_HANDLED;
1190         }
1191
1192         spi_imx->devtype_data->intctrl(spi_imx, 0);
1193         complete(&spi_imx->xfer_done);
1194
1195         return IRQ_HANDLED;
1196 }
1197
1198 static int spi_imx_dma_configure(struct spi_controller *controller)
1199 {
1200         int ret;
1201         enum dma_slave_buswidth buswidth;
1202         struct dma_slave_config rx = {}, tx = {};
1203         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1204
1205         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1206         case 4:
1207                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1208                 break;
1209         case 2:
1210                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1211                 break;
1212         case 1:
1213                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1214                 break;
1215         default:
1216                 return -EINVAL;
1217         }
1218
1219         tx.direction = DMA_MEM_TO_DEV;
1220         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1221         tx.dst_addr_width = buswidth;
1222         tx.dst_maxburst = spi_imx->wml;
1223         ret = dmaengine_slave_config(controller->dma_tx, &tx);
1224         if (ret) {
1225                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1226                 return ret;
1227         }
1228
1229         rx.direction = DMA_DEV_TO_MEM;
1230         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1231         rx.src_addr_width = buswidth;
1232         rx.src_maxburst = spi_imx->wml;
1233         ret = dmaengine_slave_config(controller->dma_rx, &rx);
1234         if (ret) {
1235                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1236                 return ret;
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int spi_imx_setupxfer(struct spi_device *spi,
1243                                  struct spi_transfer *t)
1244 {
1245         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1246
1247         if (!t)
1248                 return 0;
1249
1250         if (!t->speed_hz) {
1251                 if (!spi->max_speed_hz) {
1252                         dev_err(&spi->dev, "no speed_hz provided!\n");
1253                         return -EINVAL;
1254                 }
1255                 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1256                 spi_imx->spi_bus_clk = spi->max_speed_hz;
1257         } else
1258                 spi_imx->spi_bus_clk = t->speed_hz;
1259
1260         spi_imx->bits_per_word = t->bits_per_word;
1261
1262         /*
1263          * Initialize the functions for transfer. To transfer non byte-aligned
1264          * words, we have to use multiple word-size bursts, we can't use
1265          * dynamic_burst in that case.
1266          */
1267         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1268             !(spi->mode & SPI_CS_WORD) &&
1269             (spi_imx->bits_per_word == 8 ||
1270             spi_imx->bits_per_word == 16 ||
1271             spi_imx->bits_per_word == 32)) {
1272
1273                 spi_imx->rx = spi_imx_buf_rx_swap;
1274                 spi_imx->tx = spi_imx_buf_tx_swap;
1275                 spi_imx->dynamic_burst = 1;
1276
1277         } else {
1278                 if (spi_imx->bits_per_word <= 8) {
1279                         spi_imx->rx = spi_imx_buf_rx_u8;
1280                         spi_imx->tx = spi_imx_buf_tx_u8;
1281                 } else if (spi_imx->bits_per_word <= 16) {
1282                         spi_imx->rx = spi_imx_buf_rx_u16;
1283                         spi_imx->tx = spi_imx_buf_tx_u16;
1284                 } else {
1285                         spi_imx->rx = spi_imx_buf_rx_u32;
1286                         spi_imx->tx = spi_imx_buf_tx_u32;
1287                 }
1288                 spi_imx->dynamic_burst = 0;
1289         }
1290
1291         if (spi_imx_can_dma(spi_imx->controller, spi, t))
1292                 spi_imx->usedma = true;
1293         else
1294                 spi_imx->usedma = false;
1295
1296         spi_imx->rx_only = ((t->tx_buf == NULL)
1297                         || (t->tx_buf == spi->controller->dummy_tx));
1298
1299         if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1300                 spi_imx->rx = mx53_ecspi_rx_slave;
1301                 spi_imx->tx = mx53_ecspi_tx_slave;
1302                 spi_imx->slave_burst = t->len;
1303         }
1304
1305         spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1306
1307         return 0;
1308 }
1309
1310 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1311 {
1312         struct spi_controller *controller = spi_imx->controller;
1313
1314         if (controller->dma_rx) {
1315                 dma_release_channel(controller->dma_rx);
1316                 controller->dma_rx = NULL;
1317         }
1318
1319         if (controller->dma_tx) {
1320                 dma_release_channel(controller->dma_tx);
1321                 controller->dma_tx = NULL;
1322         }
1323 }
1324
1325 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1326                              struct spi_controller *controller)
1327 {
1328         int ret;
1329
1330         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1331
1332         /* Prepare for TX DMA: */
1333         controller->dma_tx = dma_request_chan(dev, "tx");
1334         if (IS_ERR(controller->dma_tx)) {
1335                 ret = PTR_ERR(controller->dma_tx);
1336                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1337                 controller->dma_tx = NULL;
1338                 goto err;
1339         }
1340
1341         /* Prepare for RX : */
1342         controller->dma_rx = dma_request_chan(dev, "rx");
1343         if (IS_ERR(controller->dma_rx)) {
1344                 ret = PTR_ERR(controller->dma_rx);
1345                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1346                 controller->dma_rx = NULL;
1347                 goto err;
1348         }
1349
1350         init_completion(&spi_imx->dma_rx_completion);
1351         init_completion(&spi_imx->dma_tx_completion);
1352         controller->can_dma = spi_imx_can_dma;
1353         controller->max_dma_len = MAX_SDMA_BD_BYTES;
1354         spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1355                                          SPI_CONTROLLER_MUST_TX;
1356
1357         return 0;
1358 err:
1359         spi_imx_sdma_exit(spi_imx);
1360         return ret;
1361 }
1362
1363 static void spi_imx_dma_rx_callback(void *cookie)
1364 {
1365         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1366
1367         complete(&spi_imx->dma_rx_completion);
1368 }
1369
1370 static void spi_imx_dma_tx_callback(void *cookie)
1371 {
1372         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1373
1374         complete(&spi_imx->dma_tx_completion);
1375 }
1376
1377 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1378 {
1379         unsigned long timeout = 0;
1380
1381         /* Time with actual data transfer and CS change delay related to HW */
1382         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1383
1384         /* Add extra second for scheduler related activities */
1385         timeout += 1;
1386
1387         /* Double calculated timeout */
1388         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1389 }
1390
1391 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1392                                 struct spi_transfer *transfer)
1393 {
1394         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1395         unsigned long transfer_timeout;
1396         unsigned long timeout;
1397         struct spi_controller *controller = spi_imx->controller;
1398         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1399         struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1400         unsigned int bytes_per_word, i;
1401         int ret;
1402
1403         /* Get the right burst length from the last sg to ensure no tail data */
1404         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1405         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1406                 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1407                         break;
1408         }
1409         /* Use 1 as wml in case no available burst length got */
1410         if (i == 0)
1411                 i = 1;
1412
1413         spi_imx->wml =  i;
1414
1415         ret = spi_imx_dma_configure(controller);
1416         if (ret)
1417                 goto dma_failure_no_start;
1418
1419         if (!spi_imx->devtype_data->setup_wml) {
1420                 dev_err(spi_imx->dev, "No setup_wml()?\n");
1421                 ret = -EINVAL;
1422                 goto dma_failure_no_start;
1423         }
1424         spi_imx->devtype_data->setup_wml(spi_imx);
1425
1426         /*
1427          * The TX DMA setup starts the transfer, so make sure RX is configured
1428          * before TX.
1429          */
1430         desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1431                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1432                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1433         if (!desc_rx) {
1434                 ret = -EINVAL;
1435                 goto dma_failure_no_start;
1436         }
1437
1438         desc_rx->callback = spi_imx_dma_rx_callback;
1439         desc_rx->callback_param = (void *)spi_imx;
1440         dmaengine_submit(desc_rx);
1441         reinit_completion(&spi_imx->dma_rx_completion);
1442         dma_async_issue_pending(controller->dma_rx);
1443
1444         desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1445                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1446                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1447         if (!desc_tx) {
1448                 dmaengine_terminate_all(controller->dma_tx);
1449                 dmaengine_terminate_all(controller->dma_rx);
1450                 return -EINVAL;
1451         }
1452
1453         desc_tx->callback = spi_imx_dma_tx_callback;
1454         desc_tx->callback_param = (void *)spi_imx;
1455         dmaengine_submit(desc_tx);
1456         reinit_completion(&spi_imx->dma_tx_completion);
1457         dma_async_issue_pending(controller->dma_tx);
1458
1459         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1460
1461         /* Wait SDMA to finish the data transfer.*/
1462         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1463                                                 transfer_timeout);
1464         if (!timeout) {
1465                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1466                 dmaengine_terminate_all(controller->dma_tx);
1467                 dmaengine_terminate_all(controller->dma_rx);
1468                 return -ETIMEDOUT;
1469         }
1470
1471         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1472                                               transfer_timeout);
1473         if (!timeout) {
1474                 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1475                 spi_imx->devtype_data->reset(spi_imx);
1476                 dmaengine_terminate_all(controller->dma_rx);
1477                 return -ETIMEDOUT;
1478         }
1479
1480         return 0;
1481 /* fallback to pio */
1482 dma_failure_no_start:
1483         transfer->error |= SPI_TRANS_FAIL_NO_START;
1484         return ret;
1485 }
1486
1487 static int spi_imx_pio_transfer(struct spi_device *spi,
1488                                 struct spi_transfer *transfer)
1489 {
1490         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1491         unsigned long transfer_timeout;
1492         unsigned long timeout;
1493
1494         spi_imx->tx_buf = transfer->tx_buf;
1495         spi_imx->rx_buf = transfer->rx_buf;
1496         spi_imx->count = transfer->len;
1497         spi_imx->txfifo = 0;
1498         spi_imx->remainder = 0;
1499
1500         reinit_completion(&spi_imx->xfer_done);
1501
1502         spi_imx_push(spi_imx);
1503
1504         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1505
1506         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1507
1508         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1509                                               transfer_timeout);
1510         if (!timeout) {
1511                 dev_err(&spi->dev, "I/O Error in PIO\n");
1512                 spi_imx->devtype_data->reset(spi_imx);
1513                 return -ETIMEDOUT;
1514         }
1515
1516         return 0;
1517 }
1518
1519 static int spi_imx_poll_transfer(struct spi_device *spi,
1520                                  struct spi_transfer *transfer)
1521 {
1522         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1523         unsigned long timeout;
1524
1525         spi_imx->tx_buf = transfer->tx_buf;
1526         spi_imx->rx_buf = transfer->rx_buf;
1527         spi_imx->count = transfer->len;
1528         spi_imx->txfifo = 0;
1529         spi_imx->remainder = 0;
1530
1531         /* fill in the fifo before timeout calculations if we are
1532          * interrupted here, then the data is getting transferred by
1533          * the HW while we are interrupted
1534          */
1535         spi_imx_push(spi_imx);
1536
1537         timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1538         while (spi_imx->txfifo) {
1539                 /* RX */
1540                 while (spi_imx->txfifo &&
1541                        spi_imx->devtype_data->rx_available(spi_imx)) {
1542                         spi_imx->rx(spi_imx);
1543                         spi_imx->txfifo--;
1544                 }
1545
1546                 /* TX */
1547                 if (spi_imx->count) {
1548                         spi_imx_push(spi_imx);
1549                         continue;
1550                 }
1551
1552                 if (spi_imx->txfifo &&
1553                     time_after(jiffies, timeout)) {
1554
1555                         dev_err_ratelimited(&spi->dev,
1556                                             "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1557                                             jiffies - timeout);
1558
1559                         /* fall back to interrupt mode */
1560                         return spi_imx_pio_transfer(spi, transfer);
1561                 }
1562         }
1563
1564         return 0;
1565 }
1566
1567 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1568                                       struct spi_transfer *transfer)
1569 {
1570         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1571         int ret = 0;
1572
1573         if (is_imx53_ecspi(spi_imx) &&
1574             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1575                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1576                         MX53_MAX_TRANSFER_BYTES);
1577                 return -EMSGSIZE;
1578         }
1579
1580         spi_imx->tx_buf = transfer->tx_buf;
1581         spi_imx->rx_buf = transfer->rx_buf;
1582         spi_imx->count = transfer->len;
1583         spi_imx->txfifo = 0;
1584         spi_imx->remainder = 0;
1585
1586         reinit_completion(&spi_imx->xfer_done);
1587         spi_imx->slave_aborted = false;
1588
1589         spi_imx_push(spi_imx);
1590
1591         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1592
1593         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1594             spi_imx->slave_aborted) {
1595                 dev_dbg(&spi->dev, "interrupted\n");
1596                 ret = -EINTR;
1597         }
1598
1599         /* ecspi has a HW issue when works in Slave mode,
1600          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1601          * ECSPI_TXDATA keeps shift out the last word data,
1602          * so we have to disable ECSPI when in slave mode after the
1603          * transfer completes
1604          */
1605         if (spi_imx->devtype_data->disable)
1606                 spi_imx->devtype_data->disable(spi_imx);
1607
1608         return ret;
1609 }
1610
1611 static int spi_imx_transfer_one(struct spi_controller *controller,
1612                                 struct spi_device *spi,
1613                                 struct spi_transfer *transfer)
1614 {
1615         struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1616         unsigned long hz_per_byte, byte_limit;
1617
1618         spi_imx_setupxfer(spi, transfer);
1619         transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1620
1621         /* flush rxfifo before transfer */
1622         while (spi_imx->devtype_data->rx_available(spi_imx))
1623                 readl(spi_imx->base + MXC_CSPIRXDATA);
1624
1625         if (spi_imx->slave_mode)
1626                 return spi_imx_pio_transfer_slave(spi, transfer);
1627
1628         /*
1629          * If we decided in spi_imx_can_dma() that we want to do a DMA
1630          * transfer, the SPI transfer has already been mapped, so we
1631          * have to do the DMA transfer here.
1632          */
1633         if (spi_imx->usedma)
1634                 return spi_imx_dma_transfer(spi_imx, transfer);
1635         /*
1636          * Calculate the estimated time in us the transfer runs. Find
1637          * the number of Hz per byte per polling limit.
1638          */
1639         hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
1640         byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
1641
1642         /* run in polling mode for short transfers */
1643         if (transfer->len < byte_limit)
1644                 return spi_imx_poll_transfer(spi, transfer);
1645
1646         return spi_imx_pio_transfer(spi, transfer);
1647 }
1648
1649 static int spi_imx_setup(struct spi_device *spi)
1650 {
1651         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1652                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1653
1654         return 0;
1655 }
1656
1657 static void spi_imx_cleanup(struct spi_device *spi)
1658 {
1659 }
1660
1661 static int
1662 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1663 {
1664         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1665         int ret;
1666
1667         ret = pm_runtime_resume_and_get(spi_imx->dev);
1668         if (ret < 0) {
1669                 dev_err(spi_imx->dev, "failed to enable clock\n");
1670                 return ret;
1671         }
1672
1673         ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1674         if (ret) {
1675                 pm_runtime_mark_last_busy(spi_imx->dev);
1676                 pm_runtime_put_autosuspend(spi_imx->dev);
1677         }
1678
1679         return ret;
1680 }
1681
1682 static int
1683 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1684 {
1685         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1686
1687         pm_runtime_mark_last_busy(spi_imx->dev);
1688         pm_runtime_put_autosuspend(spi_imx->dev);
1689         return 0;
1690 }
1691
1692 static int spi_imx_slave_abort(struct spi_controller *controller)
1693 {
1694         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1695
1696         spi_imx->slave_aborted = true;
1697         complete(&spi_imx->xfer_done);
1698
1699         return 0;
1700 }
1701
1702 static int spi_imx_probe(struct platform_device *pdev)
1703 {
1704         struct device_node *np = pdev->dev.of_node;
1705         struct spi_controller *controller;
1706         struct spi_imx_data *spi_imx;
1707         struct resource *res;
1708         int ret, irq, spi_drctl;
1709         const struct spi_imx_devtype_data *devtype_data =
1710                         of_device_get_match_data(&pdev->dev);
1711         bool slave_mode;
1712         u32 val;
1713
1714         slave_mode = devtype_data->has_slavemode &&
1715                         of_property_read_bool(np, "spi-slave");
1716         if (slave_mode)
1717                 controller = spi_alloc_slave(&pdev->dev,
1718                                              sizeof(struct spi_imx_data));
1719         else
1720                 controller = spi_alloc_master(&pdev->dev,
1721                                               sizeof(struct spi_imx_data));
1722         if (!controller)
1723                 return -ENOMEM;
1724
1725         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1726         if ((ret < 0) || (spi_drctl >= 0x3)) {
1727                 /* '11' is reserved */
1728                 spi_drctl = 0;
1729         }
1730
1731         platform_set_drvdata(pdev, controller);
1732
1733         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1734         controller->bus_num = np ? -1 : pdev->id;
1735         controller->use_gpio_descriptors = true;
1736
1737         spi_imx = spi_controller_get_devdata(controller);
1738         spi_imx->controller = controller;
1739         spi_imx->dev = &pdev->dev;
1740         spi_imx->slave_mode = slave_mode;
1741
1742         spi_imx->devtype_data = devtype_data;
1743
1744         /*
1745          * Get number of chip selects from device properties. This can be
1746          * coming from device tree or boardfiles, if it is not defined,
1747          * a default value of 3 chip selects will be used, as all the legacy
1748          * board files have <= 3 chip selects.
1749          */
1750         if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1751                 controller->num_chipselect = val;
1752         else
1753                 controller->num_chipselect = 3;
1754
1755         controller->transfer_one = spi_imx_transfer_one;
1756         controller->setup = spi_imx_setup;
1757         controller->cleanup = spi_imx_cleanup;
1758         controller->prepare_message = spi_imx_prepare_message;
1759         controller->unprepare_message = spi_imx_unprepare_message;
1760         controller->slave_abort = spi_imx_slave_abort;
1761         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1762                                 SPI_MOSI_IDLE_LOW;
1763
1764         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1765             is_imx53_ecspi(spi_imx))
1766                 controller->mode_bits |= SPI_LOOP | SPI_READY;
1767
1768         if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1769                 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1770
1771         if (is_imx51_ecspi(spi_imx) &&
1772             device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1773                 /*
1774                  * When using HW-CS implementing SPI_CS_WORD can be done by just
1775                  * setting the burst length to the word size. This is
1776                  * considerably faster than manually controlling the CS.
1777                  */
1778                 controller->mode_bits |= SPI_CS_WORD;
1779
1780         if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1781                 controller->max_native_cs = 4;
1782                 controller->flags |= SPI_MASTER_GPIO_SS;
1783         }
1784
1785         spi_imx->spi_drctl = spi_drctl;
1786
1787         init_completion(&spi_imx->xfer_done);
1788
1789         spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1790         if (IS_ERR(spi_imx->base)) {
1791                 ret = PTR_ERR(spi_imx->base);
1792                 goto out_controller_put;
1793         }
1794         spi_imx->base_phys = res->start;
1795
1796         irq = platform_get_irq(pdev, 0);
1797         if (irq < 0) {
1798                 ret = irq;
1799                 goto out_controller_put;
1800         }
1801
1802         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1803                                dev_name(&pdev->dev), spi_imx);
1804         if (ret) {
1805                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1806                 goto out_controller_put;
1807         }
1808
1809         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1810         if (IS_ERR(spi_imx->clk_ipg)) {
1811                 ret = PTR_ERR(spi_imx->clk_ipg);
1812                 goto out_controller_put;
1813         }
1814
1815         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1816         if (IS_ERR(spi_imx->clk_per)) {
1817                 ret = PTR_ERR(spi_imx->clk_per);
1818                 goto out_controller_put;
1819         }
1820
1821         ret = clk_prepare_enable(spi_imx->clk_per);
1822         if (ret)
1823                 goto out_controller_put;
1824
1825         ret = clk_prepare_enable(spi_imx->clk_ipg);
1826         if (ret)
1827                 goto out_put_per;
1828
1829         pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1830         pm_runtime_use_autosuspend(spi_imx->dev);
1831         pm_runtime_get_noresume(spi_imx->dev);
1832         pm_runtime_set_active(spi_imx->dev);
1833         pm_runtime_enable(spi_imx->dev);
1834
1835         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1836         /*
1837          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1838          * if validated on other chips.
1839          */
1840         if (spi_imx->devtype_data->has_dmamode) {
1841                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1842                 if (ret == -EPROBE_DEFER)
1843                         goto out_runtime_pm_put;
1844
1845                 if (ret < 0)
1846                         dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1847                                 ret);
1848         }
1849
1850         spi_imx->devtype_data->reset(spi_imx);
1851
1852         spi_imx->devtype_data->intctrl(spi_imx, 0);
1853
1854         controller->dev.of_node = pdev->dev.of_node;
1855         ret = spi_register_controller(controller);
1856         if (ret) {
1857                 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1858                 goto out_register_controller;
1859         }
1860
1861         pm_runtime_mark_last_busy(spi_imx->dev);
1862         pm_runtime_put_autosuspend(spi_imx->dev);
1863
1864         return ret;
1865
1866 out_register_controller:
1867         if (spi_imx->devtype_data->has_dmamode)
1868                 spi_imx_sdma_exit(spi_imx);
1869 out_runtime_pm_put:
1870         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1871         pm_runtime_set_suspended(&pdev->dev);
1872         pm_runtime_disable(spi_imx->dev);
1873
1874         clk_disable_unprepare(spi_imx->clk_ipg);
1875 out_put_per:
1876         clk_disable_unprepare(spi_imx->clk_per);
1877 out_controller_put:
1878         spi_controller_put(controller);
1879
1880         return ret;
1881 }
1882
1883 static void spi_imx_remove(struct platform_device *pdev)
1884 {
1885         struct spi_controller *controller = platform_get_drvdata(pdev);
1886         struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1887         int ret;
1888
1889         spi_unregister_controller(controller);
1890
1891         ret = pm_runtime_get_sync(spi_imx->dev);
1892         if (ret >= 0)
1893                 writel(0, spi_imx->base + MXC_CSPICTRL);
1894         else
1895                 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1896
1897         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1898         pm_runtime_put_sync(spi_imx->dev);
1899         pm_runtime_disable(spi_imx->dev);
1900
1901         spi_imx_sdma_exit(spi_imx);
1902 }
1903
1904 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1905 {
1906         struct spi_controller *controller = dev_get_drvdata(dev);
1907         struct spi_imx_data *spi_imx;
1908         int ret;
1909
1910         spi_imx = spi_controller_get_devdata(controller);
1911
1912         ret = clk_prepare_enable(spi_imx->clk_per);
1913         if (ret)
1914                 return ret;
1915
1916         ret = clk_prepare_enable(spi_imx->clk_ipg);
1917         if (ret) {
1918                 clk_disable_unprepare(spi_imx->clk_per);
1919                 return ret;
1920         }
1921
1922         return 0;
1923 }
1924
1925 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1926 {
1927         struct spi_controller *controller = dev_get_drvdata(dev);
1928         struct spi_imx_data *spi_imx;
1929
1930         spi_imx = spi_controller_get_devdata(controller);
1931
1932         clk_disable_unprepare(spi_imx->clk_per);
1933         clk_disable_unprepare(spi_imx->clk_ipg);
1934
1935         return 0;
1936 }
1937
1938 static int __maybe_unused spi_imx_suspend(struct device *dev)
1939 {
1940         pinctrl_pm_select_sleep_state(dev);
1941         return 0;
1942 }
1943
1944 static int __maybe_unused spi_imx_resume(struct device *dev)
1945 {
1946         pinctrl_pm_select_default_state(dev);
1947         return 0;
1948 }
1949
1950 static const struct dev_pm_ops imx_spi_pm = {
1951         SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1952                                 spi_imx_runtime_resume, NULL)
1953         SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1954 };
1955
1956 static struct platform_driver spi_imx_driver = {
1957         .driver = {
1958                    .name = DRIVER_NAME,
1959                    .of_match_table = spi_imx_dt_ids,
1960                    .pm = &imx_spi_pm,
1961         },
1962         .probe = spi_imx_probe,
1963         .remove_new = spi_imx_remove,
1964 };
1965 module_platform_driver(spi_imx_driver);
1966
1967 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1968 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1969 MODULE_LICENSE("GPL");
1970 MODULE_ALIAS("platform:" DRIVER_NAME);