drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <[email protected]>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/bug.h>
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/iommu.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/io-pgtable.h>
  17 #include <linux/list.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/soc/mediatek/infracfg.h>
  30 #include <asm/barrier.h>
  31 #include <soc/mediatek/smi.h>
  32
  33 #include <dt-bindings/memory/mtk-memory-port.h>
  34
  35 #define REG_MMU_PT_BASE_ADDR                    0x000
  36
  37 #define REG_MMU_INVALIDATE                      0x020
  38 #define F_ALL_INVLD                             0x2
  39 #define F_MMU_INV_RANGE                         0x1
  40
  41 #define REG_MMU_INVLD_START_A                   0x024
  42 #define REG_MMU_INVLD_END_A                     0x028
  43
  44 #define REG_MMU_INV_SEL_GEN2                    0x02c
  45 #define REG_MMU_INV_SEL_GEN1                    0x038
  46 #define F_INVLD_EN0                             BIT(0)
  47 #define F_INVLD_EN1                             BIT(1)
  48
  49 #define REG_MMU_MISC_CTRL                       0x048
  50 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  51 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  52
  53 #define REG_MMU_DCM_DIS                         0x050
  54 #define F_MMU_DCM                               BIT(8)
  55
  56 #define REG_MMU_WR_LEN_CTRL                     0x054
  57 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  58
  59 #define REG_MMU_CTRL_REG                        0x110
  60 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  61 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  62 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  63
  64 #define REG_MMU_IVRP_PADDR                      0x114
  65
  66 #define REG_MMU_VLD_PA_RNG                      0x118
  67 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  68
  69 #define REG_MMU_INT_CONTROL0                    0x120
  70 #define F_L2_MULIT_HIT_EN                       BIT(0)
  71 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  72 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  73 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  74 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  75 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  76 #define F_INT_CLR_BIT                           BIT(12)
  77
  78 #define REG_MMU_INT_MAIN_CONTROL                0x124
  79                                                 /* mmu0 | mmu1 */
  80 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  81 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  82 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  83 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  84 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  85 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  86 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  87
  88 #define REG_MMU_CPE_DONE                        0x12C
  89
  90 #define REG_MMU_FAULT_ST1                       0x134
  91 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  92 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  93
  94 #define REG_MMU0_FAULT_VA                       0x13c
  95 #define F_MMU_INVAL_VA_31_12_MASK               GENMASK(31, 12)
  96 #define F_MMU_INVAL_VA_34_32_MASK               GENMASK(11, 9)
  97 #define F_MMU_INVAL_PA_34_32_MASK               GENMASK(8, 6)
  98 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
  99 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
 100
 101 #define REG_MMU0_INVLD_PA                       0x140
 102 #define REG_MMU1_FAULT_VA                       0x144
 103 #define REG_MMU1_INVLD_PA                       0x148
 104 #define REG_MMU0_INT_ID                         0x150
 105 #define REG_MMU1_INT_ID                         0x154
 106 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 107 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 108 #define F_MMU_INT_ID_COMM_ID_EXT(a)             (((a) >> 10) & 0x7)
 109 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)         (((a) >> 7) & 0x7)
 110 /* Macro for 5 bits length port ID field (default) */
 111 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 112 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 113 /* Macro for 6 bits length port ID field */
 114 #define F_MMU_INT_ID_LARB_ID_WID_6(a)           (((a) >> 8) & 0x7)
 115 #define F_MMU_INT_ID_PORT_ID_WID_6(a)           (((a) >> 2) & 0x3f)
 116
 117 #define MTK_PROTECT_PA_ALIGN                    256
 118 #define MTK_IOMMU_BANK_SZ                       0x1000
 119
 120 #define PERICFG_IOMMU_1                         0x714
 121
 122 #define HAS_4GB_MODE                    BIT(0)
 123 /* HW will use the EMI clock if there isn't the "bclk". */
 124 #define HAS_BCLK                        BIT(1)
 125 #define HAS_VLD_PA_RNG                  BIT(2)
 126 #define RESET_AXI                       BIT(3)
 127 #define OUT_ORDER_WR_EN                 BIT(4)
 128 #define HAS_SUB_COMM_2BITS              BIT(5)
 129 #define HAS_SUB_COMM_3BITS              BIT(6)
 130 #define WR_THROT_EN                     BIT(7)
 131 #define HAS_LEGACY_IVRP_PADDR           BIT(8)
 132 #define IOVA_34_EN                      BIT(9)
 133 #define SHARE_PGTABLE                   BIT(10) /* 2 HW share pgtable */
 134 #define DCM_DISABLE                     BIT(11)
 135 #define STD_AXI_MODE                    BIT(12) /* For non MM iommu */
 136 /* 2 bits: iommu type */
 137 #define MTK_IOMMU_TYPE_MM               (0x0 << 13)
 138 #define MTK_IOMMU_TYPE_INFRA            (0x1 << 13)
 139 #define MTK_IOMMU_TYPE_MASK             (0x3 << 13)
 140 /* PM and clock always on. e.g. infra iommu */
 141 #define PM_CLK_AO                       BIT(15)
 142 #define IFA_IOMMU_PCIE_SUPPORT          BIT(16)
 143 #define PGTABLE_PA_35_EN                BIT(17)
 144 #define TF_PORT_TO_ADDR_MT8173          BIT(18)
 145 #define INT_ID_PORT_WIDTH_6             BIT(19)
 146
 147 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)        \
 148                                 ((((pdata)->flags) & (mask)) == (_x))
 149
 150 #define MTK_IOMMU_HAS_FLAG(pdata, _x)   MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
 151 #define MTK_IOMMU_IS_TYPE(pdata, _x)    MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
 152                                                         MTK_IOMMU_TYPE_MASK)
 153
 154 #define MTK_INVALID_LARBID              MTK_LARB_NR_MAX
 155
 156 #define MTK_LARB_COM_MAX        8
 157 #define MTK_LARB_SUBCOM_MAX     8
 158
 159 #define MTK_IOMMU_GROUP_MAX     8
 160 #define MTK_IOMMU_BANK_MAX      5
 161
 162 enum mtk_iommu_plat {
 163         M4U_MT2712,
 164         M4U_MT6779,
 165         M4U_MT6795,
 166         M4U_MT8167,
 167         M4U_MT8173,
 168         M4U_MT8183,
 169         M4U_MT8186,
 170         M4U_MT8192,
 171         M4U_MT8195,
 172         M4U_MT8365,
 173 };
 174
 175 struct mtk_iommu_iova_region {
 176         dma_addr_t              iova_base;
 177         unsigned long long      size;
 178 };
 179
 180 struct mtk_iommu_suspend_reg {
 181         u32                     misc_ctrl;
 182         u32                     dcm_dis;
 183         u32                     ctrl_reg;
 184         u32                     vld_pa_rng;
 185         u32                     wr_len_ctrl;
 186
 187         u32                     int_control[MTK_IOMMU_BANK_MAX];
 188         u32                     int_main_control[MTK_IOMMU_BANK_MAX];
 189         u32                     ivrp_paddr[MTK_IOMMU_BANK_MAX];
 190 };
 191
 192 struct mtk_iommu_plat_data {
 193         enum mtk_iommu_plat     m4u_plat;
 194         u32                     flags;
 195         u32                     inv_sel_reg;
 196
 197         char                    *pericfg_comp_str;
 198         struct list_head        *hw_list;
 199
 200         /*
 201          * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
 202          * different masters will be put in different iova ranges, for example vcodec
 203          * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
 204          * special IOVA range requirement, like CCU can only support the address
 205          * 0x40000000-0x44000000.
 206          * Here list the iova ranges this SoC supports and which larbs/ports are in
 207          * which region.
 208          *
 209          * 16GB iova all use one pgtable, but each a region is a iommu group.
 210          */
 211         struct {
 212                 unsigned int    iova_region_nr;
 213                 const struct mtk_iommu_iova_region      *iova_region;
 214                 /*
 215                  * Indicate the correspondance between larbs, ports and regions.
 216                  *
 217                  * The index is the same as iova_region and larb port numbers are
 218                  * described as bit positions.
 219                  * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2".
 220                  *              [2] = { [1] = BIT(0) }
 221                  */
 222                 const u32       (*iova_region_larb_msk)[MTK_LARB_NR_MAX];
 223         };
 224
 225         /*
 226          * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
 227          * Here list how many banks this SoC supports/enables and which ports are in which bank.
 228          */
 229         struct {
 230                 u8              banks_num;
 231                 bool            banks_enable[MTK_IOMMU_BANK_MAX];
 232                 unsigned int    banks_portmsk[MTK_IOMMU_BANK_MAX];
 233         };
 234
 235         unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
 236 };
 237
 238 struct mtk_iommu_bank_data {
 239         void __iomem                    *base;
 240         int                             irq;
 241         u8                              id;
 242         struct device                   *parent_dev;
 243         struct mtk_iommu_data           *parent_data;
 244         spinlock_t                      tlb_lock; /* lock for tlb range flush */
 245         struct mtk_iommu_domain         *m4u_dom; /* Each bank has a domain */
 246 };
 247
 248 struct mtk_iommu_data {
 249         struct device                   *dev;
 250         struct clk                      *bclk;
 251         phys_addr_t                     protect_base; /* protect memory base */
 252         struct mtk_iommu_suspend_reg    reg;
 253         struct iommu_group              *m4u_group[MTK_IOMMU_GROUP_MAX];
 254         bool                            enable_4GB;
 255
 256         struct iommu_device             iommu;
 257         const struct mtk_iommu_plat_data *plat_data;
 258         struct device                   *smicomm_dev;
 259
 260         struct mtk_iommu_bank_data      *bank;
 261         struct regmap                   *pericfg;
 262         struct mutex                    mutex; /* Protect m4u_group/m4u_dom above */
 263
 264         /*
 265          * In the sharing pgtable case, list data->list to the global list like m4ulist.
 266          * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
 267          */
 268         struct list_head                *hw_list;
 269         struct list_head                hw_list_head;
 270         struct list_head                list;
 271         struct mtk_smi_larb_iommu       larb_imu[MTK_LARB_NR_MAX];
 272 };
 273
 274 struct mtk_iommu_domain {
 275         struct io_pgtable_cfg           cfg;
 276         struct io_pgtable_ops           *iop;
 277
 278         struct mtk_iommu_bank_data      *bank;
 279         struct iommu_domain             domain;
 280
 281         struct mutex                    mutex; /* Protect "data" in this structure */
 282 };
 283
 284 static int mtk_iommu_bind(struct device *dev)
 285 {
 286         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 287
 288         return component_bind_all(dev, &data->larb_imu);
 289 }
 290
 291 static void mtk_iommu_unbind(struct device *dev)
 292 {
 293         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 294
 295         component_unbind_all(dev, &data->larb_imu);
 296 }
 297
 298 static const struct iommu_ops mtk_iommu_ops;
 299
 300 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
 301
 302 #define MTK_IOMMU_TLB_ADDR(iova) ({                                     \
 303         dma_addr_t _addr = iova;                                        \
 304         ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
 305 })
 306
 307 /*
 308  * In M4U 4GB mode, the physical address is remapped as below:
 309  *
 310  * CPU Physical address:
 311  * ====================
 312  *
 313  * 0      1G       2G     3G       4G     5G
 314  * |---A---|---B---|---C---|---D---|---E---|
 315  * +--I/O--+------------Memory-------------+
 316  *
 317  * IOMMU output physical address:
 318  *  =============================
 319  *
 320  *                                 4G      5G     6G      7G      8G
 321  *                                 |---E---|---B---|---C---|---D---|
 322  *                                 +------------Memory-------------+
 323  *
 324  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 325  * bit32 of the CPU physical address always is needed to set, and for Region
 326  * 'E', the CPU physical address keep as is.
 327  * Additionally, The iommu consumers always use the CPU phyiscal address.
 328  */
 329 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 330
 331 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 332
 333 #define for_each_m4u(data, head)  list_for_each_entry(data, head, list)
 334
 335 #define MTK_IOMMU_IOVA_SZ_4G            (SZ_4G - SZ_8M) /* 8M as gap */
 336
 337 static const struct mtk_iommu_iova_region single_domain[] = {
 338         {.iova_base = 0,                .size = MTK_IOMMU_IOVA_SZ_4G},
 339 };
 340
 341 #define MT8192_MULTI_REGION_NR_MAX      6
 342
 343 #define MT8192_MULTI_REGION_NR  (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \
 344                                  MT8192_MULTI_REGION_NR_MAX : 1)
 345
 346 static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {
 347         { .iova_base = 0x0,             .size = MTK_IOMMU_IOVA_SZ_4G},  /* 0 ~ 4G,  */
 348         #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
 349         { .iova_base = SZ_4G,           .size = MTK_IOMMU_IOVA_SZ_4G},  /* 4G ~ 8G */
 350         { .iova_base = SZ_4G * 2,       .size = MTK_IOMMU_IOVA_SZ_4G},  /* 8G ~ 12G */
 351         { .iova_base = SZ_4G * 3,       .size = MTK_IOMMU_IOVA_SZ_4G},  /* 12G ~ 16G */
 352
 353         { .iova_base = 0x240000000ULL,  .size = 0x4000000},     /* CCU0 */
 354         { .iova_base = 0x244000000ULL,  .size = 0x4000000},     /* CCU1 */
 355         #endif
 356 };
 357
 358 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
 359 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
 360 {
 361         return list_first_entry(hwlist, struct mtk_iommu_data, list);
 362 }
 363
 364 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 365 {
 366         return container_of(dom, struct mtk_iommu_domain, domain);
 367 }
 368
 369 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 370 {
 371         /* Tlb flush all always is in bank0. */
 372         struct mtk_iommu_bank_data *bank = &data->bank[0];
 373         void __iomem *base = bank->base;
 374         unsigned long flags;
 375
 376         spin_lock_irqsave(&bank->tlb_lock, flags);
 377         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
 378         writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
 379         wmb(); /* Make sure the tlb flush all done */
 380         spin_unlock_irqrestore(&bank->tlb_lock, flags);
 381 }
 382
 383 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 384                                            struct mtk_iommu_bank_data *bank)
 385 {
 386         struct list_head *head = bank->parent_data->hw_list;
 387         struct mtk_iommu_bank_data *curbank;
 388         struct mtk_iommu_data *data;
 389         bool check_pm_status;
 390         unsigned long flags;
 391         void __iomem *base;
 392         int ret;
 393         u32 tmp;
 394
 395         for_each_m4u(data, head) {
 396                 /*
 397                  * To avoid resume the iommu device frequently when the iommu device
 398                  * is not active, it doesn't always call pm_runtime_get here, then tlb
 399                  * flush depends on the tlb flush all in the runtime resume.
 400                  *
 401                  * There are 2 special cases:
 402                  *
 403                  * Case1: The iommu dev doesn't have power domain but has bclk. This case
 404                  * should also avoid the tlb flush while the dev is not active to mute
 405                  * the tlb timeout log. like mt8173.
 406                  *
 407                  * Case2: The power/clock of infra iommu is always on, and it doesn't
 408                  * have the device link with the master devices. This case should avoid
 409                  * the PM status check.
 410                  */
 411                 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
 412
 413                 if (check_pm_status) {
 414                         if (pm_runtime_get_if_in_use(data->dev) <= 0)
 415                                 continue;
 416                 }
 417
 418                 curbank = &data->bank[bank->id];
 419                 base = curbank->base;
 420
 421                 spin_lock_irqsave(&curbank->tlb_lock, flags);
 422                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 423                                base + data->plat_data->inv_sel_reg);
 424
 425                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
 426                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
 427                                base + REG_MMU_INVLD_END_A);
 428                 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
 429
 430                 /* tlb sync */
 431                 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
 432                                                 tmp, tmp != 0, 10, 1000);
 433
 434                 /* Clear the CPE status */
 435                 writel_relaxed(0, base + REG_MMU_CPE_DONE);
 436                 spin_unlock_irqrestore(&curbank->tlb_lock, flags);
 437
 438                 if (ret) {
 439                         dev_warn(data->dev,
 440                                  "Partial TLB flush timed out, falling back to full flush\n");
 441                         mtk_iommu_tlb_flush_all(data);
 442                 }
 443
 444                 if (check_pm_status)
 445                         pm_runtime_put(data->dev);
 446         }
 447 }
 448
 449 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 450 {
 451         struct mtk_iommu_bank_data *bank = dev_id;
 452         struct mtk_iommu_data *data = bank->parent_data;
 453         struct mtk_iommu_domain *dom = bank->m4u_dom;
 454         unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
 455         u32 int_state, regval, va34_32, pa34_32;
 456         const struct mtk_iommu_plat_data *plat_data = data->plat_data;
 457         void __iomem *base = bank->base;
 458         u64 fault_iova, fault_pa;
 459         bool layer, write;
 460
 461         /* Read error info from registers */
 462         int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
 463         if (int_state & F_REG_MMU0_FAULT_MASK) {
 464                 regval = readl_relaxed(base + REG_MMU0_INT_ID);
 465                 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
 466                 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
 467         } else {
 468                 regval = readl_relaxed(base + REG_MMU1_INT_ID);
 469                 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
 470                 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
 471         }
 472         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 473         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 474         if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
 475                 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
 476                 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
 477                 fault_iova |= (u64)va34_32 << 32;
 478         }
 479         pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
 480         fault_pa |= (u64)pa34_32 << 32;
 481
 482         if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
 483                 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
 484                         fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 485                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 486                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 487                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
 488                         fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
 489                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
 490                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 491                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
 492                         fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
 493                         fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
 494                 } else {
 495                         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 496                         fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 497                 }
 498                 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 499         }
 500
 501         if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
 502                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 503                 dev_err_ratelimited(
 504                         bank->parent_dev,
 505                         "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
 506                         int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
 507                         layer, write ? "write" : "read");
 508         }
 509
 510         /* Interrupt clear */
 511         regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 512         regval |= F_INT_CLR_BIT;
 513         writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
 514
 515         mtk_iommu_tlb_flush_all(data);
 516
 517         return IRQ_HANDLED;
 518 }
 519
 520 static unsigned int mtk_iommu_get_bank_id(struct device *dev,
 521                                           const struct mtk_iommu_plat_data *plat_data)
 522 {
 523         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 524         unsigned int i, portmsk = 0, bankid = 0;
 525
 526         if (plat_data->banks_num == 1)
 527                 return bankid;
 528
 529         for (i = 0; i < fwspec->num_ids; i++)
 530                 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
 531
 532         for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
 533                 if (!plat_data->banks_enable[i])
 534                         continue;
 535
 536                 if (portmsk & plat_data->banks_portmsk[i]) {
 537                         bankid = i;
 538                         break;
 539                 }
 540         }
 541         return bankid; /* default is 0 */
 542 }
 543
 544 static int mtk_iommu_get_iova_region_id(struct device *dev,
 545                                         const struct mtk_iommu_plat_data *plat_data)
 546 {
 547         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 548         unsigned int portidmsk = 0, larbid;
 549         const u32 *rgn_larb_msk;
 550         int i;
 551
 552         if (plat_data->iova_region_nr == 1)
 553                 return 0;
 554
 555         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 556         for (i = 0; i < fwspec->num_ids; i++)
 557                 portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
 558
 559         for (i = 0; i < plat_data->iova_region_nr; i++) {
 560                 rgn_larb_msk = plat_data->iova_region_larb_msk[i];
 561                 if (!rgn_larb_msk)
 562                         continue;
 563
 564                 if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk)
 565                         return i;
 566         }
 567
 568         dev_err(dev, "Can NOT find the region for larb(%d-%x).\n",
 569                 larbid, portidmsk);
 570         return -EINVAL;
 571 }
 572
 573 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
 574                             bool enable, unsigned int regionid)
 575 {
 576         struct mtk_smi_larb_iommu    *larb_mmu;
 577         unsigned int                 larbid, portid;
 578         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 579         const struct mtk_iommu_iova_region *region;
 580         u32 peri_mmuen, peri_mmuen_msk;
 581         int i, ret = 0;
 582
 583         for (i = 0; i < fwspec->num_ids; ++i) {
 584                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 585                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 586
 587                 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 588                         larb_mmu = &data->larb_imu[larbid];
 589
 590                         region = data->plat_data->iova_region + regionid;
 591                         larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
 592
 593                         dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
 594                                 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
 595                                 portid, regionid, larb_mmu->bank[portid]);
 596
 597                         if (enable)
 598                                 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 599                         else
 600                                 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 601                 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
 602                         peri_mmuen_msk = BIT(portid);
 603                         /* PCI dev has only one output id, enable the next writing bit for PCIe */
 604                         if (dev_is_pci(dev))
 605                                 peri_mmuen_msk |= BIT(portid + 1);
 606
 607                         peri_mmuen = enable ? peri_mmuen_msk : 0;
 608                         ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
 609                                                  peri_mmuen_msk, peri_mmuen);
 610                         if (ret)
 611                                 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
 612                                         enable ? "enable" : "disable",
 613                                         dev_name(data->dev), peri_mmuen_msk, ret);
 614                 }
 615         }
 616         return ret;
 617 }
 618
 619 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 620                                      struct mtk_iommu_data *data,
 621                                      unsigned int region_id)
 622 {
 623         const struct mtk_iommu_iova_region *region;
 624         struct mtk_iommu_domain *m4u_dom;
 625
 626         /* Always use bank0 in sharing pgtable case */
 627         m4u_dom = data->bank[0].m4u_dom;
 628         if (m4u_dom) {
 629                 dom->iop = m4u_dom->iop;
 630                 dom->cfg = m4u_dom->cfg;
 631                 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
 632                 goto update_iova_region;
 633         }
 634
 635         dom->cfg = (struct io_pgtable_cfg) {
 636                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 637                         IO_PGTABLE_QUIRK_NO_PERMS |
 638                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 639                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 640                 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
 641                 .iommu_dev = data->dev,
 642         };
 643
 644         if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
 645                 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
 646
 647         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
 648                 dom->cfg.oas = data->enable_4GB ? 33 : 32;
 649         else
 650                 dom->cfg.oas = 35;
 651
 652         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 653         if (!dom->iop) {
 654                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 655                 return -ENOMEM;
 656         }
 657
 658         /* Update our support page sizes bitmap */
 659         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 660
 661 update_iova_region:
 662         /* Update the iova region for this domain */
 663         region = data->plat_data->iova_region + region_id;
 664         dom->domain.geometry.aperture_start = region->iova_base;
 665         dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
 666         dom->domain.geometry.force_aperture = true;
 667         return 0;
 668 }
 669
 670 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 671 {
 672         struct mtk_iommu_domain *dom;
 673
 674         if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
 675                 return NULL;
 676
 677         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 678         if (!dom)
 679                 return NULL;
 680         mutex_init(&dom->mutex);
 681
 682         return &dom->domain;
 683 }
 684
 685 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 686 {
 687         kfree(to_mtk_domain(domain));
 688 }
 689
 690 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 691                                    struct device *dev)
 692 {
 693         struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
 694         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 695         struct list_head *hw_list = data->hw_list;
 696         struct device *m4udev = data->dev;
 697         struct mtk_iommu_bank_data *bank;
 698         unsigned int bankid;
 699         int ret, region_id;
 700
 701         region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
 702         if (region_id < 0)
 703                 return region_id;
 704
 705         bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
 706         mutex_lock(&dom->mutex);
 707         if (!dom->bank) {
 708                 /* Data is in the frstdata in sharing pgtable case. */
 709                 frstdata = mtk_iommu_get_frst_data(hw_list);
 710
 711                 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
 712                 if (ret) {
 713                         mutex_unlock(&dom->mutex);
 714                         return ret;
 715                 }
 716                 dom->bank = &data->bank[bankid];
 717         }
 718         mutex_unlock(&dom->mutex);
 719
 720         mutex_lock(&data->mutex);
 721         bank = &data->bank[bankid];
 722         if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
 723                 ret = pm_runtime_resume_and_get(m4udev);
 724                 if (ret < 0) {
 725                         dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
 726                         goto err_unlock;
 727                 }
 728
 729                 ret = mtk_iommu_hw_init(data, bankid);
 730                 if (ret) {
 731                         pm_runtime_put(m4udev);
 732                         goto err_unlock;
 733                 }
 734                 bank->m4u_dom = dom;
 735                 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
 736
 737                 pm_runtime_put(m4udev);
 738         }
 739         mutex_unlock(&data->mutex);
 740
 741         if (region_id > 0) {
 742                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
 743                 if (ret) {
 744                         dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret);
 745                         return ret;
 746                 }
 747         }
 748
 749         return mtk_iommu_config(data, dev, true, region_id);
 750
 751 err_unlock:
 752         mutex_unlock(&data->mutex);
 753         return ret;
 754 }
 755
 756 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 757                          phys_addr_t paddr, size_t pgsize, size_t pgcount,
 758                          int prot, gfp_t gfp, size_t *mapped)
 759 {
 760         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 761
 762         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 763         if (dom->bank->parent_data->enable_4GB)
 764                 paddr |= BIT_ULL(32);
 765
 766         /* Synchronize with the tlb_lock */
 767         return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
 768 }
 769
 770 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 771                               unsigned long iova, size_t pgsize, size_t pgcount,
 772                               struct iommu_iotlb_gather *gather)
 773 {
 774         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 775
 776         iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
 777         return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
 778 }
 779
 780 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 781 {
 782         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 783
 784         if (dom->bank)
 785                 mtk_iommu_tlb_flush_all(dom->bank->parent_data);
 786 }
 787
 788 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 789                                  struct iommu_iotlb_gather *gather)
 790 {
 791         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 792         size_t length = gather->end - gather->start + 1;
 793
 794         mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
 795 }
 796
 797 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
 798                                size_t size)
 799 {
 800         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 801
 802         mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
 803 }
 804
 805 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 806                                           dma_addr_t iova)
 807 {
 808         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 809         phys_addr_t pa;
 810
 811         pa = dom->iop->iova_to_phys(dom->iop, iova);
 812         if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
 813             dom->bank->parent_data->enable_4GB &&
 814             pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 815                 pa &= ~BIT_ULL(32);
 816
 817         return pa;
 818 }
 819
 820 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 821 {
 822         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 823         struct mtk_iommu_data *data;
 824         struct device_link *link;
 825         struct device *larbdev;
 826         unsigned int larbid, larbidx, i;
 827
 828         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 829                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 830
 831         data = dev_iommu_priv_get(dev);
 832
 833         if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
 834                 return &data->iommu;
 835
 836         /*
 837          * Link the consumer device with the smi-larb device(supplier).
 838          * The device that connects with each a larb is a independent HW.
 839          * All the ports in each a device should be in the same larbs.
 840          */
 841         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 842         if (larbid >= MTK_LARB_NR_MAX)
 843                 return ERR_PTR(-EINVAL);
 844
 845         for (i = 1; i < fwspec->num_ids; i++) {
 846                 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
 847                 if (larbid != larbidx) {
 848                         dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
 849                                 larbid, larbidx);
 850                         return ERR_PTR(-EINVAL);
 851                 }
 852         }
 853         larbdev = data->larb_imu[larbid].dev;
 854         if (!larbdev)
 855                 return ERR_PTR(-EINVAL);
 856
 857         link = device_link_add(dev, larbdev,
 858                                DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 859         if (!link)
 860                 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
 861         return &data->iommu;
 862 }
 863
 864 static void mtk_iommu_release_device(struct device *dev)
 865 {
 866         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 867         struct mtk_iommu_data *data;
 868         struct device *larbdev;
 869         unsigned int larbid;
 870
 871         data = dev_iommu_priv_get(dev);
 872         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 873                 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 874                 larbdev = data->larb_imu[larbid].dev;
 875                 device_link_remove(dev, larbdev);
 876         }
 877 }
 878
 879 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
 880 {
 881         unsigned int bankid;
 882
 883         /*
 884          * If the bank function is enabled, each bank is a iommu group/domain.
 885          * Otherwise, each iova region is a iommu group/domain.
 886          */
 887         bankid = mtk_iommu_get_bank_id(dev, plat_data);
 888         if (bankid)
 889                 return bankid;
 890
 891         return mtk_iommu_get_iova_region_id(dev, plat_data);
 892 }
 893
 894 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 895 {
 896         struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
 897         struct list_head *hw_list = c_data->hw_list;
 898         struct iommu_group *group;
 899         int groupid;
 900
 901         data = mtk_iommu_get_frst_data(hw_list);
 902         if (!data)
 903                 return ERR_PTR(-ENODEV);
 904
 905         groupid = mtk_iommu_get_group_id(dev, data->plat_data);
 906         if (groupid < 0)
 907                 return ERR_PTR(groupid);
 908
 909         mutex_lock(&data->mutex);
 910         group = data->m4u_group[groupid];
 911         if (!group) {
 912                 group = iommu_group_alloc();
 913                 if (!IS_ERR(group))
 914                         data->m4u_group[groupid] = group;
 915         } else {
 916                 iommu_group_ref_get(group);
 917         }
 918         mutex_unlock(&data->mutex);
 919         return group;
 920 }
 921
 922 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 923 {
 924         struct platform_device *m4updev;
 925
 926         if (args->args_count != 1) {
 927                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 928                         args->args_count);
 929                 return -EINVAL;
 930         }
 931
 932         if (!dev_iommu_priv_get(dev)) {
 933                 /* Get the m4u device */
 934                 m4updev = of_find_device_by_node(args->np);
 935                 if (WARN_ON(!m4updev))
 936                         return -EINVAL;
 937
 938                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 939         }
 940
 941         return iommu_fwspec_add_ids(dev, args->args, 1);
 942 }
 943
 944 static void mtk_iommu_get_resv_regions(struct device *dev,
 945                                        struct list_head *head)
 946 {
 947         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 948         unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
 949         const struct mtk_iommu_iova_region *resv, *curdom;
 950         struct iommu_resv_region *region;
 951         int prot = IOMMU_WRITE | IOMMU_READ;
 952
 953         if ((int)regionid < 0)
 954                 return;
 955         curdom = data->plat_data->iova_region + regionid;
 956         for (i = 0; i < data->plat_data->iova_region_nr; i++) {
 957                 resv = data->plat_data->iova_region + i;
 958
 959                 /* Only reserve when the region is inside the current domain */
 960                 if (resv->iova_base <= curdom->iova_base ||
 961                     resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
 962                         continue;
 963
 964                 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
 965                                                  prot, IOMMU_RESV_RESERVED,
 966                                                  GFP_KERNEL);
 967                 if (!region)
 968                         return;
 969
 970                 list_add_tail(&region->list, head);
 971         }
 972 }
 973
 974 static const struct iommu_ops mtk_iommu_ops = {
 975         .domain_alloc   = mtk_iommu_domain_alloc,
 976         .probe_device   = mtk_iommu_probe_device,
 977         .release_device = mtk_iommu_release_device,
 978         .device_group   = mtk_iommu_device_group,
 979         .of_xlate       = mtk_iommu_of_xlate,
 980         .get_resv_regions = mtk_iommu_get_resv_regions,
 981         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 982         .owner          = THIS_MODULE,
 983         .default_domain_ops = &(const struct iommu_domain_ops) {
 984                 .attach_dev     = mtk_iommu_attach_device,
 985                 .map_pages      = mtk_iommu_map,
 986                 .unmap_pages    = mtk_iommu_unmap,
 987                 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
 988                 .iotlb_sync     = mtk_iommu_iotlb_sync,
 989                 .iotlb_sync_map = mtk_iommu_sync_map,
 990                 .iova_to_phys   = mtk_iommu_iova_to_phys,
 991                 .free           = mtk_iommu_domain_free,
 992         }
 993 };
 994
 995 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
 996 {
 997         const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
 998         const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
 999         u32 regval;
1000
1001         /*
1002          * Global control settings are in bank0. May re-init these global registers
1003          * since no sure if there is bank0 consumers.
1004          */
1005         if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
1006                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
1007                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
1008         } else {
1009                 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
1010                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
1011         }
1012         writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
1013
1014         if (data->enable_4GB &&
1015             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
1016                 /*
1017                  * If 4GB mode is enabled, the validate PA range is from
1018                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
1019                  */
1020                 regval = F_MMU_VLD_PA_RNG(7, 4);
1021                 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
1022         }
1023         if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
1024                 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
1025         else
1026                 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
1027
1028         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
1029                 /* write command throttling mode */
1030                 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
1031                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
1032                 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
1033         }
1034
1035         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
1036                 /* The register is called STANDARD_AXI_MODE in this case */
1037                 regval = 0;
1038         } else {
1039                 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
1040                 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
1041                         regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
1042                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
1043                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
1044         }
1045         writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
1046
1047         /* Independent settings for each bank */
1048         regval = F_L2_MULIT_HIT_EN |
1049                 F_TABLE_WALK_FAULT_INT_EN |
1050                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
1051                 F_MISS_FIFO_OVERFLOW_INT_EN |
1052                 F_PREFETCH_FIFO_ERR_INT_EN |
1053                 F_MISS_FIFO_ERR_INT_EN;
1054         writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1055
1056         regval = F_INT_TRANSLATION_FAULT |
1057                 F_INT_MAIN_MULTI_HIT_FAULT |
1058                 F_INT_INVALID_PA_FAULT |
1059                 F_INT_ENTRY_REPLACEMENT_FAULT |
1060                 F_INT_TLB_MISS_FAULT |
1061                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
1062                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1063         writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1064
1065         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1066                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1067         else
1068                 regval = lower_32_bits(data->protect_base) |
1069                          upper_32_bits(data->protect_base);
1070         writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1071
1072         if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1073                              dev_name(bankx->parent_dev), (void *)bankx)) {
1074                 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1075                 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
1076                 return -ENODEV;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static const struct component_master_ops mtk_iommu_com_ops = {
1083         .bind           = mtk_iommu_bind,
1084         .unbind         = mtk_iommu_unbind,
1085 };
1086
1087 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1088                                   struct mtk_iommu_data *data)
1089 {
1090         struct device_node *larbnode, *frst_avail_smicomm_node = NULL;
1091         struct platform_device *plarbdev, *pcommdev;
1092         struct device_link *link;
1093         int i, larb_nr, ret;
1094
1095         larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1096         if (larb_nr < 0)
1097                 return larb_nr;
1098         if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX)
1099                 return -EINVAL;
1100
1101         for (i = 0; i < larb_nr; i++) {
1102                 struct device_node *smicomm_node, *smi_subcomm_node;
1103                 u32 id;
1104
1105                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
1106                 if (!larbnode) {
1107                         ret = -EINVAL;
1108                         goto err_larbdev_put;
1109                 }
1110
1111                 if (!of_device_is_available(larbnode)) {
1112                         of_node_put(larbnode);
1113                         continue;
1114                 }
1115
1116                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1117                 if (ret)/* The id is consecutive if there is no this property */
1118                         id = i;
1119                 if (id >= MTK_LARB_NR_MAX) {
1120                         of_node_put(larbnode);
1121                         ret = -EINVAL;
1122                         goto err_larbdev_put;
1123                 }
1124
1125                 plarbdev = of_find_device_by_node(larbnode);
1126                 of_node_put(larbnode);
1127                 if (!plarbdev) {
1128                         ret = -ENODEV;
1129                         goto err_larbdev_put;
1130                 }
1131                 if (data->larb_imu[id].dev) {
1132                         platform_device_put(plarbdev);
1133                         ret = -EEXIST;
1134                         goto err_larbdev_put;
1135                 }
1136                 data->larb_imu[id].dev = &plarbdev->dev;
1137
1138                 if (!plarbdev->dev.driver) {
1139                         ret = -EPROBE_DEFER;
1140                         goto err_larbdev_put;
1141                 }
1142
1143                 /* Get smi-(sub)-common dev from the last larb. */
1144                 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
1145                 if (!smi_subcomm_node) {
1146                         ret = -EINVAL;
1147                         goto err_larbdev_put;
1148                 }
1149
1150                 /*
1151                  * It may have two level smi-common. the node is smi-sub-common if it
1152                  * has a new mediatek,smi property. otherwise it is smi-commmon.
1153                  */
1154                 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1155                 if (smicomm_node)
1156                         of_node_put(smi_subcomm_node);
1157                 else
1158                         smicomm_node = smi_subcomm_node;
1159
1160                 /*
1161                  * All the larbs that connect to one IOMMU must connect with the same
1162                  * smi-common.
1163                  */
1164                 if (!frst_avail_smicomm_node) {
1165                         frst_avail_smicomm_node = smicomm_node;
1166                 } else if (frst_avail_smicomm_node != smicomm_node) {
1167                         dev_err(dev, "mediatek,smi property is not right @larb%d.", id);
1168                         of_node_put(smicomm_node);
1169                         ret = -EINVAL;
1170                         goto err_larbdev_put;
1171                 } else {
1172                         of_node_put(smicomm_node);
1173                 }
1174
1175                 component_match_add(dev, match, component_compare_dev, &plarbdev->dev);
1176                 platform_device_put(plarbdev);
1177         }
1178
1179         if (!frst_avail_smicomm_node)
1180                 return -EINVAL;
1181
1182         pcommdev = of_find_device_by_node(frst_avail_smicomm_node);
1183         of_node_put(frst_avail_smicomm_node);
1184         if (!pcommdev)
1185                 return -ENODEV;
1186         data->smicomm_dev = &pcommdev->dev;
1187
1188         link = device_link_add(data->smicomm_dev, dev,
1189                                DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1190         platform_device_put(pcommdev);
1191         if (!link) {
1192                 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1193                 return -EINVAL;
1194         }
1195         return 0;
1196
1197 err_larbdev_put:
1198         for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) {
1199                 if (!data->larb_imu[i].dev)
1200                         continue;
1201                 put_device(data->larb_imu[i].dev);
1202         }
1203         return ret;
1204 }
1205
1206 static int mtk_iommu_probe(struct platform_device *pdev)
1207 {
1208         struct mtk_iommu_data   *data;
1209         struct device           *dev = &pdev->dev;
1210         struct resource         *res;
1211         resource_size_t         ioaddr;
1212         struct component_match  *match = NULL;
1213         struct regmap           *infracfg;
1214         void                    *protect;
1215         int                     ret, banks_num, i = 0;
1216         u32                     val;
1217         char                    *p;
1218         struct mtk_iommu_bank_data *bank;
1219         void __iomem            *base;
1220
1221         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1222         if (!data)
1223                 return -ENOMEM;
1224         data->dev = dev;
1225         data->plat_data = of_device_get_match_data(dev);
1226
1227         /* Protect memory. HW will access here while translation fault.*/
1228         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
1229         if (!protect)
1230                 return -ENOMEM;
1231         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
1232
1233         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
1234                 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
1235                 if (IS_ERR(infracfg)) {
1236                         /*
1237                          * Legacy devicetrees will not specify a phandle to
1238                          * mediatek,infracfg: in that case, we use the older
1239                          * way to retrieve a syscon to infra.
1240                          *
1241                          * This is for retrocompatibility purposes only, hence
1242                          * no more compatibles shall be added to this.
1243                          */
1244                         switch (data->plat_data->m4u_plat) {
1245                         case M4U_MT2712:
1246                                 p = "mediatek,mt2712-infracfg";
1247                                 break;
1248                         case M4U_MT8173:
1249                                 p = "mediatek,mt8173-infracfg";
1250                                 break;
1251                         default:
1252                                 p = NULL;
1253                         }
1254
1255                         infracfg = syscon_regmap_lookup_by_compatible(p);
1256                         if (IS_ERR(infracfg))
1257                                 return PTR_ERR(infracfg);
1258                 }
1259
1260                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1261                 if (ret)
1262                         return ret;
1263                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1264         }
1265
1266         banks_num = data->plat_data->banks_num;
1267         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1268         if (!res)
1269                 return -EINVAL;
1270         if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
1271                 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
1272                 return -EINVAL;
1273         }
1274         base = devm_ioremap_resource(dev, res);
1275         if (IS_ERR(base))
1276                 return PTR_ERR(base);
1277         ioaddr = res->start;
1278
1279         data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
1280         if (!data->bank)
1281                 return -ENOMEM;
1282
1283         do {
1284                 if (!data->plat_data->banks_enable[i])
1285                         continue;
1286                 bank = &data->bank[i];
1287                 bank->id = i;
1288                 bank->base = base + i * MTK_IOMMU_BANK_SZ;
1289                 bank->m4u_dom = NULL;
1290
1291                 bank->irq = platform_get_irq(pdev, i);
1292                 if (bank->irq < 0)
1293                         return bank->irq;
1294                 bank->parent_dev = dev;
1295                 bank->parent_data = data;
1296                 spin_lock_init(&bank->tlb_lock);
1297         } while (++i < banks_num);
1298
1299         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1300                 data->bclk = devm_clk_get(dev, "bclk");
1301                 if (IS_ERR(data->bclk))
1302                         return PTR_ERR(data->bclk);
1303         }
1304
1305         if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
1306                 ret = dma_set_mask(dev, DMA_BIT_MASK(35));
1307                 if (ret) {
1308                         dev_err(dev, "Failed to set dma_mask 35.\n");
1309                         return ret;
1310                 }
1311         }
1312
1313         pm_runtime_enable(dev);
1314
1315         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1316                 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1317                 if (ret) {
1318                         dev_err_probe(dev, ret, "mm dts parse fail\n");
1319                         goto out_runtime_disable;
1320                 }
1321         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
1322                 p = data->plat_data->pericfg_comp_str;
1323                 data->pericfg = syscon_regmap_lookup_by_compatible(p);
1324                 if (IS_ERR(data->pericfg)) {
1325                         ret = PTR_ERR(data->pericfg);
1326                         goto out_runtime_disable;
1327                 }
1328         }
1329
1330         platform_set_drvdata(pdev, data);
1331         mutex_init(&data->mutex);
1332
1333         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1334                                      "mtk-iommu.%pa", &ioaddr);
1335         if (ret)
1336                 goto out_link_remove;
1337
1338         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1339         if (ret)
1340                 goto out_sysfs_remove;
1341
1342         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1343                 list_add_tail(&data->list, data->plat_data->hw_list);
1344                 data->hw_list = data->plat_data->hw_list;
1345         } else {
1346                 INIT_LIST_HEAD(&data->hw_list_head);
1347                 list_add_tail(&data->list, &data->hw_list_head);
1348                 data->hw_list = &data->hw_list_head;
1349         }
1350
1351         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1352                 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1353                 if (ret)
1354                         goto out_list_del;
1355         }
1356         return ret;
1357
1358 out_list_del:
1359         list_del(&data->list);
1360         iommu_device_unregister(&data->iommu);
1361 out_sysfs_remove:
1362         iommu_device_sysfs_remove(&data->iommu);
1363 out_link_remove:
1364         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1365                 device_link_remove(data->smicomm_dev, dev);
1366 out_runtime_disable:
1367         pm_runtime_disable(dev);
1368         return ret;
1369 }
1370
1371 static void mtk_iommu_remove(struct platform_device *pdev)
1372 {
1373         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1374         struct mtk_iommu_bank_data *bank;
1375         int i;
1376
1377         iommu_device_sysfs_remove(&data->iommu);
1378         iommu_device_unregister(&data->iommu);
1379
1380         list_del(&data->list);
1381
1382         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1383                 device_link_remove(data->smicomm_dev, &pdev->dev);
1384                 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1385         }
1386         pm_runtime_disable(&pdev->dev);
1387         for (i = 0; i < data->plat_data->banks_num; i++) {
1388                 bank = &data->bank[i];
1389                 if (!bank->m4u_dom)
1390                         continue;
1391                 devm_free_irq(&pdev->dev, bank->irq, bank);
1392         }
1393 }
1394
1395 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1396 {
1397         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1398         struct mtk_iommu_suspend_reg *reg = &data->reg;
1399         void __iomem *base;
1400         int i = 0;
1401
1402         base = data->bank[i].base;
1403         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1404         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1405         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1406         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1407         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1408         do {
1409                 if (!data->plat_data->banks_enable[i])
1410                         continue;
1411                 base = data->bank[i].base;
1412                 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1413                 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1414                 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1415         } while (++i < data->plat_data->banks_num);
1416         clk_disable_unprepare(data->bclk);
1417         return 0;
1418 }
1419
1420 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1421 {
1422         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1423         struct mtk_iommu_suspend_reg *reg = &data->reg;
1424         struct mtk_iommu_domain *m4u_dom;
1425         void __iomem *base;
1426         int ret, i = 0;
1427
1428         ret = clk_prepare_enable(data->bclk);
1429         if (ret) {
1430                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1431                 return ret;
1432         }
1433
1434         /*
1435          * Uppon first resume, only enable the clk and return, since the values of the
1436          * registers are not yet set.
1437          */
1438         if (!reg->wr_len_ctrl)
1439                 return 0;
1440
1441         base = data->bank[i].base;
1442         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1443         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1444         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1445         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1446         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1447         do {
1448                 m4u_dom = data->bank[i].m4u_dom;
1449                 if (!data->plat_data->banks_enable[i] || !m4u_dom)
1450                         continue;
1451                 base = data->bank[i].base;
1452                 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1453                 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1454                 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1455                 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1456         } while (++i < data->plat_data->banks_num);
1457
1458         /*
1459          * Users may allocate dma buffer before they call pm_runtime_get,
1460          * in which case it will lack the necessary tlb flush.
1461          * Thus, make sure to update the tlb after each PM resume.
1462          */
1463         mtk_iommu_tlb_flush_all(data);
1464         return 0;
1465 }
1466
1467 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1468         SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1469         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1470                                      pm_runtime_force_resume)
1471 };
1472
1473 static const struct mtk_iommu_plat_data mt2712_data = {
1474         .m4u_plat     = M4U_MT2712,
1475         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1476                         MTK_IOMMU_TYPE_MM,
1477         .hw_list      = &m4ulist,
1478         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1479         .iova_region  = single_domain,
1480         .banks_num    = 1,
1481         .banks_enable = {true},
1482         .iova_region_nr = ARRAY_SIZE(single_domain),
1483         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1484 };
1485
1486 static const struct mtk_iommu_plat_data mt6779_data = {
1487         .m4u_plat      = M4U_MT6779,
1488         .flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1489                          MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1490         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
1491         .banks_num    = 1,
1492         .banks_enable = {true},
1493         .iova_region   = single_domain,
1494         .iova_region_nr = ARRAY_SIZE(single_domain),
1495         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1496 };
1497
1498 static const struct mtk_iommu_plat_data mt6795_data = {
1499         .m4u_plat     = M4U_MT6795,
1500         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1501                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1502                         TF_PORT_TO_ADDR_MT8173,
1503         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1504         .banks_num    = 1,
1505         .banks_enable = {true},
1506         .iova_region  = single_domain,
1507         .iova_region_nr = ARRAY_SIZE(single_domain),
1508         .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
1509 };
1510
1511 static const struct mtk_iommu_plat_data mt8167_data = {
1512         .m4u_plat     = M4U_MT8167,
1513         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1514         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1515         .banks_num    = 1,
1516         .banks_enable = {true},
1517         .iova_region  = single_domain,
1518         .iova_region_nr = ARRAY_SIZE(single_domain),
1519         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1520 };
1521
1522 static const struct mtk_iommu_plat_data mt8173_data = {
1523         .m4u_plat     = M4U_MT8173,
1524         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1525                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1526                         TF_PORT_TO_ADDR_MT8173,
1527         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1528         .banks_num    = 1,
1529         .banks_enable = {true},
1530         .iova_region  = single_domain,
1531         .iova_region_nr = ARRAY_SIZE(single_domain),
1532         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1533 };
1534
1535 static const struct mtk_iommu_plat_data mt8183_data = {
1536         .m4u_plat     = M4U_MT8183,
1537         .flags        = RESET_AXI | MTK_IOMMU_TYPE_MM,
1538         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1539         .banks_num    = 1,
1540         .banks_enable = {true},
1541         .iova_region  = single_domain,
1542         .iova_region_nr = ARRAY_SIZE(single_domain),
1543         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1544 };
1545
1546 static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1547         [0] = {~0, ~0, ~0},                     /* Region0: all ports for larb0/1/2 */
1548         [1] = {0, 0, 0, 0, ~0, 0, 0, ~0},       /* Region1: larb4/7 */
1549         [2] = {0, 0, 0, 0, 0, 0, 0, 0,          /* Region2: larb8/9/11/13/16/17/19/20 */
1550                ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0,
1551                                                 /* larb13: the other ports except port9/10 */
1552                ~0, ~0, 0, ~0, ~0},
1553         [3] = {0},
1554         [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
1555         [5] = {[14] = ~0},                      /* larb14 */
1556 };
1557
1558 static const struct mtk_iommu_plat_data mt8186_data_mm = {
1559         .m4u_plat       = M4U_MT8186,
1560         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1561                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1562         .larbid_remap   = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1563                            {MTK_INVALID_LARBID, 14, 16},
1564                            {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1565         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1566         .banks_num      = 1,
1567         .banks_enable   = {true},
1568         .iova_region    = mt8192_multi_dom,
1569         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1570         .iova_region_larb_msk = mt8186_larb_region_msk,
1571 };
1572
1573 static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1574         [0] = {~0, ~0},                         /* Region0: larb0/1 */
1575         [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},      /* Region1: larb4/5/7 */
1576         [2] = {0, 0, ~0, 0, 0, 0, 0, 0,         /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
1577                0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
1578                ~0, ~0, ~0, ~0, ~0},
1579         [3] = {0},
1580         [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
1581         [5] = {[14] = BIT(4) | BIT(5)},         /* larb14 port4/5 */
1582 };
1583
1584 static const struct mtk_iommu_plat_data mt8192_data = {
1585         .m4u_plat       = M4U_MT8192,
1586         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1587                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1588         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1589         .banks_num      = 1,
1590         .banks_enable   = {true},
1591         .iova_region    = mt8192_multi_dom,
1592         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1593         .iova_region_larb_msk = mt8192_larb_region_msk,
1594         .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1595                            {0, 14, 16}, {0, 13, 18, 17}},
1596 };
1597
1598 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1599         .m4u_plat         = M4U_MT8195,
1600         .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1601                             MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1602         .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1603         .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
1604         .banks_num        = 5,
1605         .banks_enable     = {true, false, false, false, true},
1606         .banks_portmsk    = {[0] = GENMASK(19, 16),     /* PCIe */
1607                              [4] = GENMASK(31, 20),     /* USB */
1608                             },
1609         .iova_region      = single_domain,
1610         .iova_region_nr   = ARRAY_SIZE(single_domain),
1611 };
1612
1613 static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1614         [0] = {~0, ~0, ~0, ~0},               /* Region0: all ports for larb0/1/2/3 */
1615         [1] = {0, 0, 0, 0, 0, 0, 0, 0,
1616                0, 0, 0, 0, 0, 0, 0, 0,
1617                0, 0, 0, ~0, ~0, ~0, ~0, ~0,   /* Region1: larb19/20/21/22/23/24 */
1618                ~0},
1619         [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0,    /* Region2: the other larbs. */
1620                ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
1621                ~0, ~0, 0, 0, 0, 0, 0, 0,
1622                0, ~0, ~0, ~0, ~0},
1623         [3] = {0},
1624         [4] = {[18] = BIT(0) | BIT(1)},       /* Only larb18 port0/1 */
1625         [5] = {[18] = BIT(2) | BIT(3)},       /* Only larb18 port2/3 */
1626 };
1627
1628 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1629         .m4u_plat       = M4U_MT8195,
1630         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1631                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1632         .hw_list        = &m4ulist,
1633         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1634         .banks_num      = 1,
1635         .banks_enable   = {true},
1636         .iova_region    = mt8192_multi_dom,
1637         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1638         .iova_region_larb_msk = mt8195_larb_region_msk,
1639         .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1640                            {13, 17, 15/* 17b */, 25}, {5}},
1641 };
1642
1643 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1644         .m4u_plat       = M4U_MT8195,
1645         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1646                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1647         .hw_list        = &m4ulist,
1648         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1649         .banks_num      = 1,
1650         .banks_enable   = {true},
1651         .iova_region    = mt8192_multi_dom,
1652         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1653         .iova_region_larb_msk = mt8195_larb_region_msk,
1654         .larbid_remap   = {{1}, {3},
1655                            {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1656                            {8}, {20}, {12},
1657                            /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1658                            {14, 16, 29, 26, 30, 31, 18},
1659                            {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1660 };
1661
1662 static const struct mtk_iommu_plat_data mt8365_data = {
1663         .m4u_plat       = M4U_MT8365,
1664         .flags          = RESET_AXI | INT_ID_PORT_WIDTH_6,
1665         .inv_sel_reg    = REG_MMU_INV_SEL_GEN1,
1666         .banks_num      = 1,
1667         .banks_enable   = {true},
1668         .iova_region    = single_domain,
1669         .iova_region_nr = ARRAY_SIZE(single_domain),
1670         .larbid_remap   = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1671 };
1672
1673 static const struct of_device_id mtk_iommu_of_ids[] = {
1674         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1675         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1676         { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1677         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1678         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1679         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1680         { .compatible = "mediatek,mt8186-iommu-mm",    .data = &mt8186_data_mm}, /* mm: m4u */
1681         { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1682         { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1683         { .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
1684         { .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
1685         { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
1686         {}
1687 };
1688
1689 static struct platform_driver mtk_iommu_driver = {
1690         .probe  = mtk_iommu_probe,
1691         .remove_new = mtk_iommu_remove,
1692         .driver = {
1693                 .name = "mtk-iommu",
1694                 .of_match_table = mtk_iommu_of_ids,
1695                 .pm = &mtk_iommu_pm_ops,
1696         }
1697 };
1698 module_platform_driver(mtk_iommu_driver);
1699
1700 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1701 MODULE_LICENSE("GPL v2");