drivers/gpu/drm/v3d/v3d_sched.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D scheduling
   6  *
   7  * The shared DRM GPU scheduler is used to coordinate submitting jobs
   8  * to the hardware.  Each DRM fd (roughly a client process) gets its
   9  * own scheduler entity, which will process jobs in order.  The GPU
  10  * scheduler will round-robin between clients to submit the next job.
  11  *
  12  * For simplicity, and in order to keep latency low for interactive
  13  * jobs when bulk background jobs are queued up, we submit a new job
  14  * to the HW only when it has completed the last one, instead of
  15  * filling up the CT[01]Q FIFOs with jobs.  Similarly, we use
  16  * v3d_job_dependency() to manage the dependency between bin and
  17  * render, instead of having the clients submit jobs using the HW's
  18  * semaphores to interlock between them.
  19  */
  20
  21 #include <linux/kthread.h>
  22
  23 #include "v3d_drv.h"
  24 #include "v3d_regs.h"
  25 #include "v3d_trace.h"
  26
  27 static struct v3d_job *
  28 to_v3d_job(struct drm_sched_job *sched_job)
  29 {
  30         return container_of(sched_job, struct v3d_job, base);
  31 }
  32
  33 static void
  34 v3d_job_free(struct drm_sched_job *sched_job)
  35 {
  36         struct v3d_job *job = to_v3d_job(sched_job);
  37
  38         drm_sched_job_cleanup(sched_job);
  39
  40         v3d_exec_put(job->exec);
  41 }
  42
  43 /**
  44  * Returns the fences that the bin job depends on, one by one.
  45  * v3d_job_run() won't be called until all of them have been signaled.
  46  */
  47 static struct dma_fence *
  48 v3d_job_dependency(struct drm_sched_job *sched_job,
  49                    struct drm_sched_entity *s_entity)
  50 {
  51         struct v3d_job *job = to_v3d_job(sched_job);
  52         struct v3d_exec_info *exec = job->exec;
  53         enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
  54         struct dma_fence *fence;
  55
  56         fence = job->in_fence;
  57         if (fence) {
  58                 job->in_fence = NULL;
  59                 return fence;
  60         }
  61
  62         if (q == V3D_RENDER) {
  63                 /* If we had a bin job, the render job definitely depends on
  64                  * it. We first have to wait for bin to be scheduled, so that
  65                  * its done_fence is created.
  66                  */
  67                 fence = exec->bin_done_fence;
  68                 if (fence) {
  69                         exec->bin_done_fence = NULL;
  70                         return fence;
  71                 }
  72         }
  73
  74         /* XXX: Wait on a fence for switching the GMP if necessary,
  75          * and then do so.
  76          */
  77
  78         return fence;
  79 }
  80
  81 static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)
  82 {
  83         struct v3d_job *job = to_v3d_job(sched_job);
  84         struct v3d_exec_info *exec = job->exec;
  85         enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
  86         struct v3d_dev *v3d = exec->v3d;
  87         struct drm_device *dev = &v3d->drm;
  88         struct dma_fence *fence;
  89         unsigned long irqflags;
  90
  91         if (unlikely(job->base.s_fence->finished.error))
  92                 return NULL;
  93
  94         /* Lock required around bin_job update vs
  95          * v3d_overflow_mem_work().
  96          */
  97         spin_lock_irqsave(&v3d->job_lock, irqflags);
  98         if (q == V3D_BIN) {
  99                 v3d->bin_job = job->exec;
 100
 101                 /* Clear out the overflow allocation, so we don't
 102                  * reuse the overflow attached to a previous job.
 103                  */
 104                 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
 105         } else {
 106                 v3d->render_job = job->exec;
 107         }
 108         spin_unlock_irqrestore(&v3d->job_lock, irqflags);
 109
 110         /* Can we avoid this flush when q==RENDER?  We need to be
 111          * careful of scheduling, though -- imagine job0 rendering to
 112          * texture and job1 reading, and them being executed as bin0,
 113          * bin1, render0, render1, so that render1's flush at bin time
 114          * wasn't enough.
 115          */
 116         v3d_invalidate_caches(v3d);
 117
 118         fence = v3d_fence_create(v3d, q);
 119         if (IS_ERR(fence))
 120                 return NULL;
 121
 122         if (job->done_fence)
 123                 dma_fence_put(job->done_fence);
 124         job->done_fence = dma_fence_get(fence);
 125
 126         trace_v3d_submit_cl(dev, q == V3D_RENDER, to_v3d_fence(fence)->seqno,
 127                             job->start, job->end);
 128
 129         if (q == V3D_BIN) {
 130                 if (exec->qma) {
 131                         V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, exec->qma);
 132                         V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, exec->qms);
 133                 }
 134                 if (exec->qts) {
 135                         V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
 136                                        V3D_CLE_CT0QTS_ENABLE |
 137                                        exec->qts);
 138                 }
 139         } else {
 140                 /* XXX: Set the QCFG */
 141         }
 142
 143         /* Set the current and end address of the control list.
 144          * Writing the end register is what starts the job.
 145          */
 146         V3D_CORE_WRITE(0, V3D_CLE_CTNQBA(q), job->start);
 147         V3D_CORE_WRITE(0, V3D_CLE_CTNQEA(q), job->end);
 148
 149         return fence;
 150 }
 151
 152 static void
 153 v3d_job_timedout(struct drm_sched_job *sched_job)
 154 {
 155         struct v3d_job *job = to_v3d_job(sched_job);
 156         struct v3d_exec_info *exec = job->exec;
 157         struct v3d_dev *v3d = exec->v3d;
 158         enum v3d_queue job_q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
 159         enum v3d_queue q;
 160         u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
 161         u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
 162
 163         /* If the current address or return address have changed, then
 164          * the GPU has probably made progress and we should delay the
 165          * reset.  This could fail if the GPU got in an infinite loop
 166          * in the CL, but that is pretty unlikely outside of an i-g-t
 167          * testcase.
 168          */
 169         if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
 170                 job->timedout_ctca = ctca;
 171                 job->timedout_ctra = ctra;
 172                 return;
 173         }
 174
 175         mutex_lock(&v3d->reset_lock);
 176
 177         /* block scheduler */
 178         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 179                 struct drm_gpu_scheduler *sched = &v3d->queue[q].sched;
 180
 181                 kthread_park(sched->thread);
 182                 drm_sched_hw_job_reset(sched, (sched_job->sched == sched ?
 183                                                sched_job : NULL));
 184         }
 185
 186         /* get the GPU back into the init state */
 187         v3d_reset(v3d);
 188
 189         /* Unblock schedulers and restart their jobs. */
 190         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 191                 drm_sched_job_recovery(&v3d->queue[q].sched);
 192                 kthread_unpark(v3d->queue[q].sched.thread);
 193         }
 194
 195         mutex_unlock(&v3d->reset_lock);
 196 }
 197
 198 static const struct drm_sched_backend_ops v3d_sched_ops = {
 199         .dependency = v3d_job_dependency,
 200         .run_job = v3d_job_run,
 201         .timedout_job = v3d_job_timedout,
 202         .free_job = v3d_job_free
 203 };
 204
 205 int
 206 v3d_sched_init(struct v3d_dev *v3d)
 207 {
 208         int hw_jobs_limit = 1;
 209         int job_hang_limit = 0;
 210         int hang_limit_ms = 500;
 211         int ret;
 212
 213         ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
 214                              &v3d_sched_ops,
 215                              hw_jobs_limit, job_hang_limit,
 216                              msecs_to_jiffies(hang_limit_ms),
 217                              "v3d_bin");
 218         if (ret) {
 219                 dev_err(v3d->dev, "Failed to create bin scheduler: %d.", ret);
 220                 return ret;
 221         }
 222
 223         ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
 224                              &v3d_sched_ops,
 225                              hw_jobs_limit, job_hang_limit,
 226                              msecs_to_jiffies(hang_limit_ms),
 227                              "v3d_render");
 228         if (ret) {
 229                 dev_err(v3d->dev, "Failed to create render scheduler: %d.",
 230                         ret);
 231                 drm_sched_fini(&v3d->queue[V3D_BIN].sched);
 232                 return ret;
 233         }
 234
 235         return 0;
 236 }
 237
 238 void
 239 v3d_sched_fini(struct v3d_dev *v3d)
 240 {
 241         enum v3d_queue q;
 242
 243         for (q = 0; q < V3D_MAX_QUEUES; q++)
 244                 drm_sched_fini(&v3d->queue[q].sched);
 245 }